1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 I915_MAX_PIPES = _PIPE_EDP
64 #define pipe_name(p) ((p) + 'A')
73 #define transcoder_name(t) ((t) + 'A')
80 #define plane_name(p) ((p) + 'A')
82 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
92 #define port_name(p) ((p) + 'A')
94 #define I915_NUM_PHYS_VLV 1
106 enum intel_display_power_domain {
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
113 POWER_DOMAIN_TRANSCODER_A,
114 POWER_DOMAIN_TRANSCODER_B,
115 POWER_DOMAIN_TRANSCODER_C,
116 POWER_DOMAIN_TRANSCODER_EDP,
117 POWER_DOMAIN_PORT_DDI_A_2_LANES,
118 POWER_DOMAIN_PORT_DDI_A_4_LANES,
119 POWER_DOMAIN_PORT_DDI_B_2_LANES,
120 POWER_DOMAIN_PORT_DDI_B_4_LANES,
121 POWER_DOMAIN_PORT_DDI_C_2_LANES,
122 POWER_DOMAIN_PORT_DDI_C_4_LANES,
123 POWER_DOMAIN_PORT_DDI_D_2_LANES,
124 POWER_DOMAIN_PORT_DDI_D_4_LANES,
125 POWER_DOMAIN_PORT_DSI,
126 POWER_DOMAIN_PORT_CRT,
127 POWER_DOMAIN_PORT_OTHER,
135 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
136 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
138 #define POWER_DOMAIN_TRANSCODER(tran) \
139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
140 (tran) + POWER_DOMAIN_TRANSCODER_A)
144 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
145 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
155 #define I915_GEM_GPU_DOMAINS \
156 (I915_GEM_DOMAIN_RENDER | \
157 I915_GEM_DOMAIN_SAMPLER | \
158 I915_GEM_DOMAIN_COMMAND | \
159 I915_GEM_DOMAIN_INSTRUCTION | \
160 I915_GEM_DOMAIN_VERTEX)
162 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
165 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
166 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
167 if ((intel_encoder)->base.crtc == (__crtc))
169 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
170 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
171 if ((intel_connector)->base.encoder == (__encoder))
173 struct drm_i915_private;
176 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
177 /* real shared dpll ids must be >= 0 */
181 #define I915_NUM_PLLS 2
183 struct intel_dpll_hw_state {
190 struct intel_shared_dpll {
191 int refcount; /* count of number of CRTCs sharing this PLL */
192 int active; /* count of number of active CRTCs (i.e. DPMS on) */
193 bool on; /* is the PLL actually active? Disabled during modeset */
195 /* should match the index in the dev_priv->shared_dplls array */
196 enum intel_dpll_id id;
197 struct intel_dpll_hw_state hw_state;
198 void (*mode_set)(struct drm_i915_private *dev_priv,
199 struct intel_shared_dpll *pll);
200 void (*enable)(struct drm_i915_private *dev_priv,
201 struct intel_shared_dpll *pll);
202 void (*disable)(struct drm_i915_private *dev_priv,
203 struct intel_shared_dpll *pll);
204 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
205 struct intel_shared_dpll *pll,
206 struct intel_dpll_hw_state *hw_state);
209 /* Used by dp and fdi links */
210 struct intel_link_m_n {
218 void intel_link_compute_m_n(int bpp, int nlanes,
219 int pixel_clock, int link_clock,
220 struct intel_link_m_n *m_n);
222 struct intel_ddi_plls {
228 /* Interface history:
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
238 #define DRIVER_MAJOR 1
239 #define DRIVER_MINOR 6
240 #define DRIVER_PATCHLEVEL 0
242 #define WATCH_LISTS 0
245 #define I915_GEM_PHYS_CURSOR_0 1
246 #define I915_GEM_PHYS_CURSOR_1 2
247 #define I915_GEM_PHYS_OVERLAY_REGS 3
248 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250 struct drm_i915_gem_phys_object {
252 struct page **page_list;
253 drm_dma_handle_t *handle;
254 struct drm_i915_gem_object *cur_obj;
257 struct opregion_header;
258 struct opregion_acpi;
259 struct opregion_swsci;
260 struct opregion_asle;
262 struct intel_opregion {
263 struct opregion_header __iomem *header;
264 struct opregion_acpi __iomem *acpi;
265 struct opregion_swsci __iomem *swsci;
266 u32 swsci_gbda_sub_functions;
267 u32 swsci_sbcb_sub_functions;
268 struct opregion_asle __iomem *asle;
270 u32 __iomem *lid_state;
271 struct work_struct asle_work;
273 #define OPREGION_SIZE (8*1024)
275 struct intel_overlay;
276 struct intel_overlay_error_state;
278 struct drm_i915_master_private {
279 drm_local_map_t *sarea;
280 struct _drm_i915_sarea *sarea_priv;
282 #define I915_FENCE_REG_NONE -1
283 #define I915_MAX_NUM_FENCES 32
284 /* 32 fences + sign bit for FENCE_REG_NONE */
285 #define I915_MAX_NUM_FENCE_BITS 6
287 struct drm_i915_fence_reg {
288 struct list_head lru_list;
289 struct drm_i915_gem_object *obj;
293 struct sdvo_device_mapping {
302 struct intel_display_error_state;
304 struct drm_i915_error_state {
312 /* Generic register state */
319 u32 error; /* gen6+ */
320 u32 err_int; /* gen7 */
326 u32 extra_instdone[I915_NUM_INSTDONE_REG];
327 u32 pipestat[I915_MAX_PIPES];
328 u64 fence[I915_MAX_NUM_FENCES];
329 struct intel_overlay_error_state *overlay;
330 struct intel_display_error_state *display;
332 struct drm_i915_error_ring {
334 /* Software tracked state */
337 enum intel_ring_hangcheck_action hangcheck_action;
340 /* our own tracking of ring head and tail */
344 u32 semaphore_seqno[I915_NUM_RINGS - 1];
362 u32 rc_psmi; /* sleep state */
363 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
365 struct drm_i915_error_object {
369 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
371 struct drm_i915_error_request {
386 char comm[TASK_COMM_LEN];
387 } ring[I915_NUM_RINGS];
388 struct drm_i915_error_buffer {
395 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
402 } **active_bo, **pinned_bo;
404 u32 *active_bo_count, *pinned_bo_count;
407 struct intel_connector;
408 struct intel_crtc_config;
409 struct intel_plane_config;
414 struct drm_i915_display_funcs {
415 bool (*fbc_enabled)(struct drm_device *dev);
416 void (*enable_fbc)(struct drm_crtc *crtc);
417 void (*disable_fbc)(struct drm_device *dev);
418 int (*get_display_clock_speed)(struct drm_device *dev);
419 int (*get_fifo_size)(struct drm_device *dev, int plane);
421 * find_dpll() - Find the best values for the PLL
422 * @limit: limits for the PLL
423 * @crtc: current CRTC
424 * @target: target frequency in kHz
425 * @refclk: reference clock frequency in kHz
426 * @match_clock: if provided, @best_clock P divider must
427 * match the P divider from @match_clock
428 * used for LVDS downclocking
429 * @best_clock: best PLL values found
431 * Returns true on success, false on failure.
433 bool (*find_dpll)(const struct intel_limit *limit,
434 struct drm_crtc *crtc,
435 int target, int refclk,
436 struct dpll *match_clock,
437 struct dpll *best_clock);
438 void (*update_wm)(struct drm_crtc *crtc);
439 void (*update_sprite_wm)(struct drm_plane *plane,
440 struct drm_crtc *crtc,
441 uint32_t sprite_width, int pixel_size,
442 bool enable, bool scaled);
443 void (*modeset_global_resources)(struct drm_device *dev);
444 /* Returns the active state of the crtc, and if the crtc is active,
445 * fills out the pipe-config with the hw state. */
446 bool (*get_pipe_config)(struct intel_crtc *,
447 struct intel_crtc_config *);
448 void (*get_plane_config)(struct intel_crtc *,
449 struct intel_plane_config *);
450 int (*crtc_mode_set)(struct drm_crtc *crtc,
452 struct drm_framebuffer *old_fb);
453 void (*crtc_enable)(struct drm_crtc *crtc);
454 void (*crtc_disable)(struct drm_crtc *crtc);
455 void (*off)(struct drm_crtc *crtc);
456 void (*write_eld)(struct drm_connector *connector,
457 struct drm_crtc *crtc,
458 struct drm_display_mode *mode);
459 void (*fdi_link_train)(struct drm_crtc *crtc);
460 void (*init_clock_gating)(struct drm_device *dev);
461 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
462 struct drm_framebuffer *fb,
463 struct drm_i915_gem_object *obj,
465 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
467 void (*hpd_irq_setup)(struct drm_device *dev);
468 /* clock updates for mode set */
470 /* render clock increase/decrease */
471 /* display clock increase/decrease */
472 /* pll clock increase/decrease */
474 int (*setup_backlight)(struct intel_connector *connector);
475 uint32_t (*get_backlight)(struct intel_connector *connector);
476 void (*set_backlight)(struct intel_connector *connector,
478 void (*disable_backlight)(struct intel_connector *connector);
479 void (*enable_backlight)(struct intel_connector *connector);
482 struct intel_uncore_funcs {
483 void (*force_wake_get)(struct drm_i915_private *dev_priv,
485 void (*force_wake_put)(struct drm_i915_private *dev_priv,
488 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
489 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
490 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
493 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
494 uint8_t val, bool trace);
495 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
496 uint16_t val, bool trace);
497 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
498 uint32_t val, bool trace);
499 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
500 uint64_t val, bool trace);
503 struct intel_uncore {
504 spinlock_t lock; /** lock is also taken in irq contexts. */
506 struct intel_uncore_funcs funcs;
509 unsigned forcewake_count;
511 unsigned fw_rendercount;
512 unsigned fw_mediacount;
514 struct timer_list force_wake_timer;
517 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
518 func(is_mobile) sep \
521 func(is_i945gm) sep \
523 func(need_gfx_hws) sep \
525 func(is_pineview) sep \
526 func(is_broadwater) sep \
527 func(is_crestline) sep \
528 func(is_ivybridge) sep \
529 func(is_valleyview) sep \
530 func(is_haswell) sep \
531 func(is_preliminary) sep \
533 func(has_pipe_cxsr) sep \
534 func(has_hotplug) sep \
535 func(cursor_needs_physical) sep \
536 func(has_overlay) sep \
537 func(overlay_needs_physical) sep \
538 func(supports_tv) sep \
543 #define DEFINE_FLAG(name) u8 name:1
544 #define SEP_SEMICOLON ;
546 struct intel_device_info {
547 u32 display_mmio_offset;
549 u8 num_sprites[I915_MAX_PIPES];
551 u8 ring_mask; /* Rings supported by the HW */
552 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
553 /* Register offsets for the various display pipes and transcoders */
554 int pipe_offsets[I915_MAX_TRANSCODERS];
555 int trans_offsets[I915_MAX_TRANSCODERS];
556 int dpll_offsets[I915_MAX_PIPES];
557 int dpll_md_offsets[I915_MAX_PIPES];
558 int palette_offsets[I915_MAX_PIPES];
564 enum i915_cache_level {
566 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
567 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
568 caches, eg sampler/render caches, and the
569 large Last-Level-Cache. LLC is coherent with
570 the CPU, but L3 is only visible to the GPU. */
571 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
574 typedef uint32_t gen6_gtt_pte_t;
577 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
578 * VMA's presence cannot be guaranteed before binding, or after unbinding the
579 * object into/from the address space.
581 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
582 * will always be <= an objects lifetime. So object refcounting should cover us.
585 struct drm_mm_node node;
586 struct drm_i915_gem_object *obj;
587 struct i915_address_space *vm;
589 /** This object's place on the active/inactive lists */
590 struct list_head mm_list;
592 struct list_head vma_link; /* Link in the object's VMA list */
594 /** This vma's place in the batchbuffer or on the eviction list */
595 struct list_head exec_list;
598 * Used for performing relocations during execbuffer insertion.
600 struct hlist_node exec_node;
601 unsigned long exec_handle;
602 struct drm_i915_gem_exec_object2 *exec_entry;
605 * How many users have pinned this object in GTT space. The following
606 * users can each hold at most one reference: pwrite/pread, pin_ioctl
607 * (via user_pin_count), execbuffer (objects are not allowed multiple
608 * times for the same batchbuffer), and the framebuffer code. When
609 * switching/pageflipping, the framebuffer code has at most two buffers
612 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
613 * bits with absolutely no headroom. So use 4 bits. */
614 unsigned int pin_count:4;
615 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
617 /** Unmap an object from an address space. This usually consists of
618 * setting the valid PTE entries to a reserved scratch page. */
619 void (*unbind_vma)(struct i915_vma *vma);
620 /* Map an object into an address space with the given cache flags. */
621 #define GLOBAL_BIND (1<<0)
622 void (*bind_vma)(struct i915_vma *vma,
623 enum i915_cache_level cache_level,
627 struct i915_address_space {
629 struct drm_device *dev;
630 struct list_head global_link;
631 unsigned long start; /* Start offset always 0 for dri2 */
632 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
640 * List of objects currently involved in rendering.
642 * Includes buffers having the contents of their GPU caches
643 * flushed, not necessarily primitives. last_rendering_seqno
644 * represents when the rendering involved will be completed.
646 * A reference is held on the buffer while on this list.
648 struct list_head active_list;
651 * LRU list of objects which are not in the ringbuffer and
652 * are ready to unbind, but are still in the GTT.
654 * last_rendering_seqno is 0 while an object is in this list.
656 * A reference is not held on the buffer while on this list,
657 * as merely being GTT-bound shouldn't prevent its being
658 * freed, and we'll pull it off the list in the free path.
660 struct list_head inactive_list;
662 /* FIXME: Need a more generic return type */
663 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
664 enum i915_cache_level level,
665 bool valid); /* Create a valid PTE */
666 void (*clear_range)(struct i915_address_space *vm,
670 void (*insert_entries)(struct i915_address_space *vm,
673 enum i915_cache_level cache_level);
674 void (*cleanup)(struct i915_address_space *vm);
677 /* The Graphics Translation Table is the way in which GEN hardware translates a
678 * Graphics Virtual Address into a Physical Address. In addition to the normal
679 * collateral associated with any va->pa translations GEN hardware also has a
680 * portion of the GTT which can be mapped by the CPU and remain both coherent
681 * and correct (in cases like swizzling). That region is referred to as GMADR in
685 struct i915_address_space base;
686 size_t stolen_size; /* Total size of stolen memory */
688 unsigned long mappable_end; /* End offset that we can CPU map */
689 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
690 phys_addr_t mappable_base; /* PA of our GMADR */
692 /** "Graphics Stolen Memory" holds the global PTEs */
700 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
701 size_t *stolen, phys_addr_t *mappable_base,
702 unsigned long *mappable_end);
704 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
706 #define GEN8_LEGACY_PDPS 4
707 struct i915_hw_ppgtt {
708 struct i915_address_space base;
710 struct drm_mm_node node;
711 unsigned num_pd_entries;
712 unsigned num_pd_pages; /* gen8+ */
714 struct page **pt_pages;
715 struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
717 struct page *pd_pages;
720 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
723 dma_addr_t *pt_dma_addr;
724 dma_addr_t *gen8_pt_dma_addr[4];
727 int (*enable)(struct i915_hw_ppgtt *ppgtt);
728 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
729 struct intel_ring_buffer *ring,
731 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
734 struct i915_ctx_hang_stats {
735 /* This context had batch pending when hang was declared */
736 unsigned batch_pending;
738 /* This context had batch active when hang was declared */
739 unsigned batch_active;
741 /* Time when this context was last blamed for a GPU reset */
742 unsigned long guilty_ts;
744 /* This context is banned to submit more work */
748 /* This must match up with the value previously used for execbuf2.rsvd1. */
749 #define DEFAULT_CONTEXT_ID 0
750 struct i915_hw_context {
755 struct drm_i915_file_private *file_priv;
756 struct intel_ring_buffer *last_ring;
757 struct drm_i915_gem_object *obj;
758 struct i915_ctx_hang_stats hang_stats;
759 struct i915_address_space *vm;
761 struct list_head link;
770 struct drm_mm_node *compressed_fb;
771 struct drm_mm_node *compressed_llb;
773 struct intel_fbc_work {
774 struct delayed_work work;
775 struct drm_crtc *crtc;
776 struct drm_framebuffer *fb;
780 FBC_OK, /* FBC is enabled */
781 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
782 FBC_NO_OUTPUT, /* no outputs enabled to compress */
783 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
784 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
785 FBC_MODE_TOO_LARGE, /* mode too large for compression */
786 FBC_BAD_PLANE, /* fbc not supported on plane */
787 FBC_NOT_TILED, /* buffer not tiled */
788 FBC_MULTIPLE_PIPES, /* more than one pipe active */
790 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
800 PCH_NONE = 0, /* No PCH present */
801 PCH_IBX, /* Ibexpeak PCH */
802 PCH_CPT, /* Cougarpoint PCH */
803 PCH_LPT, /* Lynxpoint PCH */
807 enum intel_sbi_destination {
812 #define QUIRK_PIPEA_FORCE (1<<0)
813 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
814 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
817 struct intel_fbc_work;
820 struct i2c_adapter adapter;
824 struct i2c_algo_bit_data bit_algo;
825 struct drm_i915_private *dev_priv;
828 struct i915_suspend_saved_registers {
849 u32 saveTRANS_HTOTAL_A;
850 u32 saveTRANS_HBLANK_A;
851 u32 saveTRANS_HSYNC_A;
852 u32 saveTRANS_VTOTAL_A;
853 u32 saveTRANS_VBLANK_A;
854 u32 saveTRANS_VSYNC_A;
862 u32 savePFIT_PGM_RATIOS;
863 u32 saveBLC_HIST_CTL;
865 u32 saveBLC_PWM_CTL2;
866 u32 saveBLC_HIST_CTL_B;
867 u32 saveBLC_CPU_PWM_CTL;
868 u32 saveBLC_CPU_PWM_CTL2;
881 u32 saveTRANS_HTOTAL_B;
882 u32 saveTRANS_HBLANK_B;
883 u32 saveTRANS_HSYNC_B;
884 u32 saveTRANS_VTOTAL_B;
885 u32 saveTRANS_VBLANK_B;
886 u32 saveTRANS_VSYNC_B;
900 u32 savePP_ON_DELAYS;
901 u32 savePP_OFF_DELAYS;
909 u32 savePFIT_CONTROL;
910 u32 save_palette_a[256];
911 u32 save_palette_b[256];
922 u32 saveCACHE_MODE_0;
923 u32 saveMI_ARB_STATE;
934 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
945 u32 savePIPEA_GMCH_DATA_M;
946 u32 savePIPEB_GMCH_DATA_M;
947 u32 savePIPEA_GMCH_DATA_N;
948 u32 savePIPEB_GMCH_DATA_N;
949 u32 savePIPEA_DP_LINK_M;
950 u32 savePIPEB_DP_LINK_M;
951 u32 savePIPEA_DP_LINK_N;
952 u32 savePIPEB_DP_LINK_N;
963 u32 savePCH_DREF_CONTROL;
964 u32 saveDISP_ARB_CTL;
965 u32 savePIPEA_DATA_M1;
966 u32 savePIPEA_DATA_N1;
967 u32 savePIPEA_LINK_M1;
968 u32 savePIPEA_LINK_N1;
969 u32 savePIPEB_DATA_M1;
970 u32 savePIPEB_DATA_N1;
971 u32 savePIPEB_LINK_M1;
972 u32 savePIPEB_LINK_N1;
973 u32 saveMCHBAR_RENDER_STANDBY;
974 u32 savePCH_PORT_HOTPLUG;
977 struct intel_gen6_power_mgmt {
978 /* work and pm_iir are protected by dev_priv->irq_lock */
979 struct work_struct work;
994 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
997 struct delayed_work delayed_resume_work;
1000 * Protects RPS/RC6 register access and PCU communication.
1001 * Must be taken after struct_mutex if nested.
1003 struct mutex hw_lock;
1006 /* defined intel_pm.c */
1007 extern spinlock_t mchdev_lock;
1009 struct intel_ilk_power_mgmt {
1017 unsigned long last_time1;
1018 unsigned long chipset_power;
1020 struct timespec last_time2;
1021 unsigned long gfx_power;
1027 struct drm_i915_gem_object *pwrctx;
1028 struct drm_i915_gem_object *renderctx;
1031 struct drm_i915_private;
1032 struct i915_power_well;
1034 struct i915_power_well_ops {
1036 * Synchronize the well's hw state to match the current sw state, for
1037 * example enable/disable it based on the current refcount. Called
1038 * during driver init and resume time, possibly after first calling
1039 * the enable/disable handlers.
1041 void (*sync_hw)(struct drm_i915_private *dev_priv,
1042 struct i915_power_well *power_well);
1044 * Enable the well and resources that depend on it (for example
1045 * interrupts located on the well). Called after the 0->1 refcount
1048 void (*enable)(struct drm_i915_private *dev_priv,
1049 struct i915_power_well *power_well);
1051 * Disable the well and resources that depend on it. Called after
1052 * the 1->0 refcount transition.
1054 void (*disable)(struct drm_i915_private *dev_priv,
1055 struct i915_power_well *power_well);
1056 /* Returns the hw enabled state. */
1057 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1058 struct i915_power_well *power_well);
1061 /* Power well structure for haswell */
1062 struct i915_power_well {
1065 /* power well enable/disable usage count */
1067 unsigned long domains;
1069 const struct i915_power_well_ops *ops;
1072 struct i915_power_domains {
1074 * Power wells needed for initialization at driver init and suspend
1075 * time are on. They are kept on until after the first modeset.
1078 int power_well_count;
1081 int domain_use_count[POWER_DOMAIN_NUM];
1082 struct i915_power_well *power_wells;
1085 struct i915_dri1_state {
1086 unsigned allow_batchbuffer : 1;
1087 u32 __iomem *gfx_hws_cpu_addr;
1098 struct i915_ums_state {
1100 * Flag if the X Server, and thus DRM, is not currently in
1101 * control of the device.
1103 * This is set between LeaveVT and EnterVT. It needs to be
1104 * replaced with a semaphore. It also needs to be
1105 * transitioned away from for kernel modesetting.
1110 #define MAX_L3_SLICES 2
1111 struct intel_l3_parity {
1112 u32 *remap_info[MAX_L3_SLICES];
1113 struct work_struct error_work;
1117 struct i915_gem_mm {
1118 /** Memory allocator for GTT stolen memory */
1119 struct drm_mm stolen;
1120 /** List of all objects in gtt_space. Used to restore gtt
1121 * mappings on resume */
1122 struct list_head bound_list;
1124 * List of objects which are not bound to the GTT (thus
1125 * are idle and not used by the GPU) but still have
1126 * (presumably uncached) pages still attached.
1128 struct list_head unbound_list;
1130 /** Usable portion of the GTT for GEM */
1131 unsigned long stolen_base; /* limited to low memory (32-bit) */
1133 /** PPGTT used for aliasing the PPGTT with the GTT */
1134 struct i915_hw_ppgtt *aliasing_ppgtt;
1136 struct shrinker inactive_shrinker;
1137 bool shrinker_no_lock_stealing;
1139 /** LRU list of objects with fence regs on them. */
1140 struct list_head fence_list;
1143 * We leave the user IRQ off as much as possible,
1144 * but this means that requests will finish and never
1145 * be retired once the system goes idle. Set a timer to
1146 * fire periodically while the ring is running. When it
1147 * fires, go retire requests.
1149 struct delayed_work retire_work;
1152 * When we detect an idle GPU, we want to turn on
1153 * powersaving features. So once we see that there
1154 * are no more requests outstanding and no more
1155 * arrive within a small period of time, we fire
1156 * off the idle_work.
1158 struct delayed_work idle_work;
1161 * Are we in a non-interruptible section of code like
1167 * Is the GPU currently considered idle, or busy executing userspace
1168 * requests? Whilst idle, we attempt to power down the hardware and
1169 * display clocks. In order to reduce the effect on performance, there
1170 * is a slight delay before we do so.
1174 /** Bit 6 swizzling required for X tiling */
1175 uint32_t bit_6_swizzle_x;
1176 /** Bit 6 swizzling required for Y tiling */
1177 uint32_t bit_6_swizzle_y;
1179 /* storage for physical objects */
1180 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1182 /* accounting, useful for userland debugging */
1183 spinlock_t object_stat_lock;
1184 size_t object_memory;
1188 struct drm_i915_error_state_buf {
1197 struct i915_error_state_file_priv {
1198 struct drm_device *dev;
1199 struct drm_i915_error_state *error;
1202 struct i915_gpu_error {
1203 /* For hangcheck timer */
1204 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1205 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1206 /* Hang gpu twice in this window and your context gets banned */
1207 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1209 struct timer_list hangcheck_timer;
1211 /* For reset and error_state handling. */
1213 /* Protected by the above dev->gpu_error.lock. */
1214 struct drm_i915_error_state *first_error;
1215 struct work_struct work;
1218 unsigned long missed_irq_rings;
1221 * State variable controlling the reset flow and count
1223 * This is a counter which gets incremented when reset is triggered,
1224 * and again when reset has been handled. So odd values (lowest bit set)
1225 * means that reset is in progress and even values that
1226 * (reset_counter >> 1):th reset was successfully completed.
1228 * If reset is not completed succesfully, the I915_WEDGE bit is
1229 * set meaning that hardware is terminally sour and there is no
1230 * recovery. All waiters on the reset_queue will be woken when
1233 * This counter is used by the wait_seqno code to notice that reset
1234 * event happened and it needs to restart the entire ioctl (since most
1235 * likely the seqno it waited for won't ever signal anytime soon).
1237 * This is important for lock-free wait paths, where no contended lock
1238 * naturally enforces the correct ordering between the bail-out of the
1239 * waiter and the gpu reset work code.
1241 atomic_t reset_counter;
1243 #define I915_RESET_IN_PROGRESS_FLAG 1
1244 #define I915_WEDGED (1 << 31)
1247 * Waitqueue to signal when the reset has completed. Used by clients
1248 * that wait for dev_priv->mm.wedged to settle.
1250 wait_queue_head_t reset_queue;
1252 /* For gpu hang simulation. */
1253 unsigned int stop_rings;
1255 /* For missed irq/seqno simulation. */
1256 unsigned int test_irq_rings;
1259 enum modeset_restore {
1260 MODESET_ON_LID_OPEN,
1265 struct ddi_vbt_port_info {
1266 uint8_t hdmi_level_shift;
1268 uint8_t supports_dvi:1;
1269 uint8_t supports_hdmi:1;
1270 uint8_t supports_dp:1;
1273 struct intel_vbt_data {
1274 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1275 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1278 unsigned int int_tv_support:1;
1279 unsigned int lvds_dither:1;
1280 unsigned int lvds_vbt:1;
1281 unsigned int int_crt_support:1;
1282 unsigned int lvds_use_ssc:1;
1283 unsigned int display_clock_mode:1;
1284 unsigned int fdi_rx_polarity_inverted:1;
1286 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1291 int edp_preemphasis;
1293 bool edp_initialized;
1296 struct edp_power_seq edp_pps;
1300 bool active_low_pwm;
1311 union child_device_config *child_dev;
1313 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1316 enum intel_ddb_partitioning {
1318 INTEL_DDB_PART_5_6, /* IVB+ */
1321 struct intel_wm_level {
1329 struct ilk_wm_values {
1330 uint32_t wm_pipe[3];
1332 uint32_t wm_lp_spr[3];
1333 uint32_t wm_linetime[3];
1335 enum intel_ddb_partitioning partitioning;
1339 * This struct tracks the state needed for the Package C8+ feature.
1341 * Package states C8 and deeper are really deep PC states that can only be
1342 * reached when all the devices on the system allow it, so even if the graphics
1343 * device allows PC8+, it doesn't mean the system will actually get to these
1346 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1347 * is disabled and the GPU is idle. When these conditions are met, we manually
1348 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1351 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1352 * the state of some registers, so when we come back from PC8+ we need to
1353 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1354 * need to take care of the registers kept by RC6.
1356 * The interrupt disabling is part of the requirements. We can only leave the
1357 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1358 * can lock the machine.
1360 * Ideally every piece of our code that needs PC8+ disabled would call
1361 * hsw_disable_package_c8, which would increment disable_count and prevent the
1362 * system from reaching PC8+. But we don't have a symmetric way to do this for
1363 * everything, so we have the requirements_met variable. When we switch
1364 * requirements_met to true we decrease disable_count, and increase it in the
1365 * opposite case. The requirements_met variable is true when all the CRTCs,
1366 * encoders and the power well are disabled.
1368 * In addition to everything, we only actually enable PC8+ if disable_count
1369 * stays at zero for at least some seconds. This is implemented with the
1370 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1371 * consecutive times when all screens are disabled and some background app
1372 * queries the state of our connectors, or we have some application constantly
1373 * waking up to use the GPU. Only after the enable_work function actually
1374 * enables PC8+ the "enable" variable will become true, which means that it can
1375 * be false even if disable_count is 0.
1377 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1378 * goes back to false exactly before we reenable the IRQs. We use this variable
1379 * to check if someone is trying to enable/disable IRQs while they're supposed
1380 * to be disabled. This shouldn't happen and we'll print some error messages in
1381 * case it happens, but if it actually happens we'll also update the variables
1382 * inside struct regsave so when we restore the IRQs they will contain the
1383 * latest expected values.
1385 * For more, read "Display Sequences for Package C8" on our documentation.
1387 struct i915_package_c8 {
1388 bool requirements_met;
1390 /* Only true after the delayed work task actually enables it. */
1394 struct delayed_work enable_work;
1401 uint32_t gen6_pmimr;
1405 struct i915_runtime_pm {
1409 enum intel_pipe_crc_source {
1410 INTEL_PIPE_CRC_SOURCE_NONE,
1411 INTEL_PIPE_CRC_SOURCE_PLANE1,
1412 INTEL_PIPE_CRC_SOURCE_PLANE2,
1413 INTEL_PIPE_CRC_SOURCE_PF,
1414 INTEL_PIPE_CRC_SOURCE_PIPE,
1415 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1416 INTEL_PIPE_CRC_SOURCE_TV,
1417 INTEL_PIPE_CRC_SOURCE_DP_B,
1418 INTEL_PIPE_CRC_SOURCE_DP_C,
1419 INTEL_PIPE_CRC_SOURCE_DP_D,
1420 INTEL_PIPE_CRC_SOURCE_AUTO,
1421 INTEL_PIPE_CRC_SOURCE_MAX,
1424 struct intel_pipe_crc_entry {
1429 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1430 struct intel_pipe_crc {
1432 bool opened; /* exclusive access to the result file */
1433 struct intel_pipe_crc_entry *entries;
1434 enum intel_pipe_crc_source source;
1436 wait_queue_head_t wq;
1439 typedef struct drm_i915_private {
1440 struct drm_device *dev;
1441 struct kmem_cache *slab;
1443 const struct intel_device_info info;
1445 int relative_constants_mode;
1449 struct intel_uncore uncore;
1451 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1454 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1455 * controller on different i2c buses. */
1456 struct mutex gmbus_mutex;
1459 * Base address of the gmbus and gpio block.
1461 uint32_t gpio_mmio_base;
1463 wait_queue_head_t gmbus_wait_queue;
1465 struct pci_dev *bridge_dev;
1466 struct intel_ring_buffer ring[I915_NUM_RINGS];
1467 uint32_t last_seqno, next_seqno;
1469 drm_dma_handle_t *status_page_dmah;
1470 struct resource mch_res;
1472 /* protects the irq masks */
1473 spinlock_t irq_lock;
1475 bool display_irqs_enabled;
1477 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1478 struct pm_qos_request pm_qos;
1480 /* DPIO indirect register protection */
1481 struct mutex dpio_lock;
1483 /** Cached value of IMR to avoid reads in updating the bitfield */
1486 u32 de_irq_mask[I915_MAX_PIPES];
1490 u32 pipestat_irq_mask[I915_MAX_PIPES];
1492 struct work_struct hotplug_work;
1493 bool enable_hotplug_processing;
1495 unsigned long hpd_last_jiffies;
1500 HPD_MARK_DISABLED = 2
1502 } hpd_stats[HPD_NUM_PINS];
1504 struct timer_list hotplug_reenable_timer;
1506 struct i915_fbc fbc;
1507 struct intel_opregion opregion;
1508 struct intel_vbt_data vbt;
1511 struct intel_overlay *overlay;
1513 /* backlight registers and fields in struct intel_panel */
1514 spinlock_t backlight_lock;
1517 bool no_aux_handshake;
1519 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1520 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1521 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1523 unsigned int fsb_freq, mem_freq, is_ddr3;
1526 * wq - Driver workqueue for GEM.
1528 * NOTE: Work items scheduled here are not allowed to grab any modeset
1529 * locks, for otherwise the flushing done in the pageflip code will
1530 * result in deadlocks.
1532 struct workqueue_struct *wq;
1534 /* Display functions */
1535 struct drm_i915_display_funcs display;
1537 /* PCH chipset type */
1538 enum intel_pch pch_type;
1539 unsigned short pch_id;
1541 unsigned long quirks;
1543 enum modeset_restore modeset_restore;
1544 struct mutex modeset_restore_lock;
1546 struct list_head vm_list; /* Global list of all address spaces */
1547 struct i915_gtt gtt; /* VMA representing the global address space */
1549 struct i915_gem_mm mm;
1551 /* Kernel Modesetting */
1553 struct sdvo_device_mapping sdvo_mappings[2];
1555 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1556 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1557 wait_queue_head_t pending_flip_queue;
1559 #ifdef CONFIG_DEBUG_FS
1560 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1563 int num_shared_dpll;
1564 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1565 struct intel_ddi_plls ddi_plls;
1566 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1568 /* Reclocking support */
1569 bool render_reclock_avail;
1570 bool lvds_downclock_avail;
1571 /* indicates the reduced downclock for LVDS*/
1575 bool mchbar_need_disable;
1577 struct intel_l3_parity l3_parity;
1579 /* Cannot be determined by PCIID. You must always read a register. */
1582 /* gen6+ rps state */
1583 struct intel_gen6_power_mgmt rps;
1585 /* ilk-only ips/rps state. Everything in here is protected by the global
1586 * mchdev_lock in intel_pm.c */
1587 struct intel_ilk_power_mgmt ips;
1589 struct i915_power_domains power_domains;
1591 struct i915_psr psr;
1593 struct i915_gpu_error gpu_error;
1595 struct drm_i915_gem_object *vlv_pctx;
1597 #ifdef CONFIG_DRM_I915_FBDEV
1598 /* list of fbdev register on this device */
1599 struct intel_fbdev *fbdev;
1603 * The console may be contended at resume, but we don't
1604 * want it to block on it.
1606 struct work_struct console_resume_work;
1608 struct drm_property *broadcast_rgb_property;
1609 struct drm_property *force_audio_property;
1611 uint32_t hw_context_size;
1612 struct list_head context_list;
1617 struct i915_suspend_saved_registers regfile;
1621 * Raw watermark latency values:
1622 * in 0.1us units for WM0,
1623 * in 0.5us units for WM1+.
1626 uint16_t pri_latency[5];
1628 uint16_t spr_latency[5];
1630 uint16_t cur_latency[5];
1632 /* current hardware state */
1633 struct ilk_wm_values hw;
1636 struct i915_package_c8 pc8;
1638 struct i915_runtime_pm pm;
1640 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1642 struct i915_dri1_state dri1;
1643 /* Old ums support infrastructure, same warning applies. */
1644 struct i915_ums_state ums;
1645 } drm_i915_private_t;
1647 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1649 return dev->dev_private;
1652 /* Iterate over initialised rings */
1653 #define for_each_ring(ring__, dev_priv__, i__) \
1654 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1655 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1657 enum hdmi_force_audio {
1658 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1659 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1660 HDMI_AUDIO_AUTO, /* trust EDID */
1661 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1664 #define I915_GTT_OFFSET_NONE ((u32)-1)
1666 struct drm_i915_gem_object_ops {
1667 /* Interface between the GEM object and its backing storage.
1668 * get_pages() is called once prior to the use of the associated set
1669 * of pages before to binding them into the GTT, and put_pages() is
1670 * called after we no longer need them. As we expect there to be
1671 * associated cost with migrating pages between the backing storage
1672 * and making them available for the GPU (e.g. clflush), we may hold
1673 * onto the pages after they are no longer referenced by the GPU
1674 * in case they may be used again shortly (for example migrating the
1675 * pages to a different memory domain within the GTT). put_pages()
1676 * will therefore most likely be called when the object itself is
1677 * being released or under memory pressure (where we attempt to
1678 * reap pages for the shrinker).
1680 int (*get_pages)(struct drm_i915_gem_object *);
1681 void (*put_pages)(struct drm_i915_gem_object *);
1684 struct drm_i915_gem_object {
1685 struct drm_gem_object base;
1687 const struct drm_i915_gem_object_ops *ops;
1689 /** List of VMAs backed by this object */
1690 struct list_head vma_list;
1692 /** Stolen memory for this object, instead of being backed by shmem. */
1693 struct drm_mm_node *stolen;
1694 struct list_head global_list;
1696 struct list_head ring_list;
1697 /** Used in execbuf to temporarily hold a ref */
1698 struct list_head obj_exec_link;
1701 * This is set if the object is on the active lists (has pending
1702 * rendering and so a non-zero seqno), and is not set if it i s on
1703 * inactive (ready to be unbound) list.
1705 unsigned int active:1;
1708 * This is set if the object has been written to since last bound
1711 unsigned int dirty:1;
1714 * Fence register bits (if any) for this object. Will be set
1715 * as needed when mapped into the GTT.
1716 * Protected by dev->struct_mutex.
1718 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1721 * Advice: are the backing pages purgeable?
1723 unsigned int madv:2;
1726 * Current tiling mode for the object.
1728 unsigned int tiling_mode:2;
1730 * Whether the tiling parameters for the currently associated fence
1731 * register have changed. Note that for the purposes of tracking
1732 * tiling changes we also treat the unfenced register, the register
1733 * slot that the object occupies whilst it executes a fenced
1734 * command (such as BLT on gen2/3), as a "fence".
1736 unsigned int fence_dirty:1;
1739 * Is the object at the current location in the gtt mappable and
1740 * fenceable? Used to avoid costly recalculations.
1742 unsigned int map_and_fenceable:1;
1745 * Whether the current gtt mapping needs to be mappable (and isn't just
1746 * mappable by accident). Track pin and fault separate for a more
1747 * accurate mappable working set.
1749 unsigned int fault_mappable:1;
1750 unsigned int pin_mappable:1;
1751 unsigned int pin_display:1;
1754 * Is the GPU currently using a fence to access this buffer,
1756 unsigned int pending_fenced_gpu_access:1;
1757 unsigned int fenced_gpu_access:1;
1759 unsigned int cache_level:3;
1761 unsigned int has_aliasing_ppgtt_mapping:1;
1762 unsigned int has_global_gtt_mapping:1;
1763 unsigned int has_dma_mapping:1;
1765 struct sg_table *pages;
1766 int pages_pin_count;
1768 /* prime dma-buf support */
1769 void *dma_buf_vmapping;
1772 struct intel_ring_buffer *ring;
1774 /** Breadcrumb of last rendering to the buffer. */
1775 uint32_t last_read_seqno;
1776 uint32_t last_write_seqno;
1777 /** Breadcrumb of last fenced GPU access to the buffer. */
1778 uint32_t last_fenced_seqno;
1780 /** Current tiling stride for the object, if it's tiled. */
1783 /** References from framebuffers, locks out tiling changes. */
1784 unsigned long framebuffer_references;
1786 /** Record of address bit 17 of each page at last unbind. */
1787 unsigned long *bit_17;
1789 /** User space pin count and filp owning the pin */
1790 unsigned long user_pin_count;
1791 struct drm_file *pin_filp;
1793 /** for phy allocated objects */
1794 struct drm_i915_gem_phys_object *phys_obj;
1797 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1800 * Request queue structure.
1802 * The request queue allows us to note sequence numbers that have been emitted
1803 * and may be associated with active buffers to be retired.
1805 * By keeping this list, we can avoid having to do questionable
1806 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1807 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1809 struct drm_i915_gem_request {
1810 /** On Which ring this request was generated */
1811 struct intel_ring_buffer *ring;
1813 /** GEM sequence number associated with this request. */
1816 /** Position in the ringbuffer of the start of the request */
1819 /** Position in the ringbuffer of the end of the request */
1822 /** Context related to this request */
1823 struct i915_hw_context *ctx;
1825 /** Batch buffer related to this request if any */
1826 struct drm_i915_gem_object *batch_obj;
1828 /** Time at which this request was emitted, in jiffies. */
1829 unsigned long emitted_jiffies;
1831 /** global list entry for this request */
1832 struct list_head list;
1834 struct drm_i915_file_private *file_priv;
1835 /** file_priv list entry for this request */
1836 struct list_head client_list;
1839 struct drm_i915_file_private {
1840 struct drm_i915_private *dev_priv;
1841 struct drm_file *file;
1845 struct list_head request_list;
1846 struct delayed_work idle_work;
1848 struct idr context_idr;
1850 struct i915_hw_context *private_default_ctx;
1851 atomic_t rps_wait_boost;
1855 * A command that requires special handling by the command parser.
1857 struct drm_i915_cmd_descriptor {
1859 * Flags describing how the command parser processes the command.
1861 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1862 * a length mask if not set
1863 * CMD_DESC_SKIP: The command is allowed but does not follow the
1864 * standard length encoding for the opcode range in
1866 * CMD_DESC_REJECT: The command is never allowed
1867 * CMD_DESC_REGISTER: The command should be checked against the
1868 * register whitelist for the appropriate ring
1869 * CMD_DESC_MASTER: The command is allowed if the submitting process
1873 #define CMD_DESC_FIXED (1<<0)
1874 #define CMD_DESC_SKIP (1<<1)
1875 #define CMD_DESC_REJECT (1<<2)
1876 #define CMD_DESC_REGISTER (1<<3)
1877 #define CMD_DESC_BITMASK (1<<4)
1878 #define CMD_DESC_MASTER (1<<5)
1881 * The command's unique identification bits and the bitmask to get them.
1882 * This isn't strictly the opcode field as defined in the spec and may
1883 * also include type, subtype, and/or subop fields.
1891 * The command's length. The command is either fixed length (i.e. does
1892 * not include a length field) or has a length field mask. The flag
1893 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1894 * a length mask. All command entries in a command table must include
1895 * length information.
1903 * Describes where to find a register address in the command to check
1904 * against the ring's register whitelist. Only valid if flags has the
1905 * CMD_DESC_REGISTER bit set.
1912 #define MAX_CMD_DESC_BITMASKS 3
1914 * Describes command checks where a particular dword is masked and
1915 * compared against an expected value. If the command does not match
1916 * the expected value, the parser rejects it. Only valid if flags has
1917 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1924 } bits[MAX_CMD_DESC_BITMASKS];
1928 * A table of commands requiring special handling by the command parser.
1930 * Each ring has an array of tables. Each table consists of an array of command
1931 * descriptors, which must be sorted with command opcodes in ascending order.
1933 struct drm_i915_cmd_table {
1934 const struct drm_i915_cmd_descriptor *table;
1938 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1940 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1941 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1942 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1943 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1944 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1945 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1946 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1947 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1948 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1949 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1950 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1951 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1952 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1953 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1954 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1955 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1956 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1957 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1958 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1959 (dev)->pdev->device == 0x0152 || \
1960 (dev)->pdev->device == 0x015a)
1961 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1962 (dev)->pdev->device == 0x0106 || \
1963 (dev)->pdev->device == 0x010A)
1964 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1965 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1966 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1967 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1968 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1969 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1970 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1971 (((dev)->pdev->device & 0xf) == 0x2 || \
1972 ((dev)->pdev->device & 0xf) == 0x6 || \
1973 ((dev)->pdev->device & 0xf) == 0xe))
1974 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1975 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1976 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1977 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1978 ((dev)->pdev->device & 0x00F0) == 0x0020)
1979 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1982 * The genX designation typically refers to the render engine, so render
1983 * capability related checks should use IS_GEN, while display and other checks
1984 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1987 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1988 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1989 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1990 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1991 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1992 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1993 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1995 #define RENDER_RING (1<<RCS)
1996 #define BSD_RING (1<<VCS)
1997 #define BLT_RING (1<<BCS)
1998 #define VEBOX_RING (1<<VECS)
1999 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2000 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2001 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2002 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2003 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
2004 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2006 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2007 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
2008 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
2009 && !IS_BROADWELL(dev))
2010 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
2011 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
2013 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2014 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2016 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2017 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2019 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2020 * even when in MSI mode. This results in spurious interrupt warnings if the
2021 * legacy irq no. is shared with another device. The kernel then disables that
2022 * interrupt source and so prevents the other device from working properly.
2024 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2025 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2027 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2028 * rows, which changed the alignment requirements and fence programming.
2030 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2032 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2033 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2034 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2035 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2036 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2038 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2039 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2040 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2042 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2044 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2045 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2046 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2047 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
2048 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
2050 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2051 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2052 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2053 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2054 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2055 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2057 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2058 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2059 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2060 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2061 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2062 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2064 /* DPF == dynamic parity feature */
2065 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2066 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2068 #define GT_FREQUENCY_MULTIPLIER 50
2070 #include "i915_trace.h"
2072 extern const struct drm_ioctl_desc i915_ioctls[];
2073 extern int i915_max_ioctl;
2075 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2076 extern int i915_resume(struct drm_device *dev);
2077 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2078 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2081 struct i915_params {
2083 int panel_ignore_lid;
2084 unsigned int powersave;
2086 unsigned int lvds_downclock;
2087 int lvds_channel_mode;
2089 int vbt_sdvo_panel_type;
2094 unsigned int preliminary_hw_support;
2095 int disable_power_well;
2099 int invert_brightness;
2100 int enable_cmd_parser;
2101 /* leave bools at the end to not create holes */
2102 bool enable_hangcheck;
2104 bool prefault_disable;
2106 bool disable_display;
2108 extern struct i915_params i915 __read_mostly;
2111 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2112 extern void i915_kernel_lost_context(struct drm_device * dev);
2113 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2114 extern int i915_driver_unload(struct drm_device *);
2115 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2116 extern void i915_driver_lastclose(struct drm_device * dev);
2117 extern void i915_driver_preclose(struct drm_device *dev,
2118 struct drm_file *file_priv);
2119 extern void i915_driver_postclose(struct drm_device *dev,
2120 struct drm_file *file_priv);
2121 extern int i915_driver_device_is_agp(struct drm_device * dev);
2122 #ifdef CONFIG_COMPAT
2123 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2126 extern int i915_emit_box(struct drm_device *dev,
2127 struct drm_clip_rect *box,
2129 extern int intel_gpu_reset(struct drm_device *dev);
2130 extern int i915_reset(struct drm_device *dev);
2131 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2132 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2133 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2134 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2136 extern void intel_console_resume(struct work_struct *work);
2139 void i915_queue_hangcheck(struct drm_device *dev);
2141 void i915_handle_error(struct drm_device *dev, bool wedged,
2142 const char *fmt, ...);
2144 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2146 extern void intel_irq_init(struct drm_device *dev);
2147 extern void intel_hpd_init(struct drm_device *dev);
2149 extern void intel_uncore_sanitize(struct drm_device *dev);
2150 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2151 extern void intel_uncore_init(struct drm_device *dev);
2152 extern void intel_uncore_check_errors(struct drm_device *dev);
2153 extern void intel_uncore_fini(struct drm_device *dev);
2156 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2160 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2163 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2164 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2167 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *file_priv);
2169 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *file_priv);
2171 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *file_priv);
2173 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *file_priv);
2175 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *file_priv);
2177 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *file_priv);
2179 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2180 struct drm_file *file_priv);
2181 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2182 struct drm_file *file_priv);
2183 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2184 struct drm_file *file_priv);
2185 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2186 struct drm_file *file_priv);
2187 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2188 struct drm_file *file_priv);
2189 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2190 struct drm_file *file_priv);
2191 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2192 struct drm_file *file_priv);
2193 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *file);
2195 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2196 struct drm_file *file);
2197 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2198 struct drm_file *file_priv);
2199 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2200 struct drm_file *file_priv);
2201 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2202 struct drm_file *file_priv);
2203 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2204 struct drm_file *file_priv);
2205 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2206 struct drm_file *file_priv);
2207 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2208 struct drm_file *file_priv);
2209 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2210 struct drm_file *file_priv);
2211 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *file_priv);
2213 void i915_gem_load(struct drm_device *dev);
2214 void *i915_gem_object_alloc(struct drm_device *dev);
2215 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2216 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2217 const struct drm_i915_gem_object_ops *ops);
2218 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2220 void i915_init_vm(struct drm_i915_private *dev_priv,
2221 struct i915_address_space *vm);
2222 void i915_gem_free_object(struct drm_gem_object *obj);
2223 void i915_gem_vma_destroy(struct i915_vma *vma);
2225 #define PIN_MAPPABLE 0x1
2226 #define PIN_NONBLOCK 0x2
2227 #define PIN_GLOBAL 0x4
2228 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2229 struct i915_address_space *vm,
2232 int __must_check i915_vma_unbind(struct i915_vma *vma);
2233 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2234 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2235 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2236 void i915_gem_lastclose(struct drm_device *dev);
2238 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2239 int *needs_clflush);
2241 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2242 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2244 struct sg_page_iter sg_iter;
2246 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2247 return sg_page_iter_page(&sg_iter);
2251 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2253 BUG_ON(obj->pages == NULL);
2254 obj->pages_pin_count++;
2256 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2258 BUG_ON(obj->pages_pin_count == 0);
2259 obj->pages_pin_count--;
2262 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2263 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2264 struct intel_ring_buffer *to);
2265 void i915_vma_move_to_active(struct i915_vma *vma,
2266 struct intel_ring_buffer *ring);
2267 int i915_gem_dumb_create(struct drm_file *file_priv,
2268 struct drm_device *dev,
2269 struct drm_mode_create_dumb *args);
2270 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2271 uint32_t handle, uint64_t *offset);
2273 * Returns true if seq1 is later than seq2.
2276 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2278 return (int32_t)(seq1 - seq2) >= 0;
2281 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2282 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2283 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2284 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2287 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2289 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2290 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2291 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2298 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2300 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2301 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2302 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2303 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2307 struct drm_i915_gem_request *
2308 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2310 bool i915_gem_retire_requests(struct drm_device *dev);
2311 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2312 bool interruptible);
2313 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2315 return unlikely(atomic_read(&error->reset_counter)
2316 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2319 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2321 return atomic_read(&error->reset_counter) & I915_WEDGED;
2324 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2326 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2329 void i915_gem_reset(struct drm_device *dev);
2330 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2331 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2332 int __must_check i915_gem_init(struct drm_device *dev);
2333 int __must_check i915_gem_init_hw(struct drm_device *dev);
2334 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2335 void i915_gem_init_swizzling(struct drm_device *dev);
2336 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2337 int __must_check i915_gpu_idle(struct drm_device *dev);
2338 int __must_check i915_gem_suspend(struct drm_device *dev);
2339 int __i915_add_request(struct intel_ring_buffer *ring,
2340 struct drm_file *file,
2341 struct drm_i915_gem_object *batch_obj,
2343 #define i915_add_request(ring, seqno) \
2344 __i915_add_request(ring, NULL, NULL, seqno)
2345 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2347 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2349 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2352 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2354 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2356 struct intel_ring_buffer *pipelined);
2357 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2358 int i915_gem_attach_phys_object(struct drm_device *dev,
2359 struct drm_i915_gem_object *obj,
2362 void i915_gem_detach_phys_object(struct drm_device *dev,
2363 struct drm_i915_gem_object *obj);
2364 void i915_gem_free_all_phys_object(struct drm_device *dev);
2365 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2366 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2369 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2371 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2372 int tiling_mode, bool fenced);
2374 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2375 enum i915_cache_level cache_level);
2377 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2378 struct dma_buf *dma_buf);
2380 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2381 struct drm_gem_object *gem_obj, int flags);
2383 void i915_gem_restore_fences(struct drm_device *dev);
2385 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2386 struct i915_address_space *vm);
2387 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2388 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2389 struct i915_address_space *vm);
2390 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2391 struct i915_address_space *vm);
2392 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2393 struct i915_address_space *vm);
2395 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2396 struct i915_address_space *vm);
2398 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2399 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2400 struct i915_vma *vma;
2401 list_for_each_entry(vma, &obj->vma_list, vma_link)
2402 if (vma->pin_count > 0)
2407 /* Some GGTT VM helpers */
2408 #define obj_to_ggtt(obj) \
2409 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2410 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2412 struct i915_address_space *ggtt =
2413 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2417 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2419 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2422 static inline unsigned long
2423 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2425 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2428 static inline unsigned long
2429 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2431 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2434 static inline int __must_check
2435 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2439 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2443 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2445 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2448 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2450 /* i915_gem_context.c */
2451 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2452 int __must_check i915_gem_context_init(struct drm_device *dev);
2453 void i915_gem_context_fini(struct drm_device *dev);
2454 void i915_gem_context_reset(struct drm_device *dev);
2455 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2456 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2457 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2458 int i915_switch_context(struct intel_ring_buffer *ring,
2459 struct drm_file *file, struct i915_hw_context *to);
2460 struct i915_hw_context *
2461 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2462 void i915_gem_context_free(struct kref *ctx_ref);
2463 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2465 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2466 kref_get(&ctx->ref);
2469 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2471 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2472 kref_put(&ctx->ref, i915_gem_context_free);
2475 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2477 return c->id == DEFAULT_CONTEXT_ID;
2480 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2481 struct drm_file *file);
2482 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2483 struct drm_file *file);
2485 /* i915_gem_evict.c */
2486 int __must_check i915_gem_evict_something(struct drm_device *dev,
2487 struct i915_address_space *vm,
2490 unsigned cache_level,
2492 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2493 int i915_gem_evict_everything(struct drm_device *dev);
2495 /* i915_gem_gtt.c */
2496 void i915_check_and_clear_faults(struct drm_device *dev);
2497 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2498 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2499 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2500 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2501 void i915_gem_init_global_gtt(struct drm_device *dev);
2502 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2503 unsigned long mappable_end, unsigned long end);
2504 int i915_gem_gtt_init(struct drm_device *dev);
2505 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2507 if (INTEL_INFO(dev)->gen < 6)
2508 intel_gtt_chipset_flush();
2510 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2511 bool intel_enable_ppgtt(struct drm_device *dev, bool full);
2513 /* i915_gem_stolen.c */
2514 int i915_gem_init_stolen(struct drm_device *dev);
2515 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2516 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2517 void i915_gem_cleanup_stolen(struct drm_device *dev);
2518 struct drm_i915_gem_object *
2519 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2520 struct drm_i915_gem_object *
2521 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2525 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2527 /* i915_gem_tiling.c */
2528 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2530 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2532 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2533 obj->tiling_mode != I915_TILING_NONE;
2536 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2537 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2538 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2540 /* i915_gem_debug.c */
2542 int i915_verify_lists(struct drm_device *dev);
2544 #define i915_verify_lists(dev) 0
2547 /* i915_debugfs.c */
2548 int i915_debugfs_init(struct drm_minor *minor);
2549 void i915_debugfs_cleanup(struct drm_minor *minor);
2550 #ifdef CONFIG_DEBUG_FS
2551 void intel_display_crc_init(struct drm_device *dev);
2553 static inline void intel_display_crc_init(struct drm_device *dev) {}
2556 /* i915_gpu_error.c */
2558 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2559 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2560 const struct i915_error_state_file_priv *error);
2561 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2562 size_t count, loff_t pos);
2563 static inline void i915_error_state_buf_release(
2564 struct drm_i915_error_state_buf *eb)
2568 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2569 const char *error_msg);
2570 void i915_error_state_get(struct drm_device *dev,
2571 struct i915_error_state_file_priv *error_priv);
2572 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2573 void i915_destroy_error_state(struct drm_device *dev);
2575 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2576 const char *i915_cache_level_str(int type);
2578 /* i915_cmd_parser.c */
2579 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2580 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2581 int i915_parse_cmds(struct intel_ring_buffer *ring,
2582 struct drm_i915_gem_object *batch_obj,
2583 u32 batch_start_offset,
2586 /* i915_suspend.c */
2587 extern int i915_save_state(struct drm_device *dev);
2588 extern int i915_restore_state(struct drm_device *dev);
2591 void i915_save_display_reg(struct drm_device *dev);
2592 void i915_restore_display_reg(struct drm_device *dev);
2595 void i915_setup_sysfs(struct drm_device *dev_priv);
2596 void i915_teardown_sysfs(struct drm_device *dev_priv);
2599 extern int intel_setup_gmbus(struct drm_device *dev);
2600 extern void intel_teardown_gmbus(struct drm_device *dev);
2601 static inline bool intel_gmbus_is_port_valid(unsigned port)
2603 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2606 extern struct i2c_adapter *intel_gmbus_get_adapter(
2607 struct drm_i915_private *dev_priv, unsigned port);
2608 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2609 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2610 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2612 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2614 extern void intel_i2c_reset(struct drm_device *dev);
2616 /* intel_opregion.c */
2617 struct intel_encoder;
2619 extern int intel_opregion_setup(struct drm_device *dev);
2620 extern void intel_opregion_init(struct drm_device *dev);
2621 extern void intel_opregion_fini(struct drm_device *dev);
2622 extern void intel_opregion_asle_intr(struct drm_device *dev);
2623 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2625 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2628 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2629 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2630 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2631 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2633 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2638 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2646 extern void intel_register_dsm_handler(void);
2647 extern void intel_unregister_dsm_handler(void);
2649 static inline void intel_register_dsm_handler(void) { return; }
2650 static inline void intel_unregister_dsm_handler(void) { return; }
2651 #endif /* CONFIG_ACPI */
2654 extern void intel_modeset_init_hw(struct drm_device *dev);
2655 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2656 extern void intel_modeset_init(struct drm_device *dev);
2657 extern void intel_modeset_gem_init(struct drm_device *dev);
2658 extern void intel_modeset_cleanup(struct drm_device *dev);
2659 extern void intel_connector_unregister(struct intel_connector *);
2660 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2661 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2662 bool force_restore);
2663 extern void i915_redisable_vga(struct drm_device *dev);
2664 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2665 extern bool intel_fbc_enabled(struct drm_device *dev);
2666 extern void intel_disable_fbc(struct drm_device *dev);
2667 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2668 extern void intel_init_pch_refclk(struct drm_device *dev);
2669 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2670 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2671 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2672 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2673 extern void intel_detect_pch(struct drm_device *dev);
2674 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2675 extern int intel_enable_rc6(const struct drm_device *dev);
2677 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2678 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2679 struct drm_file *file);
2680 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2681 struct drm_file *file);
2684 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2685 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2686 struct intel_overlay_error_state *error);
2688 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2689 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2690 struct drm_device *dev,
2691 struct intel_display_error_state *error);
2693 /* On SNB platform, before reading ring registers forcewake bit
2694 * must be set to prevent GT core from power down and stale values being
2697 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2698 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2699 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2701 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2702 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2704 /* intel_sideband.c */
2705 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2706 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2707 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2708 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2709 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2710 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2711 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2712 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2713 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2714 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2715 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2716 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2717 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2718 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2719 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2720 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2721 enum intel_sbi_destination destination);
2722 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2723 enum intel_sbi_destination destination);
2724 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2725 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2727 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2728 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2730 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2731 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2733 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2734 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2735 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2736 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2737 ((reg) >= 0x2E000 && (reg) < 0x30000))
2739 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2740 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2741 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2742 ((reg) >= 0x30000 && (reg) < 0x40000))
2744 #define FORCEWAKE_RENDER (1 << 0)
2745 #define FORCEWAKE_MEDIA (1 << 1)
2746 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2749 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2750 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2752 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2753 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2754 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2755 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2757 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2758 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2759 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2760 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2762 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2763 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2765 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2766 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2768 /* "Broadcast RGB" property */
2769 #define INTEL_BROADCAST_RGB_AUTO 0
2770 #define INTEL_BROADCAST_RGB_FULL 1
2771 #define INTEL_BROADCAST_RGB_LIMITED 2
2773 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2775 if (HAS_PCH_SPLIT(dev))
2776 return CPU_VGACNTRL;
2777 else if (IS_VALLEYVIEW(dev))
2778 return VLV_VGACNTRL;
2783 static inline void __user *to_user_ptr(u64 address)
2785 return (void __user *)(uintptr_t)address;
2788 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2790 unsigned long j = msecs_to_jiffies(m);
2792 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2795 static inline unsigned long
2796 timespec_to_jiffies_timeout(const struct timespec *value)
2798 unsigned long j = timespec_to_jiffies(value);
2800 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2804 * If you need to wait X milliseconds between events A and B, but event B
2805 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2806 * when event A happened, then just before event B you call this function and
2807 * pass the timestamp as the first argument, and X as the second argument.
2810 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2812 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2815 * Don't re-read the value of "jiffies" every time since it may change
2816 * behind our back and break the math.
2818 tmp_jiffies = jiffies;
2819 target_jiffies = timestamp_jiffies +
2820 msecs_to_jiffies_timeout(to_wait_ms);
2822 if (time_after(target_jiffies, tmp_jiffies)) {
2823 remaining_jiffies = target_jiffies - tmp_jiffies;
2824 while (remaining_jiffies)
2826 schedule_timeout_uninterruptible(remaining_jiffies);