drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static struct drm_driver driver;
  42
  43 #define GEN_DEFAULT_PIPEOFFSETS \
  44         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  45                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  46         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  47                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  48         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
  49         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
  58                           CHV_DPLL_C_OFFSET }, \
  59         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
  60                              CHV_DPLL_C_MD_OFFSET }, \
  61         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  62                              CHV_PALETTE_C_OFFSET }
  63
  64 #define CURSOR_OFFSETS \
  65         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  66
  67 #define IVB_CURSOR_OFFSETS \
  68         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  69
  70 static const struct intel_device_info intel_i830_info = {
  71         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  72         .has_overlay = 1, .overlay_needs_physical = 1,
  73         .ring_mask = RENDER_RING,
  74         GEN_DEFAULT_PIPEOFFSETS,
  75         CURSOR_OFFSETS,
  76 };
  77
  78 static const struct intel_device_info intel_845g_info = {
  79         .gen = 2, .num_pipes = 1,
  80         .has_overlay = 1, .overlay_needs_physical = 1,
  81         .ring_mask = RENDER_RING,
  82         GEN_DEFAULT_PIPEOFFSETS,
  83         CURSOR_OFFSETS,
  84 };
  85
  86 static const struct intel_device_info intel_i85x_info = {
  87         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  88         .cursor_needs_physical = 1,
  89         .has_overlay = 1, .overlay_needs_physical = 1,
  90         .has_fbc = 1,
  91         .ring_mask = RENDER_RING,
  92         GEN_DEFAULT_PIPEOFFSETS,
  93         CURSOR_OFFSETS,
  94 };
  95
  96 static const struct intel_device_info intel_i865g_info = {
  97         .gen = 2, .num_pipes = 1,
  98         .has_overlay = 1, .overlay_needs_physical = 1,
  99         .ring_mask = RENDER_RING,
 100         GEN_DEFAULT_PIPEOFFSETS,
 101         CURSOR_OFFSETS,
 102 };
 103
 104 static const struct intel_device_info intel_i915g_info = {
 105         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 106         .has_overlay = 1, .overlay_needs_physical = 1,
 107         .ring_mask = RENDER_RING,
 108         GEN_DEFAULT_PIPEOFFSETS,
 109         CURSOR_OFFSETS,
 110 };
 111 static const struct intel_device_info intel_i915gm_info = {
 112         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 113         .cursor_needs_physical = 1,
 114         .has_overlay = 1, .overlay_needs_physical = 1,
 115         .supports_tv = 1,
 116         .has_fbc = 1,
 117         .ring_mask = RENDER_RING,
 118         GEN_DEFAULT_PIPEOFFSETS,
 119         CURSOR_OFFSETS,
 120 };
 121 static const struct intel_device_info intel_i945g_info = {
 122         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 123         .has_overlay = 1, .overlay_needs_physical = 1,
 124         .ring_mask = RENDER_RING,
 125         GEN_DEFAULT_PIPEOFFSETS,
 126         CURSOR_OFFSETS,
 127 };
 128 static const struct intel_device_info intel_i945gm_info = {
 129         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 130         .has_hotplug = 1, .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132         .supports_tv = 1,
 133         .has_fbc = 1,
 134         .ring_mask = RENDER_RING,
 135         GEN_DEFAULT_PIPEOFFSETS,
 136         CURSOR_OFFSETS,
 137 };
 138
 139 static const struct intel_device_info intel_i965g_info = {
 140         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 141         .has_hotplug = 1,
 142         .has_overlay = 1,
 143         .ring_mask = RENDER_RING,
 144         GEN_DEFAULT_PIPEOFFSETS,
 145         CURSOR_OFFSETS,
 146 };
 147
 148 static const struct intel_device_info intel_i965gm_info = {
 149         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 150         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 151         .has_overlay = 1,
 152         .supports_tv = 1,
 153         .ring_mask = RENDER_RING,
 154         GEN_DEFAULT_PIPEOFFSETS,
 155         CURSOR_OFFSETS,
 156 };
 157
 158 static const struct intel_device_info intel_g33_info = {
 159         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 160         .need_gfx_hws = 1, .has_hotplug = 1,
 161         .has_overlay = 1,
 162         .ring_mask = RENDER_RING,
 163         GEN_DEFAULT_PIPEOFFSETS,
 164         CURSOR_OFFSETS,
 165 };
 166
 167 static const struct intel_device_info intel_g45_info = {
 168         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 169         .has_pipe_cxsr = 1, .has_hotplug = 1,
 170         .ring_mask = RENDER_RING | BSD_RING,
 171         GEN_DEFAULT_PIPEOFFSETS,
 172         CURSOR_OFFSETS,
 173 };
 174
 175 static const struct intel_device_info intel_gm45_info = {
 176         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 177         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 178         .has_pipe_cxsr = 1, .has_hotplug = 1,
 179         .supports_tv = 1,
 180         .ring_mask = RENDER_RING | BSD_RING,
 181         GEN_DEFAULT_PIPEOFFSETS,
 182         CURSOR_OFFSETS,
 183 };
 184
 185 static const struct intel_device_info intel_pineview_info = {
 186         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 187         .need_gfx_hws = 1, .has_hotplug = 1,
 188         .has_overlay = 1,
 189         GEN_DEFAULT_PIPEOFFSETS,
 190         CURSOR_OFFSETS,
 191 };
 192
 193 static const struct intel_device_info intel_ironlake_d_info = {
 194         .gen = 5, .num_pipes = 2,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .ring_mask = RENDER_RING | BSD_RING,
 197         GEN_DEFAULT_PIPEOFFSETS,
 198         CURSOR_OFFSETS,
 199 };
 200
 201 static const struct intel_device_info intel_ironlake_m_info = {
 202         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 203         .need_gfx_hws = 1, .has_hotplug = 1,
 204         .has_fbc = 1,
 205         .ring_mask = RENDER_RING | BSD_RING,
 206         GEN_DEFAULT_PIPEOFFSETS,
 207         CURSOR_OFFSETS,
 208 };
 209
 210 static const struct intel_device_info intel_sandybridge_d_info = {
 211         .gen = 6, .num_pipes = 2,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_fbc = 1,
 214         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 215         .has_llc = 1,
 216         GEN_DEFAULT_PIPEOFFSETS,
 217         CURSOR_OFFSETS,
 218 };
 219
 220 static const struct intel_device_info intel_sandybridge_m_info = {
 221         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 222         .need_gfx_hws = 1, .has_hotplug = 1,
 223         .has_fbc = 1,
 224         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 225         .has_llc = 1,
 226         GEN_DEFAULT_PIPEOFFSETS,
 227         CURSOR_OFFSETS,
 228 };
 229
 230 #define GEN7_FEATURES  \
 231         .gen = 7, .num_pipes = 3, \
 232         .need_gfx_hws = 1, .has_hotplug = 1, \
 233         .has_fbc = 1, \
 234         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 235         .has_llc = 1
 236
 237 static const struct intel_device_info intel_ivybridge_d_info = {
 238         GEN7_FEATURES,
 239         .is_ivybridge = 1,
 240         GEN_DEFAULT_PIPEOFFSETS,
 241         IVB_CURSOR_OFFSETS,
 242 };
 243
 244 static const struct intel_device_info intel_ivybridge_m_info = {
 245         GEN7_FEATURES,
 246         .is_ivybridge = 1,
 247         .is_mobile = 1,
 248         GEN_DEFAULT_PIPEOFFSETS,
 249         IVB_CURSOR_OFFSETS,
 250 };
 251
 252 static const struct intel_device_info intel_ivybridge_q_info = {
 253         GEN7_FEATURES,
 254         .is_ivybridge = 1,
 255         .num_pipes = 0, /* legal, last one wins */
 256         GEN_DEFAULT_PIPEOFFSETS,
 257         IVB_CURSOR_OFFSETS,
 258 };
 259
 260 static const struct intel_device_info intel_valleyview_m_info = {
 261         GEN7_FEATURES,
 262         .is_mobile = 1,
 263         .num_pipes = 2,
 264         .is_valleyview = 1,
 265         .display_mmio_offset = VLV_DISPLAY_BASE,
 266         .has_fbc = 0, /* legal, last one wins */
 267         .has_llc = 0, /* legal, last one wins */
 268         GEN_DEFAULT_PIPEOFFSETS,
 269         CURSOR_OFFSETS,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_d_info = {
 273         GEN7_FEATURES,
 274         .num_pipes = 2,
 275         .is_valleyview = 1,
 276         .display_mmio_offset = VLV_DISPLAY_BASE,
 277         .has_fbc = 0, /* legal, last one wins */
 278         .has_llc = 0, /* legal, last one wins */
 279         GEN_DEFAULT_PIPEOFFSETS,
 280         CURSOR_OFFSETS,
 281 };
 282
 283 static const struct intel_device_info intel_haswell_d_info = {
 284         GEN7_FEATURES,
 285         .is_haswell = 1,
 286         .has_ddi = 1,
 287         .has_fpga_dbg = 1,
 288         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 289         GEN_DEFAULT_PIPEOFFSETS,
 290         IVB_CURSOR_OFFSETS,
 291 };
 292
 293 static const struct intel_device_info intel_haswell_m_info = {
 294         GEN7_FEATURES,
 295         .is_haswell = 1,
 296         .is_mobile = 1,
 297         .has_ddi = 1,
 298         .has_fpga_dbg = 1,
 299         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 300         GEN_DEFAULT_PIPEOFFSETS,
 301         IVB_CURSOR_OFFSETS,
 302 };
 303
 304 static const struct intel_device_info intel_broadwell_d_info = {
 305         .gen = 8, .num_pipes = 3,
 306         .need_gfx_hws = 1, .has_hotplug = 1,
 307         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 308         .has_llc = 1,
 309         .has_ddi = 1,
 310         .has_fbc = 1,
 311         GEN_DEFAULT_PIPEOFFSETS,
 312         IVB_CURSOR_OFFSETS,
 313 };
 314
 315 static const struct intel_device_info intel_broadwell_m_info = {
 316         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 317         .need_gfx_hws = 1, .has_hotplug = 1,
 318         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 319         .has_llc = 1,
 320         .has_ddi = 1,
 321         .has_fbc = 1,
 322         GEN_DEFAULT_PIPEOFFSETS,
 323 };
 324
 325 static const struct intel_device_info intel_broadwell_gt3d_info = {
 326         .gen = 8, .num_pipes = 3,
 327         .need_gfx_hws = 1, .has_hotplug = 1,
 328         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 329         .has_llc = 1,
 330         .has_ddi = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333 };
 334
 335 static const struct intel_device_info intel_broadwell_gt3m_info = {
 336         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 337         .need_gfx_hws = 1, .has_hotplug = 1,
 338         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 339         .has_llc = 1,
 340         .has_ddi = 1,
 341         .has_fbc = 1,
 342         GEN_DEFAULT_PIPEOFFSETS,
 343         IVB_CURSOR_OFFSETS,
 344 };
 345
 346 static const struct intel_device_info intel_cherryview_info = {
 347         .is_preliminary = 1,
 348         .gen = 8, .num_pipes = 3,
 349         .need_gfx_hws = 1, .has_hotplug = 1,
 350         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 351         .is_valleyview = 1,
 352         .display_mmio_offset = VLV_DISPLAY_BASE,
 353         GEN_CHV_PIPEOFFSETS,
 354         CURSOR_OFFSETS,
 355 };
 356
 357 /*
 358  * Make sure any device matches here are from most specific to most
 359  * general.  For example, since the Quanta match is based on the subsystem
 360  * and subvendor IDs, we need it to come before the more general IVB
 361  * PCI ID matches, otherwise we'll use the wrong info struct above.
 362  */
 363 #define INTEL_PCI_IDS \
 364         INTEL_I830_IDS(&intel_i830_info),       \
 365         INTEL_I845G_IDS(&intel_845g_info),      \
 366         INTEL_I85X_IDS(&intel_i85x_info),       \
 367         INTEL_I865G_IDS(&intel_i865g_info),     \
 368         INTEL_I915G_IDS(&intel_i915g_info),     \
 369         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 370         INTEL_I945G_IDS(&intel_i945g_info),     \
 371         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 372         INTEL_I965G_IDS(&intel_i965g_info),     \
 373         INTEL_G33_IDS(&intel_g33_info),         \
 374         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 375         INTEL_GM45_IDS(&intel_gm45_info),       \
 376         INTEL_G45_IDS(&intel_g45_info),         \
 377         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 378         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 379         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 380         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 381         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 382         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 383         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 384         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 385         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 386         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 387         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 388         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 389         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 390         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 391         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 392         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 393         INTEL_CHV_IDS(&intel_cherryview_info)
 394
 395 static const struct pci_device_id pciidlist[] = {               /* aka */
 396         INTEL_PCI_IDS,
 397         {0, 0, 0}
 398 };
 399
 400 #if defined(CONFIG_DRM_I915_KMS)
 401 MODULE_DEVICE_TABLE(pci, pciidlist);
 402 #endif
 403
 404 void intel_detect_pch(struct drm_device *dev)
 405 {
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         struct pci_dev *pch = NULL;
 408
 409         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 410          * (which really amounts to a PCH but no South Display).
 411          */
 412         if (INTEL_INFO(dev)->num_pipes == 0) {
 413                 dev_priv->pch_type = PCH_NOP;
 414                 return;
 415         }
 416
 417         /*
 418          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 419          * make graphics device passthrough work easy for VMM, that only
 420          * need to expose ISA bridge to let driver know the real hardware
 421          * underneath. This is a requirement from virtualization team.
 422          *
 423          * In some virtualized environments (e.g. XEN), there is irrelevant
 424          * ISA bridge in the system. To work reliably, we should scan trhough
 425          * all the ISA bridge devices and check for the first match, instead
 426          * of only checking the first one.
 427          */
 428         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 429                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 430                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 431                         dev_priv->pch_id = id;
 432
 433                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 434                                 dev_priv->pch_type = PCH_IBX;
 435                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 436                                 WARN_ON(!IS_GEN5(dev));
 437                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 438                                 dev_priv->pch_type = PCH_CPT;
 439                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 440                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 441                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 442                                 /* PantherPoint is CPT compatible */
 443                                 dev_priv->pch_type = PCH_CPT;
 444                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 445                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 446                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 447                                 dev_priv->pch_type = PCH_LPT;
 448                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 449                                 WARN_ON(!IS_HASWELL(dev));
 450                                 WARN_ON(IS_ULT(dev));
 451                         } else if (IS_BROADWELL(dev)) {
 452                                 dev_priv->pch_type = PCH_LPT;
 453                                 dev_priv->pch_id =
 454                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 455                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 456                                               "LynxPoint LP PCH\n");
 457                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 458                                 dev_priv->pch_type = PCH_LPT;
 459                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 460                                 WARN_ON(!IS_HASWELL(dev));
 461                                 WARN_ON(!IS_ULT(dev));
 462                         } else
 463                                 continue;
 464
 465                         break;
 466                 }
 467         }
 468         if (!pch)
 469                 DRM_DEBUG_KMS("No PCH found.\n");
 470
 471         pci_dev_put(pch);
 472 }
 473
 474 bool i915_semaphore_is_enabled(struct drm_device *dev)
 475 {
 476         if (INTEL_INFO(dev)->gen < 6)
 477                 return false;
 478
 479         if (i915.semaphores >= 0)
 480                 return i915.semaphores;
 481
 482         /* Until we get further testing... */
 483         if (IS_GEN8(dev))
 484                 return false;
 485
 486 #ifdef CONFIG_INTEL_IOMMU
 487         /* Enable semaphores on SNB when IO remapping is off */
 488         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 489                 return false;
 490 #endif
 491
 492         return true;
 493 }
 494
 495 static int i915_drm_freeze(struct drm_device *dev)
 496 {
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         struct drm_crtc *crtc;
 499
 500         intel_runtime_pm_get(dev_priv);
 501
 502         /* ignore lid events during suspend */
 503         mutex_lock(&dev_priv->modeset_restore_lock);
 504         dev_priv->modeset_restore = MODESET_SUSPENDED;
 505         mutex_unlock(&dev_priv->modeset_restore_lock);
 506
 507         /* We do a lot of poking in a lot of registers, make sure they work
 508          * properly. */
 509         intel_display_set_init_power(dev_priv, true);
 510
 511         drm_kms_helper_poll_disable(dev);
 512
 513         pci_save_state(dev->pdev);
 514
 515         /* If KMS is active, we do the leavevt stuff here */
 516         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 517                 int error;
 518
 519                 error = i915_gem_suspend(dev);
 520                 if (error) {
 521                         dev_err(&dev->pdev->dev,
 522                                 "GEM idle failed, resume might fail\n");
 523                         return error;
 524                 }
 525
 526                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 527
 528                 drm_irq_uninstall(dev);
 529                 dev_priv->enable_hotplug_processing = false;
 530                 /*
 531                  * Disable CRTCs directly since we want to preserve sw state
 532                  * for _thaw.
 533                  */
 534                 mutex_lock(&dev->mode_config.mutex);
 535                 for_each_crtc(dev, crtc) {
 536                         mutex_lock(&crtc->mutex);
 537                         dev_priv->display.crtc_disable(crtc);
 538                         mutex_unlock(&crtc->mutex);
 539                 }
 540                 mutex_unlock(&dev->mode_config.mutex);
 541
 542                 intel_modeset_suspend_hw(dev);
 543         }
 544
 545         i915_gem_suspend_gtt_mappings(dev);
 546
 547         i915_save_state(dev);
 548
 549         intel_opregion_fini(dev);
 550         intel_uncore_fini(dev);
 551
 552         console_lock();
 553         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 554         console_unlock();
 555
 556         dev_priv->suspend_count++;
 557
 558         return 0;
 559 }
 560
 561 int i915_suspend(struct drm_device *dev, pm_message_t state)
 562 {
 563         int error;
 564
 565         if (!dev || !dev->dev_private) {
 566                 DRM_ERROR("dev: %p\n", dev);
 567                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 568                 return -ENODEV;
 569         }
 570
 571         if (state.event == PM_EVENT_PRETHAW)
 572                 return 0;
 573
 574
 575         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 576                 return 0;
 577
 578         error = i915_drm_freeze(dev);
 579         if (error)
 580                 return error;
 581
 582         if (state.event == PM_EVENT_SUSPEND) {
 583                 /* Shut down the device */
 584                 pci_disable_device(dev->pdev);
 585                 pci_set_power_state(dev->pdev, PCI_D3hot);
 586         }
 587
 588         return 0;
 589 }
 590
 591 void intel_console_resume(struct work_struct *work)
 592 {
 593         struct drm_i915_private *dev_priv =
 594                 container_of(work, struct drm_i915_private,
 595                              console_resume_work);
 596         struct drm_device *dev = dev_priv->dev;
 597
 598         console_lock();
 599         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 600         console_unlock();
 601 }
 602
 603 static int i915_drm_thaw_early(struct drm_device *dev)
 604 {
 605         struct drm_i915_private *dev_priv = dev->dev_private;
 606
 607         intel_uncore_early_sanitize(dev);
 608         intel_uncore_sanitize(dev);
 609         intel_power_domains_init_hw(dev_priv);
 610
 611         return 0;
 612 }
 613
 614 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 615 {
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617
 618         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 619             restore_gtt_mappings) {
 620                 mutex_lock(&dev->struct_mutex);
 621                 i915_gem_restore_gtt_mappings(dev);
 622                 mutex_unlock(&dev->struct_mutex);
 623         }
 624
 625         i915_restore_state(dev);
 626         intel_opregion_setup(dev);
 627
 628         /* KMS EnterVT equivalent */
 629         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 630                 intel_init_pch_refclk(dev);
 631                 drm_mode_config_reset(dev);
 632
 633                 mutex_lock(&dev->struct_mutex);
 634                 if (i915_gem_init_hw(dev)) {
 635                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 636                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 637                 }
 638                 mutex_unlock(&dev->struct_mutex);
 639
 640                 /* We need working interrupts for modeset enabling ... */
 641                 drm_irq_install(dev, dev->pdev->irq);
 642
 643                 intel_modeset_init_hw(dev);
 644
 645                 drm_modeset_lock_all(dev);
 646                 intel_modeset_setup_hw_state(dev, true);
 647                 drm_modeset_unlock_all(dev);
 648
 649                 /*
 650                  * ... but also need to make sure that hotplug processing
 651                  * doesn't cause havoc. Like in the driver load code we don't
 652                  * bother with the tiny race here where we might loose hotplug
 653                  * notifications.
 654                  * */
 655                 intel_hpd_init(dev);
 656                 dev_priv->enable_hotplug_processing = true;
 657                 /* Config may have changed between suspend and resume */
 658                 drm_helper_hpd_irq_event(dev);
 659         }
 660
 661         intel_opregion_init(dev);
 662
 663         /*
 664          * The console lock can be pretty contented on resume due
 665          * to all the printk activity.  Try to keep it out of the hot
 666          * path of resume if possible.
 667          */
 668         if (console_trylock()) {
 669                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 670                 console_unlock();
 671         } else {
 672                 schedule_work(&dev_priv->console_resume_work);
 673         }
 674
 675         mutex_lock(&dev_priv->modeset_restore_lock);
 676         dev_priv->modeset_restore = MODESET_DONE;
 677         mutex_unlock(&dev_priv->modeset_restore_lock);
 678
 679         intel_runtime_pm_put(dev_priv);
 680         return 0;
 681 }
 682
 683 static int i915_drm_thaw(struct drm_device *dev)
 684 {
 685         if (drm_core_check_feature(dev, DRIVER_MODESET))
 686                 i915_check_and_clear_faults(dev);
 687
 688         return __i915_drm_thaw(dev, true);
 689 }
 690
 691 static int i915_resume_early(struct drm_device *dev)
 692 {
 693         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 694                 return 0;
 695
 696         /*
 697          * We have a resume ordering issue with the snd-hda driver also
 698          * requiring our device to be power up. Due to the lack of a
 699          * parent/child relationship we currently solve this with an early
 700          * resume hook.
 701          *
 702          * FIXME: This should be solved with a special hdmi sink device or
 703          * similar so that power domains can be employed.
 704          */
 705         if (pci_enable_device(dev->pdev))
 706                 return -EIO;
 707
 708         pci_set_master(dev->pdev);
 709
 710         return i915_drm_thaw_early(dev);
 711 }
 712
 713 int i915_resume(struct drm_device *dev)
 714 {
 715         struct drm_i915_private *dev_priv = dev->dev_private;
 716         int ret;
 717
 718         /*
 719          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 720          * earlier) need to restore the GTT mappings since the BIOS might clear
 721          * all our scratch PTEs.
 722          */
 723         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 724         if (ret)
 725                 return ret;
 726
 727         drm_kms_helper_poll_enable(dev);
 728         return 0;
 729 }
 730
 731 static int i915_resume_legacy(struct drm_device *dev)
 732 {
 733         i915_resume_early(dev);
 734         i915_resume(dev);
 735
 736         return 0;
 737 }
 738
 739 /**
 740  * i915_reset - reset chip after a hang
 741  * @dev: drm device to reset
 742  *
 743  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 744  * reset or otherwise an error code.
 745  *
 746  * Procedure is fairly simple:
 747  *   - reset the chip using the reset reg
 748  *   - re-init context state
 749  *   - re-init hardware status page
 750  *   - re-init ring buffer
 751  *   - re-init interrupt state
 752  *   - re-init display
 753  */
 754 int i915_reset(struct drm_device *dev)
 755 {
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         bool simulated;
 758         int ret;
 759
 760         if (!i915.reset)
 761                 return 0;
 762
 763         mutex_lock(&dev->struct_mutex);
 764
 765         i915_gem_reset(dev);
 766
 767         simulated = dev_priv->gpu_error.stop_rings != 0;
 768
 769         ret = intel_gpu_reset(dev);
 770
 771         /* Also reset the gpu hangman. */
 772         if (simulated) {
 773                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 774                 dev_priv->gpu_error.stop_rings = 0;
 775                 if (ret == -ENODEV) {
 776                         DRM_INFO("Reset not implemented, but ignoring "
 777                                  "error for simulated gpu hangs\n");
 778                         ret = 0;
 779                 }
 780         }
 781
 782         if (ret) {
 783                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 784                 mutex_unlock(&dev->struct_mutex);
 785                 return ret;
 786         }
 787
 788         /* Ok, now get things going again... */
 789
 790         /*
 791          * Everything depends on having the GTT running, so we need to start
 792          * there.  Fortunately we don't need to do this unless we reset the
 793          * chip at a PCI level.
 794          *
 795          * Next we need to restore the context, but we don't use those
 796          * yet either...
 797          *
 798          * Ring buffer needs to be re-initialized in the KMS case, or if X
 799          * was running at the time of the reset (i.e. we weren't VT
 800          * switched away).
 801          */
 802         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 803                         !dev_priv->ums.mm_suspended) {
 804                 dev_priv->ums.mm_suspended = 0;
 805
 806                 ret = i915_gem_init_hw(dev);
 807                 mutex_unlock(&dev->struct_mutex);
 808                 if (ret) {
 809                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 810                         return ret;
 811                 }
 812
 813                 /*
 814                  * FIXME: This is horribly race against concurrent pageflip and
 815                  * vblank wait ioctls since they can observe dev->irqs_disabled
 816                  * being false when they shouldn't be able to.
 817                  */
 818                 drm_irq_uninstall(dev);
 819                 drm_irq_install(dev, dev->pdev->irq);
 820
 821                 /* rps/rc6 re-init is necessary to restore state lost after the
 822                  * reset and the re-install of drm irq. Skip for ironlake per
 823                  * previous concerns that it doesn't respond well to some forms
 824                  * of re-init after reset. */
 825                 if (INTEL_INFO(dev)->gen > 5)
 826                         intel_reset_gt_powersave(dev);
 827
 828                 intel_hpd_init(dev);
 829         } else {
 830                 mutex_unlock(&dev->struct_mutex);
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 837 {
 838         struct intel_device_info *intel_info =
 839                 (struct intel_device_info *) ent->driver_data;
 840
 841         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 842                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 843                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 844                 return -ENODEV;
 845         }
 846
 847         /* Only bind to function 0 of the device. Early generations
 848          * used function 1 as a placeholder for multi-head. This causes
 849          * us confusion instead, especially on the systems where both
 850          * functions have the same PCI-ID!
 851          */
 852         if (PCI_FUNC(pdev->devfn))
 853                 return -ENODEV;
 854
 855         driver.driver_features &= ~(DRIVER_USE_AGP);
 856
 857         return drm_get_pci_dev(pdev, ent, &driver);
 858 }
 859
 860 static void
 861 i915_pci_remove(struct pci_dev *pdev)
 862 {
 863         struct drm_device *dev = pci_get_drvdata(pdev);
 864
 865         drm_put_dev(dev);
 866 }
 867
 868 static int i915_pm_suspend(struct device *dev)
 869 {
 870         struct pci_dev *pdev = to_pci_dev(dev);
 871         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 872
 873         if (!drm_dev || !drm_dev->dev_private) {
 874                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 875                 return -ENODEV;
 876         }
 877
 878         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 879                 return 0;
 880
 881         return i915_drm_freeze(drm_dev);
 882 }
 883
 884 static int i915_pm_suspend_late(struct device *dev)
 885 {
 886         struct pci_dev *pdev = to_pci_dev(dev);
 887         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 888
 889         /*
 890          * We have a suspedn ordering issue with the snd-hda driver also
 891          * requiring our device to be power up. Due to the lack of a
 892          * parent/child relationship we currently solve this with an late
 893          * suspend hook.
 894          *
 895          * FIXME: This should be solved with a special hdmi sink device or
 896          * similar so that power domains can be employed.
 897          */
 898         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 899                 return 0;
 900
 901         pci_disable_device(pdev);
 902         pci_set_power_state(pdev, PCI_D3hot);
 903
 904         return 0;
 905 }
 906
 907 static int i915_pm_resume_early(struct device *dev)
 908 {
 909         struct pci_dev *pdev = to_pci_dev(dev);
 910         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 911
 912         return i915_resume_early(drm_dev);
 913 }
 914
 915 static int i915_pm_resume(struct device *dev)
 916 {
 917         struct pci_dev *pdev = to_pci_dev(dev);
 918         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 919
 920         return i915_resume(drm_dev);
 921 }
 922
 923 static int i915_pm_freeze(struct device *dev)
 924 {
 925         struct pci_dev *pdev = to_pci_dev(dev);
 926         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 927
 928         if (!drm_dev || !drm_dev->dev_private) {
 929                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 930                 return -ENODEV;
 931         }
 932
 933         return i915_drm_freeze(drm_dev);
 934 }
 935
 936 static int i915_pm_thaw_early(struct device *dev)
 937 {
 938         struct pci_dev *pdev = to_pci_dev(dev);
 939         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 940
 941         return i915_drm_thaw_early(drm_dev);
 942 }
 943
 944 static int i915_pm_thaw(struct device *dev)
 945 {
 946         struct pci_dev *pdev = to_pci_dev(dev);
 947         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 948
 949         return i915_drm_thaw(drm_dev);
 950 }
 951
 952 static int i915_pm_poweroff(struct device *dev)
 953 {
 954         struct pci_dev *pdev = to_pci_dev(dev);
 955         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 956
 957         return i915_drm_freeze(drm_dev);
 958 }
 959
 960 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 961 {
 962         hsw_enable_pc8(dev_priv);
 963
 964         return 0;
 965 }
 966
 967 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 968 {
 969         struct drm_device *dev = dev_priv->dev;
 970
 971         intel_init_pch_refclk(dev);
 972
 973         return 0;
 974 }
 975
 976 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
 977 {
 978         hsw_disable_pc8(dev_priv);
 979
 980         return 0;
 981 }
 982
 983 /*
 984  * Save all Gunit registers that may be lost after a D3 and a subsequent
 985  * S0i[R123] transition. The list of registers needing a save/restore is
 986  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 987  * registers in the following way:
 988  * - Driver: saved/restored by the driver
 989  * - Punit : saved/restored by the Punit firmware
 990  * - No, w/o marking: no need to save/restore, since the register is R/O or
 991  *                    used internally by the HW in a way that doesn't depend
 992  *                    keeping the content across a suspend/resume.
 993  * - Debug : used for debugging
 994  *
 995  * We save/restore all registers marked with 'Driver', with the following
 996  * exceptions:
 997  * - Registers out of use, including also registers marked with 'Debug'.
 998  *   These have no effect on the driver's operation, so we don't save/restore
 999  *   them to reduce the overhead.
1000  * - Registers that are fully setup by an initialization function called from
1001  *   the resume path. For example many clock gating and RPS/RC6 registers.
1002  * - Registers that provide the right functionality with their reset defaults.
1003  *
1004  * TODO: Except for registers that based on the above 3 criteria can be safely
1005  * ignored, we save/restore all others, practically treating the HW context as
1006  * a black-box for the driver. Further investigation is needed to reduce the
1007  * saved/restored registers even further, by following the same 3 criteria.
1008  */
1009 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1010 {
1011         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1012         int i;
1013
1014         /* GAM 0x4000-0x4770 */
1015         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1016         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1017         s->arb_mode             = I915_READ(ARB_MODE);
1018         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1019         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1020
1021         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1022                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1023
1024         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1025         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1026
1027         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1028         s->ecochk               = I915_READ(GAM_ECOCHK);
1029         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1030         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1031
1032         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1033
1034         /* MBC 0x9024-0x91D0, 0x8500 */
1035         s->g3dctl               = I915_READ(VLV_G3DCTL);
1036         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1037         s->mbctl                = I915_READ(GEN6_MBCTL);
1038
1039         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1040         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1041         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1042         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1043         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1044         s->rstctl               = I915_READ(GEN6_RSTCTL);
1045         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1046
1047         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1048         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1049         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1050         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1051         s->ecobus               = I915_READ(ECOBUS);
1052         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1053         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1054         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1055         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1056         s->rcedata              = I915_READ(VLV_RCEDATA);
1057         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1058
1059         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1060         s->gt_imr               = I915_READ(GTIMR);
1061         s->gt_ier               = I915_READ(GTIER);
1062         s->pm_imr               = I915_READ(GEN6_PMIMR);
1063         s->pm_ier               = I915_READ(GEN6_PMIER);
1064
1065         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1066                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1067
1068         /* GT SA CZ domain, 0x100000-0x138124 */
1069         s->tilectl              = I915_READ(TILECTL);
1070         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1071         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1072         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1073         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1074
1075         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1076         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1077         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1078         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1079
1080         /*
1081          * Not saving any of:
1082          * DFT,         0x9800-0x9EC0
1083          * SARB,        0xB000-0xB1FC
1084          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1085          * PCI CFG
1086          */
1087 }
1088
1089 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1090 {
1091         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1092         u32 val;
1093         int i;
1094
1095         /* GAM 0x4000-0x4770 */
1096         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1097         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1098         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1099         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1100         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1101
1102         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1103                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1104
1105         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1106         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1107
1108         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1109         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1110         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1111         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1112
1113         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1114
1115         /* MBC 0x9024-0x91D0, 0x8500 */
1116         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1117         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1118         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1119
1120         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1121         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1122         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1123         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1124         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1125         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1126         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1127
1128         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1129         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1130         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1131         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1132         I915_WRITE(ECOBUS,              s->ecobus);
1133         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1134         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1135         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1136         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1137         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1138         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1139
1140         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1141         I915_WRITE(GTIMR,               s->gt_imr);
1142         I915_WRITE(GTIER,               s->gt_ier);
1143         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1144         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1145
1146         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1147                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1148
1149         /* GT SA CZ domain, 0x100000-0x138124 */
1150         I915_WRITE(TILECTL,                     s->tilectl);
1151         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1152         /*
1153          * Preserve the GT allow wake and GFX force clock bit, they are not
1154          * be restored, as they are used to control the s0ix suspend/resume
1155          * sequence by the caller.
1156          */
1157         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1158         val &= VLV_GTLC_ALLOWWAKEREQ;
1159         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1160         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1161
1162         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1163         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1164         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1165         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1166
1167         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1168
1169         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1170         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1171         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1172         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1173 }
1174
1175 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1176 {
1177         u32 val;
1178         int err;
1179
1180         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1181         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1182
1183 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1184         /* Wait for a previous force-off to settle */
1185         if (force_on) {
1186                 err = wait_for(!COND, 20);
1187                 if (err) {
1188                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1189                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1190                         return err;
1191                 }
1192         }
1193
1194         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1195         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1196         if (force_on)
1197                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1198         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1199
1200         if (!force_on)
1201                 return 0;
1202
1203         err = wait_for(COND, 20);
1204         if (err)
1205                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1206                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1207
1208         return err;
1209 #undef COND
1210 }
1211
1212 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1213 {
1214         u32 val;
1215         int err = 0;
1216
1217         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1218         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1219         if (allow)
1220                 val |= VLV_GTLC_ALLOWWAKEREQ;
1221         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1222         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1223
1224 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1225               allow)
1226         err = wait_for(COND, 1);
1227         if (err)
1228                 DRM_ERROR("timeout disabling GT waking\n");
1229         return err;
1230 #undef COND
1231 }
1232
1233 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1234                                  bool wait_for_on)
1235 {
1236         u32 mask;
1237         u32 val;
1238         int err;
1239
1240         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1241         val = wait_for_on ? mask : 0;
1242 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1243         if (COND)
1244                 return 0;
1245
1246         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1247                         wait_for_on ? "on" : "off",
1248                         I915_READ(VLV_GTLC_PW_STATUS));
1249
1250         /*
1251          * RC6 transitioning can be delayed up to 2 msec (see
1252          * valleyview_enable_rps), use 3 msec for safety.
1253          */
1254         err = wait_for(COND, 3);
1255         if (err)
1256                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1257                           wait_for_on ? "on" : "off");
1258
1259         return err;
1260 #undef COND
1261 }
1262
1263 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1264 {
1265         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1266                 return;
1267
1268         DRM_ERROR("GT register access while GT waking disabled\n");
1269         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1270 }
1271
1272 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1273 {
1274         u32 mask;
1275         int err;
1276
1277         /*
1278          * Bspec defines the following GT well on flags as debug only, so
1279          * don't treat them as hard failures.
1280          */
1281         (void)vlv_wait_for_gt_wells(dev_priv, false);
1282
1283         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1284         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1285
1286         vlv_check_no_gt_access(dev_priv);
1287
1288         err = vlv_force_gfx_clock(dev_priv, true);
1289         if (err)
1290                 goto err1;
1291
1292         err = vlv_allow_gt_wake(dev_priv, false);
1293         if (err)
1294                 goto err2;
1295         vlv_save_gunit_s0ix_state(dev_priv);
1296
1297         err = vlv_force_gfx_clock(dev_priv, false);
1298         if (err)
1299                 goto err2;
1300
1301         return 0;
1302
1303 err2:
1304         /* For safety always re-enable waking and disable gfx clock forcing */
1305         vlv_allow_gt_wake(dev_priv, true);
1306 err1:
1307         vlv_force_gfx_clock(dev_priv, false);
1308
1309         return err;
1310 }
1311
1312 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1313 {
1314         struct drm_device *dev = dev_priv->dev;
1315         int err;
1316         int ret;
1317
1318         /*
1319          * If any of the steps fail just try to continue, that's the best we
1320          * can do at this point. Return the first error code (which will also
1321          * leave RPM permanently disabled).
1322          */
1323         ret = vlv_force_gfx_clock(dev_priv, true);
1324
1325         vlv_restore_gunit_s0ix_state(dev_priv);
1326
1327         err = vlv_allow_gt_wake(dev_priv, true);
1328         if (!ret)
1329                 ret = err;
1330
1331         err = vlv_force_gfx_clock(dev_priv, false);
1332         if (!ret)
1333                 ret = err;
1334
1335         vlv_check_no_gt_access(dev_priv);
1336
1337         intel_init_clock_gating(dev);
1338         i915_gem_restore_fences(dev);
1339
1340         return ret;
1341 }
1342
1343 static int intel_runtime_suspend(struct device *device)
1344 {
1345         struct pci_dev *pdev = to_pci_dev(device);
1346         struct drm_device *dev = pci_get_drvdata(pdev);
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348         int ret;
1349
1350         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1351                 return -ENODEV;
1352
1353         WARN_ON(!HAS_RUNTIME_PM(dev));
1354         assert_force_wake_inactive(dev_priv);
1355
1356         DRM_DEBUG_KMS("Suspending device\n");
1357
1358         /*
1359          * rps.work can't be rearmed here, since we get here only after making
1360          * sure the GPU is idle and the RPS freq is set to the minimum. See
1361          * intel_mark_idle().
1362          */
1363         cancel_work_sync(&dev_priv->rps.work);
1364         intel_runtime_pm_disable_interrupts(dev);
1365
1366         if (IS_GEN6(dev)) {
1367                 ret = 0;
1368         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1369                 ret = hsw_runtime_suspend(dev_priv);
1370         } else if (IS_VALLEYVIEW(dev)) {
1371                 ret = vlv_runtime_suspend(dev_priv);
1372         } else {
1373                 ret = -ENODEV;
1374                 WARN_ON(1);
1375         }
1376
1377         if (ret) {
1378                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1379                 intel_runtime_pm_restore_interrupts(dev);
1380
1381                 return ret;
1382         }
1383
1384         i915_gem_release_all_mmaps(dev_priv);
1385
1386         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1387         dev_priv->pm.suspended = true;
1388
1389         /*
1390          * current versions of firmware which depend on this opregion
1391          * notification have repurposed the D1 definition to mean
1392          * "runtime suspended" vs. what you would normally expect (D3)
1393          * to distinguish it from notifications that might be sent
1394          * via the suspend path.
1395          */
1396         intel_opregion_notify_adapter(dev, PCI_D1);
1397
1398         DRM_DEBUG_KMS("Device suspended\n");
1399         return 0;
1400 }
1401
1402 static int intel_runtime_resume(struct device *device)
1403 {
1404         struct pci_dev *pdev = to_pci_dev(device);
1405         struct drm_device *dev = pci_get_drvdata(pdev);
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         int ret;
1408
1409         WARN_ON(!HAS_RUNTIME_PM(dev));
1410
1411         DRM_DEBUG_KMS("Resuming device\n");
1412
1413         intel_opregion_notify_adapter(dev, PCI_D0);
1414         dev_priv->pm.suspended = false;
1415
1416         if (IS_GEN6(dev)) {
1417                 ret = snb_runtime_resume(dev_priv);
1418         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1419                 ret = hsw_runtime_resume(dev_priv);
1420         } else if (IS_VALLEYVIEW(dev)) {
1421                 ret = vlv_runtime_resume(dev_priv);
1422         } else {
1423                 WARN_ON(1);
1424                 ret = -ENODEV;
1425         }
1426
1427         /*
1428          * No point of rolling back things in case of an error, as the best
1429          * we can do is to hope that things will still work (and disable RPM).
1430          */
1431         i915_gem_init_swizzling(dev);
1432         gen6_update_ring_freq(dev);
1433
1434         intel_runtime_pm_restore_interrupts(dev);
1435         intel_reset_gt_powersave(dev);
1436
1437         if (ret)
1438                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1439         else
1440                 DRM_DEBUG_KMS("Device resumed\n");
1441
1442         return ret;
1443 }
1444
1445 static const struct dev_pm_ops i915_pm_ops = {
1446         .suspend = i915_pm_suspend,
1447         .suspend_late = i915_pm_suspend_late,
1448         .resume_early = i915_pm_resume_early,
1449         .resume = i915_pm_resume,
1450         .freeze = i915_pm_freeze,
1451         .thaw_early = i915_pm_thaw_early,
1452         .thaw = i915_pm_thaw,
1453         .poweroff = i915_pm_poweroff,
1454         .restore_early = i915_pm_resume_early,
1455         .restore = i915_pm_resume,
1456         .runtime_suspend = intel_runtime_suspend,
1457         .runtime_resume = intel_runtime_resume,
1458 };
1459
1460 static const struct vm_operations_struct i915_gem_vm_ops = {
1461         .fault = i915_gem_fault,
1462         .open = drm_gem_vm_open,
1463         .close = drm_gem_vm_close,
1464 };
1465
1466 static const struct file_operations i915_driver_fops = {
1467         .owner = THIS_MODULE,
1468         .open = drm_open,
1469         .release = drm_release,
1470         .unlocked_ioctl = drm_ioctl,
1471         .mmap = drm_gem_mmap,
1472         .poll = drm_poll,
1473         .read = drm_read,
1474 #ifdef CONFIG_COMPAT
1475         .compat_ioctl = i915_compat_ioctl,
1476 #endif
1477         .llseek = noop_llseek,
1478 };
1479
1480 static struct drm_driver driver = {
1481         /* Don't use MTRRs here; the Xserver or userspace app should
1482          * deal with them for Intel hardware.
1483          */
1484         .driver_features =
1485             DRIVER_USE_AGP |
1486             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1487             DRIVER_RENDER,
1488         .load = i915_driver_load,
1489         .unload = i915_driver_unload,
1490         .open = i915_driver_open,
1491         .lastclose = i915_driver_lastclose,
1492         .preclose = i915_driver_preclose,
1493         .postclose = i915_driver_postclose,
1494
1495         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1496         .suspend = i915_suspend,
1497         .resume = i915_resume_legacy,
1498
1499         .device_is_agp = i915_driver_device_is_agp,
1500         .master_create = i915_master_create,
1501         .master_destroy = i915_master_destroy,
1502 #if defined(CONFIG_DEBUG_FS)
1503         .debugfs_init = i915_debugfs_init,
1504         .debugfs_cleanup = i915_debugfs_cleanup,
1505 #endif
1506         .gem_free_object = i915_gem_free_object,
1507         .gem_vm_ops = &i915_gem_vm_ops,
1508
1509         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1510         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1511         .gem_prime_export = i915_gem_prime_export,
1512         .gem_prime_import = i915_gem_prime_import,
1513
1514         .dumb_create = i915_gem_dumb_create,
1515         .dumb_map_offset = i915_gem_mmap_gtt,
1516         .dumb_destroy = drm_gem_dumb_destroy,
1517         .ioctls = i915_ioctls,
1518         .fops = &i915_driver_fops,
1519         .name = DRIVER_NAME,
1520         .desc = DRIVER_DESC,
1521         .date = DRIVER_DATE,
1522         .major = DRIVER_MAJOR,
1523         .minor = DRIVER_MINOR,
1524         .patchlevel = DRIVER_PATCHLEVEL,
1525 };
1526
1527 static struct pci_driver i915_pci_driver = {
1528         .name = DRIVER_NAME,
1529         .id_table = pciidlist,
1530         .probe = i915_pci_probe,
1531         .remove = i915_pci_remove,
1532         .driver.pm = &i915_pm_ops,
1533 };
1534
1535 static int __init i915_init(void)
1536 {
1537         driver.num_ioctls = i915_max_ioctl;
1538
1539         /*
1540          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1541          * explicitly disabled with the module pararmeter.
1542          *
1543          * Otherwise, just follow the parameter (defaulting to off).
1544          *
1545          * Allow optional vga_text_mode_force boot option to override
1546          * the default behavior.
1547          */
1548 #if defined(CONFIG_DRM_I915_KMS)
1549         if (i915.modeset != 0)
1550                 driver.driver_features |= DRIVER_MODESET;
1551 #endif
1552         if (i915.modeset == 1)
1553                 driver.driver_features |= DRIVER_MODESET;
1554
1555 #ifdef CONFIG_VGA_CONSOLE
1556         if (vgacon_text_force() && i915.modeset == -1)
1557                 driver.driver_features &= ~DRIVER_MODESET;
1558 #endif
1559
1560         if (!(driver.driver_features & DRIVER_MODESET)) {
1561                 driver.get_vblank_timestamp = NULL;
1562 #ifndef CONFIG_DRM_I915_UMS
1563                 /* Silently fail loading to not upset userspace. */
1564                 return 0;
1565 #endif
1566         }
1567
1568         return drm_pci_init(&driver, &i915_pci_driver);
1569 }
1570
1571 static void __exit i915_exit(void)
1572 {
1573 #ifndef CONFIG_DRM_I915_UMS
1574         if (!(driver.driver_features & DRIVER_MODESET))
1575                 return; /* Never loaded a driver. */
1576 #endif
1577
1578         drm_pci_exit(&driver, &i915_pci_driver);
1579 }
1580
1581 module_init(i915_init);
1582 module_exit(i915_exit);
1583
1584 MODULE_AUTHOR(DRIVER_AUTHOR);
1585 MODULE_DESCRIPTION(DRIVER_DESC);
1586 MODULE_LICENSE("GPL and additional rights");