drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_lvds_channel_mode __read_mostly;
  84 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  85 MODULE_PARM_DESC(lvds_channel_mode,
  86                  "Specify LVDS channel mode "
  87                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  88
  89 int i915_panel_use_ssc __read_mostly = -1;
  90 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  91 MODULE_PARM_DESC(lvds_use_ssc,
  92                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  93                 "(default: auto from VBT)");
  94
  95 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  96 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  97 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  98                 "Override/Ignore selection of SDVO panel mode in the VBT "
  99                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 100
 101 static bool i915_try_reset __read_mostly = true;
 102 module_param_named(reset, i915_try_reset, bool, 0600);
 103 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 104
 105 bool i915_enable_hangcheck __read_mostly = true;
 106 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 107 MODULE_PARM_DESC(enable_hangcheck,
 108                 "Periodically check GPU activity for detecting hangs. "
 109                 "WARNING: Disabling this can cause system wide hangs. "
 110                 "(default: true)");
 111
 112 bool i915_enable_ppgtt __read_mostly = 1;
 113 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 114 MODULE_PARM_DESC(i915_enable_ppgtt,
 115                 "Enable PPGTT (default: true)");
 116
 117 static struct drm_driver driver;
 118 extern int intel_agp_enabled;
 119
 120 #define INTEL_VGA_DEVICE(id, info) {            \
 121         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 122         .class_mask = 0xff0000,                 \
 123         .vendor = 0x8086,                       \
 124         .device = id,                           \
 125         .subvendor = PCI_ANY_ID,                \
 126         .subdevice = PCI_ANY_ID,                \
 127         .driver_data = (unsigned long) info }
 128
 129 static const struct intel_device_info intel_i830_info = {
 130         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_845g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i85x_info = {
 140         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 141         .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_i865g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i915g_info = {
 151         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153 };
 154 static const struct intel_device_info intel_i915gm_info = {
 155         .gen = 3, .is_mobile = 1,
 156         .cursor_needs_physical = 1,
 157         .has_overlay = 1, .overlay_needs_physical = 1,
 158         .supports_tv = 1,
 159 };
 160 static const struct intel_device_info intel_i945g_info = {
 161         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163 };
 164 static const struct intel_device_info intel_i945gm_info = {
 165         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 166         .has_hotplug = 1, .cursor_needs_physical = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .supports_tv = 1,
 169 };
 170
 171 static const struct intel_device_info intel_i965g_info = {
 172         .gen = 4, .is_broadwater = 1,
 173         .has_hotplug = 1,
 174         .has_overlay = 1,
 175 };
 176
 177 static const struct intel_device_info intel_i965gm_info = {
 178         .gen = 4, .is_crestline = 1,
 179         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 180         .has_overlay = 1,
 181         .supports_tv = 1,
 182 };
 183
 184 static const struct intel_device_info intel_g33_info = {
 185         .gen = 3, .is_g33 = 1,
 186         .need_gfx_hws = 1, .has_hotplug = 1,
 187         .has_overlay = 1,
 188 };
 189
 190 static const struct intel_device_info intel_g45_info = {
 191         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 192         .has_pipe_cxsr = 1, .has_hotplug = 1,
 193         .has_bsd_ring = 1,
 194 };
 195
 196 static const struct intel_device_info intel_gm45_info = {
 197         .gen = 4, .is_g4x = 1,
 198         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 199         .has_pipe_cxsr = 1, .has_hotplug = 1,
 200         .supports_tv = 1,
 201         .has_bsd_ring = 1,
 202 };
 203
 204 static const struct intel_device_info intel_pineview_info = {
 205         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 206         .need_gfx_hws = 1, .has_hotplug = 1,
 207         .has_overlay = 1,
 208 };
 209
 210 static const struct intel_device_info intel_ironlake_d_info = {
 211         .gen = 5,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_bsd_ring = 1,
 214         .has_pch_split = 1,
 215 };
 216
 217 static const struct intel_device_info intel_ironlake_m_info = {
 218         .gen = 5, .is_mobile = 1,
 219         .need_gfx_hws = 1, .has_hotplug = 1,
 220         .has_fbc = 1,
 221         .has_bsd_ring = 1,
 222         .has_pch_split = 1,
 223 };
 224
 225 static const struct intel_device_info intel_sandybridge_d_info = {
 226         .gen = 6,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_bsd_ring = 1,
 229         .has_blt_ring = 1,
 230         .has_llc = 1,
 231         .has_pch_split = 1,
 232 };
 233
 234 static const struct intel_device_info intel_sandybridge_m_info = {
 235         .gen = 6, .is_mobile = 1,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_fbc = 1,
 238         .has_bsd_ring = 1,
 239         .has_blt_ring = 1,
 240         .has_llc = 1,
 241         .has_pch_split = 1,
 242 };
 243
 244 static const struct intel_device_info intel_ivybridge_d_info = {
 245         .is_ivybridge = 1, .gen = 7,
 246         .need_gfx_hws = 1, .has_hotplug = 1,
 247         .has_bsd_ring = 1,
 248         .has_blt_ring = 1,
 249         .has_llc = 1,
 250         .has_pch_split = 1,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_m_info = {
 254         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 255         .need_gfx_hws = 1, .has_hotplug = 1,
 256         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 257         .has_bsd_ring = 1,
 258         .has_blt_ring = 1,
 259         .has_llc = 1,
 260         .has_pch_split = 1,
 261 };
 262
 263 static const struct intel_device_info intel_valleyview_m_info = {
 264         .gen = 7, .is_mobile = 1,
 265         .need_gfx_hws = 1, .has_hotplug = 1,
 266         .has_fbc = 0,
 267         .has_bsd_ring = 1,
 268         .has_blt_ring = 1,
 269         .is_valleyview = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_d_info = {
 273         .gen = 7,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279 };
 280
 281 static const struct intel_device_info intel_haswell_d_info = {
 282         .is_haswell = 1, .gen = 7,
 283         .need_gfx_hws = 1, .has_hotplug = 1,
 284         .has_bsd_ring = 1,
 285         .has_blt_ring = 1,
 286         .has_llc = 1,
 287         .has_pch_split = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_m_info = {
 291         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 292         .need_gfx_hws = 1, .has_hotplug = 1,
 293         .has_bsd_ring = 1,
 294         .has_blt_ring = 1,
 295         .has_llc = 1,
 296         .has_pch_split = 1,
 297 };
 298
 299 static const struct pci_device_id pciidlist[] = {               /* aka */
 300         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 301         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 302         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 303         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 304         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 305         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 306         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 307         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 308         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 309         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 310         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 311         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 312         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 313         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 314         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 315         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 316         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 317         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 318         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 319         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 320         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 321         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 322         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 323         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 324         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 325         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 326         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 327         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 328         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 329         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 330         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 331         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 332         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 333         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 334         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 335         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 336         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 337         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 338         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 339         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 340         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 341         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 342         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 343         {0, 0, 0}
 344 };
 345
 346 #if defined(CONFIG_DRM_I915_KMS)
 347 MODULE_DEVICE_TABLE(pci, pciidlist);
 348 #endif
 349
 350 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 351 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 352 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 353 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 354
 355 void intel_detect_pch(struct drm_device *dev)
 356 {
 357         struct drm_i915_private *dev_priv = dev->dev_private;
 358         struct pci_dev *pch;
 359
 360         /*
 361          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 362          * make graphics device passthrough work easy for VMM, that only
 363          * need to expose ISA bridge to let driver know the real hardware
 364          * underneath. This is a requirement from virtualization team.
 365          */
 366         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 367         if (pch) {
 368                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 369                         int id;
 370                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 371
 372                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 373                                 dev_priv->pch_type = PCH_IBX;
 374                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 375                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 376                                 dev_priv->pch_type = PCH_CPT;
 377                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 378                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 379                                 /* PantherPoint is CPT compatible */
 380                                 dev_priv->pch_type = PCH_CPT;
 381                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 382                         }
 383                 }
 384                 pci_dev_put(pch);
 385         }
 386 }
 387
 388 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 389 {
 390         int count;
 391
 392         count = 0;
 393         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 394                 udelay(10);
 395
 396         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 397         POSTING_READ(FORCEWAKE);
 398
 399         count = 0;
 400         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 401                 udelay(10);
 402 }
 403
 404 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 405 {
 406         int count;
 407
 408         count = 0;
 409         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 410                 udelay(10);
 411
 412         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 413         POSTING_READ(FORCEWAKE_MT);
 414
 415         count = 0;
 416         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 417                 udelay(10);
 418 }
 419
 420 /*
 421  * Generally this is called implicitly by the register read function. However,
 422  * if some sequence requires the GT to not power down then this function should
 423  * be called at the beginning of the sequence followed by a call to
 424  * gen6_gt_force_wake_put() at the end of the sequence.
 425  */
 426 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 427 {
 428         unsigned long irqflags;
 429
 430         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 431         if (dev_priv->forcewake_count++ == 0)
 432                 dev_priv->display.force_wake_get(dev_priv);
 433         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 434 }
 435
 436 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 437 {
 438         u32 gtfifodbg;
 439         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 440         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 441              "MMIO read or write has been dropped %x\n", gtfifodbg))
 442                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 443 }
 444
 445 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 446 {
 447         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 448         /* The below doubles as a POSTING_READ */
 449         gen6_gt_check_fifodbg(dev_priv);
 450 }
 451
 452 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 453 {
 454         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 455         /* The below doubles as a POSTING_READ */
 456         gen6_gt_check_fifodbg(dev_priv);
 457 }
 458
 459 /*
 460  * see gen6_gt_force_wake_get()
 461  */
 462 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 463 {
 464         unsigned long irqflags;
 465
 466         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 467         if (--dev_priv->forcewake_count == 0)
 468                 dev_priv->display.force_wake_put(dev_priv);
 469         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 470 }
 471
 472 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 473 {
 474         int ret = 0;
 475
 476         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 477                 int loop = 500;
 478                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 479                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 480                         udelay(10);
 481                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 482                 }
 483                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 484                         ++ret;
 485                 dev_priv->gt_fifo_count = fifo;
 486         }
 487         dev_priv->gt_fifo_count--;
 488
 489         return ret;
 490 }
 491
 492 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 493 {
 494         int count;
 495
 496         count = 0;
 497
 498         /* Already awake? */
 499         if ((I915_READ(0x130094) & 0xa1) == 0xa1)
 500                 return;
 501
 502         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
 503         POSTING_READ(FORCEWAKE_VLV);
 504
 505         count = 0;
 506         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
 507                 udelay(10);
 508 }
 509
 510 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 511 {
 512         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
 513         /* FIXME: confirm VLV behavior with Punit folks */
 514         POSTING_READ(FORCEWAKE_VLV);
 515 }
 516
 517 static int i915_drm_freeze(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520
 521         drm_kms_helper_poll_disable(dev);
 522
 523         pci_save_state(dev->pdev);
 524
 525         /* If KMS is active, we do the leavevt stuff here */
 526         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 527                 int error = i915_gem_idle(dev);
 528                 if (error) {
 529                         dev_err(&dev->pdev->dev,
 530                                 "GEM idle failed, resume might fail\n");
 531                         return error;
 532                 }
 533                 drm_irq_uninstall(dev);
 534         }
 535
 536         i915_save_state(dev);
 537
 538         intel_opregion_fini(dev);
 539
 540         /* Modeset on resume, not lid events */
 541         dev_priv->modeset_on_lid = 0;
 542
 543         return 0;
 544 }
 545
 546 int i915_suspend(struct drm_device *dev, pm_message_t state)
 547 {
 548         int error;
 549
 550         if (!dev || !dev->dev_private) {
 551                 DRM_ERROR("dev: %p\n", dev);
 552                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 553                 return -ENODEV;
 554         }
 555
 556         if (state.event == PM_EVENT_PRETHAW)
 557                 return 0;
 558
 559
 560         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 561                 return 0;
 562
 563         error = i915_drm_freeze(dev);
 564         if (error)
 565                 return error;
 566
 567         if (state.event == PM_EVENT_SUSPEND) {
 568                 /* Shut down the device */
 569                 pci_disable_device(dev->pdev);
 570                 pci_set_power_state(dev->pdev, PCI_D3hot);
 571         }
 572
 573         return 0;
 574 }
 575
 576 static int i915_drm_thaw(struct drm_device *dev)
 577 {
 578         struct drm_i915_private *dev_priv = dev->dev_private;
 579         int error = 0;
 580
 581         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 582                 mutex_lock(&dev->struct_mutex);
 583                 i915_gem_restore_gtt_mappings(dev);
 584                 mutex_unlock(&dev->struct_mutex);
 585         }
 586
 587         i915_restore_state(dev);
 588         intel_opregion_setup(dev);
 589
 590         /* KMS EnterVT equivalent */
 591         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 592                 mutex_lock(&dev->struct_mutex);
 593                 dev_priv->mm.suspended = 0;
 594
 595                 error = i915_gem_init_hw(dev);
 596                 mutex_unlock(&dev->struct_mutex);
 597
 598                 if (HAS_PCH_SPLIT(dev))
 599                         ironlake_init_pch_refclk(dev);
 600
 601                 drm_mode_config_reset(dev);
 602                 drm_irq_install(dev);
 603
 604                 /* Resume the modeset for every activated CRTC */
 605                 drm_helper_resume_force_mode(dev);
 606
 607                 if (IS_IRONLAKE_M(dev))
 608                         ironlake_enable_rc6(dev);
 609         }
 610
 611         intel_opregion_init(dev);
 612
 613         dev_priv->modeset_on_lid = 0;
 614
 615         return error;
 616 }
 617
 618 int i915_resume(struct drm_device *dev)
 619 {
 620         int ret;
 621
 622         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 623                 return 0;
 624
 625         if (pci_enable_device(dev->pdev))
 626                 return -EIO;
 627
 628         pci_set_master(dev->pdev);
 629
 630         ret = i915_drm_thaw(dev);
 631         if (ret)
 632                 return ret;
 633
 634         drm_kms_helper_poll_enable(dev);
 635         return 0;
 636 }
 637
 638 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 639 {
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641
 642         if (IS_I85X(dev))
 643                 return -ENODEV;
 644
 645         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 646         POSTING_READ(D_STATE);
 647
 648         if (IS_I830(dev) || IS_845G(dev)) {
 649                 I915_WRITE(DEBUG_RESET_I830,
 650                            DEBUG_RESET_DISPLAY |
 651                            DEBUG_RESET_RENDER |
 652                            DEBUG_RESET_FULL);
 653                 POSTING_READ(DEBUG_RESET_I830);
 654                 msleep(1);
 655
 656                 I915_WRITE(DEBUG_RESET_I830, 0);
 657                 POSTING_READ(DEBUG_RESET_I830);
 658         }
 659
 660         msleep(1);
 661
 662         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 663         POSTING_READ(D_STATE);
 664
 665         return 0;
 666 }
 667
 668 static int i965_reset_complete(struct drm_device *dev)
 669 {
 670         u8 gdrst;
 671         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 672         return gdrst & 0x1;
 673 }
 674
 675 static int i965_do_reset(struct drm_device *dev, u8 flags)
 676 {
 677         u8 gdrst;
 678
 679         /*
 680          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 681          * well as the reset bit (GR/bit 0).  Setting the GR bit
 682          * triggers the reset; when done, the hardware will clear it.
 683          */
 684         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 685         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 686
 687         return wait_for(i965_reset_complete(dev), 500);
 688 }
 689
 690 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 691 {
 692         struct drm_i915_private *dev_priv = dev->dev_private;
 693         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 694         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 695         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 696 }
 697
 698 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701         int     ret;
 702         unsigned long irqflags;
 703
 704         /* Hold gt_lock across reset to prevent any register access
 705          * with forcewake not set correctly
 706          */
 707         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 708
 709         /* Reset the chip */
 710
 711         /* GEN6_GDRST is not in the gt power well, no need to check
 712          * for fifo space for the write or forcewake the chip for
 713          * the read
 714          */
 715         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 716
 717         /* Spin waiting for the device to ack the reset request */
 718         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 719
 720         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 721         if (dev_priv->forcewake_count)
 722                 dev_priv->display.force_wake_get(dev_priv);
 723         else
 724                 dev_priv->display.force_wake_put(dev_priv);
 725
 726         /* Restore fifo count */
 727         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 728
 729         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 730         return ret;
 731 }
 732
 733 /**
 734  * i915_reset - reset chip after a hang
 735  * @dev: drm device to reset
 736  * @flags: reset domains
 737  *
 738  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 739  * reset or otherwise an error code.
 740  *
 741  * Procedure is fairly simple:
 742  *   - reset the chip using the reset reg
 743  *   - re-init context state
 744  *   - re-init hardware status page
 745  *   - re-init ring buffer
 746  *   - re-init interrupt state
 747  *   - re-init display
 748  */
 749 int i915_reset(struct drm_device *dev, u8 flags)
 750 {
 751         drm_i915_private_t *dev_priv = dev->dev_private;
 752         /*
 753          * We really should only reset the display subsystem if we actually
 754          * need to
 755          */
 756         bool need_display = true;
 757         int ret;
 758
 759         if (!i915_try_reset)
 760                 return 0;
 761
 762         if (!mutex_trylock(&dev->struct_mutex))
 763                 return -EBUSY;
 764
 765         i915_gem_reset(dev);
 766
 767         ret = -ENODEV;
 768         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 769                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 770         } else switch (INTEL_INFO(dev)->gen) {
 771         case 7:
 772         case 6:
 773                 ret = gen6_do_reset(dev, flags);
 774                 break;
 775         case 5:
 776                 ret = ironlake_do_reset(dev, flags);
 777                 break;
 778         case 4:
 779                 ret = i965_do_reset(dev, flags);
 780                 break;
 781         case 2:
 782                 ret = i8xx_do_reset(dev, flags);
 783                 break;
 784         }
 785         dev_priv->last_gpu_reset = get_seconds();
 786         if (ret) {
 787                 DRM_ERROR("Failed to reset chip.\n");
 788                 mutex_unlock(&dev->struct_mutex);
 789                 return ret;
 790         }
 791
 792         /* Ok, now get things going again... */
 793
 794         /*
 795          * Everything depends on having the GTT running, so we need to start
 796          * there.  Fortunately we don't need to do this unless we reset the
 797          * chip at a PCI level.
 798          *
 799          * Next we need to restore the context, but we don't use those
 800          * yet either...
 801          *
 802          * Ring buffer needs to be re-initialized in the KMS case, or if X
 803          * was running at the time of the reset (i.e. we weren't VT
 804          * switched away).
 805          */
 806         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 807                         !dev_priv->mm.suspended) {
 808                 dev_priv->mm.suspended = 0;
 809
 810                 i915_gem_init_swizzling(dev);
 811
 812                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 813                 if (HAS_BSD(dev))
 814                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 815                 if (HAS_BLT(dev))
 816                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 817
 818                 i915_gem_init_ppgtt(dev);
 819
 820                 mutex_unlock(&dev->struct_mutex);
 821                 drm_irq_uninstall(dev);
 822                 drm_mode_config_reset(dev);
 823                 drm_irq_install(dev);
 824                 mutex_lock(&dev->struct_mutex);
 825         }
 826
 827         mutex_unlock(&dev->struct_mutex);
 828
 829         /*
 830          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 831          * need to retrain the display link and cannot just restore the register
 832          * values.
 833          */
 834         if (need_display) {
 835                 mutex_lock(&dev->mode_config.mutex);
 836                 drm_helper_resume_force_mode(dev);
 837                 mutex_unlock(&dev->mode_config.mutex);
 838         }
 839
 840         return 0;
 841 }
 842
 843
 844 static int __devinit
 845 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 846 {
 847         /* Only bind to function 0 of the device. Early generations
 848          * used function 1 as a placeholder for multi-head. This causes
 849          * us confusion instead, especially on the systems where both
 850          * functions have the same PCI-ID!
 851          */
 852         if (PCI_FUNC(pdev->devfn))
 853                 return -ENODEV;
 854
 855         return drm_get_pci_dev(pdev, ent, &driver);
 856 }
 857
 858 static void
 859 i915_pci_remove(struct pci_dev *pdev)
 860 {
 861         struct drm_device *dev = pci_get_drvdata(pdev);
 862
 863         drm_put_dev(dev);
 864 }
 865
 866 static int i915_pm_suspend(struct device *dev)
 867 {
 868         struct pci_dev *pdev = to_pci_dev(dev);
 869         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 870         int error;
 871
 872         if (!drm_dev || !drm_dev->dev_private) {
 873                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 874                 return -ENODEV;
 875         }
 876
 877         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 878                 return 0;
 879
 880         error = i915_drm_freeze(drm_dev);
 881         if (error)
 882                 return error;
 883
 884         pci_disable_device(pdev);
 885         pci_set_power_state(pdev, PCI_D3hot);
 886
 887         return 0;
 888 }
 889
 890 static int i915_pm_resume(struct device *dev)
 891 {
 892         struct pci_dev *pdev = to_pci_dev(dev);
 893         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 894
 895         return i915_resume(drm_dev);
 896 }
 897
 898 static int i915_pm_freeze(struct device *dev)
 899 {
 900         struct pci_dev *pdev = to_pci_dev(dev);
 901         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 902
 903         if (!drm_dev || !drm_dev->dev_private) {
 904                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 905                 return -ENODEV;
 906         }
 907
 908         return i915_drm_freeze(drm_dev);
 909 }
 910
 911 static int i915_pm_thaw(struct device *dev)
 912 {
 913         struct pci_dev *pdev = to_pci_dev(dev);
 914         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 915
 916         return i915_drm_thaw(drm_dev);
 917 }
 918
 919 static int i915_pm_poweroff(struct device *dev)
 920 {
 921         struct pci_dev *pdev = to_pci_dev(dev);
 922         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 923
 924         return i915_drm_freeze(drm_dev);
 925 }
 926
 927 static const struct dev_pm_ops i915_pm_ops = {
 928         .suspend = i915_pm_suspend,
 929         .resume = i915_pm_resume,
 930         .freeze = i915_pm_freeze,
 931         .thaw = i915_pm_thaw,
 932         .poweroff = i915_pm_poweroff,
 933         .restore = i915_pm_resume,
 934 };
 935
 936 static struct vm_operations_struct i915_gem_vm_ops = {
 937         .fault = i915_gem_fault,
 938         .open = drm_gem_vm_open,
 939         .close = drm_gem_vm_close,
 940 };
 941
 942 static const struct file_operations i915_driver_fops = {
 943         .owner = THIS_MODULE,
 944         .open = drm_open,
 945         .release = drm_release,
 946         .unlocked_ioctl = drm_ioctl,
 947         .mmap = drm_gem_mmap,
 948         .poll = drm_poll,
 949         .fasync = drm_fasync,
 950         .read = drm_read,
 951 #ifdef CONFIG_COMPAT
 952         .compat_ioctl = i915_compat_ioctl,
 953 #endif
 954         .llseek = noop_llseek,
 955 };
 956
 957 static struct drm_driver driver = {
 958         /* Don't use MTRRs here; the Xserver or userspace app should
 959          * deal with them for Intel hardware.
 960          */
 961         .driver_features =
 962             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 963             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 964         .load = i915_driver_load,
 965         .unload = i915_driver_unload,
 966         .open = i915_driver_open,
 967         .lastclose = i915_driver_lastclose,
 968         .preclose = i915_driver_preclose,
 969         .postclose = i915_driver_postclose,
 970
 971         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 972         .suspend = i915_suspend,
 973         .resume = i915_resume,
 974
 975         .device_is_agp = i915_driver_device_is_agp,
 976         .reclaim_buffers = drm_core_reclaim_buffers,
 977         .master_create = i915_master_create,
 978         .master_destroy = i915_master_destroy,
 979 #if defined(CONFIG_DEBUG_FS)
 980         .debugfs_init = i915_debugfs_init,
 981         .debugfs_cleanup = i915_debugfs_cleanup,
 982 #endif
 983         .gem_init_object = i915_gem_init_object,
 984         .gem_free_object = i915_gem_free_object,
 985         .gem_vm_ops = &i915_gem_vm_ops,
 986         .dumb_create = i915_gem_dumb_create,
 987         .dumb_map_offset = i915_gem_mmap_gtt,
 988         .dumb_destroy = i915_gem_dumb_destroy,
 989         .ioctls = i915_ioctls,
 990         .fops = &i915_driver_fops,
 991         .name = DRIVER_NAME,
 992         .desc = DRIVER_DESC,
 993         .date = DRIVER_DATE,
 994         .major = DRIVER_MAJOR,
 995         .minor = DRIVER_MINOR,
 996         .patchlevel = DRIVER_PATCHLEVEL,
 997 };
 998
 999 static struct pci_driver i915_pci_driver = {
1000         .name = DRIVER_NAME,
1001         .id_table = pciidlist,
1002         .probe = i915_pci_probe,
1003         .remove = i915_pci_remove,
1004         .driver.pm = &i915_pm_ops,
1005 };
1006
1007 static int __init i915_init(void)
1008 {
1009         if (!intel_agp_enabled) {
1010                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1011                 return -ENODEV;
1012         }
1013
1014         driver.num_ioctls = i915_max_ioctl;
1015
1016         /*
1017          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1018          * explicitly disabled with the module pararmeter.
1019          *
1020          * Otherwise, just follow the parameter (defaulting to off).
1021          *
1022          * Allow optional vga_text_mode_force boot option to override
1023          * the default behavior.
1024          */
1025 #if defined(CONFIG_DRM_I915_KMS)
1026         if (i915_modeset != 0)
1027                 driver.driver_features |= DRIVER_MODESET;
1028 #endif
1029         if (i915_modeset == 1)
1030                 driver.driver_features |= DRIVER_MODESET;
1031
1032 #ifdef CONFIG_VGA_CONSOLE
1033         if (vgacon_text_force() && i915_modeset == -1)
1034                 driver.driver_features &= ~DRIVER_MODESET;
1035 #endif
1036
1037         if (!(driver.driver_features & DRIVER_MODESET))
1038                 driver.get_vblank_timestamp = NULL;
1039
1040         return drm_pci_init(&driver, &i915_pci_driver);
1041 }
1042
1043 static void __exit i915_exit(void)
1044 {
1045         drm_pci_exit(&driver, &i915_pci_driver);
1046 }
1047
1048 module_init(i915_init);
1049 module_exit(i915_exit);
1050
1051 MODULE_AUTHOR(DRIVER_AUTHOR);
1052 MODULE_DESCRIPTION(DRIVER_DESC);
1053 MODULE_LICENSE("GPL and additional rights");
1054
1055 /* We give fast paths for the really cool registers */
1056 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1057        (((dev_priv)->info->gen >= 6) && \
1058         ((reg) < 0x40000) &&            \
1059         ((reg) != FORCEWAKE)) && \
1060        (!IS_VALLEYVIEW((dev_priv)->dev))
1061
1062 #define __i915_read(x, y) \
1063 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1064         u##x val = 0; \
1065         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1066                 unsigned long irqflags; \
1067                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1068                 if (dev_priv->forcewake_count == 0) \
1069                         dev_priv->display.force_wake_get(dev_priv); \
1070                 val = read##y(dev_priv->regs + reg); \
1071                 if (dev_priv->forcewake_count == 0) \
1072                         dev_priv->display.force_wake_put(dev_priv); \
1073                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1074         } else { \
1075                 val = read##y(dev_priv->regs + reg); \
1076         } \
1077         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1078         return val; \
1079 }
1080
1081 __i915_read(8, b)
1082 __i915_read(16, w)
1083 __i915_read(32, l)
1084 __i915_read(64, q)
1085 #undef __i915_read
1086
1087 #define __i915_write(x, y) \
1088 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1089         u32 __fifo_ret = 0; \
1090         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1091         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1092                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1093         } \
1094         write##y(val, dev_priv->regs + reg); \
1095         if (unlikely(__fifo_ret)) { \
1096                 gen6_gt_check_fifodbg(dev_priv); \
1097         } \
1098 }
1099 __i915_write(8, b)
1100 __i915_write(16, w)
1101 __i915_write(32, l)
1102 __i915_write(64, q)
1103 #undef __i915_write