drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_lvds_channel_mode __read_mostly;
  84 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  85 MODULE_PARM_DESC(lvds_channel_mode,
  86                  "Specify LVDS channel mode "
  87                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  88
  89 int i915_panel_use_ssc __read_mostly = -1;
  90 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  91 MODULE_PARM_DESC(lvds_use_ssc,
  92                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  93                 "(default: auto from VBT)");
  94
  95 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  96 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  97 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  98                 "Override/Ignore selection of SDVO panel mode in the VBT "
  99                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 100
 101 static bool i915_try_reset __read_mostly = true;
 102 module_param_named(reset, i915_try_reset, bool, 0600);
 103 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 104
 105 bool i915_enable_hangcheck __read_mostly = true;
 106 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 107 MODULE_PARM_DESC(enable_hangcheck,
 108                 "Periodically check GPU activity for detecting hangs. "
 109                 "WARNING: Disabling this can cause system wide hangs. "
 110                 "(default: true)");
 111
 112 bool i915_enable_ppgtt __read_mostly = 1;
 113 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 114 MODULE_PARM_DESC(i915_enable_ppgtt,
 115                 "Enable PPGTT (default: true)");
 116
 117 static struct drm_driver driver;
 118 extern int intel_agp_enabled;
 119
 120 #define INTEL_VGA_DEVICE(id, info) {            \
 121         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 122         .class_mask = 0xff0000,                 \
 123         .vendor = 0x8086,                       \
 124         .device = id,                           \
 125         .subvendor = PCI_ANY_ID,                \
 126         .subdevice = PCI_ANY_ID,                \
 127         .driver_data = (unsigned long) info }
 128
 129 static const struct intel_device_info intel_i830_info = {
 130         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_845g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i85x_info = {
 140         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 141         .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_i865g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i915g_info = {
 151         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153 };
 154 static const struct intel_device_info intel_i915gm_info = {
 155         .gen = 3, .is_mobile = 1,
 156         .cursor_needs_physical = 1,
 157         .has_overlay = 1, .overlay_needs_physical = 1,
 158         .supports_tv = 1,
 159 };
 160 static const struct intel_device_info intel_i945g_info = {
 161         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163 };
 164 static const struct intel_device_info intel_i945gm_info = {
 165         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 166         .has_hotplug = 1, .cursor_needs_physical = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .supports_tv = 1,
 169 };
 170
 171 static const struct intel_device_info intel_i965g_info = {
 172         .gen = 4, .is_broadwater = 1,
 173         .has_hotplug = 1,
 174         .has_overlay = 1,
 175 };
 176
 177 static const struct intel_device_info intel_i965gm_info = {
 178         .gen = 4, .is_crestline = 1,
 179         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 180         .has_overlay = 1,
 181         .supports_tv = 1,
 182 };
 183
 184 static const struct intel_device_info intel_g33_info = {
 185         .gen = 3, .is_g33 = 1,
 186         .need_gfx_hws = 1, .has_hotplug = 1,
 187         .has_overlay = 1,
 188 };
 189
 190 static const struct intel_device_info intel_g45_info = {
 191         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 192         .has_pipe_cxsr = 1, .has_hotplug = 1,
 193         .has_bsd_ring = 1,
 194 };
 195
 196 static const struct intel_device_info intel_gm45_info = {
 197         .gen = 4, .is_g4x = 1,
 198         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 199         .has_pipe_cxsr = 1, .has_hotplug = 1,
 200         .supports_tv = 1,
 201         .has_bsd_ring = 1,
 202 };
 203
 204 static const struct intel_device_info intel_pineview_info = {
 205         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 206         .need_gfx_hws = 1, .has_hotplug = 1,
 207         .has_overlay = 1,
 208 };
 209
 210 static const struct intel_device_info intel_ironlake_d_info = {
 211         .gen = 5,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_bsd_ring = 1,
 214         .has_pch_split = 1,
 215 };
 216
 217 static const struct intel_device_info intel_ironlake_m_info = {
 218         .gen = 5, .is_mobile = 1,
 219         .need_gfx_hws = 1, .has_hotplug = 1,
 220         .has_fbc = 1,
 221         .has_bsd_ring = 1,
 222         .has_pch_split = 1,
 223 };
 224
 225 static const struct intel_device_info intel_sandybridge_d_info = {
 226         .gen = 6,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_bsd_ring = 1,
 229         .has_blt_ring = 1,
 230         .has_llc = 1,
 231         .has_pch_split = 1,
 232 };
 233
 234 static const struct intel_device_info intel_sandybridge_m_info = {
 235         .gen = 6, .is_mobile = 1,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_fbc = 1,
 238         .has_bsd_ring = 1,
 239         .has_blt_ring = 1,
 240         .has_llc = 1,
 241         .has_pch_split = 1,
 242 };
 243
 244 static const struct intel_device_info intel_ivybridge_d_info = {
 245         .is_ivybridge = 1, .gen = 7,
 246         .need_gfx_hws = 1, .has_hotplug = 1,
 247         .has_bsd_ring = 1,
 248         .has_blt_ring = 1,
 249         .has_llc = 1,
 250         .has_pch_split = 1,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_m_info = {
 254         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 255         .need_gfx_hws = 1, .has_hotplug = 1,
 256         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 257         .has_bsd_ring = 1,
 258         .has_blt_ring = 1,
 259         .has_llc = 1,
 260         .has_pch_split = 1,
 261 };
 262
 263 static const struct intel_device_info intel_valleyview_m_info = {
 264         .gen = 7, .is_mobile = 1,
 265         .need_gfx_hws = 1, .has_hotplug = 1,
 266         .has_fbc = 0,
 267         .has_bsd_ring = 1,
 268         .has_blt_ring = 1,
 269         .is_valleyview = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_d_info = {
 273         .gen = 7,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279 };
 280
 281 static const struct pci_device_id pciidlist[] = {               /* aka */
 282         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 283         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 284         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 285         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 286         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 287         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 288         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 289         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 290         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 291         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 292         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 293         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 294         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 295         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 296         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 297         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 298         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 299         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 300         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 301         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 302         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 303         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 304         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 305         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 306         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 307         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 308         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 309         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 310         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 311         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 312         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 313         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 314         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 315         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 316         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 317         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 318         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 319         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 320         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 321         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 322         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 323         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 324         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 325         {0, 0, 0}
 326 };
 327
 328 #if defined(CONFIG_DRM_I915_KMS)
 329 MODULE_DEVICE_TABLE(pci, pciidlist);
 330 #endif
 331
 332 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 333 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 334 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 335 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 336
 337 void intel_detect_pch(struct drm_device *dev)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         struct pci_dev *pch;
 341
 342         /*
 343          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 344          * make graphics device passthrough work easy for VMM, that only
 345          * need to expose ISA bridge to let driver know the real hardware
 346          * underneath. This is a requirement from virtualization team.
 347          */
 348         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 349         if (pch) {
 350                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 351                         int id;
 352                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 353
 354                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 355                                 dev_priv->pch_type = PCH_IBX;
 356                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 357                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 358                                 dev_priv->pch_type = PCH_CPT;
 359                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 360                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 361                                 /* PantherPoint is CPT compatible */
 362                                 dev_priv->pch_type = PCH_CPT;
 363                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 364                         }
 365                 }
 366                 pci_dev_put(pch);
 367         }
 368 }
 369
 370 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 371 {
 372         int count;
 373
 374         count = 0;
 375         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 376                 udelay(10);
 377
 378         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 379         POSTING_READ(FORCEWAKE);
 380
 381         count = 0;
 382         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 383                 udelay(10);
 384 }
 385
 386 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 387 {
 388         int count;
 389
 390         count = 0;
 391         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 392                 udelay(10);
 393
 394         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 395         POSTING_READ(FORCEWAKE_MT);
 396
 397         count = 0;
 398         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 399                 udelay(10);
 400 }
 401
 402 /*
 403  * Generally this is called implicitly by the register read function. However,
 404  * if some sequence requires the GT to not power down then this function should
 405  * be called at the beginning of the sequence followed by a call to
 406  * gen6_gt_force_wake_put() at the end of the sequence.
 407  */
 408 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 409 {
 410         unsigned long irqflags;
 411
 412         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 413         if (dev_priv->forcewake_count++ == 0)
 414                 dev_priv->display.force_wake_get(dev_priv);
 415         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 416 }
 417
 418 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 419 {
 420         u32 gtfifodbg;
 421         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 422         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 423              "MMIO read or write has been dropped %x\n", gtfifodbg))
 424                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 425 }
 426
 427 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 428 {
 429         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 430         /* The below doubles as a POSTING_READ */
 431         gen6_gt_check_fifodbg(dev_priv);
 432 }
 433
 434 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 435 {
 436         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 437         /* The below doubles as a POSTING_READ */
 438         gen6_gt_check_fifodbg(dev_priv);
 439 }
 440
 441 /*
 442  * see gen6_gt_force_wake_get()
 443  */
 444 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 445 {
 446         unsigned long irqflags;
 447
 448         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 449         if (--dev_priv->forcewake_count == 0)
 450                 dev_priv->display.force_wake_put(dev_priv);
 451         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 452 }
 453
 454 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 455 {
 456         int ret = 0;
 457
 458         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 459                 int loop = 500;
 460                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 461                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 462                         udelay(10);
 463                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 464                 }
 465                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 466                         ++ret;
 467                 dev_priv->gt_fifo_count = fifo;
 468         }
 469         dev_priv->gt_fifo_count--;
 470
 471         return ret;
 472 }
 473
 474 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 475 {
 476         int count;
 477
 478         count = 0;
 479
 480         /* Already awake? */
 481         if ((I915_READ(0x130094) & 0xa1) == 0xa1)
 482                 return;
 483
 484         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
 485         POSTING_READ(FORCEWAKE_VLV);
 486
 487         count = 0;
 488         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
 489                 udelay(10);
 490 }
 491
 492 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 493 {
 494         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
 495         /* FIXME: confirm VLV behavior with Punit folks */
 496         POSTING_READ(FORCEWAKE_VLV);
 497 }
 498
 499 static int i915_drm_freeze(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502
 503         drm_kms_helper_poll_disable(dev);
 504
 505         pci_save_state(dev->pdev);
 506
 507         /* If KMS is active, we do the leavevt stuff here */
 508         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 509                 int error = i915_gem_idle(dev);
 510                 if (error) {
 511                         dev_err(&dev->pdev->dev,
 512                                 "GEM idle failed, resume might fail\n");
 513                         return error;
 514                 }
 515                 drm_irq_uninstall(dev);
 516         }
 517
 518         i915_save_state(dev);
 519
 520         intel_opregion_fini(dev);
 521
 522         /* Modeset on resume, not lid events */
 523         dev_priv->modeset_on_lid = 0;
 524
 525         return 0;
 526 }
 527
 528 int i915_suspend(struct drm_device *dev, pm_message_t state)
 529 {
 530         int error;
 531
 532         if (!dev || !dev->dev_private) {
 533                 DRM_ERROR("dev: %p\n", dev);
 534                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 535                 return -ENODEV;
 536         }
 537
 538         if (state.event == PM_EVENT_PRETHAW)
 539                 return 0;
 540
 541
 542         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 543                 return 0;
 544
 545         error = i915_drm_freeze(dev);
 546         if (error)
 547                 return error;
 548
 549         if (state.event == PM_EVENT_SUSPEND) {
 550                 /* Shut down the device */
 551                 pci_disable_device(dev->pdev);
 552                 pci_set_power_state(dev->pdev, PCI_D3hot);
 553         }
 554
 555         return 0;
 556 }
 557
 558 static int i915_drm_thaw(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         int error = 0;
 562
 563         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 564                 mutex_lock(&dev->struct_mutex);
 565                 i915_gem_restore_gtt_mappings(dev);
 566                 mutex_unlock(&dev->struct_mutex);
 567         }
 568
 569         i915_restore_state(dev);
 570         intel_opregion_setup(dev);
 571
 572         /* KMS EnterVT equivalent */
 573         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 574                 mutex_lock(&dev->struct_mutex);
 575                 dev_priv->mm.suspended = 0;
 576
 577                 error = i915_gem_init_hw(dev);
 578                 mutex_unlock(&dev->struct_mutex);
 579
 580                 if (HAS_PCH_SPLIT(dev))
 581                         ironlake_init_pch_refclk(dev);
 582
 583                 drm_mode_config_reset(dev);
 584                 drm_irq_install(dev);
 585
 586                 /* Resume the modeset for every activated CRTC */
 587                 drm_helper_resume_force_mode(dev);
 588
 589                 if (IS_IRONLAKE_M(dev))
 590                         ironlake_enable_rc6(dev);
 591         }
 592
 593         intel_opregion_init(dev);
 594
 595         dev_priv->modeset_on_lid = 0;
 596
 597         return error;
 598 }
 599
 600 int i915_resume(struct drm_device *dev)
 601 {
 602         int ret;
 603
 604         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 605                 return 0;
 606
 607         if (pci_enable_device(dev->pdev))
 608                 return -EIO;
 609
 610         pci_set_master(dev->pdev);
 611
 612         ret = i915_drm_thaw(dev);
 613         if (ret)
 614                 return ret;
 615
 616         drm_kms_helper_poll_enable(dev);
 617         return 0;
 618 }
 619
 620 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 621 {
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623
 624         if (IS_I85X(dev))
 625                 return -ENODEV;
 626
 627         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 628         POSTING_READ(D_STATE);
 629
 630         if (IS_I830(dev) || IS_845G(dev)) {
 631                 I915_WRITE(DEBUG_RESET_I830,
 632                            DEBUG_RESET_DISPLAY |
 633                            DEBUG_RESET_RENDER |
 634                            DEBUG_RESET_FULL);
 635                 POSTING_READ(DEBUG_RESET_I830);
 636                 msleep(1);
 637
 638                 I915_WRITE(DEBUG_RESET_I830, 0);
 639                 POSTING_READ(DEBUG_RESET_I830);
 640         }
 641
 642         msleep(1);
 643
 644         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 645         POSTING_READ(D_STATE);
 646
 647         return 0;
 648 }
 649
 650 static int i965_reset_complete(struct drm_device *dev)
 651 {
 652         u8 gdrst;
 653         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 654         return gdrst & 0x1;
 655 }
 656
 657 static int i965_do_reset(struct drm_device *dev, u8 flags)
 658 {
 659         u8 gdrst;
 660
 661         /*
 662          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 663          * well as the reset bit (GR/bit 0).  Setting the GR bit
 664          * triggers the reset; when done, the hardware will clear it.
 665          */
 666         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 667         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 668
 669         return wait_for(i965_reset_complete(dev), 500);
 670 }
 671
 672 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 673 {
 674         struct drm_i915_private *dev_priv = dev->dev_private;
 675         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 676         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 677         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 678 }
 679
 680 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 681 {
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         int     ret;
 684         unsigned long irqflags;
 685
 686         /* Hold gt_lock across reset to prevent any register access
 687          * with forcewake not set correctly
 688          */
 689         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 690
 691         /* Reset the chip */
 692
 693         /* GEN6_GDRST is not in the gt power well, no need to check
 694          * for fifo space for the write or forcewake the chip for
 695          * the read
 696          */
 697         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 698
 699         /* Spin waiting for the device to ack the reset request */
 700         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 701
 702         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 703         if (dev_priv->forcewake_count)
 704                 dev_priv->display.force_wake_get(dev_priv);
 705         else
 706                 dev_priv->display.force_wake_put(dev_priv);
 707
 708         /* Restore fifo count */
 709         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 710
 711         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 712         return ret;
 713 }
 714
 715 /**
 716  * i915_reset - reset chip after a hang
 717  * @dev: drm device to reset
 718  * @flags: reset domains
 719  *
 720  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 721  * reset or otherwise an error code.
 722  *
 723  * Procedure is fairly simple:
 724  *   - reset the chip using the reset reg
 725  *   - re-init context state
 726  *   - re-init hardware status page
 727  *   - re-init ring buffer
 728  *   - re-init interrupt state
 729  *   - re-init display
 730  */
 731 int i915_reset(struct drm_device *dev, u8 flags)
 732 {
 733         drm_i915_private_t *dev_priv = dev->dev_private;
 734         /*
 735          * We really should only reset the display subsystem if we actually
 736          * need to
 737          */
 738         bool need_display = true;
 739         int ret;
 740
 741         if (!i915_try_reset)
 742                 return 0;
 743
 744         if (!mutex_trylock(&dev->struct_mutex))
 745                 return -EBUSY;
 746
 747         i915_gem_reset(dev);
 748
 749         ret = -ENODEV;
 750         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 751                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 752         } else switch (INTEL_INFO(dev)->gen) {
 753         case 7:
 754         case 6:
 755                 ret = gen6_do_reset(dev, flags);
 756                 break;
 757         case 5:
 758                 ret = ironlake_do_reset(dev, flags);
 759                 break;
 760         case 4:
 761                 ret = i965_do_reset(dev, flags);
 762                 break;
 763         case 2:
 764                 ret = i8xx_do_reset(dev, flags);
 765                 break;
 766         }
 767         dev_priv->last_gpu_reset = get_seconds();
 768         if (ret) {
 769                 DRM_ERROR("Failed to reset chip.\n");
 770                 mutex_unlock(&dev->struct_mutex);
 771                 return ret;
 772         }
 773
 774         /* Ok, now get things going again... */
 775
 776         /*
 777          * Everything depends on having the GTT running, so we need to start
 778          * there.  Fortunately we don't need to do this unless we reset the
 779          * chip at a PCI level.
 780          *
 781          * Next we need to restore the context, but we don't use those
 782          * yet either...
 783          *
 784          * Ring buffer needs to be re-initialized in the KMS case, or if X
 785          * was running at the time of the reset (i.e. we weren't VT
 786          * switched away).
 787          */
 788         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 789                         !dev_priv->mm.suspended) {
 790                 dev_priv->mm.suspended = 0;
 791
 792                 i915_gem_init_swizzling(dev);
 793
 794                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 795                 if (HAS_BSD(dev))
 796                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 797                 if (HAS_BLT(dev))
 798                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 799
 800                 i915_gem_init_ppgtt(dev);
 801
 802                 mutex_unlock(&dev->struct_mutex);
 803                 drm_irq_uninstall(dev);
 804                 drm_mode_config_reset(dev);
 805                 drm_irq_install(dev);
 806                 mutex_lock(&dev->struct_mutex);
 807         }
 808
 809         mutex_unlock(&dev->struct_mutex);
 810
 811         /*
 812          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 813          * need to retrain the display link and cannot just restore the register
 814          * values.
 815          */
 816         if (need_display) {
 817                 mutex_lock(&dev->mode_config.mutex);
 818                 drm_helper_resume_force_mode(dev);
 819                 mutex_unlock(&dev->mode_config.mutex);
 820         }
 821
 822         return 0;
 823 }
 824
 825
 826 static int __devinit
 827 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 828 {
 829         /* Only bind to function 0 of the device. Early generations
 830          * used function 1 as a placeholder for multi-head. This causes
 831          * us confusion instead, especially on the systems where both
 832          * functions have the same PCI-ID!
 833          */
 834         if (PCI_FUNC(pdev->devfn))
 835                 return -ENODEV;
 836
 837         return drm_get_pci_dev(pdev, ent, &driver);
 838 }
 839
 840 static void
 841 i915_pci_remove(struct pci_dev *pdev)
 842 {
 843         struct drm_device *dev = pci_get_drvdata(pdev);
 844
 845         drm_put_dev(dev);
 846 }
 847
 848 static int i915_pm_suspend(struct device *dev)
 849 {
 850         struct pci_dev *pdev = to_pci_dev(dev);
 851         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 852         int error;
 853
 854         if (!drm_dev || !drm_dev->dev_private) {
 855                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 856                 return -ENODEV;
 857         }
 858
 859         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 860                 return 0;
 861
 862         error = i915_drm_freeze(drm_dev);
 863         if (error)
 864                 return error;
 865
 866         pci_disable_device(pdev);
 867         pci_set_power_state(pdev, PCI_D3hot);
 868
 869         return 0;
 870 }
 871
 872 static int i915_pm_resume(struct device *dev)
 873 {
 874         struct pci_dev *pdev = to_pci_dev(dev);
 875         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 876
 877         return i915_resume(drm_dev);
 878 }
 879
 880 static int i915_pm_freeze(struct device *dev)
 881 {
 882         struct pci_dev *pdev = to_pci_dev(dev);
 883         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 884
 885         if (!drm_dev || !drm_dev->dev_private) {
 886                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 887                 return -ENODEV;
 888         }
 889
 890         return i915_drm_freeze(drm_dev);
 891 }
 892
 893 static int i915_pm_thaw(struct device *dev)
 894 {
 895         struct pci_dev *pdev = to_pci_dev(dev);
 896         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 897
 898         return i915_drm_thaw(drm_dev);
 899 }
 900
 901 static int i915_pm_poweroff(struct device *dev)
 902 {
 903         struct pci_dev *pdev = to_pci_dev(dev);
 904         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 905
 906         return i915_drm_freeze(drm_dev);
 907 }
 908
 909 static const struct dev_pm_ops i915_pm_ops = {
 910         .suspend = i915_pm_suspend,
 911         .resume = i915_pm_resume,
 912         .freeze = i915_pm_freeze,
 913         .thaw = i915_pm_thaw,
 914         .poweroff = i915_pm_poweroff,
 915         .restore = i915_pm_resume,
 916 };
 917
 918 static struct vm_operations_struct i915_gem_vm_ops = {
 919         .fault = i915_gem_fault,
 920         .open = drm_gem_vm_open,
 921         .close = drm_gem_vm_close,
 922 };
 923
 924 static const struct file_operations i915_driver_fops = {
 925         .owner = THIS_MODULE,
 926         .open = drm_open,
 927         .release = drm_release,
 928         .unlocked_ioctl = drm_ioctl,
 929         .mmap = drm_gem_mmap,
 930         .poll = drm_poll,
 931         .fasync = drm_fasync,
 932         .read = drm_read,
 933 #ifdef CONFIG_COMPAT
 934         .compat_ioctl = i915_compat_ioctl,
 935 #endif
 936         .llseek = noop_llseek,
 937 };
 938
 939 static struct drm_driver driver = {
 940         /* Don't use MTRRs here; the Xserver or userspace app should
 941          * deal with them for Intel hardware.
 942          */
 943         .driver_features =
 944             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 945             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 946         .load = i915_driver_load,
 947         .unload = i915_driver_unload,
 948         .open = i915_driver_open,
 949         .lastclose = i915_driver_lastclose,
 950         .preclose = i915_driver_preclose,
 951         .postclose = i915_driver_postclose,
 952
 953         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 954         .suspend = i915_suspend,
 955         .resume = i915_resume,
 956
 957         .device_is_agp = i915_driver_device_is_agp,
 958         .reclaim_buffers = drm_core_reclaim_buffers,
 959         .master_create = i915_master_create,
 960         .master_destroy = i915_master_destroy,
 961 #if defined(CONFIG_DEBUG_FS)
 962         .debugfs_init = i915_debugfs_init,
 963         .debugfs_cleanup = i915_debugfs_cleanup,
 964 #endif
 965         .gem_init_object = i915_gem_init_object,
 966         .gem_free_object = i915_gem_free_object,
 967         .gem_vm_ops = &i915_gem_vm_ops,
 968         .dumb_create = i915_gem_dumb_create,
 969         .dumb_map_offset = i915_gem_mmap_gtt,
 970         .dumb_destroy = i915_gem_dumb_destroy,
 971         .ioctls = i915_ioctls,
 972         .fops = &i915_driver_fops,
 973         .name = DRIVER_NAME,
 974         .desc = DRIVER_DESC,
 975         .date = DRIVER_DATE,
 976         .major = DRIVER_MAJOR,
 977         .minor = DRIVER_MINOR,
 978         .patchlevel = DRIVER_PATCHLEVEL,
 979 };
 980
 981 static struct pci_driver i915_pci_driver = {
 982         .name = DRIVER_NAME,
 983         .id_table = pciidlist,
 984         .probe = i915_pci_probe,
 985         .remove = i915_pci_remove,
 986         .driver.pm = &i915_pm_ops,
 987 };
 988
 989 static int __init i915_init(void)
 990 {
 991         if (!intel_agp_enabled) {
 992                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 993                 return -ENODEV;
 994         }
 995
 996         driver.num_ioctls = i915_max_ioctl;
 997
 998         /*
 999          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1000          * explicitly disabled with the module pararmeter.
1001          *
1002          * Otherwise, just follow the parameter (defaulting to off).
1003          *
1004          * Allow optional vga_text_mode_force boot option to override
1005          * the default behavior.
1006          */
1007 #if defined(CONFIG_DRM_I915_KMS)
1008         if (i915_modeset != 0)
1009                 driver.driver_features |= DRIVER_MODESET;
1010 #endif
1011         if (i915_modeset == 1)
1012                 driver.driver_features |= DRIVER_MODESET;
1013
1014 #ifdef CONFIG_VGA_CONSOLE
1015         if (vgacon_text_force() && i915_modeset == -1)
1016                 driver.driver_features &= ~DRIVER_MODESET;
1017 #endif
1018
1019         if (!(driver.driver_features & DRIVER_MODESET))
1020                 driver.get_vblank_timestamp = NULL;
1021
1022         return drm_pci_init(&driver, &i915_pci_driver);
1023 }
1024
1025 static void __exit i915_exit(void)
1026 {
1027         drm_pci_exit(&driver, &i915_pci_driver);
1028 }
1029
1030 module_init(i915_init);
1031 module_exit(i915_exit);
1032
1033 MODULE_AUTHOR(DRIVER_AUTHOR);
1034 MODULE_DESCRIPTION(DRIVER_DESC);
1035 MODULE_LICENSE("GPL and additional rights");
1036
1037 /* We give fast paths for the really cool registers */
1038 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1039        (((dev_priv)->info->gen >= 6) && \
1040         ((reg) < 0x40000) &&            \
1041         ((reg) != FORCEWAKE)) && \
1042        (!IS_VALLEYVIEW((dev_priv)->dev))
1043
1044 #define __i915_read(x, y) \
1045 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1046         u##x val = 0; \
1047         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1048                 unsigned long irqflags; \
1049                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1050                 if (dev_priv->forcewake_count == 0) \
1051                         dev_priv->display.force_wake_get(dev_priv); \
1052                 val = read##y(dev_priv->regs + reg); \
1053                 if (dev_priv->forcewake_count == 0) \
1054                         dev_priv->display.force_wake_put(dev_priv); \
1055                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1056         } else { \
1057                 val = read##y(dev_priv->regs + reg); \
1058         } \
1059         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1060         return val; \
1061 }
1062
1063 __i915_read(8, b)
1064 __i915_read(16, w)
1065 __i915_read(32, l)
1066 __i915_read(64, q)
1067 #undef __i915_read
1068
1069 #define __i915_write(x, y) \
1070 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1071         u32 __fifo_ret = 0; \
1072         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1073         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1074                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1075         } \
1076         write##y(val, dev_priv->regs + reg); \
1077         if (unlikely(__fifo_ret)) { \
1078                 gen6_gt_check_fifodbg(dev_priv); \
1079         } \
1080 }
1081 __i915_write(8, b)
1082 __i915_write(16, w)
1083 __i915_write(32, l)
1084 __i915_write(64, q)
1085 #undef __i915_write