drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pnp.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/slab.h>
  42
  43 /**
  44  * Sets up the hardware status page for devices that need a physical address
  45  * in the register.
  46  */
  47 static int i915_init_phys_hws(struct drm_device *dev)
  48 {
  49         drm_i915_private_t *dev_priv = dev->dev_private;
  50         /* Program Hardware Status Page */
  51         dev_priv->status_page_dmah =
  52                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  53
  54         if (!dev_priv->status_page_dmah) {
  55                 DRM_ERROR("Can not allocate hardware status page\n");
  56                 return -ENOMEM;
  57         }
  58         dev_priv->render_ring.status_page.page_addr
  59                 = dev_priv->status_page_dmah->vaddr;
  60         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  61
  62         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  63
  64         if (IS_I965G(dev))
  65                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  66                                              0xf0;
  67
  68         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  69         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  70         return 0;
  71 }
  72
  73 /**
  74  * Frees the hardware status page, whether it's a physical address or a virtual
  75  * address set up by the X Server.
  76  */
  77 static void i915_free_hws(struct drm_device *dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         if (dev_priv->status_page_dmah) {
  81                 drm_pci_free(dev, dev_priv->status_page_dmah);
  82                 dev_priv->status_page_dmah = NULL;
  83         }
  84
  85         if (dev_priv->render_ring.status_page.gfx_addr) {
  86                 dev_priv->render_ring.status_page.gfx_addr = 0;
  87                 dev_priv->status_gfx_addr = 0;
  88                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  89         }
  90
  91         /* Need to rewrite hardware status page */
  92         I915_WRITE(HWS_PGA, 0x1ffff000);
  93 }
  94
  95 void i915_kernel_lost_context(struct drm_device * dev)
  96 {
  97         drm_i915_private_t *dev_priv = dev->dev_private;
  98         struct drm_i915_master_private *master_priv;
  99         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 100
 101         /*
 102          * We should never lose context on the ring with modesetting
 103          * as we don't expose it to userspace
 104          */
 105         if (drm_core_check_feature(dev, DRIVER_MODESET))
 106                 return;
 107
 108         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 109         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 110         ring->space = ring->head - (ring->tail + 8);
 111         if (ring->space < 0)
 112                 ring->space += ring->size;
 113
 114         if (!dev->primary->master)
 115                 return;
 116
 117         master_priv = dev->primary->master->driver_priv;
 118         if (ring->head == ring->tail && master_priv->sarea_priv)
 119                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 120 }
 121
 122 static int i915_dma_cleanup(struct drm_device * dev)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         /* Make sure interrupts are disabled here because the uninstall ioctl
 126          * may not have been called from userspace and after dev_private
 127          * is freed, it's too late.
 128          */
 129         if (dev->irq_enabled)
 130                 drm_irq_uninstall(dev);
 131
 132         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 133
 134         /* Clear the HWS virtual address at teardown */
 135         if (I915_NEED_GFX_HWS(dev))
 136                 i915_free_hws(dev);
 137
 138         return 0;
 139 }
 140
 141 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 142 {
 143         drm_i915_private_t *dev_priv = dev->dev_private;
 144         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 145
 146         master_priv->sarea = drm_getsarea(dev);
 147         if (master_priv->sarea) {
 148                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 149                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 150         } else {
 151                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 152         }
 153
 154         if (init->ring_size != 0) {
 155                 if (dev_priv->render_ring.gem_object != NULL) {
 156                         i915_dma_cleanup(dev);
 157                         DRM_ERROR("Client tried to initialize ringbuffer in "
 158                                   "GEM mode\n");
 159                         return -EINVAL;
 160                 }
 161
 162                 dev_priv->render_ring.size = init->ring_size;
 163
 164                 dev_priv->render_ring.map.offset = init->ring_start;
 165                 dev_priv->render_ring.map.size = init->ring_size;
 166                 dev_priv->render_ring.map.type = 0;
 167                 dev_priv->render_ring.map.flags = 0;
 168                 dev_priv->render_ring.map.mtrr = 0;
 169
 170                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 171
 172                 if (dev_priv->render_ring.map.handle == NULL) {
 173                         i915_dma_cleanup(dev);
 174                         DRM_ERROR("can not ioremap virtual address for"
 175                                   " ring buffer\n");
 176                         return -ENOMEM;
 177                 }
 178         }
 179
 180         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 181
 182         dev_priv->cpp = init->cpp;
 183         dev_priv->back_offset = init->back_offset;
 184         dev_priv->front_offset = init->front_offset;
 185         dev_priv->current_page = 0;
 186         if (master_priv->sarea_priv)
 187                 master_priv->sarea_priv->pf_current_page = 0;
 188
 189         /* Allow hardware batchbuffers unless told otherwise.
 190          */
 191         dev_priv->allow_batchbuffer = 1;
 192
 193         return 0;
 194 }
 195
 196 static int i915_dma_resume(struct drm_device * dev)
 197 {
 198         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 199
 200         struct intel_ring_buffer *ring;
 201         DRM_DEBUG_DRIVER("%s\n", __func__);
 202
 203         ring = &dev_priv->render_ring;
 204
 205         if (ring->map.handle == NULL) {
 206                 DRM_ERROR("can not ioremap virtual address for"
 207                           " ring buffer\n");
 208                 return -ENOMEM;
 209         }
 210
 211         /* Program Hardware Status Page */
 212         if (!ring->status_page.page_addr) {
 213                 DRM_ERROR("Can not find hardware status page\n");
 214                 return -EINVAL;
 215         }
 216         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 217                                 ring->status_page.page_addr);
 218         if (ring->status_page.gfx_addr != 0)
 219                 ring->setup_status_page(dev, ring);
 220         else
 221                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 222
 223         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 224
 225         return 0;
 226 }
 227
 228 static int i915_dma_init(struct drm_device *dev, void *data,
 229                          struct drm_file *file_priv)
 230 {
 231         drm_i915_init_t *init = data;
 232         int retcode = 0;
 233
 234         switch (init->func) {
 235         case I915_INIT_DMA:
 236                 retcode = i915_initialize(dev, init);
 237                 break;
 238         case I915_CLEANUP_DMA:
 239                 retcode = i915_dma_cleanup(dev);
 240                 break;
 241         case I915_RESUME_DMA:
 242                 retcode = i915_dma_resume(dev);
 243                 break;
 244         default:
 245                 retcode = -EINVAL;
 246                 break;
 247         }
 248
 249         return retcode;
 250 }
 251
 252 /* Implement basically the same security restrictions as hardware does
 253  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 254  *
 255  * Most of the calculations below involve calculating the size of a
 256  * particular instruction.  It's important to get the size right as
 257  * that tells us where the next instruction to check is.  Any illegal
 258  * instruction detected will be given a size of zero, which is a
 259  * signal to abort the rest of the buffer.
 260  */
 261 static int do_validate_cmd(int cmd)
 262 {
 263         switch (((cmd >> 29) & 0x7)) {
 264         case 0x0:
 265                 switch ((cmd >> 23) & 0x3f) {
 266                 case 0x0:
 267                         return 1;       /* MI_NOOP */
 268                 case 0x4:
 269                         return 1;       /* MI_FLUSH */
 270                 default:
 271                         return 0;       /* disallow everything else */
 272                 }
 273                 break;
 274         case 0x1:
 275                 return 0;       /* reserved */
 276         case 0x2:
 277                 return (cmd & 0xff) + 2;        /* 2d commands */
 278         case 0x3:
 279                 if (((cmd >> 24) & 0x1f) <= 0x18)
 280                         return 1;
 281
 282                 switch ((cmd >> 24) & 0x1f) {
 283                 case 0x1c:
 284                         return 1;
 285                 case 0x1d:
 286                         switch ((cmd >> 16) & 0xff) {
 287                         case 0x3:
 288                                 return (cmd & 0x1f) + 2;
 289                         case 0x4:
 290                                 return (cmd & 0xf) + 2;
 291                         default:
 292                                 return (cmd & 0xffff) + 2;
 293                         }
 294                 case 0x1e:
 295                         if (cmd & (1 << 23))
 296                                 return (cmd & 0xffff) + 1;
 297                         else
 298                                 return 1;
 299                 case 0x1f:
 300                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 301                                 return (cmd & 0x1ffff) + 2;
 302                         else if (cmd & (1 << 17))       /* indirect random */
 303                                 if ((cmd & 0xffff) == 0)
 304                                         return 0;       /* unknown length, too hard */
 305                                 else
 306                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 307                         else
 308                                 return 2;       /* indirect sequential */
 309                 default:
 310                         return 0;
 311                 }
 312         default:
 313                 return 0;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int validate_cmd(int cmd)
 320 {
 321         int ret = do_validate_cmd(cmd);
 322
 323 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 324
 325         return ret;
 326 }
 327
 328 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 329 {
 330         drm_i915_private_t *dev_priv = dev->dev_private;
 331         int i;
 332
 333         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 334                 return -EINVAL;
 335
 336         BEGIN_LP_RING((dwords+1)&~1);
 337
 338         for (i = 0; i < dwords;) {
 339                 int cmd, sz;
 340
 341                 cmd = buffer[i];
 342
 343                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 344                         return -EINVAL;
 345
 346                 OUT_RING(cmd);
 347
 348                 while (++i, --sz) {
 349                         OUT_RING(buffer[i]);
 350                 }
 351         }
 352
 353         if (dwords & 1)
 354                 OUT_RING(0);
 355
 356         ADVANCE_LP_RING();
 357
 358         return 0;
 359 }
 360
 361 int
 362 i915_emit_box(struct drm_device *dev,
 363               struct drm_clip_rect *boxes,
 364               int i, int DR1, int DR4)
 365 {
 366         struct drm_clip_rect box = boxes[i];
 367
 368         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 369                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 370                           box.x1, box.y1, box.x2, box.y2);
 371                 return -EINVAL;
 372         }
 373
 374         if (IS_I965G(dev)) {
 375                 BEGIN_LP_RING(4);
 376                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 377                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 378                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 379                 OUT_RING(DR4);
 380                 ADVANCE_LP_RING();
 381         } else {
 382                 BEGIN_LP_RING(6);
 383                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 384                 OUT_RING(DR1);
 385                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 386                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 387                 OUT_RING(DR4);
 388                 OUT_RING(0);
 389                 ADVANCE_LP_RING();
 390         }
 391
 392         return 0;
 393 }
 394
 395 /* XXX: Emitting the counter should really be moved to part of the IRQ
 396  * emit. For now, do it in both places:
 397  */
 398
 399 static void i915_emit_breadcrumb(struct drm_device *dev)
 400 {
 401         drm_i915_private_t *dev_priv = dev->dev_private;
 402         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 403
 404         dev_priv->counter++;
 405         if (dev_priv->counter > 0x7FFFFFFFUL)
 406                 dev_priv->counter = 0;
 407         if (master_priv->sarea_priv)
 408                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 409
 410         BEGIN_LP_RING(4);
 411         OUT_RING(MI_STORE_DWORD_INDEX);
 412         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 413         OUT_RING(dev_priv->counter);
 414         OUT_RING(0);
 415         ADVANCE_LP_RING();
 416 }
 417
 418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 419                                    drm_i915_cmdbuffer_t *cmd,
 420                                    struct drm_clip_rect *cliprects,
 421                                    void *cmdbuf)
 422 {
 423         int nbox = cmd->num_cliprects;
 424         int i = 0, count, ret;
 425
 426         if (cmd->sz & 0x3) {
 427                 DRM_ERROR("alignment");
 428                 return -EINVAL;
 429         }
 430
 431         i915_kernel_lost_context(dev);
 432
 433         count = nbox ? nbox : 1;
 434
 435         for (i = 0; i < count; i++) {
 436                 if (i < nbox) {
 437                         ret = i915_emit_box(dev, cliprects, i,
 438                                             cmd->DR1, cmd->DR4);
 439                         if (ret)
 440                                 return ret;
 441                 }
 442
 443                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         i915_emit_breadcrumb(dev);
 449         return 0;
 450 }
 451
 452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 453                                      drm_i915_batchbuffer_t * batch,
 454                                      struct drm_clip_rect *cliprects)
 455 {
 456         int nbox = batch->num_cliprects;
 457         int i = 0, count;
 458
 459         if ((batch->start | batch->used) & 0x7) {
 460                 DRM_ERROR("alignment");
 461                 return -EINVAL;
 462         }
 463
 464         i915_kernel_lost_context(dev);
 465
 466         count = nbox ? nbox : 1;
 467
 468         for (i = 0; i < count; i++) {
 469                 if (i < nbox) {
 470                         int ret = i915_emit_box(dev, cliprects, i,
 471                                                 batch->DR1, batch->DR4);
 472                         if (ret)
 473                                 return ret;
 474                 }
 475
 476                 if (!IS_I830(dev) && !IS_845G(dev)) {
 477                         BEGIN_LP_RING(2);
 478                         if (IS_I965G(dev)) {
 479                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 480                                 OUT_RING(batch->start);
 481                         } else {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 483                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 484                         }
 485                         ADVANCE_LP_RING();
 486                 } else {
 487                         BEGIN_LP_RING(4);
 488                         OUT_RING(MI_BATCH_BUFFER);
 489                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 490                         OUT_RING(batch->start + batch->used - 4);
 491                         OUT_RING(0);
 492                         ADVANCE_LP_RING();
 493                 }
 494         }
 495
 496         i915_emit_breadcrumb(dev);
 497
 498         return 0;
 499 }
 500
 501 static int i915_dispatch_flip(struct drm_device * dev)
 502 {
 503         drm_i915_private_t *dev_priv = dev->dev_private;
 504         struct drm_i915_master_private *master_priv =
 505                 dev->primary->master->driver_priv;
 506
 507         if (!master_priv->sarea_priv)
 508                 return -EINVAL;
 509
 510         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 511                           __func__,
 512                          dev_priv->current_page,
 513                          master_priv->sarea_priv->pf_current_page);
 514
 515         i915_kernel_lost_context(dev);
 516
 517         BEGIN_LP_RING(2);
 518         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 519         OUT_RING(0);
 520         ADVANCE_LP_RING();
 521
 522         BEGIN_LP_RING(6);
 523         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 524         OUT_RING(0);
 525         if (dev_priv->current_page == 0) {
 526                 OUT_RING(dev_priv->back_offset);
 527                 dev_priv->current_page = 1;
 528         } else {
 529                 OUT_RING(dev_priv->front_offset);
 530                 dev_priv->current_page = 0;
 531         }
 532         OUT_RING(0);
 533         ADVANCE_LP_RING();
 534
 535         BEGIN_LP_RING(2);
 536         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 537         OUT_RING(0);
 538         ADVANCE_LP_RING();
 539
 540         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 541
 542         BEGIN_LP_RING(4);
 543         OUT_RING(MI_STORE_DWORD_INDEX);
 544         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 545         OUT_RING(dev_priv->counter);
 546         OUT_RING(0);
 547         ADVANCE_LP_RING();
 548
 549         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 550         return 0;
 551 }
 552
 553 static int i915_quiescent(struct drm_device * dev)
 554 {
 555         drm_i915_private_t *dev_priv = dev->dev_private;
 556
 557         i915_kernel_lost_context(dev);
 558         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 559                                       dev_priv->render_ring.size - 8);
 560 }
 561
 562 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 563                             struct drm_file *file_priv)
 564 {
 565         int ret;
 566
 567         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 568
 569         mutex_lock(&dev->struct_mutex);
 570         ret = i915_quiescent(dev);
 571         mutex_unlock(&dev->struct_mutex);
 572
 573         return ret;
 574 }
 575
 576 static int i915_batchbuffer(struct drm_device *dev, void *data,
 577                             struct drm_file *file_priv)
 578 {
 579         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 580         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 581         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 582             master_priv->sarea_priv;
 583         drm_i915_batchbuffer_t *batch = data;
 584         int ret;
 585         struct drm_clip_rect *cliprects = NULL;
 586
 587         if (!dev_priv->allow_batchbuffer) {
 588                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 589                 return -EINVAL;
 590         }
 591
 592         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 593                         batch->start, batch->used, batch->num_cliprects);
 594
 595         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 596
 597         if (batch->num_cliprects < 0)
 598                 return -EINVAL;
 599
 600         if (batch->num_cliprects) {
 601                 cliprects = kcalloc(batch->num_cliprects,
 602                                     sizeof(struct drm_clip_rect),
 603                                     GFP_KERNEL);
 604                 if (cliprects == NULL)
 605                         return -ENOMEM;
 606
 607                 ret = copy_from_user(cliprects, batch->cliprects,
 608                                      batch->num_cliprects *
 609                                      sizeof(struct drm_clip_rect));
 610                 if (ret != 0)
 611                         goto fail_free;
 612         }
 613
 614         mutex_lock(&dev->struct_mutex);
 615         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 616         mutex_unlock(&dev->struct_mutex);
 617
 618         if (sarea_priv)
 619                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 620
 621 fail_free:
 622         kfree(cliprects);
 623
 624         return ret;
 625 }
 626
 627 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 628                           struct drm_file *file_priv)
 629 {
 630         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 631         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 632         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 633             master_priv->sarea_priv;
 634         drm_i915_cmdbuffer_t *cmdbuf = data;
 635         struct drm_clip_rect *cliprects = NULL;
 636         void *batch_data;
 637         int ret;
 638
 639         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 640                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 641
 642         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 643
 644         if (cmdbuf->num_cliprects < 0)
 645                 return -EINVAL;
 646
 647         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 648         if (batch_data == NULL)
 649                 return -ENOMEM;
 650
 651         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 652         if (ret != 0)
 653                 goto fail_batch_free;
 654
 655         if (cmdbuf->num_cliprects) {
 656                 cliprects = kcalloc(cmdbuf->num_cliprects,
 657                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 658                 if (cliprects == NULL) {
 659                         ret = -ENOMEM;
 660                         goto fail_batch_free;
 661                 }
 662
 663                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 664                                      cmdbuf->num_cliprects *
 665                                      sizeof(struct drm_clip_rect));
 666                 if (ret != 0)
 667                         goto fail_clip_free;
 668         }
 669
 670         mutex_lock(&dev->struct_mutex);
 671         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 672         mutex_unlock(&dev->struct_mutex);
 673         if (ret) {
 674                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 675                 goto fail_clip_free;
 676         }
 677
 678         if (sarea_priv)
 679                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 680
 681 fail_clip_free:
 682         kfree(cliprects);
 683 fail_batch_free:
 684         kfree(batch_data);
 685
 686         return ret;
 687 }
 688
 689 static int i915_flip_bufs(struct drm_device *dev, void *data,
 690                           struct drm_file *file_priv)
 691 {
 692         int ret;
 693
 694         DRM_DEBUG_DRIVER("%s\n", __func__);
 695
 696         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 697
 698         mutex_lock(&dev->struct_mutex);
 699         ret = i915_dispatch_flip(dev);
 700         mutex_unlock(&dev->struct_mutex);
 701
 702         return ret;
 703 }
 704
 705 static int i915_getparam(struct drm_device *dev, void *data,
 706                          struct drm_file *file_priv)
 707 {
 708         drm_i915_private_t *dev_priv = dev->dev_private;
 709         drm_i915_getparam_t *param = data;
 710         int value;
 711
 712         if (!dev_priv) {
 713                 DRM_ERROR("called with no initialization\n");
 714                 return -EINVAL;
 715         }
 716
 717         switch (param->param) {
 718         case I915_PARAM_IRQ_ACTIVE:
 719                 value = dev->pdev->irq ? 1 : 0;
 720                 break;
 721         case I915_PARAM_ALLOW_BATCHBUFFER:
 722                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 723                 break;
 724         case I915_PARAM_LAST_DISPATCH:
 725                 value = READ_BREADCRUMB(dev_priv);
 726                 break;
 727         case I915_PARAM_CHIPSET_ID:
 728                 value = dev->pci_device;
 729                 break;
 730         case I915_PARAM_HAS_GEM:
 731                 value = dev_priv->has_gem;
 732                 break;
 733         case I915_PARAM_NUM_FENCES_AVAIL:
 734                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 735                 break;
 736         case I915_PARAM_HAS_OVERLAY:
 737                 value = dev_priv->overlay ? 1 : 0;
 738                 break;
 739         case I915_PARAM_HAS_PAGEFLIPPING:
 740                 value = 1;
 741                 break;
 742         case I915_PARAM_HAS_EXECBUF2:
 743                 /* depends on GEM */
 744                 value = dev_priv->has_gem;
 745                 break;
 746         default:
 747                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 748                                  param->param);
 749                 return -EINVAL;
 750         }
 751
 752         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 753                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 754                 return -EFAULT;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int i915_setparam(struct drm_device *dev, void *data,
 761                          struct drm_file *file_priv)
 762 {
 763         drm_i915_private_t *dev_priv = dev->dev_private;
 764         drm_i915_setparam_t *param = data;
 765
 766         if (!dev_priv) {
 767                 DRM_ERROR("called with no initialization\n");
 768                 return -EINVAL;
 769         }
 770
 771         switch (param->param) {
 772         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 773                 break;
 774         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 775                 dev_priv->tex_lru_log_granularity = param->value;
 776                 break;
 777         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 778                 dev_priv->allow_batchbuffer = param->value;
 779                 break;
 780         case I915_SETPARAM_NUM_USED_FENCES:
 781                 if (param->value > dev_priv->num_fence_regs ||
 782                     param->value < 0)
 783                         return -EINVAL;
 784                 /* Userspace can use first N regs */
 785                 dev_priv->fence_reg_start = param->value;
 786                 break;
 787         default:
 788                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 789                                         param->param);
 790                 return -EINVAL;
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int i915_set_status_page(struct drm_device *dev, void *data,
 797                                 struct drm_file *file_priv)
 798 {
 799         drm_i915_private_t *dev_priv = dev->dev_private;
 800         drm_i915_hws_addr_t *hws = data;
 801         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 802
 803         if (!I915_NEED_GFX_HWS(dev))
 804                 return -EINVAL;
 805
 806         if (!dev_priv) {
 807                 DRM_ERROR("called with no initialization\n");
 808                 return -EINVAL;
 809         }
 810
 811         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 812                 WARN(1, "tried to set status page when mode setting active\n");
 813                 return 0;
 814         }
 815
 816         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 817
 818         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 819
 820         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 821         dev_priv->hws_map.size = 4*1024;
 822         dev_priv->hws_map.type = 0;
 823         dev_priv->hws_map.flags = 0;
 824         dev_priv->hws_map.mtrr = 0;
 825
 826         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 827         if (dev_priv->hws_map.handle == NULL) {
 828                 i915_dma_cleanup(dev);
 829                 dev_priv->status_gfx_addr = 0;
 830                 DRM_ERROR("can not ioremap virtual address for"
 831                                 " G33 hw status page\n");
 832                 return -ENOMEM;
 833         }
 834         ring->status_page.page_addr = dev_priv->hws_map.handle;
 835         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 836         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 837
 838         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 839                         dev_priv->status_gfx_addr);
 840         DRM_DEBUG_DRIVER("load hws at %p\n",
 841                         dev_priv->hw_status_page);
 842         return 0;
 843 }
 844
 845 static int i915_get_bridge_dev(struct drm_device *dev)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848
 849         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 850         if (!dev_priv->bridge_dev) {
 851                 DRM_ERROR("bridge device not found\n");
 852                 return -1;
 853         }
 854         return 0;
 855 }
 856
 857 #define MCHBAR_I915 0x44
 858 #define MCHBAR_I965 0x48
 859 #define MCHBAR_SIZE (4*4096)
 860
 861 #define DEVEN_REG 0x54
 862 #define   DEVEN_MCHBAR_EN (1 << 28)
 863
 864 /* Allocate space for the MCH regs if needed, return nonzero on error */
 865 static int
 866 intel_alloc_mchbar_resource(struct drm_device *dev)
 867 {
 868         drm_i915_private_t *dev_priv = dev->dev_private;
 869         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 870         u32 temp_lo, temp_hi = 0;
 871         u64 mchbar_addr;
 872         int ret = 0;
 873
 874         if (IS_I965G(dev))
 875                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 876         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 877         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 878
 879         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 880 #ifdef CONFIG_PNP
 881         if (mchbar_addr &&
 882             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 883                 ret = 0;
 884                 goto out;
 885         }
 886 #endif
 887
 888         /* Get some space for it */
 889         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 890                                      MCHBAR_SIZE, MCHBAR_SIZE,
 891                                      PCIBIOS_MIN_MEM,
 892                                      0,   pcibios_align_resource,
 893                                      dev_priv->bridge_dev);
 894         if (ret) {
 895                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 896                 dev_priv->mch_res.start = 0;
 897                 goto out;
 898         }
 899
 900         if (IS_I965G(dev))
 901                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 902                                        upper_32_bits(dev_priv->mch_res.start));
 903
 904         pci_write_config_dword(dev_priv->bridge_dev, reg,
 905                                lower_32_bits(dev_priv->mch_res.start));
 906 out:
 907         return ret;
 908 }
 909
 910 /* Setup MCHBAR if possible, return true if we should disable it again */
 911 static void
 912 intel_setup_mchbar(struct drm_device *dev)
 913 {
 914         drm_i915_private_t *dev_priv = dev->dev_private;
 915         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 916         u32 temp;
 917         bool enabled;
 918
 919         dev_priv->mchbar_need_disable = false;
 920
 921         if (IS_I915G(dev) || IS_I915GM(dev)) {
 922                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 923                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 924         } else {
 925                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 926                 enabled = temp & 1;
 927         }
 928
 929         /* If it's already enabled, don't have to do anything */
 930         if (enabled)
 931                 return;
 932
 933         if (intel_alloc_mchbar_resource(dev))
 934                 return;
 935
 936         dev_priv->mchbar_need_disable = true;
 937
 938         /* Space is allocated or reserved, so enable it. */
 939         if (IS_I915G(dev) || IS_I915GM(dev)) {
 940                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 941                                        temp | DEVEN_MCHBAR_EN);
 942         } else {
 943                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 944                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 945         }
 946 }
 947
 948 static void
 949 intel_teardown_mchbar(struct drm_device *dev)
 950 {
 951         drm_i915_private_t *dev_priv = dev->dev_private;
 952         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 953         u32 temp;
 954
 955         if (dev_priv->mchbar_need_disable) {
 956                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 957                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 958                         temp &= ~DEVEN_MCHBAR_EN;
 959                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 960                 } else {
 961                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 962                         temp &= ~1;
 963                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 964                 }
 965         }
 966
 967         if (dev_priv->mch_res.start)
 968                 release_resource(&dev_priv->mch_res);
 969 }
 970
 971 /**
 972  * i915_probe_agp - get AGP bootup configuration
 973  * @pdev: PCI device
 974  * @aperture_size: returns AGP aperture configured size
 975  * @preallocated_size: returns size of BIOS preallocated AGP space
 976  *
 977  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 978  * some RAM for the framebuffer at early boot.  This code figures out
 979  * how much was set aside so we can use it for our own purposes.
 980  */
 981 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 982                           uint32_t *preallocated_size,
 983                           uint32_t *start)
 984 {
 985         struct drm_i915_private *dev_priv = dev->dev_private;
 986         u16 tmp = 0;
 987         unsigned long overhead;
 988         unsigned long stolen;
 989
 990         /* Get the fb aperture size and "stolen" memory amount. */
 991         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 992
 993         *aperture_size = 1024 * 1024;
 994         *preallocated_size = 1024 * 1024;
 995
 996         switch (dev->pdev->device) {
 997         case PCI_DEVICE_ID_INTEL_82830_CGC:
 998         case PCI_DEVICE_ID_INTEL_82845G_IG:
 999         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1000         case PCI_DEVICE_ID_INTEL_82865_IG:
1001                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1002                         *aperture_size *= 64;
1003                 else
1004                         *aperture_size *= 128;
1005                 break;
1006         default:
1007                 /* 9xx supports large sizes, just look at the length */
1008                 *aperture_size = pci_resource_len(dev->pdev, 2);
1009                 break;
1010         }
1011
1012         /*
1013          * Some of the preallocated space is taken by the GTT
1014          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1015          */
1016         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1017                 overhead = 4096;
1018         else
1019                 overhead = (*aperture_size / 1024) + 4096;
1020
1021         if (IS_GEN6(dev)) {
1022                 /* SNB has memory control reg at 0x50.w */
1023                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1024
1025                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1026                 case INTEL_855_GMCH_GMS_DISABLED:
1027                         DRM_ERROR("video memory is disabled\n");
1028                         return -1;
1029                 case SNB_GMCH_GMS_STOLEN_32M:
1030                         stolen = 32 * 1024 * 1024;
1031                         break;
1032                 case SNB_GMCH_GMS_STOLEN_64M:
1033                         stolen = 64 * 1024 * 1024;
1034                         break;
1035                 case SNB_GMCH_GMS_STOLEN_96M:
1036                         stolen = 96 * 1024 * 1024;
1037                         break;
1038                 case SNB_GMCH_GMS_STOLEN_128M:
1039                         stolen = 128 * 1024 * 1024;
1040                         break;
1041                 case SNB_GMCH_GMS_STOLEN_160M:
1042                         stolen = 160 * 1024 * 1024;
1043                         break;
1044                 case SNB_GMCH_GMS_STOLEN_192M:
1045                         stolen = 192 * 1024 * 1024;
1046                         break;
1047                 case SNB_GMCH_GMS_STOLEN_224M:
1048                         stolen = 224 * 1024 * 1024;
1049                         break;
1050                 case SNB_GMCH_GMS_STOLEN_256M:
1051                         stolen = 256 * 1024 * 1024;
1052                         break;
1053                 case SNB_GMCH_GMS_STOLEN_288M:
1054                         stolen = 288 * 1024 * 1024;
1055                         break;
1056                 case SNB_GMCH_GMS_STOLEN_320M:
1057                         stolen = 320 * 1024 * 1024;
1058                         break;
1059                 case SNB_GMCH_GMS_STOLEN_352M:
1060                         stolen = 352 * 1024 * 1024;
1061                         break;
1062                 case SNB_GMCH_GMS_STOLEN_384M:
1063                         stolen = 384 * 1024 * 1024;
1064                         break;
1065                 case SNB_GMCH_GMS_STOLEN_416M:
1066                         stolen = 416 * 1024 * 1024;
1067                         break;
1068                 case SNB_GMCH_GMS_STOLEN_448M:
1069                         stolen = 448 * 1024 * 1024;
1070                         break;
1071                 case SNB_GMCH_GMS_STOLEN_480M:
1072                         stolen = 480 * 1024 * 1024;
1073                         break;
1074                 case SNB_GMCH_GMS_STOLEN_512M:
1075                         stolen = 512 * 1024 * 1024;
1076                         break;
1077                 default:
1078                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1079                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1080                         return -1;
1081                 }
1082         } else {
1083                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1084                 case INTEL_855_GMCH_GMS_DISABLED:
1085                         DRM_ERROR("video memory is disabled\n");
1086                         return -1;
1087                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1088                         stolen = 1 * 1024 * 1024;
1089                         break;
1090                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1091                         stolen = 4 * 1024 * 1024;
1092                         break;
1093                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1094                         stolen = 8 * 1024 * 1024;
1095                         break;
1096                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1097                         stolen = 16 * 1024 * 1024;
1098                         break;
1099                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1100                         stolen = 32 * 1024 * 1024;
1101                         break;
1102                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1103                         stolen = 48 * 1024 * 1024;
1104                         break;
1105                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1106                         stolen = 64 * 1024 * 1024;
1107                         break;
1108                 case INTEL_GMCH_GMS_STOLEN_128M:
1109                         stolen = 128 * 1024 * 1024;
1110                         break;
1111                 case INTEL_GMCH_GMS_STOLEN_256M:
1112                         stolen = 256 * 1024 * 1024;
1113                         break;
1114                 case INTEL_GMCH_GMS_STOLEN_96M:
1115                         stolen = 96 * 1024 * 1024;
1116                         break;
1117                 case INTEL_GMCH_GMS_STOLEN_160M:
1118                         stolen = 160 * 1024 * 1024;
1119                         break;
1120                 case INTEL_GMCH_GMS_STOLEN_224M:
1121                         stolen = 224 * 1024 * 1024;
1122                         break;
1123                 case INTEL_GMCH_GMS_STOLEN_352M:
1124                         stolen = 352 * 1024 * 1024;
1125                         break;
1126                 default:
1127                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1128                                   tmp & INTEL_GMCH_GMS_MASK);
1129                         return -1;
1130                 }
1131         }
1132
1133         *preallocated_size = stolen - overhead;
1134         *start = overhead;
1135
1136         return 0;
1137 }
1138
1139 #define PTE_ADDRESS_MASK                0xfffff000
1140 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1141 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1142 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1143 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1144 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1145 #define PTE_VALID                       (1 << 0)
1146
1147 /**
1148  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1149  * @dev: drm device
1150  * @gtt_addr: address to translate
1151  *
1152  * Some chip functions require allocations from stolen space but need the
1153  * physical address of the memory in question.  We use this routine
1154  * to get a physical address suitable for register programming from a given
1155  * GTT address.
1156  */
1157 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1158                                       unsigned long gtt_addr)
1159 {
1160         unsigned long *gtt;
1161         unsigned long entry, phys;
1162         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1163         int gtt_offset, gtt_size;
1164
1165         if (IS_I965G(dev)) {
1166                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1167                         gtt_offset = 2*1024*1024;
1168                         gtt_size = 2*1024*1024;
1169                 } else {
1170                         gtt_offset = 512*1024;
1171                         gtt_size = 512*1024;
1172                 }
1173         } else {
1174                 gtt_bar = 3;
1175                 gtt_offset = 0;
1176                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1177         }
1178
1179         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1180                          gtt_size);
1181         if (!gtt) {
1182                 DRM_ERROR("ioremap of GTT failed\n");
1183                 return 0;
1184         }
1185
1186         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1187
1188         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1189
1190         /* Mask out these reserved bits on this hardware. */
1191         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1192             IS_I945G(dev) || IS_I945GM(dev)) {
1193                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1194         }
1195
1196         /* If it's not a mapping type we know, then bail. */
1197         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1198             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1199                 iounmap(gtt);
1200                 return 0;
1201         }
1202
1203         if (!(entry & PTE_VALID)) {
1204                 DRM_ERROR("bad GTT entry in stolen space\n");
1205                 iounmap(gtt);
1206                 return 0;
1207         }
1208
1209         iounmap(gtt);
1210
1211         phys =(entry & PTE_ADDRESS_MASK) |
1212                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1213
1214         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1215
1216         return phys;
1217 }
1218
1219 static void i915_warn_stolen(struct drm_device *dev)
1220 {
1221         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1222         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1223 }
1224
1225 static void i915_setup_compression(struct drm_device *dev, int size)
1226 {
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         struct drm_mm_node *compressed_fb, *compressed_llb;
1229         unsigned long cfb_base;
1230         unsigned long ll_base = 0;
1231
1232         /* Leave 1M for line length buffer & misc. */
1233         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1234         if (!compressed_fb) {
1235                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1236                 i915_warn_stolen(dev);
1237                 return;
1238         }
1239
1240         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1241         if (!compressed_fb) {
1242                 i915_warn_stolen(dev);
1243                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1244                 return;
1245         }
1246
1247         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1248         if (!cfb_base) {
1249                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1250                 drm_mm_put_block(compressed_fb);
1251         }
1252
1253         if (!IS_GM45(dev)) {
1254                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1255                                                     4096, 0);
1256                 if (!compressed_llb) {
1257                         i915_warn_stolen(dev);
1258                         return;
1259                 }
1260
1261                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1262                 if (!compressed_llb) {
1263                         i915_warn_stolen(dev);
1264                         return;
1265                 }
1266
1267                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1268                 if (!ll_base) {
1269                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1270                         drm_mm_put_block(compressed_fb);
1271                         drm_mm_put_block(compressed_llb);
1272                 }
1273         }
1274
1275         dev_priv->cfb_size = size;
1276
1277         intel_disable_fbc(dev);
1278         dev_priv->compressed_fb = compressed_fb;
1279
1280         if (IS_GM45(dev)) {
1281                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1282         } else {
1283                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1284                 I915_WRITE(FBC_LL_BASE, ll_base);
1285                 dev_priv->compressed_llb = compressed_llb;
1286         }
1287
1288         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1289                   ll_base, size >> 20);
1290 }
1291
1292 static void i915_cleanup_compression(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         drm_mm_put_block(dev_priv->compressed_fb);
1297         if (!IS_GM45(dev))
1298                 drm_mm_put_block(dev_priv->compressed_llb);
1299 }
1300
1301 /* true = enable decode, false = disable decoder */
1302 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1303 {
1304         struct drm_device *dev = cookie;
1305
1306         intel_modeset_vga_set_state(dev, state);
1307         if (state)
1308                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1309                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1310         else
1311                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1312 }
1313
1314 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1315 {
1316         struct drm_device *dev = pci_get_drvdata(pdev);
1317         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1318         if (state == VGA_SWITCHEROO_ON) {
1319                 printk(KERN_INFO "i915: switched off\n");
1320                 /* i915 resume handler doesn't set to D0 */
1321                 pci_set_power_state(dev->pdev, PCI_D0);
1322                 i915_resume(dev);
1323         } else {
1324                 printk(KERN_ERR "i915: switched off\n");
1325                 i915_suspend(dev, pmm);
1326         }
1327 }
1328
1329 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1330 {
1331         struct drm_device *dev = pci_get_drvdata(pdev);
1332         bool can_switch;
1333
1334         spin_lock(&dev->count_lock);
1335         can_switch = (dev->open_count == 0);
1336         spin_unlock(&dev->count_lock);
1337         return can_switch;
1338 }
1339
1340 static int i915_load_modeset_init(struct drm_device *dev,
1341                                   unsigned long prealloc_start,
1342                                   unsigned long prealloc_size,
1343                                   unsigned long agp_size)
1344 {
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1347         int ret = 0;
1348
1349         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1350                 0xff000000;
1351
1352         /* Basic memrange allocator for stolen space (aka vram) */
1353         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1354         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1355
1356         /* We're off and running w/KMS */
1357         dev_priv->mm.suspended = 0;
1358
1359         /* Let GEM Manage from end of prealloc space to end of aperture.
1360          *
1361          * However, leave one page at the end still bound to the scratch page.
1362          * There are a number of places where the hardware apparently
1363          * prefetches past the end of the object, and we've seen multiple
1364          * hangs with the GPU head pointer stuck in a batchbuffer bound
1365          * at the last page of the aperture.  One page should be enough to
1366          * keep any prefetching inside of the aperture.
1367          */
1368         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1369
1370         mutex_lock(&dev->struct_mutex);
1371         ret = i915_gem_init_ringbuffer(dev);
1372         mutex_unlock(&dev->struct_mutex);
1373         if (ret)
1374                 goto out;
1375
1376         /* Try to set up FBC with a reasonable compressed buffer size */
1377         if (I915_HAS_FBC(dev) && i915_powersave) {
1378                 int cfb_size;
1379
1380                 /* Try to get an 8M buffer... */
1381                 if (prealloc_size > (9*1024*1024))
1382                         cfb_size = 8*1024*1024;
1383                 else /* fall back to 7/8 of the stolen space */
1384                         cfb_size = prealloc_size * 7 / 8;
1385                 i915_setup_compression(dev, cfb_size);
1386         }
1387
1388         /* Allow hardware batchbuffers unless told otherwise.
1389          */
1390         dev_priv->allow_batchbuffer = 1;
1391
1392         ret = intel_init_bios(dev);
1393         if (ret)
1394                 DRM_INFO("failed to find VBIOS tables\n");
1395
1396         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1397         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1398         if (ret)
1399                 goto destroy_ringbuffer;
1400
1401         ret = vga_switcheroo_register_client(dev->pdev,
1402                                              i915_switcheroo_set_state,
1403                                              i915_switcheroo_can_switch);
1404         if (ret)
1405                 goto destroy_ringbuffer;
1406
1407         intel_modeset_init(dev);
1408
1409         ret = drm_irq_install(dev);
1410         if (ret)
1411                 goto destroy_ringbuffer;
1412
1413         /* Always safe in the mode setting case. */
1414         /* FIXME: do pre/post-mode set stuff in core KMS code */
1415         dev->vblank_disable_allowed = 1;
1416
1417         /*
1418          * Initialize the hardware status page IRQ location.
1419          */
1420
1421         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1422
1423         intel_fbdev_init(dev);
1424         drm_kms_helper_poll_init(dev);
1425         return 0;
1426
1427 destroy_ringbuffer:
1428         mutex_lock(&dev->struct_mutex);
1429         i915_gem_cleanup_ringbuffer(dev);
1430         mutex_unlock(&dev->struct_mutex);
1431 out:
1432         return ret;
1433 }
1434
1435 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1436 {
1437         struct drm_i915_master_private *master_priv;
1438
1439         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1440         if (!master_priv)
1441                 return -ENOMEM;
1442
1443         master->driver_priv = master_priv;
1444         return 0;
1445 }
1446
1447 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1448 {
1449         struct drm_i915_master_private *master_priv = master->driver_priv;
1450
1451         if (!master_priv)
1452                 return;
1453
1454         kfree(master_priv);
1455
1456         master->driver_priv = NULL;
1457 }
1458
1459 static void i915_get_mem_freq(struct drm_device *dev)
1460 {
1461         drm_i915_private_t *dev_priv = dev->dev_private;
1462         u32 tmp;
1463
1464         if (!IS_PINEVIEW(dev))
1465                 return;
1466
1467         tmp = I915_READ(CLKCFG);
1468
1469         switch (tmp & CLKCFG_FSB_MASK) {
1470         case CLKCFG_FSB_533:
1471                 dev_priv->fsb_freq = 533; /* 133*4 */
1472                 break;
1473         case CLKCFG_FSB_800:
1474                 dev_priv->fsb_freq = 800; /* 200*4 */
1475                 break;
1476         case CLKCFG_FSB_667:
1477                 dev_priv->fsb_freq =  667; /* 167*4 */
1478                 break;
1479         case CLKCFG_FSB_400:
1480                 dev_priv->fsb_freq = 400; /* 100*4 */
1481                 break;
1482         }
1483
1484         switch (tmp & CLKCFG_MEM_MASK) {
1485         case CLKCFG_MEM_533:
1486                 dev_priv->mem_freq = 533;
1487                 break;
1488         case CLKCFG_MEM_667:
1489                 dev_priv->mem_freq = 667;
1490                 break;
1491         case CLKCFG_MEM_800:
1492                 dev_priv->mem_freq = 800;
1493                 break;
1494         }
1495 }
1496
1497 /**
1498  * i915_driver_load - setup chip and create an initial config
1499  * @dev: DRM device
1500  * @flags: startup flags
1501  *
1502  * The driver load routine has to do several things:
1503  *   - drive output discovery via intel_modeset_init()
1504  *   - initialize the memory manager
1505  *   - allocate initial config memory
1506  *   - setup the DRM framebuffer with the allocated memory
1507  */
1508 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1509 {
1510         struct drm_i915_private *dev_priv;
1511         resource_size_t base, size;
1512         int ret = 0, mmio_bar;
1513         uint32_t agp_size, prealloc_size, prealloc_start;
1514         /* i915 has 4 more counters */
1515         dev->counters += 4;
1516         dev->types[6] = _DRM_STAT_IRQ;
1517         dev->types[7] = _DRM_STAT_PRIMARY;
1518         dev->types[8] = _DRM_STAT_SECONDARY;
1519         dev->types[9] = _DRM_STAT_DMA;
1520
1521         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1522         if (dev_priv == NULL)
1523                 return -ENOMEM;
1524
1525         dev->dev_private = (void *)dev_priv;
1526         dev_priv->dev = dev;
1527         dev_priv->info = (struct intel_device_info *) flags;
1528
1529         /* Add register map (needed for suspend/resume) */
1530         mmio_bar = IS_I9XX(dev) ? 0 : 1;
1531         base = drm_get_resource_start(dev, mmio_bar);
1532         size = drm_get_resource_len(dev, mmio_bar);
1533
1534         if (i915_get_bridge_dev(dev)) {
1535                 ret = -EIO;
1536                 goto free_priv;
1537         }
1538
1539         dev_priv->regs = ioremap(base, size);
1540         if (!dev_priv->regs) {
1541                 DRM_ERROR("failed to map registers\n");
1542                 ret = -EIO;
1543                 goto put_bridge;
1544         }
1545
1546         dev_priv->mm.gtt_mapping =
1547                 io_mapping_create_wc(dev->agp->base,
1548                                      dev->agp->agp_info.aper_size * 1024*1024);
1549         if (dev_priv->mm.gtt_mapping == NULL) {
1550                 ret = -EIO;
1551                 goto out_rmmap;
1552         }
1553
1554         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1555          * one would think, because the kernel disables PAT on first
1556          * generation Core chips because WC PAT gets overridden by a UC
1557          * MTRR if present.  Even if a UC MTRR isn't present.
1558          */
1559         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1560                                          dev->agp->agp_info.aper_size *
1561                                          1024 * 1024,
1562                                          MTRR_TYPE_WRCOMB, 1);
1563         if (dev_priv->mm.gtt_mtrr < 0) {
1564                 DRM_INFO("MTRR allocation failed.  Graphics "
1565                          "performance may suffer.\n");
1566         }
1567
1568         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1569         if (ret)
1570                 goto out_iomapfree;
1571
1572         dev_priv->wq = create_singlethread_workqueue("i915");
1573         if (dev_priv->wq == NULL) {
1574                 DRM_ERROR("Failed to create our workqueue.\n");
1575                 ret = -ENOMEM;
1576                 goto out_iomapfree;
1577         }
1578
1579         /* enable GEM by default */
1580         dev_priv->has_gem = 1;
1581
1582         if (prealloc_size > agp_size * 3 / 4) {
1583                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1584                           "memory stolen.\n",
1585                           prealloc_size / 1024, agp_size / 1024);
1586                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1587                           "updating the BIOS to fix).\n");
1588                 dev_priv->has_gem = 0;
1589         }
1590
1591         if (dev_priv->has_gem == 0 &&
1592             drm_core_check_feature(dev, DRIVER_MODESET)) {
1593                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1594                 ret = -ENODEV;
1595                 goto out_iomapfree;
1596         }
1597
1598         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1599         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1600         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1601                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1602                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1603         }
1604
1605         /* Try to make sure MCHBAR is enabled before poking at it */
1606         intel_setup_mchbar(dev);
1607
1608         i915_gem_load(dev);
1609
1610         /* Init HWS */
1611         if (!I915_NEED_GFX_HWS(dev)) {
1612                 ret = i915_init_phys_hws(dev);
1613                 if (ret != 0)
1614                         goto out_workqueue_free;
1615         }
1616
1617         i915_get_mem_freq(dev);
1618
1619         /* On the 945G/GM, the chipset reports the MSI capability on the
1620          * integrated graphics even though the support isn't actually there
1621          * according to the published specs.  It doesn't appear to function
1622          * correctly in testing on 945G.
1623          * This may be a side effect of MSI having been made available for PEG
1624          * and the registers being closely associated.
1625          *
1626          * According to chipset errata, on the 965GM, MSI interrupts may
1627          * be lost or delayed, but we use them anyways to avoid
1628          * stuck interrupts on some machines.
1629          */
1630         if (!IS_I945G(dev) && !IS_I945GM(dev))
1631                 pci_enable_msi(dev->pdev);
1632
1633         spin_lock_init(&dev_priv->user_irq_lock);
1634         spin_lock_init(&dev_priv->error_lock);
1635         dev_priv->trace_irq_seqno = 0;
1636
1637         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1638
1639         if (ret) {
1640                 (void) i915_driver_unload(dev);
1641                 return ret;
1642         }
1643
1644         /* Start out suspended */
1645         dev_priv->mm.suspended = 1;
1646
1647         intel_detect_pch(dev);
1648
1649         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1650                 ret = i915_load_modeset_init(dev, prealloc_start,
1651                                              prealloc_size, agp_size);
1652                 if (ret < 0) {
1653                         DRM_ERROR("failed to init modeset\n");
1654                         goto out_workqueue_free;
1655                 }
1656         }
1657
1658         /* Must be done after probing outputs */
1659         intel_opregion_init(dev, 0);
1660
1661         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1662                     (unsigned long) dev);
1663         return 0;
1664
1665 out_workqueue_free:
1666         destroy_workqueue(dev_priv->wq);
1667 out_iomapfree:
1668         io_mapping_free(dev_priv->mm.gtt_mapping);
1669 out_rmmap:
1670         iounmap(dev_priv->regs);
1671 put_bridge:
1672         pci_dev_put(dev_priv->bridge_dev);
1673 free_priv:
1674         kfree(dev_priv);
1675         return ret;
1676 }
1677
1678 int i915_driver_unload(struct drm_device *dev)
1679 {
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681
1682         i915_destroy_error_state(dev);
1683
1684         destroy_workqueue(dev_priv->wq);
1685         del_timer_sync(&dev_priv->hangcheck_timer);
1686
1687         io_mapping_free(dev_priv->mm.gtt_mapping);
1688         if (dev_priv->mm.gtt_mtrr >= 0) {
1689                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1690                          dev->agp->agp_info.aper_size * 1024 * 1024);
1691                 dev_priv->mm.gtt_mtrr = -1;
1692         }
1693
1694         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1695                 intel_modeset_cleanup(dev);
1696
1697                 /*
1698                  * free the memory space allocated for the child device
1699                  * config parsed from VBT
1700                  */
1701                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1702                         kfree(dev_priv->child_dev);
1703                         dev_priv->child_dev = NULL;
1704                         dev_priv->child_dev_num = 0;
1705                 }
1706                 drm_irq_uninstall(dev);
1707                 vga_switcheroo_unregister_client(dev->pdev);
1708                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1709         }
1710
1711         if (dev->pdev->msi_enabled)
1712                 pci_disable_msi(dev->pdev);
1713
1714         if (dev_priv->regs != NULL)
1715                 iounmap(dev_priv->regs);
1716
1717         intel_opregion_free(dev, 0);
1718
1719         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1720                 i915_gem_free_all_phys_object(dev);
1721
1722                 mutex_lock(&dev->struct_mutex);
1723                 i915_gem_cleanup_ringbuffer(dev);
1724                 mutex_unlock(&dev->struct_mutex);
1725                 if (I915_HAS_FBC(dev) && i915_powersave)
1726                         i915_cleanup_compression(dev);
1727                 drm_mm_takedown(&dev_priv->vram);
1728                 i915_gem_lastclose(dev);
1729
1730                 intel_cleanup_overlay(dev);
1731         }
1732
1733         intel_teardown_mchbar(dev);
1734
1735         pci_dev_put(dev_priv->bridge_dev);
1736         kfree(dev->dev_private);
1737
1738         return 0;
1739 }
1740
1741 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1742 {
1743         struct drm_i915_file_private *i915_file_priv;
1744
1745         DRM_DEBUG_DRIVER("\n");
1746         i915_file_priv = (struct drm_i915_file_private *)
1747             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1748
1749         if (!i915_file_priv)
1750                 return -ENOMEM;
1751
1752         file_priv->driver_priv = i915_file_priv;
1753
1754         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1755
1756         return 0;
1757 }
1758
1759 /**
1760  * i915_driver_lastclose - clean up after all DRM clients have exited
1761  * @dev: DRM device
1762  *
1763  * Take care of cleaning up after all DRM clients have exited.  In the
1764  * mode setting case, we want to restore the kernel's initial mode (just
1765  * in case the last client left us in a bad state).
1766  *
1767  * Additionally, in the non-mode setting case, we'll tear down the AGP
1768  * and DMA structures, since the kernel won't be using them, and clea
1769  * up any GEM state.
1770  */
1771 void i915_driver_lastclose(struct drm_device * dev)
1772 {
1773         drm_i915_private_t *dev_priv = dev->dev_private;
1774
1775         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1776                 drm_fb_helper_restore();
1777                 vga_switcheroo_process_delayed_switch();
1778                 return;
1779         }
1780
1781         i915_gem_lastclose(dev);
1782
1783         if (dev_priv->agp_heap)
1784                 i915_mem_takedown(&(dev_priv->agp_heap));
1785
1786         i915_dma_cleanup(dev);
1787 }
1788
1789 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1790 {
1791         drm_i915_private_t *dev_priv = dev->dev_private;
1792         i915_gem_release(dev, file_priv);
1793         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1794                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1795 }
1796
1797 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1798 {
1799         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1800
1801         kfree(i915_file_priv);
1802 }
1803
1804 struct drm_ioctl_desc i915_ioctls[] = {
1805         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1806         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1807         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1808         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1809         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1810         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1811         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1812         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1813         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1814         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1815         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1816         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1817         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1818         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1819         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1820         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1821         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1822         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1823         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1824         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1825         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1826         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1827         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1828         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1829         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1830         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1831         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1832         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1833         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1834         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1835         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1836         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1837         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1838         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1839         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1840         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1841         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1842         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1843         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1844         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1845 };
1846
1847 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1848
1849 /**
1850  * Determine if the device really is AGP or not.
1851  *
1852  * All Intel graphics chipsets are treated as AGP, even if they are really
1853  * PCI-e.
1854  *
1855  * \param dev   The device to be tested.
1856  *
1857  * \returns
1858  * A value of 1 is always retured to indictate every i9x5 is AGP.
1859  */
1860 int i915_driver_device_is_agp(struct drm_device * dev)
1861 {
1862         return 1;
1863 }