1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/slab.h>
44 * Sets up the hardware status page for devices that need a physical address
47 static int i915_init_phys_hws(struct drm_device *dev)
49 drm_i915_private_t *dev_priv = dev->dev_private;
50 /* Program Hardware Status Page */
51 dev_priv->status_page_dmah =
52 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
54 if (!dev_priv->status_page_dmah) {
55 DRM_ERROR("Can not allocate hardware status page\n");
58 dev_priv->render_ring.status_page.page_addr
59 = dev_priv->status_page_dmah->vaddr;
60 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
62 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
65 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
68 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
69 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
74 * Frees the hardware status page, whether it's a physical address or a virtual
75 * address set up by the X Server.
77 static void i915_free_hws(struct drm_device *dev)
79 drm_i915_private_t *dev_priv = dev->dev_private;
80 if (dev_priv->status_page_dmah) {
81 drm_pci_free(dev, dev_priv->status_page_dmah);
82 dev_priv->status_page_dmah = NULL;
85 if (dev_priv->render_ring.status_page.gfx_addr) {
86 dev_priv->render_ring.status_page.gfx_addr = 0;
87 dev_priv->status_gfx_addr = 0;
88 drm_core_ioremapfree(&dev_priv->hws_map, dev);
91 /* Need to rewrite hardware status page */
92 I915_WRITE(HWS_PGA, 0x1ffff000);
95 void i915_kernel_lost_context(struct drm_device * dev)
97 drm_i915_private_t *dev_priv = dev->dev_private;
98 struct drm_i915_master_private *master_priv;
99 struct intel_ring_buffer *ring = &dev_priv->render_ring;
102 * We should never lose context on the ring with modesetting
103 * as we don't expose it to userspace
105 if (drm_core_check_feature(dev, DRIVER_MODESET))
108 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
109 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
110 ring->space = ring->head - (ring->tail + 8);
112 ring->space += ring->size;
114 if (!dev->primary->master)
117 master_priv = dev->primary->master->driver_priv;
118 if (ring->head == ring->tail && master_priv->sarea_priv)
119 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
122 static int i915_dma_cleanup(struct drm_device * dev)
124 drm_i915_private_t *dev_priv = dev->dev_private;
125 /* Make sure interrupts are disabled here because the uninstall ioctl
126 * may not have been called from userspace and after dev_private
127 * is freed, it's too late.
129 if (dev->irq_enabled)
130 drm_irq_uninstall(dev);
132 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
134 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
136 /* Clear the HWS virtual address at teardown */
137 if (I915_NEED_GFX_HWS(dev))
143 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
145 drm_i915_private_t *dev_priv = dev->dev_private;
146 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
148 master_priv->sarea = drm_getsarea(dev);
149 if (master_priv->sarea) {
150 master_priv->sarea_priv = (drm_i915_sarea_t *)
151 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
153 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
156 if (init->ring_size != 0) {
157 if (dev_priv->render_ring.gem_object != NULL) {
158 i915_dma_cleanup(dev);
159 DRM_ERROR("Client tried to initialize ringbuffer in "
164 dev_priv->render_ring.size = init->ring_size;
166 dev_priv->render_ring.map.offset = init->ring_start;
167 dev_priv->render_ring.map.size = init->ring_size;
168 dev_priv->render_ring.map.type = 0;
169 dev_priv->render_ring.map.flags = 0;
170 dev_priv->render_ring.map.mtrr = 0;
172 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
174 if (dev_priv->render_ring.map.handle == NULL) {
175 i915_dma_cleanup(dev);
176 DRM_ERROR("can not ioremap virtual address for"
182 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
184 dev_priv->cpp = init->cpp;
185 dev_priv->back_offset = init->back_offset;
186 dev_priv->front_offset = init->front_offset;
187 dev_priv->current_page = 0;
188 if (master_priv->sarea_priv)
189 master_priv->sarea_priv->pf_current_page = 0;
191 /* Allow hardware batchbuffers unless told otherwise.
193 dev_priv->allow_batchbuffer = 1;
198 static int i915_dma_resume(struct drm_device * dev)
200 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
202 struct intel_ring_buffer *ring;
203 DRM_DEBUG_DRIVER("%s\n", __func__);
205 ring = &dev_priv->render_ring;
207 if (ring->map.handle == NULL) {
208 DRM_ERROR("can not ioremap virtual address for"
213 /* Program Hardware Status Page */
214 if (!ring->status_page.page_addr) {
215 DRM_ERROR("Can not find hardware status page\n");
218 DRM_DEBUG_DRIVER("hw status page @ %p\n",
219 ring->status_page.page_addr);
220 if (ring->status_page.gfx_addr != 0)
221 ring->setup_status_page(dev, ring);
223 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
225 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
230 static int i915_dma_init(struct drm_device *dev, void *data,
231 struct drm_file *file_priv)
233 drm_i915_init_t *init = data;
236 switch (init->func) {
238 retcode = i915_initialize(dev, init);
240 case I915_CLEANUP_DMA:
241 retcode = i915_dma_cleanup(dev);
243 case I915_RESUME_DMA:
244 retcode = i915_dma_resume(dev);
254 /* Implement basically the same security restrictions as hardware does
255 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
257 * Most of the calculations below involve calculating the size of a
258 * particular instruction. It's important to get the size right as
259 * that tells us where the next instruction to check is. Any illegal
260 * instruction detected will be given a size of zero, which is a
261 * signal to abort the rest of the buffer.
263 static int do_validate_cmd(int cmd)
265 switch (((cmd >> 29) & 0x7)) {
267 switch ((cmd >> 23) & 0x3f) {
269 return 1; /* MI_NOOP */
271 return 1; /* MI_FLUSH */
273 return 0; /* disallow everything else */
277 return 0; /* reserved */
279 return (cmd & 0xff) + 2; /* 2d commands */
281 if (((cmd >> 24) & 0x1f) <= 0x18)
284 switch ((cmd >> 24) & 0x1f) {
288 switch ((cmd >> 16) & 0xff) {
290 return (cmd & 0x1f) + 2;
292 return (cmd & 0xf) + 2;
294 return (cmd & 0xffff) + 2;
298 return (cmd & 0xffff) + 1;
302 if ((cmd & (1 << 23)) == 0) /* inline vertices */
303 return (cmd & 0x1ffff) + 2;
304 else if (cmd & (1 << 17)) /* indirect random */
305 if ((cmd & 0xffff) == 0)
306 return 0; /* unknown length, too hard */
308 return (((cmd & 0xffff) + 1) / 2) + 1;
310 return 2; /* indirect sequential */
321 static int validate_cmd(int cmd)
323 int ret = do_validate_cmd(cmd);
325 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
330 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
332 drm_i915_private_t *dev_priv = dev->dev_private;
335 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
338 BEGIN_LP_RING((dwords+1)&~1);
340 for (i = 0; i < dwords;) {
345 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
364 i915_emit_box(struct drm_device *dev,
365 struct drm_clip_rect *boxes,
366 int i, int DR1, int DR4)
368 struct drm_clip_rect box = boxes[i];
370 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
371 DRM_ERROR("Bad box %d,%d..%d,%d\n",
372 box.x1, box.y1, box.x2, box.y2);
378 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
379 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
380 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
385 OUT_RING(GFX_OP_DRAWRECT_INFO);
387 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
388 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
397 /* XXX: Emitting the counter should really be moved to part of the IRQ
398 * emit. For now, do it in both places:
401 static void i915_emit_breadcrumb(struct drm_device *dev)
403 drm_i915_private_t *dev_priv = dev->dev_private;
404 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
407 if (dev_priv->counter > 0x7FFFFFFFUL)
408 dev_priv->counter = 0;
409 if (master_priv->sarea_priv)
410 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
413 OUT_RING(MI_STORE_DWORD_INDEX);
414 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
415 OUT_RING(dev_priv->counter);
420 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
421 drm_i915_cmdbuffer_t *cmd,
422 struct drm_clip_rect *cliprects,
425 int nbox = cmd->num_cliprects;
426 int i = 0, count, ret;
429 DRM_ERROR("alignment");
433 i915_kernel_lost_context(dev);
435 count = nbox ? nbox : 1;
437 for (i = 0; i < count; i++) {
439 ret = i915_emit_box(dev, cliprects, i,
445 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
450 i915_emit_breadcrumb(dev);
454 static int i915_dispatch_batchbuffer(struct drm_device * dev,
455 drm_i915_batchbuffer_t * batch,
456 struct drm_clip_rect *cliprects)
458 int nbox = batch->num_cliprects;
461 if ((batch->start | batch->used) & 0x7) {
462 DRM_ERROR("alignment");
466 i915_kernel_lost_context(dev);
468 count = nbox ? nbox : 1;
470 for (i = 0; i < count; i++) {
472 int ret = i915_emit_box(dev, cliprects, i,
473 batch->DR1, batch->DR4);
478 if (!IS_I830(dev) && !IS_845G(dev)) {
481 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
482 OUT_RING(batch->start);
484 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
485 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 OUT_RING(MI_BATCH_BUFFER);
491 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
492 OUT_RING(batch->start + batch->used - 4);
498 i915_emit_breadcrumb(dev);
503 static int i915_dispatch_flip(struct drm_device * dev)
505 drm_i915_private_t *dev_priv = dev->dev_private;
506 struct drm_i915_master_private *master_priv =
507 dev->primary->master->driver_priv;
509 if (!master_priv->sarea_priv)
512 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
514 dev_priv->current_page,
515 master_priv->sarea_priv->pf_current_page);
517 i915_kernel_lost_context(dev);
520 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
525 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
527 if (dev_priv->current_page == 0) {
528 OUT_RING(dev_priv->back_offset);
529 dev_priv->current_page = 1;
531 OUT_RING(dev_priv->front_offset);
532 dev_priv->current_page = 0;
538 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
542 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
545 OUT_RING(MI_STORE_DWORD_INDEX);
546 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
547 OUT_RING(dev_priv->counter);
551 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
555 static int i915_quiescent(struct drm_device * dev)
557 drm_i915_private_t *dev_priv = dev->dev_private;
559 i915_kernel_lost_context(dev);
560 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
561 dev_priv->render_ring.size - 8);
564 static int i915_flush_ioctl(struct drm_device *dev, void *data,
565 struct drm_file *file_priv)
569 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
571 mutex_lock(&dev->struct_mutex);
572 ret = i915_quiescent(dev);
573 mutex_unlock(&dev->struct_mutex);
578 static int i915_batchbuffer(struct drm_device *dev, void *data,
579 struct drm_file *file_priv)
581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
582 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
583 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
584 master_priv->sarea_priv;
585 drm_i915_batchbuffer_t *batch = data;
587 struct drm_clip_rect *cliprects = NULL;
589 if (!dev_priv->allow_batchbuffer) {
590 DRM_ERROR("Batchbuffer ioctl disabled\n");
594 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
595 batch->start, batch->used, batch->num_cliprects);
597 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
599 if (batch->num_cliprects < 0)
602 if (batch->num_cliprects) {
603 cliprects = kcalloc(batch->num_cliprects,
604 sizeof(struct drm_clip_rect),
606 if (cliprects == NULL)
609 ret = copy_from_user(cliprects, batch->cliprects,
610 batch->num_cliprects *
611 sizeof(struct drm_clip_rect));
616 mutex_lock(&dev->struct_mutex);
617 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
618 mutex_unlock(&dev->struct_mutex);
621 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
629 static int i915_cmdbuffer(struct drm_device *dev, void *data,
630 struct drm_file *file_priv)
632 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
633 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
634 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
635 master_priv->sarea_priv;
636 drm_i915_cmdbuffer_t *cmdbuf = data;
637 struct drm_clip_rect *cliprects = NULL;
641 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
642 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
644 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
646 if (cmdbuf->num_cliprects < 0)
649 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
650 if (batch_data == NULL)
653 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
655 goto fail_batch_free;
657 if (cmdbuf->num_cliprects) {
658 cliprects = kcalloc(cmdbuf->num_cliprects,
659 sizeof(struct drm_clip_rect), GFP_KERNEL);
660 if (cliprects == NULL) {
662 goto fail_batch_free;
665 ret = copy_from_user(cliprects, cmdbuf->cliprects,
666 cmdbuf->num_cliprects *
667 sizeof(struct drm_clip_rect));
672 mutex_lock(&dev->struct_mutex);
673 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
674 mutex_unlock(&dev->struct_mutex);
676 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
681 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
691 static int i915_flip_bufs(struct drm_device *dev, void *data,
692 struct drm_file *file_priv)
696 DRM_DEBUG_DRIVER("%s\n", __func__);
698 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
700 mutex_lock(&dev->struct_mutex);
701 ret = i915_dispatch_flip(dev);
702 mutex_unlock(&dev->struct_mutex);
707 static int i915_getparam(struct drm_device *dev, void *data,
708 struct drm_file *file_priv)
710 drm_i915_private_t *dev_priv = dev->dev_private;
711 drm_i915_getparam_t *param = data;
715 DRM_ERROR("called with no initialization\n");
719 switch (param->param) {
720 case I915_PARAM_IRQ_ACTIVE:
721 value = dev->pdev->irq ? 1 : 0;
723 case I915_PARAM_ALLOW_BATCHBUFFER:
724 value = dev_priv->allow_batchbuffer ? 1 : 0;
726 case I915_PARAM_LAST_DISPATCH:
727 value = READ_BREADCRUMB(dev_priv);
729 case I915_PARAM_CHIPSET_ID:
730 value = dev->pci_device;
732 case I915_PARAM_HAS_GEM:
733 value = dev_priv->has_gem;
735 case I915_PARAM_NUM_FENCES_AVAIL:
736 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
738 case I915_PARAM_HAS_OVERLAY:
739 value = dev_priv->overlay ? 1 : 0;
741 case I915_PARAM_HAS_PAGEFLIPPING:
744 case I915_PARAM_HAS_EXECBUF2:
746 value = dev_priv->has_gem;
749 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
754 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
755 DRM_ERROR("DRM_COPY_TO_USER failed\n");
762 static int i915_setparam(struct drm_device *dev, void *data,
763 struct drm_file *file_priv)
765 drm_i915_private_t *dev_priv = dev->dev_private;
766 drm_i915_setparam_t *param = data;
769 DRM_ERROR("called with no initialization\n");
773 switch (param->param) {
774 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
776 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
777 dev_priv->tex_lru_log_granularity = param->value;
779 case I915_SETPARAM_ALLOW_BATCHBUFFER:
780 dev_priv->allow_batchbuffer = param->value;
782 case I915_SETPARAM_NUM_USED_FENCES:
783 if (param->value > dev_priv->num_fence_regs ||
786 /* Userspace can use first N regs */
787 dev_priv->fence_reg_start = param->value;
790 DRM_DEBUG_DRIVER("unknown parameter %d\n",
798 static int i915_set_status_page(struct drm_device *dev, void *data,
799 struct drm_file *file_priv)
801 drm_i915_private_t *dev_priv = dev->dev_private;
802 drm_i915_hws_addr_t *hws = data;
803 struct intel_ring_buffer *ring = &dev_priv->render_ring;
805 if (!I915_NEED_GFX_HWS(dev))
809 DRM_ERROR("called with no initialization\n");
813 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
814 WARN(1, "tried to set status page when mode setting active\n");
818 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
820 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
822 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
823 dev_priv->hws_map.size = 4*1024;
824 dev_priv->hws_map.type = 0;
825 dev_priv->hws_map.flags = 0;
826 dev_priv->hws_map.mtrr = 0;
828 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
829 if (dev_priv->hws_map.handle == NULL) {
830 i915_dma_cleanup(dev);
831 dev_priv->status_gfx_addr = 0;
832 DRM_ERROR("can not ioremap virtual address for"
833 " G33 hw status page\n");
836 ring->status_page.page_addr = dev_priv->hws_map.handle;
837 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
838 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
840 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
841 dev_priv->status_gfx_addr);
842 DRM_DEBUG_DRIVER("load hws at %p\n",
843 dev_priv->hw_status_page);
847 static int i915_get_bridge_dev(struct drm_device *dev)
849 struct drm_i915_private *dev_priv = dev->dev_private;
851 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
852 if (!dev_priv->bridge_dev) {
853 DRM_ERROR("bridge device not found\n");
859 #define MCHBAR_I915 0x44
860 #define MCHBAR_I965 0x48
861 #define MCHBAR_SIZE (4*4096)
863 #define DEVEN_REG 0x54
864 #define DEVEN_MCHBAR_EN (1 << 28)
866 /* Allocate space for the MCH regs if needed, return nonzero on error */
868 intel_alloc_mchbar_resource(struct drm_device *dev)
870 drm_i915_private_t *dev_priv = dev->dev_private;
871 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
872 u32 temp_lo, temp_hi = 0;
877 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
878 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
879 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
881 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
884 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
890 /* Get some space for it */
891 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
892 MCHBAR_SIZE, MCHBAR_SIZE,
894 0, pcibios_align_resource,
895 dev_priv->bridge_dev);
897 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
898 dev_priv->mch_res.start = 0;
903 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
904 upper_32_bits(dev_priv->mch_res.start));
906 pci_write_config_dword(dev_priv->bridge_dev, reg,
907 lower_32_bits(dev_priv->mch_res.start));
912 /* Setup MCHBAR if possible, return true if we should disable it again */
914 intel_setup_mchbar(struct drm_device *dev)
916 drm_i915_private_t *dev_priv = dev->dev_private;
917 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
921 dev_priv->mchbar_need_disable = false;
923 if (IS_I915G(dev) || IS_I915GM(dev)) {
924 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
925 enabled = !!(temp & DEVEN_MCHBAR_EN);
927 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
931 /* If it's already enabled, don't have to do anything */
935 if (intel_alloc_mchbar_resource(dev))
938 dev_priv->mchbar_need_disable = true;
940 /* Space is allocated or reserved, so enable it. */
941 if (IS_I915G(dev) || IS_I915GM(dev)) {
942 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
943 temp | DEVEN_MCHBAR_EN);
945 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
946 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
951 intel_teardown_mchbar(struct drm_device *dev)
953 drm_i915_private_t *dev_priv = dev->dev_private;
954 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
957 if (dev_priv->mchbar_need_disable) {
958 if (IS_I915G(dev) || IS_I915GM(dev)) {
959 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
960 temp &= ~DEVEN_MCHBAR_EN;
961 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
963 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
965 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
969 if (dev_priv->mch_res.start)
970 release_resource(&dev_priv->mch_res);
974 * i915_probe_agp - get AGP bootup configuration
976 * @aperture_size: returns AGP aperture configured size
977 * @preallocated_size: returns size of BIOS preallocated AGP space
979 * Since Intel integrated graphics are UMA, the BIOS has to set aside
980 * some RAM for the framebuffer at early boot. This code figures out
981 * how much was set aside so we can use it for our own purposes.
983 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
984 uint32_t *preallocated_size,
987 struct drm_i915_private *dev_priv = dev->dev_private;
989 unsigned long overhead;
990 unsigned long stolen;
992 /* Get the fb aperture size and "stolen" memory amount. */
993 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
995 *aperture_size = 1024 * 1024;
996 *preallocated_size = 1024 * 1024;
998 switch (dev->pdev->device) {
999 case PCI_DEVICE_ID_INTEL_82830_CGC:
1000 case PCI_DEVICE_ID_INTEL_82845G_IG:
1001 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1002 case PCI_DEVICE_ID_INTEL_82865_IG:
1003 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1004 *aperture_size *= 64;
1006 *aperture_size *= 128;
1009 /* 9xx supports large sizes, just look at the length */
1010 *aperture_size = pci_resource_len(dev->pdev, 2);
1015 * Some of the preallocated space is taken by the GTT
1016 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1018 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1021 overhead = (*aperture_size / 1024) + 4096;
1024 /* SNB has memory control reg at 0x50.w */
1025 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1027 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1028 case INTEL_855_GMCH_GMS_DISABLED:
1029 DRM_ERROR("video memory is disabled\n");
1031 case SNB_GMCH_GMS_STOLEN_32M:
1032 stolen = 32 * 1024 * 1024;
1034 case SNB_GMCH_GMS_STOLEN_64M:
1035 stolen = 64 * 1024 * 1024;
1037 case SNB_GMCH_GMS_STOLEN_96M:
1038 stolen = 96 * 1024 * 1024;
1040 case SNB_GMCH_GMS_STOLEN_128M:
1041 stolen = 128 * 1024 * 1024;
1043 case SNB_GMCH_GMS_STOLEN_160M:
1044 stolen = 160 * 1024 * 1024;
1046 case SNB_GMCH_GMS_STOLEN_192M:
1047 stolen = 192 * 1024 * 1024;
1049 case SNB_GMCH_GMS_STOLEN_224M:
1050 stolen = 224 * 1024 * 1024;
1052 case SNB_GMCH_GMS_STOLEN_256M:
1053 stolen = 256 * 1024 * 1024;
1055 case SNB_GMCH_GMS_STOLEN_288M:
1056 stolen = 288 * 1024 * 1024;
1058 case SNB_GMCH_GMS_STOLEN_320M:
1059 stolen = 320 * 1024 * 1024;
1061 case SNB_GMCH_GMS_STOLEN_352M:
1062 stolen = 352 * 1024 * 1024;
1064 case SNB_GMCH_GMS_STOLEN_384M:
1065 stolen = 384 * 1024 * 1024;
1067 case SNB_GMCH_GMS_STOLEN_416M:
1068 stolen = 416 * 1024 * 1024;
1070 case SNB_GMCH_GMS_STOLEN_448M:
1071 stolen = 448 * 1024 * 1024;
1073 case SNB_GMCH_GMS_STOLEN_480M:
1074 stolen = 480 * 1024 * 1024;
1076 case SNB_GMCH_GMS_STOLEN_512M:
1077 stolen = 512 * 1024 * 1024;
1080 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1081 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1085 switch (tmp & INTEL_GMCH_GMS_MASK) {
1086 case INTEL_855_GMCH_GMS_DISABLED:
1087 DRM_ERROR("video memory is disabled\n");
1089 case INTEL_855_GMCH_GMS_STOLEN_1M:
1090 stolen = 1 * 1024 * 1024;
1092 case INTEL_855_GMCH_GMS_STOLEN_4M:
1093 stolen = 4 * 1024 * 1024;
1095 case INTEL_855_GMCH_GMS_STOLEN_8M:
1096 stolen = 8 * 1024 * 1024;
1098 case INTEL_855_GMCH_GMS_STOLEN_16M:
1099 stolen = 16 * 1024 * 1024;
1101 case INTEL_855_GMCH_GMS_STOLEN_32M:
1102 stolen = 32 * 1024 * 1024;
1104 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1105 stolen = 48 * 1024 * 1024;
1107 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1108 stolen = 64 * 1024 * 1024;
1110 case INTEL_GMCH_GMS_STOLEN_128M:
1111 stolen = 128 * 1024 * 1024;
1113 case INTEL_GMCH_GMS_STOLEN_256M:
1114 stolen = 256 * 1024 * 1024;
1116 case INTEL_GMCH_GMS_STOLEN_96M:
1117 stolen = 96 * 1024 * 1024;
1119 case INTEL_GMCH_GMS_STOLEN_160M:
1120 stolen = 160 * 1024 * 1024;
1122 case INTEL_GMCH_GMS_STOLEN_224M:
1123 stolen = 224 * 1024 * 1024;
1125 case INTEL_GMCH_GMS_STOLEN_352M:
1126 stolen = 352 * 1024 * 1024;
1129 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1130 tmp & INTEL_GMCH_GMS_MASK);
1135 *preallocated_size = stolen - overhead;
1141 #define PTE_ADDRESS_MASK 0xfffff000
1142 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1143 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1144 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1145 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1146 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1147 #define PTE_VALID (1 << 0)
1150 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1152 * @gtt_addr: address to translate
1154 * Some chip functions require allocations from stolen space but need the
1155 * physical address of the memory in question. We use this routine
1156 * to get a physical address suitable for register programming from a given
1159 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1160 unsigned long gtt_addr)
1163 unsigned long entry, phys;
1164 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1165 int gtt_offset, gtt_size;
1167 if (IS_I965G(dev)) {
1168 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1169 gtt_offset = 2*1024*1024;
1170 gtt_size = 2*1024*1024;
1172 gtt_offset = 512*1024;
1173 gtt_size = 512*1024;
1178 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1181 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1184 DRM_ERROR("ioremap of GTT failed\n");
1188 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1190 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1192 /* Mask out these reserved bits on this hardware. */
1193 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1194 IS_I945G(dev) || IS_I945GM(dev)) {
1195 entry &= ~PTE_ADDRESS_MASK_HIGH;
1198 /* If it's not a mapping type we know, then bail. */
1199 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1200 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1205 if (!(entry & PTE_VALID)) {
1206 DRM_ERROR("bad GTT entry in stolen space\n");
1213 phys =(entry & PTE_ADDRESS_MASK) |
1214 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1216 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1221 static void i915_warn_stolen(struct drm_device *dev)
1223 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1224 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1227 static void i915_setup_compression(struct drm_device *dev, int size)
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 struct drm_mm_node *compressed_fb, *compressed_llb;
1231 unsigned long cfb_base;
1232 unsigned long ll_base = 0;
1234 /* Leave 1M for line length buffer & misc. */
1235 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1236 if (!compressed_fb) {
1237 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1238 i915_warn_stolen(dev);
1242 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1243 if (!compressed_fb) {
1244 i915_warn_stolen(dev);
1245 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1249 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1251 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1252 drm_mm_put_block(compressed_fb);
1255 if (!IS_GM45(dev)) {
1256 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1258 if (!compressed_llb) {
1259 i915_warn_stolen(dev);
1263 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1264 if (!compressed_llb) {
1265 i915_warn_stolen(dev);
1269 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1271 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1272 drm_mm_put_block(compressed_fb);
1273 drm_mm_put_block(compressed_llb);
1277 dev_priv->cfb_size = size;
1279 intel_disable_fbc(dev);
1280 dev_priv->compressed_fb = compressed_fb;
1283 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1285 I915_WRITE(FBC_CFB_BASE, cfb_base);
1286 I915_WRITE(FBC_LL_BASE, ll_base);
1287 dev_priv->compressed_llb = compressed_llb;
1290 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1291 ll_base, size >> 20);
1294 static void i915_cleanup_compression(struct drm_device *dev)
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1298 drm_mm_put_block(dev_priv->compressed_fb);
1300 drm_mm_put_block(dev_priv->compressed_llb);
1303 /* true = enable decode, false = disable decoder */
1304 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1306 struct drm_device *dev = cookie;
1308 intel_modeset_vga_set_state(dev, state);
1310 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1311 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1313 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1316 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1318 struct drm_device *dev = pci_get_drvdata(pdev);
1319 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1320 if (state == VGA_SWITCHEROO_ON) {
1321 printk(KERN_INFO "i915: switched off\n");
1322 /* i915 resume handler doesn't set to D0 */
1323 pci_set_power_state(dev->pdev, PCI_D0);
1326 printk(KERN_ERR "i915: switched off\n");
1327 i915_suspend(dev, pmm);
1331 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1333 struct drm_device *dev = pci_get_drvdata(pdev);
1336 spin_lock(&dev->count_lock);
1337 can_switch = (dev->open_count == 0);
1338 spin_unlock(&dev->count_lock);
1342 static int i915_load_modeset_init(struct drm_device *dev,
1343 unsigned long prealloc_start,
1344 unsigned long prealloc_size,
1345 unsigned long agp_size)
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1351 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1354 /* Basic memrange allocator for stolen space (aka vram) */
1355 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1356 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1358 /* We're off and running w/KMS */
1359 dev_priv->mm.suspended = 0;
1361 /* Let GEM Manage from end of prealloc space to end of aperture.
1363 * However, leave one page at the end still bound to the scratch page.
1364 * There are a number of places where the hardware apparently
1365 * prefetches past the end of the object, and we've seen multiple
1366 * hangs with the GPU head pointer stuck in a batchbuffer bound
1367 * at the last page of the aperture. One page should be enough to
1368 * keep any prefetching inside of the aperture.
1370 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1372 mutex_lock(&dev->struct_mutex);
1373 ret = i915_gem_init_ringbuffer(dev);
1374 mutex_unlock(&dev->struct_mutex);
1378 /* Try to set up FBC with a reasonable compressed buffer size */
1379 if (I915_HAS_FBC(dev) && i915_powersave) {
1382 /* Try to get an 8M buffer... */
1383 if (prealloc_size > (9*1024*1024))
1384 cfb_size = 8*1024*1024;
1385 else /* fall back to 7/8 of the stolen space */
1386 cfb_size = prealloc_size * 7 / 8;
1387 i915_setup_compression(dev, cfb_size);
1390 /* Allow hardware batchbuffers unless told otherwise.
1392 dev_priv->allow_batchbuffer = 1;
1394 ret = intel_init_bios(dev);
1396 DRM_INFO("failed to find VBIOS tables\n");
1398 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1399 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1401 goto destroy_ringbuffer;
1403 ret = vga_switcheroo_register_client(dev->pdev,
1404 i915_switcheroo_set_state,
1405 i915_switcheroo_can_switch);
1407 goto destroy_ringbuffer;
1409 intel_modeset_init(dev);
1411 ret = drm_irq_install(dev);
1413 goto destroy_ringbuffer;
1415 /* Always safe in the mode setting case. */
1416 /* FIXME: do pre/post-mode set stuff in core KMS code */
1417 dev->vblank_disable_allowed = 1;
1420 * Initialize the hardware status page IRQ location.
1423 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1425 intel_fbdev_init(dev);
1426 drm_kms_helper_poll_init(dev);
1430 mutex_lock(&dev->struct_mutex);
1431 i915_gem_cleanup_ringbuffer(dev);
1432 mutex_unlock(&dev->struct_mutex);
1437 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1439 struct drm_i915_master_private *master_priv;
1441 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1445 master->driver_priv = master_priv;
1449 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1451 struct drm_i915_master_private *master_priv = master->driver_priv;
1458 master->driver_priv = NULL;
1461 static void i915_get_mem_freq(struct drm_device *dev)
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1466 if (!IS_PINEVIEW(dev))
1469 tmp = I915_READ(CLKCFG);
1471 switch (tmp & CLKCFG_FSB_MASK) {
1472 case CLKCFG_FSB_533:
1473 dev_priv->fsb_freq = 533; /* 133*4 */
1475 case CLKCFG_FSB_800:
1476 dev_priv->fsb_freq = 800; /* 200*4 */
1478 case CLKCFG_FSB_667:
1479 dev_priv->fsb_freq = 667; /* 167*4 */
1481 case CLKCFG_FSB_400:
1482 dev_priv->fsb_freq = 400; /* 100*4 */
1486 switch (tmp & CLKCFG_MEM_MASK) {
1487 case CLKCFG_MEM_533:
1488 dev_priv->mem_freq = 533;
1490 case CLKCFG_MEM_667:
1491 dev_priv->mem_freq = 667;
1493 case CLKCFG_MEM_800:
1494 dev_priv->mem_freq = 800;
1500 * i915_driver_load - setup chip and create an initial config
1502 * @flags: startup flags
1504 * The driver load routine has to do several things:
1505 * - drive output discovery via intel_modeset_init()
1506 * - initialize the memory manager
1507 * - allocate initial config memory
1508 * - setup the DRM framebuffer with the allocated memory
1510 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1512 struct drm_i915_private *dev_priv;
1513 resource_size_t base, size;
1514 int ret = 0, mmio_bar;
1515 uint32_t agp_size, prealloc_size, prealloc_start;
1516 /* i915 has 4 more counters */
1518 dev->types[6] = _DRM_STAT_IRQ;
1519 dev->types[7] = _DRM_STAT_PRIMARY;
1520 dev->types[8] = _DRM_STAT_SECONDARY;
1521 dev->types[9] = _DRM_STAT_DMA;
1523 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1524 if (dev_priv == NULL)
1527 dev->dev_private = (void *)dev_priv;
1528 dev_priv->dev = dev;
1529 dev_priv->info = (struct intel_device_info *) flags;
1531 /* Add register map (needed for suspend/resume) */
1532 mmio_bar = IS_I9XX(dev) ? 0 : 1;
1533 base = drm_get_resource_start(dev, mmio_bar);
1534 size = drm_get_resource_len(dev, mmio_bar);
1536 if (i915_get_bridge_dev(dev)) {
1541 dev_priv->regs = ioremap(base, size);
1542 if (!dev_priv->regs) {
1543 DRM_ERROR("failed to map registers\n");
1548 dev_priv->mm.gtt_mapping =
1549 io_mapping_create_wc(dev->agp->base,
1550 dev->agp->agp_info.aper_size * 1024*1024);
1551 if (dev_priv->mm.gtt_mapping == NULL) {
1556 /* Set up a WC MTRR for non-PAT systems. This is more common than
1557 * one would think, because the kernel disables PAT on first
1558 * generation Core chips because WC PAT gets overridden by a UC
1559 * MTRR if present. Even if a UC MTRR isn't present.
1561 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1562 dev->agp->agp_info.aper_size *
1564 MTRR_TYPE_WRCOMB, 1);
1565 if (dev_priv->mm.gtt_mtrr < 0) {
1566 DRM_INFO("MTRR allocation failed. Graphics "
1567 "performance may suffer.\n");
1570 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1574 dev_priv->wq = create_singlethread_workqueue("i915");
1575 if (dev_priv->wq == NULL) {
1576 DRM_ERROR("Failed to create our workqueue.\n");
1581 /* enable GEM by default */
1582 dev_priv->has_gem = 1;
1584 if (prealloc_size > agp_size * 3 / 4) {
1585 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1587 prealloc_size / 1024, agp_size / 1024);
1588 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1589 "updating the BIOS to fix).\n");
1590 dev_priv->has_gem = 0;
1593 if (dev_priv->has_gem == 0 &&
1594 drm_core_check_feature(dev, DRIVER_MODESET)) {
1595 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1600 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1601 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1602 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1603 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1604 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1607 /* Try to make sure MCHBAR is enabled before poking at it */
1608 intel_setup_mchbar(dev);
1613 if (!I915_NEED_GFX_HWS(dev)) {
1614 ret = i915_init_phys_hws(dev);
1616 goto out_workqueue_free;
1619 i915_get_mem_freq(dev);
1621 /* On the 945G/GM, the chipset reports the MSI capability on the
1622 * integrated graphics even though the support isn't actually there
1623 * according to the published specs. It doesn't appear to function
1624 * correctly in testing on 945G.
1625 * This may be a side effect of MSI having been made available for PEG
1626 * and the registers being closely associated.
1628 * According to chipset errata, on the 965GM, MSI interrupts may
1629 * be lost or delayed, but we use them anyways to avoid
1630 * stuck interrupts on some machines.
1632 if (!IS_I945G(dev) && !IS_I945GM(dev))
1633 pci_enable_msi(dev->pdev);
1635 spin_lock_init(&dev_priv->user_irq_lock);
1636 spin_lock_init(&dev_priv->error_lock);
1637 dev_priv->trace_irq_seqno = 0;
1639 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1642 (void) i915_driver_unload(dev);
1646 /* Start out suspended */
1647 dev_priv->mm.suspended = 1;
1649 intel_detect_pch(dev);
1651 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1652 ret = i915_load_modeset_init(dev, prealloc_start,
1653 prealloc_size, agp_size);
1655 DRM_ERROR("failed to init modeset\n");
1656 goto out_workqueue_free;
1660 /* Must be done after probing outputs */
1661 intel_opregion_init(dev, 0);
1663 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1664 (unsigned long) dev);
1668 destroy_workqueue(dev_priv->wq);
1670 io_mapping_free(dev_priv->mm.gtt_mapping);
1672 iounmap(dev_priv->regs);
1674 pci_dev_put(dev_priv->bridge_dev);
1680 int i915_driver_unload(struct drm_device *dev)
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1684 i915_destroy_error_state(dev);
1686 destroy_workqueue(dev_priv->wq);
1687 del_timer_sync(&dev_priv->hangcheck_timer);
1689 io_mapping_free(dev_priv->mm.gtt_mapping);
1690 if (dev_priv->mm.gtt_mtrr >= 0) {
1691 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1692 dev->agp->agp_info.aper_size * 1024 * 1024);
1693 dev_priv->mm.gtt_mtrr = -1;
1696 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1697 intel_modeset_cleanup(dev);
1700 * free the memory space allocated for the child device
1701 * config parsed from VBT
1703 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1704 kfree(dev_priv->child_dev);
1705 dev_priv->child_dev = NULL;
1706 dev_priv->child_dev_num = 0;
1708 drm_irq_uninstall(dev);
1709 vga_switcheroo_unregister_client(dev->pdev);
1710 vga_client_register(dev->pdev, NULL, NULL, NULL);
1713 if (dev->pdev->msi_enabled)
1714 pci_disable_msi(dev->pdev);
1716 if (dev_priv->regs != NULL)
1717 iounmap(dev_priv->regs);
1719 intel_opregion_free(dev, 0);
1721 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1722 i915_gem_free_all_phys_object(dev);
1724 mutex_lock(&dev->struct_mutex);
1725 i915_gem_cleanup_ringbuffer(dev);
1726 mutex_unlock(&dev->struct_mutex);
1727 if (I915_HAS_FBC(dev) && i915_powersave)
1728 i915_cleanup_compression(dev);
1729 drm_mm_takedown(&dev_priv->vram);
1730 i915_gem_lastclose(dev);
1732 intel_cleanup_overlay(dev);
1735 intel_teardown_mchbar(dev);
1737 pci_dev_put(dev_priv->bridge_dev);
1738 kfree(dev->dev_private);
1743 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1745 struct drm_i915_file_private *i915_file_priv;
1747 DRM_DEBUG_DRIVER("\n");
1748 i915_file_priv = (struct drm_i915_file_private *)
1749 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1751 if (!i915_file_priv)
1754 file_priv->driver_priv = i915_file_priv;
1756 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1762 * i915_driver_lastclose - clean up after all DRM clients have exited
1765 * Take care of cleaning up after all DRM clients have exited. In the
1766 * mode setting case, we want to restore the kernel's initial mode (just
1767 * in case the last client left us in a bad state).
1769 * Additionally, in the non-mode setting case, we'll tear down the AGP
1770 * and DMA structures, since the kernel won't be using them, and clea
1773 void i915_driver_lastclose(struct drm_device * dev)
1775 drm_i915_private_t *dev_priv = dev->dev_private;
1777 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1778 drm_fb_helper_restore();
1779 vga_switcheroo_process_delayed_switch();
1783 i915_gem_lastclose(dev);
1785 if (dev_priv->agp_heap)
1786 i915_mem_takedown(&(dev_priv->agp_heap));
1788 i915_dma_cleanup(dev);
1791 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1793 drm_i915_private_t *dev_priv = dev->dev_private;
1794 i915_gem_release(dev, file_priv);
1795 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1796 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1799 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1801 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1803 kfree(i915_file_priv);
1806 struct drm_ioctl_desc i915_ioctls[] = {
1807 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1808 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1809 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1810 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1811 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1812 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1813 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1814 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1815 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1816 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1817 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1818 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1819 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1820 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1821 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1822 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1823 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1824 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1825 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1826 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1827 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1828 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1829 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1830 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1831 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1832 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1833 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1834 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1835 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1836 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1837 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1838 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1839 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1840 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1841 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1842 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1843 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1844 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1845 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1846 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1849 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1852 * Determine if the device really is AGP or not.
1854 * All Intel graphics chipsets are treated as AGP, even if they are really
1857 * \param dev The device to be tested.
1860 * A value of 1 is always retured to indictate every i9x5 is AGP.
1862 int i915_driver_device_is_agp(struct drm_device * dev)