drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define count_vmas(list, member) do { \
 364         list_for_each_entry(vma, list, member) { \
 365                 size += i915_gem_obj_ggtt_size(vma->obj); \
 366                 ++count; \
 367                 if (vma->obj->map_and_fenceable) { \
 368                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 369                         ++mappable_count; \
 370                 } \
 371         } \
 372 } while (0)
 373
 374 static int i915_gem_object_info(struct seq_file *m, void* data)
 375 {
 376         struct drm_info_node *node = m->private;
 377         struct drm_device *dev = node->minor->dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         u32 count, mappable_count, purgeable_count;
 380         size_t size, mappable_size, purgeable_size;
 381         struct drm_i915_gem_object *obj;
 382         struct i915_address_space *vm = &dev_priv->gtt.base;
 383         struct drm_file *file;
 384         struct i915_vma *vma;
 385         int ret;
 386
 387         ret = mutex_lock_interruptible(&dev->struct_mutex);
 388         if (ret)
 389                 return ret;
 390
 391         seq_printf(m, "%u objects, %zu bytes\n",
 392                    dev_priv->mm.object_count,
 393                    dev_priv->mm.object_memory);
 394
 395         size = count = mappable_size = mappable_count = 0;
 396         count_objects(&dev_priv->mm.bound_list, global_list);
 397         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 398                    count, mappable_count, size, mappable_size);
 399
 400         size = count = mappable_size = mappable_count = 0;
 401         count_vmas(&vm->active_list, mm_list);
 402         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 403                    count, mappable_count, size, mappable_size);
 404
 405         size = count = mappable_size = mappable_count = 0;
 406         count_vmas(&vm->inactive_list, mm_list);
 407         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 408                    count, mappable_count, size, mappable_size);
 409
 410         size = count = purgeable_size = purgeable_count = 0;
 411         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 412                 size += obj->base.size, ++count;
 413                 if (obj->madv == I915_MADV_DONTNEED)
 414                         purgeable_size += obj->base.size, ++purgeable_count;
 415         }
 416         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 417
 418         size = count = mappable_size = mappable_count = 0;
 419         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 420                 if (obj->fault_mappable) {
 421                         size += i915_gem_obj_ggtt_size(obj);
 422                         ++count;
 423                 }
 424                 if (obj->pin_mappable) {
 425                         mappable_size += i915_gem_obj_ggtt_size(obj);
 426                         ++mappable_count;
 427                 }
 428                 if (obj->madv == I915_MADV_DONTNEED) {
 429                         purgeable_size += obj->base.size;
 430                         ++purgeable_count;
 431                 }
 432         }
 433         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 434                    purgeable_count, purgeable_size);
 435         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 436                    mappable_count, mappable_size);
 437         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 438                    count, size);
 439
 440         seq_printf(m, "%zu [%lu] gtt total\n",
 441                    dev_priv->gtt.base.total,
 442                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 443
 444         seq_putc(m, '\n');
 445         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 446                 struct file_stats stats;
 447                 struct task_struct *task;
 448
 449                 memset(&stats, 0, sizeof(stats));
 450                 stats.file_priv = file->driver_priv;
 451                 spin_lock(&file->table_lock);
 452                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 453                 spin_unlock(&file->table_lock);
 454                 /*
 455                  * Although we have a valid reference on file->pid, that does
 456                  * not guarantee that the task_struct who called get_pid() is
 457                  * still alive (e.g. get_pid(current) => fork() => exit()).
 458                  * Therefore, we need to protect this ->comm access using RCU.
 459                  */
 460                 rcu_read_lock();
 461                 task = pid_task(file->pid, PIDTYPE_PID);
 462                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
 463                            task ? task->comm : "<unknown>",
 464                            stats.count,
 465                            stats.total,
 466                            stats.active,
 467                            stats.inactive,
 468                            stats.global,
 469                            stats.shared,
 470                            stats.unbound);
 471                 rcu_read_unlock();
 472         }
 473
 474         mutex_unlock(&dev->struct_mutex);
 475
 476         return 0;
 477 }
 478
 479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 480 {
 481         struct drm_info_node *node = m->private;
 482         struct drm_device *dev = node->minor->dev;
 483         uintptr_t list = (uintptr_t) node->info_ent->data;
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         struct drm_i915_gem_object *obj;
 486         size_t total_obj_size, total_gtt_size;
 487         int count, ret;
 488
 489         ret = mutex_lock_interruptible(&dev->struct_mutex);
 490         if (ret)
 491                 return ret;
 492
 493         total_obj_size = total_gtt_size = count = 0;
 494         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 495                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 496                         continue;
 497
 498                 seq_puts(m, "   ");
 499                 describe_obj(m, obj);
 500                 seq_putc(m, '\n');
 501                 total_obj_size += obj->base.size;
 502                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 503                 count++;
 504         }
 505
 506         mutex_unlock(&dev->struct_mutex);
 507
 508         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 509                    count, total_obj_size, total_gtt_size);
 510
 511         return 0;
 512 }
 513
 514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 515 {
 516         struct drm_info_node *node = m->private;
 517         struct drm_device *dev = node->minor->dev;
 518         struct drm_i915_private *dev_priv = dev->dev_private;
 519         struct intel_crtc *crtc;
 520         int ret;
 521
 522         ret = mutex_lock_interruptible(&dev->struct_mutex);
 523         if (ret)
 524                 return ret;
 525
 526         for_each_intel_crtc(dev, crtc) {
 527                 const char pipe = pipe_name(crtc->pipe);
 528                 const char plane = plane_name(crtc->plane);
 529                 struct intel_unpin_work *work;
 530
 531                 spin_lock_irq(&dev->event_lock);
 532                 work = crtc->unpin_work;
 533                 if (work == NULL) {
 534                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 535                                    pipe, plane);
 536                 } else {
 537                         u32 addr;
 538
 539                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 540                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 541                                            pipe, plane);
 542                         } else {
 543                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 544                                            pipe, plane);
 545                         }
 546                         if (work->flip_queued_req) {
 547                                 struct intel_engine_cs *ring =
 548                                         i915_gem_request_get_ring(work->flip_queued_req);
 549
 550                                 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
 551                                            ring->name,
 552                                            i915_gem_request_get_seqno(work->flip_queued_req),
 553                                            dev_priv->next_seqno,
 554                                            ring->get_seqno(ring, true),
 555                                            i915_gem_request_completed(work->flip_queued_req, true));
 556                         } else
 557                                 seq_printf(m, "Flip not associated with any ring\n");
 558                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 559                                    work->flip_queued_vblank,
 560                                    work->flip_ready_vblank,
 561                                    drm_vblank_count(dev, crtc->pipe));
 562                         if (work->enable_stall_check)
 563                                 seq_puts(m, "Stall check enabled, ");
 564                         else
 565                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 566                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 567
 568                         if (INTEL_INFO(dev)->gen >= 4)
 569                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 570                         else
 571                                 addr = I915_READ(DSPADDR(crtc->plane));
 572                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 573
 574                         if (work->pending_flip_obj) {
 575                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 576                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 577                         }
 578                 }
 579                 spin_unlock_irq(&dev->event_lock);
 580         }
 581
 582         mutex_unlock(&dev->struct_mutex);
 583
 584         return 0;
 585 }
 586
 587 static int i915_gem_request_info(struct seq_file *m, void *data)
 588 {
 589         struct drm_info_node *node = m->private;
 590         struct drm_device *dev = node->minor->dev;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct intel_engine_cs *ring;
 593         struct drm_i915_gem_request *gem_request;
 594         int ret, count, i;
 595
 596         ret = mutex_lock_interruptible(&dev->struct_mutex);
 597         if (ret)
 598                 return ret;
 599
 600         count = 0;
 601         for_each_ring(ring, dev_priv, i) {
 602                 if (list_empty(&ring->request_list))
 603                         continue;
 604
 605                 seq_printf(m, "%s requests:\n", ring->name);
 606                 list_for_each_entry(gem_request,
 607                                     &ring->request_list,
 608                                     list) {
 609                         seq_printf(m, "    %d @ %d\n",
 610                                    gem_request->seqno,
 611                                    (int) (jiffies - gem_request->emitted_jiffies));
 612                 }
 613                 count++;
 614         }
 615         mutex_unlock(&dev->struct_mutex);
 616
 617         if (count == 0)
 618                 seq_puts(m, "No requests\n");
 619
 620         return 0;
 621 }
 622
 623 static void i915_ring_seqno_info(struct seq_file *m,
 624                                  struct intel_engine_cs *ring)
 625 {
 626         if (ring->get_seqno) {
 627                 seq_printf(m, "Current sequence (%s): %u\n",
 628                            ring->name, ring->get_seqno(ring, false));
 629         }
 630 }
 631
 632 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 633 {
 634         struct drm_info_node *node = m->private;
 635         struct drm_device *dev = node->minor->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         struct intel_engine_cs *ring;
 638         int ret, i;
 639
 640         ret = mutex_lock_interruptible(&dev->struct_mutex);
 641         if (ret)
 642                 return ret;
 643         intel_runtime_pm_get(dev_priv);
 644
 645         for_each_ring(ring, dev_priv, i)
 646                 i915_ring_seqno_info(m, ring);
 647
 648         intel_runtime_pm_put(dev_priv);
 649         mutex_unlock(&dev->struct_mutex);
 650
 651         return 0;
 652 }
 653
 654
 655 static int i915_interrupt_info(struct seq_file *m, void *data)
 656 {
 657         struct drm_info_node *node = m->private;
 658         struct drm_device *dev = node->minor->dev;
 659         struct drm_i915_private *dev_priv = dev->dev_private;
 660         struct intel_engine_cs *ring;
 661         int ret, i, pipe;
 662
 663         ret = mutex_lock_interruptible(&dev->struct_mutex);
 664         if (ret)
 665                 return ret;
 666         intel_runtime_pm_get(dev_priv);
 667
 668         if (IS_CHERRYVIEW(dev)) {
 669                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 670                            I915_READ(GEN8_MASTER_IRQ));
 671
 672                 seq_printf(m, "Display IER:\t%08x\n",
 673                            I915_READ(VLV_IER));
 674                 seq_printf(m, "Display IIR:\t%08x\n",
 675                            I915_READ(VLV_IIR));
 676                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 677                            I915_READ(VLV_IIR_RW));
 678                 seq_printf(m, "Display IMR:\t%08x\n",
 679                            I915_READ(VLV_IMR));
 680                 for_each_pipe(dev_priv, pipe)
 681                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 682                                    pipe_name(pipe),
 683                                    I915_READ(PIPESTAT(pipe)));
 684
 685                 seq_printf(m, "Port hotplug:\t%08x\n",
 686                            I915_READ(PORT_HOTPLUG_EN));
 687                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 688                            I915_READ(VLV_DPFLIPSTAT));
 689                 seq_printf(m, "DPINVGTT:\t%08x\n",
 690                            I915_READ(DPINVGTT));
 691
 692                 for (i = 0; i < 4; i++) {
 693                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 694                                    i, I915_READ(GEN8_GT_IMR(i)));
 695                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 696                                    i, I915_READ(GEN8_GT_IIR(i)));
 697                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 698                                    i, I915_READ(GEN8_GT_IER(i)));
 699                 }
 700
 701                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 702                            I915_READ(GEN8_PCU_IMR));
 703                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 704                            I915_READ(GEN8_PCU_IIR));
 705                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 706                            I915_READ(GEN8_PCU_IER));
 707         } else if (INTEL_INFO(dev)->gen >= 8) {
 708                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 709                            I915_READ(GEN8_MASTER_IRQ));
 710
 711                 for (i = 0; i < 4; i++) {
 712                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 713                                    i, I915_READ(GEN8_GT_IMR(i)));
 714                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 715                                    i, I915_READ(GEN8_GT_IIR(i)));
 716                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 717                                    i, I915_READ(GEN8_GT_IER(i)));
 718                 }
 719
 720                 for_each_pipe(dev_priv, pipe) {
 721                         if (!intel_display_power_is_enabled(dev_priv,
 722                                                 POWER_DOMAIN_PIPE(pipe))) {
 723                                 seq_printf(m, "Pipe %c power disabled\n",
 724                                            pipe_name(pipe));
 725                                 continue;
 726                         }
 727                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 728                                    pipe_name(pipe),
 729                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 730                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 731                                    pipe_name(pipe),
 732                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 733                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 736                 }
 737
 738                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 739                            I915_READ(GEN8_DE_PORT_IMR));
 740                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 741                            I915_READ(GEN8_DE_PORT_IIR));
 742                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 743                            I915_READ(GEN8_DE_PORT_IER));
 744
 745                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 746                            I915_READ(GEN8_DE_MISC_IMR));
 747                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 748                            I915_READ(GEN8_DE_MISC_IIR));
 749                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 750                            I915_READ(GEN8_DE_MISC_IER));
 751
 752                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 753                            I915_READ(GEN8_PCU_IMR));
 754                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 755                            I915_READ(GEN8_PCU_IIR));
 756                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 757                            I915_READ(GEN8_PCU_IER));
 758         } else if (IS_VALLEYVIEW(dev)) {
 759                 seq_printf(m, "Display IER:\t%08x\n",
 760                            I915_READ(VLV_IER));
 761                 seq_printf(m, "Display IIR:\t%08x\n",
 762                            I915_READ(VLV_IIR));
 763                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 764                            I915_READ(VLV_IIR_RW));
 765                 seq_printf(m, "Display IMR:\t%08x\n",
 766                            I915_READ(VLV_IMR));
 767                 for_each_pipe(dev_priv, pipe)
 768                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 769                                    pipe_name(pipe),
 770                                    I915_READ(PIPESTAT(pipe)));
 771
 772                 seq_printf(m, "Master IER:\t%08x\n",
 773                            I915_READ(VLV_MASTER_IER));
 774
 775                 seq_printf(m, "Render IER:\t%08x\n",
 776                            I915_READ(GTIER));
 777                 seq_printf(m, "Render IIR:\t%08x\n",
 778                            I915_READ(GTIIR));
 779                 seq_printf(m, "Render IMR:\t%08x\n",
 780                            I915_READ(GTIMR));
 781
 782                 seq_printf(m, "PM IER:\t\t%08x\n",
 783                            I915_READ(GEN6_PMIER));
 784                 seq_printf(m, "PM IIR:\t\t%08x\n",
 785                            I915_READ(GEN6_PMIIR));
 786                 seq_printf(m, "PM IMR:\t\t%08x\n",
 787                            I915_READ(GEN6_PMIMR));
 788
 789                 seq_printf(m, "Port hotplug:\t%08x\n",
 790                            I915_READ(PORT_HOTPLUG_EN));
 791                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 792                            I915_READ(VLV_DPFLIPSTAT));
 793                 seq_printf(m, "DPINVGTT:\t%08x\n",
 794                            I915_READ(DPINVGTT));
 795
 796         } else if (!HAS_PCH_SPLIT(dev)) {
 797                 seq_printf(m, "Interrupt enable:    %08x\n",
 798                            I915_READ(IER));
 799                 seq_printf(m, "Interrupt identity:  %08x\n",
 800                            I915_READ(IIR));
 801                 seq_printf(m, "Interrupt mask:      %08x\n",
 802                            I915_READ(IMR));
 803                 for_each_pipe(dev_priv, pipe)
 804                         seq_printf(m, "Pipe %c stat:         %08x\n",
 805                                    pipe_name(pipe),
 806                                    I915_READ(PIPESTAT(pipe)));
 807         } else {
 808                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 809                            I915_READ(DEIER));
 810                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 811                            I915_READ(DEIIR));
 812                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 813                            I915_READ(DEIMR));
 814                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 815                            I915_READ(SDEIER));
 816                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 817                            I915_READ(SDEIIR));
 818                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 819                            I915_READ(SDEIMR));
 820                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 821                            I915_READ(GTIER));
 822                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 823                            I915_READ(GTIIR));
 824                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 825                            I915_READ(GTIMR));
 826         }
 827         for_each_ring(ring, dev_priv, i) {
 828                 if (INTEL_INFO(dev)->gen >= 6) {
 829                         seq_printf(m,
 830                                    "Graphics Interrupt mask (%s):       %08x\n",
 831                                    ring->name, I915_READ_IMR(ring));
 832                 }
 833                 i915_ring_seqno_info(m, ring);
 834         }
 835         intel_runtime_pm_put(dev_priv);
 836         mutex_unlock(&dev->struct_mutex);
 837
 838         return 0;
 839 }
 840
 841 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 842 {
 843         struct drm_info_node *node = m->private;
 844         struct drm_device *dev = node->minor->dev;
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         int i, ret;
 847
 848         ret = mutex_lock_interruptible(&dev->struct_mutex);
 849         if (ret)
 850                 return ret;
 851
 852         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 853         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 854         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 855                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 856
 857                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 858                            i, dev_priv->fence_regs[i].pin_count);
 859                 if (obj == NULL)
 860                         seq_puts(m, "unused");
 861                 else
 862                         describe_obj(m, obj);
 863                 seq_putc(m, '\n');
 864         }
 865
 866         mutex_unlock(&dev->struct_mutex);
 867         return 0;
 868 }
 869
 870 static int i915_hws_info(struct seq_file *m, void *data)
 871 {
 872         struct drm_info_node *node = m->private;
 873         struct drm_device *dev = node->minor->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         struct intel_engine_cs *ring;
 876         const u32 *hws;
 877         int i;
 878
 879         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 880         hws = ring->status_page.page_addr;
 881         if (hws == NULL)
 882                 return 0;
 883
 884         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 885                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 886                            i * 4,
 887                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 888         }
 889         return 0;
 890 }
 891
 892 static ssize_t
 893 i915_error_state_write(struct file *filp,
 894                        const char __user *ubuf,
 895                        size_t cnt,
 896                        loff_t *ppos)
 897 {
 898         struct i915_error_state_file_priv *error_priv = filp->private_data;
 899         struct drm_device *dev = error_priv->dev;
 900         int ret;
 901
 902         DRM_DEBUG_DRIVER("Resetting error state\n");
 903
 904         ret = mutex_lock_interruptible(&dev->struct_mutex);
 905         if (ret)
 906                 return ret;
 907
 908         i915_destroy_error_state(dev);
 909         mutex_unlock(&dev->struct_mutex);
 910
 911         return cnt;
 912 }
 913
 914 static int i915_error_state_open(struct inode *inode, struct file *file)
 915 {
 916         struct drm_device *dev = inode->i_private;
 917         struct i915_error_state_file_priv *error_priv;
 918
 919         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 920         if (!error_priv)
 921                 return -ENOMEM;
 922
 923         error_priv->dev = dev;
 924
 925         i915_error_state_get(dev, error_priv);
 926
 927         file->private_data = error_priv;
 928
 929         return 0;
 930 }
 931
 932 static int i915_error_state_release(struct inode *inode, struct file *file)
 933 {
 934         struct i915_error_state_file_priv *error_priv = file->private_data;
 935
 936         i915_error_state_put(error_priv);
 937         kfree(error_priv);
 938
 939         return 0;
 940 }
 941
 942 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 943                                      size_t count, loff_t *pos)
 944 {
 945         struct i915_error_state_file_priv *error_priv = file->private_data;
 946         struct drm_i915_error_state_buf error_str;
 947         loff_t tmp_pos = 0;
 948         ssize_t ret_count = 0;
 949         int ret;
 950
 951         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
 952         if (ret)
 953                 return ret;
 954
 955         ret = i915_error_state_to_str(&error_str, error_priv);
 956         if (ret)
 957                 goto out;
 958
 959         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 960                                             error_str.buf,
 961                                             error_str.bytes);
 962
 963         if (ret_count < 0)
 964                 ret = ret_count;
 965         else
 966                 *pos = error_str.start + ret_count;
 967 out:
 968         i915_error_state_buf_release(&error_str);
 969         return ret ?: ret_count;
 970 }
 971
 972 static const struct file_operations i915_error_state_fops = {
 973         .owner = THIS_MODULE,
 974         .open = i915_error_state_open,
 975         .read = i915_error_state_read,
 976         .write = i915_error_state_write,
 977         .llseek = default_llseek,
 978         .release = i915_error_state_release,
 979 };
 980
 981 static int
 982 i915_next_seqno_get(void *data, u64 *val)
 983 {
 984         struct drm_device *dev = data;
 985         struct drm_i915_private *dev_priv = dev->dev_private;
 986         int ret;
 987
 988         ret = mutex_lock_interruptible(&dev->struct_mutex);
 989         if (ret)
 990                 return ret;
 991
 992         *val = dev_priv->next_seqno;
 993         mutex_unlock(&dev->struct_mutex);
 994
 995         return 0;
 996 }
 997
 998 static int
 999 i915_next_seqno_set(void *data, u64 val)
1000 {
1001         struct drm_device *dev = data;
1002         int ret;
1003
1004         ret = mutex_lock_interruptible(&dev->struct_mutex);
1005         if (ret)
1006                 return ret;
1007
1008         ret = i915_gem_set_seqno(dev, val);
1009         mutex_unlock(&dev->struct_mutex);
1010
1011         return ret;
1012 }
1013
1014 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1015                         i915_next_seqno_get, i915_next_seqno_set,
1016                         "0x%llx\n");
1017
1018 static int i915_frequency_info(struct seq_file *m, void *unused)
1019 {
1020         struct drm_info_node *node = m->private;
1021         struct drm_device *dev = node->minor->dev;
1022         struct drm_i915_private *dev_priv = dev->dev_private;
1023         int ret = 0;
1024
1025         intel_runtime_pm_get(dev_priv);
1026
1027         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1028
1029         if (IS_GEN5(dev)) {
1030                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1031                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1032
1033                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1034                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1035                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1036                            MEMSTAT_VID_SHIFT);
1037                 seq_printf(m, "Current P-state: %d\n",
1038                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1039         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1040                    IS_BROADWELL(dev)) {
1041                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1042                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1043                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1044                 u32 rpmodectl, rpinclimit, rpdeclimit;
1045                 u32 rpstat, cagf, reqf;
1046                 u32 rpupei, rpcurup, rpprevup;
1047                 u32 rpdownei, rpcurdown, rpprevdown;
1048                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1049                 int max_freq;
1050
1051                 /* RPSTAT1 is in the GT power well */
1052                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1053                 if (ret)
1054                         goto out;
1055
1056                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1057
1058                 reqf = I915_READ(GEN6_RPNSWREQ);
1059                 reqf &= ~GEN6_TURBO_DISABLE;
1060                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1061                         reqf >>= 24;
1062                 else
1063                         reqf >>= 25;
1064                 reqf *= GT_FREQUENCY_MULTIPLIER;
1065
1066                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1067                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1068                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1069
1070                 rpstat = I915_READ(GEN6_RPSTAT1);
1071                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1072                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1073                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1074                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1075                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1076                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1077                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1078                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1079                 else
1080                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1081                 cagf *= GT_FREQUENCY_MULTIPLIER;
1082
1083                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1084                 mutex_unlock(&dev->struct_mutex);
1085
1086                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1087                         pm_ier = I915_READ(GEN6_PMIER);
1088                         pm_imr = I915_READ(GEN6_PMIMR);
1089                         pm_isr = I915_READ(GEN6_PMISR);
1090                         pm_iir = I915_READ(GEN6_PMIIR);
1091                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1092                 } else {
1093                         pm_ier = I915_READ(GEN8_GT_IER(2));
1094                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1095                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1096                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1097                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1098                 }
1099                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1100                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1101                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1102                 seq_printf(m, "Render p-state ratio: %d\n",
1103                            (gt_perf_status & 0xff00) >> 8);
1104                 seq_printf(m, "Render p-state VID: %d\n",
1105                            gt_perf_status & 0xff);
1106                 seq_printf(m, "Render p-state limit: %d\n",
1107                            rp_state_limits & 0xff);
1108                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1109                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1110                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1111                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1112                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1113                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1114                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1115                            GEN6_CURICONT_MASK);
1116                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1117                            GEN6_CURBSYTAVG_MASK);
1118                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1119                            GEN6_CURBSYTAVG_MASK);
1120                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1121                            GEN6_CURIAVG_MASK);
1122                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1123                            GEN6_CURBSYTAVG_MASK);
1124                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1125                            GEN6_CURBSYTAVG_MASK);
1126
1127                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1128                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1129                            max_freq * GT_FREQUENCY_MULTIPLIER);
1130
1131                 max_freq = (rp_state_cap & 0xff00) >> 8;
1132                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1133                            max_freq * GT_FREQUENCY_MULTIPLIER);
1134
1135                 max_freq = rp_state_cap & 0xff;
1136                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1137                            max_freq * GT_FREQUENCY_MULTIPLIER);
1138
1139                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1140                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1141         } else if (IS_VALLEYVIEW(dev)) {
1142                 u32 freq_sts;
1143
1144                 mutex_lock(&dev_priv->rps.hw_lock);
1145                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1146                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1147                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1148
1149                 seq_printf(m, "max GPU freq: %d MHz\n",
1150                            vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1151
1152                 seq_printf(m, "min GPU freq: %d MHz\n",
1153                            vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1154
1155                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1156                            vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1157
1158                 seq_printf(m, "current GPU freq: %d MHz\n",
1159                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1160                 mutex_unlock(&dev_priv->rps.hw_lock);
1161         } else {
1162                 seq_puts(m, "no P-state info available\n");
1163         }
1164
1165 out:
1166         intel_runtime_pm_put(dev_priv);
1167         return ret;
1168 }
1169
1170 static int ironlake_drpc_info(struct seq_file *m)
1171 {
1172         struct drm_info_node *node = m->private;
1173         struct drm_device *dev = node->minor->dev;
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         u32 rgvmodectl, rstdbyctl;
1176         u16 crstandvid;
1177         int ret;
1178
1179         ret = mutex_lock_interruptible(&dev->struct_mutex);
1180         if (ret)
1181                 return ret;
1182         intel_runtime_pm_get(dev_priv);
1183
1184         rgvmodectl = I915_READ(MEMMODECTL);
1185         rstdbyctl = I915_READ(RSTDBYCTL);
1186         crstandvid = I915_READ16(CRSTANDVID);
1187
1188         intel_runtime_pm_put(dev_priv);
1189         mutex_unlock(&dev->struct_mutex);
1190
1191         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1192                    "yes" : "no");
1193         seq_printf(m, "Boost freq: %d\n",
1194                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1195                    MEMMODE_BOOST_FREQ_SHIFT);
1196         seq_printf(m, "HW control enabled: %s\n",
1197                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1198         seq_printf(m, "SW control enabled: %s\n",
1199                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1200         seq_printf(m, "Gated voltage change: %s\n",
1201                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1202         seq_printf(m, "Starting frequency: P%d\n",
1203                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1204         seq_printf(m, "Max P-state: P%d\n",
1205                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1206         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1207         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1208         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1209         seq_printf(m, "Render standby enabled: %s\n",
1210                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1211         seq_puts(m, "Current RS state: ");
1212         switch (rstdbyctl & RSX_STATUS_MASK) {
1213         case RSX_STATUS_ON:
1214                 seq_puts(m, "on\n");
1215                 break;
1216         case RSX_STATUS_RC1:
1217                 seq_puts(m, "RC1\n");
1218                 break;
1219         case RSX_STATUS_RC1E:
1220                 seq_puts(m, "RC1E\n");
1221                 break;
1222         case RSX_STATUS_RS1:
1223                 seq_puts(m, "RS1\n");
1224                 break;
1225         case RSX_STATUS_RS2:
1226                 seq_puts(m, "RS2 (RC6)\n");
1227                 break;
1228         case RSX_STATUS_RS3:
1229                 seq_puts(m, "RC3 (RC6+)\n");
1230                 break;
1231         default:
1232                 seq_puts(m, "unknown\n");
1233                 break;
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int vlv_drpc_info(struct seq_file *m)
1240 {
1241
1242         struct drm_info_node *node = m->private;
1243         struct drm_device *dev = node->minor->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         u32 rpmodectl1, rcctl1, pw_status;
1246         unsigned fw_rendercount = 0, fw_mediacount = 0;
1247
1248         intel_runtime_pm_get(dev_priv);
1249
1250         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1251         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1252         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1253
1254         intel_runtime_pm_put(dev_priv);
1255
1256         seq_printf(m, "Video Turbo Mode: %s\n",
1257                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1258         seq_printf(m, "Turbo enabled: %s\n",
1259                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1260         seq_printf(m, "HW control enabled: %s\n",
1261                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1262         seq_printf(m, "SW control enabled: %s\n",
1263                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1264                           GEN6_RP_MEDIA_SW_MODE));
1265         seq_printf(m, "RC6 Enabled: %s\n",
1266                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1267                                         GEN6_RC_CTL_EI_MODE(1))));
1268         seq_printf(m, "Render Power Well: %s\n",
1269                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1270         seq_printf(m, "Media Power Well: %s\n",
1271                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1272
1273         seq_printf(m, "Render RC6 residency since boot: %u\n",
1274                    I915_READ(VLV_GT_RENDER_RC6));
1275         seq_printf(m, "Media RC6 residency since boot: %u\n",
1276                    I915_READ(VLV_GT_MEDIA_RC6));
1277
1278         spin_lock_irq(&dev_priv->uncore.lock);
1279         fw_rendercount = dev_priv->uncore.fw_rendercount;
1280         fw_mediacount = dev_priv->uncore.fw_mediacount;
1281         spin_unlock_irq(&dev_priv->uncore.lock);
1282
1283         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1284         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1285
1286
1287         return 0;
1288 }
1289
1290
1291 static int gen6_drpc_info(struct seq_file *m)
1292 {
1293
1294         struct drm_info_node *node = m->private;
1295         struct drm_device *dev = node->minor->dev;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1298         unsigned forcewake_count;
1299         int count = 0, ret;
1300
1301         ret = mutex_lock_interruptible(&dev->struct_mutex);
1302         if (ret)
1303                 return ret;
1304         intel_runtime_pm_get(dev_priv);
1305
1306         spin_lock_irq(&dev_priv->uncore.lock);
1307         forcewake_count = dev_priv->uncore.forcewake_count;
1308         spin_unlock_irq(&dev_priv->uncore.lock);
1309
1310         if (forcewake_count) {
1311                 seq_puts(m, "RC information inaccurate because somebody "
1312                             "holds a forcewake reference \n");
1313         } else {
1314                 /* NB: we cannot use forcewake, else we read the wrong values */
1315                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1316                         udelay(10);
1317                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1318         }
1319
1320         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1321         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1322
1323         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1324         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1325         mutex_unlock(&dev->struct_mutex);
1326         mutex_lock(&dev_priv->rps.hw_lock);
1327         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1328         mutex_unlock(&dev_priv->rps.hw_lock);
1329
1330         intel_runtime_pm_put(dev_priv);
1331
1332         seq_printf(m, "Video Turbo Mode: %s\n",
1333                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1334         seq_printf(m, "HW control enabled: %s\n",
1335                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1336         seq_printf(m, "SW control enabled: %s\n",
1337                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1338                           GEN6_RP_MEDIA_SW_MODE));
1339         seq_printf(m, "RC1e Enabled: %s\n",
1340                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1341         seq_printf(m, "RC6 Enabled: %s\n",
1342                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1343         seq_printf(m, "Deep RC6 Enabled: %s\n",
1344                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1345         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1346                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1347         seq_puts(m, "Current RC state: ");
1348         switch (gt_core_status & GEN6_RCn_MASK) {
1349         case GEN6_RC0:
1350                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1351                         seq_puts(m, "Core Power Down\n");
1352                 else
1353                         seq_puts(m, "on\n");
1354                 break;
1355         case GEN6_RC3:
1356                 seq_puts(m, "RC3\n");
1357                 break;
1358         case GEN6_RC6:
1359                 seq_puts(m, "RC6\n");
1360                 break;
1361         case GEN6_RC7:
1362                 seq_puts(m, "RC7\n");
1363                 break;
1364         default:
1365                 seq_puts(m, "Unknown\n");
1366                 break;
1367         }
1368
1369         seq_printf(m, "Core Power Down: %s\n",
1370                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1371
1372         /* Not exactly sure what this is */
1373         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1374                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1375         seq_printf(m, "RC6 residency since boot: %u\n",
1376                    I915_READ(GEN6_GT_GFX_RC6));
1377         seq_printf(m, "RC6+ residency since boot: %u\n",
1378                    I915_READ(GEN6_GT_GFX_RC6p));
1379         seq_printf(m, "RC6++ residency since boot: %u\n",
1380                    I915_READ(GEN6_GT_GFX_RC6pp));
1381
1382         seq_printf(m, "RC6   voltage: %dmV\n",
1383                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1384         seq_printf(m, "RC6+  voltage: %dmV\n",
1385                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1386         seq_printf(m, "RC6++ voltage: %dmV\n",
1387                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1388         return 0;
1389 }
1390
1391 static int i915_drpc_info(struct seq_file *m, void *unused)
1392 {
1393         struct drm_info_node *node = m->private;
1394         struct drm_device *dev = node->minor->dev;
1395
1396         if (IS_VALLEYVIEW(dev))
1397                 return vlv_drpc_info(m);
1398         else if (INTEL_INFO(dev)->gen >= 6)
1399                 return gen6_drpc_info(m);
1400         else
1401                 return ironlake_drpc_info(m);
1402 }
1403
1404 static int i915_fbc_status(struct seq_file *m, void *unused)
1405 {
1406         struct drm_info_node *node = m->private;
1407         struct drm_device *dev = node->minor->dev;
1408         struct drm_i915_private *dev_priv = dev->dev_private;
1409
1410         if (!HAS_FBC(dev)) {
1411                 seq_puts(m, "FBC unsupported on this chipset\n");
1412                 return 0;
1413         }
1414
1415         intel_runtime_pm_get(dev_priv);
1416
1417         if (intel_fbc_enabled(dev)) {
1418                 seq_puts(m, "FBC enabled\n");
1419         } else {
1420                 seq_puts(m, "FBC disabled: ");
1421                 switch (dev_priv->fbc.no_fbc_reason) {
1422                 case FBC_OK:
1423                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1424                         break;
1425                 case FBC_UNSUPPORTED:
1426                         seq_puts(m, "unsupported by this chipset");
1427                         break;
1428                 case FBC_NO_OUTPUT:
1429                         seq_puts(m, "no outputs");
1430                         break;
1431                 case FBC_STOLEN_TOO_SMALL:
1432                         seq_puts(m, "not enough stolen memory");
1433                         break;
1434                 case FBC_UNSUPPORTED_MODE:
1435                         seq_puts(m, "mode not supported");
1436                         break;
1437                 case FBC_MODE_TOO_LARGE:
1438                         seq_puts(m, "mode too large");
1439                         break;
1440                 case FBC_BAD_PLANE:
1441                         seq_puts(m, "FBC unsupported on plane");
1442                         break;
1443                 case FBC_NOT_TILED:
1444                         seq_puts(m, "scanout buffer not tiled");
1445                         break;
1446                 case FBC_MULTIPLE_PIPES:
1447                         seq_puts(m, "multiple pipes are enabled");
1448                         break;
1449                 case FBC_MODULE_PARAM:
1450                         seq_puts(m, "disabled per module param (default off)");
1451                         break;
1452                 case FBC_CHIP_DEFAULT:
1453                         seq_puts(m, "disabled per chip default");
1454                         break;
1455                 default:
1456                         seq_puts(m, "unknown reason");
1457                 }
1458                 seq_putc(m, '\n');
1459         }
1460
1461         intel_runtime_pm_put(dev_priv);
1462
1463         return 0;
1464 }
1465
1466 static int i915_fbc_fc_get(void *data, u64 *val)
1467 {
1468         struct drm_device *dev = data;
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1472                 return -ENODEV;
1473
1474         drm_modeset_lock_all(dev);
1475         *val = dev_priv->fbc.false_color;
1476         drm_modeset_unlock_all(dev);
1477
1478         return 0;
1479 }
1480
1481 static int i915_fbc_fc_set(void *data, u64 val)
1482 {
1483         struct drm_device *dev = data;
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         u32 reg;
1486
1487         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1488                 return -ENODEV;
1489
1490         drm_modeset_lock_all(dev);
1491
1492         reg = I915_READ(ILK_DPFC_CONTROL);
1493         dev_priv->fbc.false_color = val;
1494
1495         I915_WRITE(ILK_DPFC_CONTROL, val ?
1496                    (reg | FBC_CTL_FALSE_COLOR) :
1497                    (reg & ~FBC_CTL_FALSE_COLOR));
1498
1499         drm_modeset_unlock_all(dev);
1500         return 0;
1501 }
1502
1503 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1504                         i915_fbc_fc_get, i915_fbc_fc_set,
1505                         "%llu\n");
1506
1507 static int i915_ips_status(struct seq_file *m, void *unused)
1508 {
1509         struct drm_info_node *node = m->private;
1510         struct drm_device *dev = node->minor->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513         if (!HAS_IPS(dev)) {
1514                 seq_puts(m, "not supported\n");
1515                 return 0;
1516         }
1517
1518         intel_runtime_pm_get(dev_priv);
1519
1520         seq_printf(m, "Enabled by kernel parameter: %s\n",
1521                    yesno(i915.enable_ips));
1522
1523         if (INTEL_INFO(dev)->gen >= 8) {
1524                 seq_puts(m, "Currently: unknown\n");
1525         } else {
1526                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1527                         seq_puts(m, "Currently: enabled\n");
1528                 else
1529                         seq_puts(m, "Currently: disabled\n");
1530         }
1531
1532         intel_runtime_pm_put(dev_priv);
1533
1534         return 0;
1535 }
1536
1537 static int i915_sr_status(struct seq_file *m, void *unused)
1538 {
1539         struct drm_info_node *node = m->private;
1540         struct drm_device *dev = node->minor->dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         bool sr_enabled = false;
1543
1544         intel_runtime_pm_get(dev_priv);
1545
1546         if (HAS_PCH_SPLIT(dev))
1547                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1548         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1549                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1550         else if (IS_I915GM(dev))
1551                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1552         else if (IS_PINEVIEW(dev))
1553                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1554
1555         intel_runtime_pm_put(dev_priv);
1556
1557         seq_printf(m, "self-refresh: %s\n",
1558                    sr_enabled ? "enabled" : "disabled");
1559
1560         return 0;
1561 }
1562
1563 static int i915_emon_status(struct seq_file *m, void *unused)
1564 {
1565         struct drm_info_node *node = m->private;
1566         struct drm_device *dev = node->minor->dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         unsigned long temp, chipset, gfx;
1569         int ret;
1570
1571         if (!IS_GEN5(dev))
1572                 return -ENODEV;
1573
1574         ret = mutex_lock_interruptible(&dev->struct_mutex);
1575         if (ret)
1576                 return ret;
1577
1578         temp = i915_mch_val(dev_priv);
1579         chipset = i915_chipset_val(dev_priv);
1580         gfx = i915_gfx_val(dev_priv);
1581         mutex_unlock(&dev->struct_mutex);
1582
1583         seq_printf(m, "GMCH temp: %ld\n", temp);
1584         seq_printf(m, "Chipset power: %ld\n", chipset);
1585         seq_printf(m, "GFX power: %ld\n", gfx);
1586         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1587
1588         return 0;
1589 }
1590
1591 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1592 {
1593         struct drm_info_node *node = m->private;
1594         struct drm_device *dev = node->minor->dev;
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         int ret = 0;
1597         int gpu_freq, ia_freq;
1598
1599         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1600                 seq_puts(m, "unsupported on this chipset\n");
1601                 return 0;
1602         }
1603
1604         intel_runtime_pm_get(dev_priv);
1605
1606         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1607
1608         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1609         if (ret)
1610                 goto out;
1611
1612         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1613
1614         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1615              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1616              gpu_freq++) {
1617                 ia_freq = gpu_freq;
1618                 sandybridge_pcode_read(dev_priv,
1619                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1620                                        &ia_freq);
1621                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1622                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1623                            ((ia_freq >> 0) & 0xff) * 100,
1624                            ((ia_freq >> 8) & 0xff) * 100);
1625         }
1626
1627         mutex_unlock(&dev_priv->rps.hw_lock);
1628
1629 out:
1630         intel_runtime_pm_put(dev_priv);
1631         return ret;
1632 }
1633
1634 static int i915_opregion(struct seq_file *m, void *unused)
1635 {
1636         struct drm_info_node *node = m->private;
1637         struct drm_device *dev = node->minor->dev;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         struct intel_opregion *opregion = &dev_priv->opregion;
1640         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1641         int ret;
1642
1643         if (data == NULL)
1644                 return -ENOMEM;
1645
1646         ret = mutex_lock_interruptible(&dev->struct_mutex);
1647         if (ret)
1648                 goto out;
1649
1650         if (opregion->header) {
1651                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1652                 seq_write(m, data, OPREGION_SIZE);
1653         }
1654
1655         mutex_unlock(&dev->struct_mutex);
1656
1657 out:
1658         kfree(data);
1659         return 0;
1660 }
1661
1662 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1663 {
1664         struct drm_info_node *node = m->private;
1665         struct drm_device *dev = node->minor->dev;
1666         struct intel_fbdev *ifbdev = NULL;
1667         struct intel_framebuffer *fb;
1668
1669 #ifdef CONFIG_DRM_I915_FBDEV
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671
1672         ifbdev = dev_priv->fbdev;
1673         fb = to_intel_framebuffer(ifbdev->helper.fb);
1674
1675         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1676                    fb->base.width,
1677                    fb->base.height,
1678                    fb->base.depth,
1679                    fb->base.bits_per_pixel,
1680                    atomic_read(&fb->base.refcount.refcount));
1681         describe_obj(m, fb->obj);
1682         seq_putc(m, '\n');
1683 #endif
1684
1685         mutex_lock(&dev->mode_config.fb_lock);
1686         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1687                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1688                         continue;
1689
1690                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1691                            fb->base.width,
1692                            fb->base.height,
1693                            fb->base.depth,
1694                            fb->base.bits_per_pixel,
1695                            atomic_read(&fb->base.refcount.refcount));
1696                 describe_obj(m, fb->obj);
1697                 seq_putc(m, '\n');
1698         }
1699         mutex_unlock(&dev->mode_config.fb_lock);
1700
1701         return 0;
1702 }
1703
1704 static void describe_ctx_ringbuf(struct seq_file *m,
1705                                  struct intel_ringbuffer *ringbuf)
1706 {
1707         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1708                    ringbuf->space, ringbuf->head, ringbuf->tail,
1709                    ringbuf->last_retired_head);
1710 }
1711
1712 static int i915_context_status(struct seq_file *m, void *unused)
1713 {
1714         struct drm_info_node *node = m->private;
1715         struct drm_device *dev = node->minor->dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct intel_engine_cs *ring;
1718         struct intel_context *ctx;
1719         int ret, i;
1720
1721         ret = mutex_lock_interruptible(&dev->struct_mutex);
1722         if (ret)
1723                 return ret;
1724
1725         if (dev_priv->ips.pwrctx) {
1726                 seq_puts(m, "power context ");
1727                 describe_obj(m, dev_priv->ips.pwrctx);
1728                 seq_putc(m, '\n');
1729         }
1730
1731         if (dev_priv->ips.renderctx) {
1732                 seq_puts(m, "render context ");
1733                 describe_obj(m, dev_priv->ips.renderctx);
1734                 seq_putc(m, '\n');
1735         }
1736
1737         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1738                 if (!i915.enable_execlists &&
1739                     ctx->legacy_hw_ctx.rcs_state == NULL)
1740                         continue;
1741
1742                 seq_puts(m, "HW context ");
1743                 describe_ctx(m, ctx);
1744                 for_each_ring(ring, dev_priv, i) {
1745                         if (ring->default_context == ctx)
1746                                 seq_printf(m, "(default context %s) ",
1747                                            ring->name);
1748                 }
1749
1750                 if (i915.enable_execlists) {
1751                         seq_putc(m, '\n');
1752                         for_each_ring(ring, dev_priv, i) {
1753                                 struct drm_i915_gem_object *ctx_obj =
1754                                         ctx->engine[i].state;
1755                                 struct intel_ringbuffer *ringbuf =
1756                                         ctx->engine[i].ringbuf;
1757
1758                                 seq_printf(m, "%s: ", ring->name);
1759                                 if (ctx_obj)
1760                                         describe_obj(m, ctx_obj);
1761                                 if (ringbuf)
1762                                         describe_ctx_ringbuf(m, ringbuf);
1763                                 seq_putc(m, '\n');
1764                         }
1765                 } else {
1766                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1767                 }
1768
1769                 seq_putc(m, '\n');
1770         }
1771
1772         mutex_unlock(&dev->struct_mutex);
1773
1774         return 0;
1775 }
1776
1777 static void i915_dump_lrc_obj(struct seq_file *m,
1778                               struct intel_engine_cs *ring,
1779                               struct drm_i915_gem_object *ctx_obj)
1780 {
1781         struct page *page;
1782         uint32_t *reg_state;
1783         int j;
1784         unsigned long ggtt_offset = 0;
1785
1786         if (ctx_obj == NULL) {
1787                 seq_printf(m, "Context on %s with no gem object\n",
1788                            ring->name);
1789                 return;
1790         }
1791
1792         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1793                    intel_execlists_ctx_id(ctx_obj));
1794
1795         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1796                 seq_puts(m, "\tNot bound in GGTT\n");
1797         else
1798                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1799
1800         if (i915_gem_object_get_pages(ctx_obj)) {
1801                 seq_puts(m, "\tFailed to get pages for context object\n");
1802                 return;
1803         }
1804
1805         page = i915_gem_object_get_page(ctx_obj, 1);
1806         if (!WARN_ON(page == NULL)) {
1807                 reg_state = kmap_atomic(page);
1808
1809                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1810                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1811                                    ggtt_offset + 4096 + (j * 4),
1812                                    reg_state[j], reg_state[j + 1],
1813                                    reg_state[j + 2], reg_state[j + 3]);
1814                 }
1815                 kunmap_atomic(reg_state);
1816         }
1817
1818         seq_putc(m, '\n');
1819 }
1820
1821 static int i915_dump_lrc(struct seq_file *m, void *unused)
1822 {
1823         struct drm_info_node *node = (struct drm_info_node *) m->private;
1824         struct drm_device *dev = node->minor->dev;
1825         struct drm_i915_private *dev_priv = dev->dev_private;
1826         struct intel_engine_cs *ring;
1827         struct intel_context *ctx;
1828         int ret, i;
1829
1830         if (!i915.enable_execlists) {
1831                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1832                 return 0;
1833         }
1834
1835         ret = mutex_lock_interruptible(&dev->struct_mutex);
1836         if (ret)
1837                 return ret;
1838
1839         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1840                 for_each_ring(ring, dev_priv, i) {
1841                         if (ring->default_context != ctx)
1842                                 i915_dump_lrc_obj(m, ring,
1843                                                   ctx->engine[i].state);
1844                 }
1845         }
1846
1847         mutex_unlock(&dev->struct_mutex);
1848
1849         return 0;
1850 }
1851
1852 static int i915_execlists(struct seq_file *m, void *data)
1853 {
1854         struct drm_info_node *node = (struct drm_info_node *)m->private;
1855         struct drm_device *dev = node->minor->dev;
1856         struct drm_i915_private *dev_priv = dev->dev_private;
1857         struct intel_engine_cs *ring;
1858         u32 status_pointer;
1859         u8 read_pointer;
1860         u8 write_pointer;
1861         u32 status;
1862         u32 ctx_id;
1863         struct list_head *cursor;
1864         int ring_id, i;
1865         int ret;
1866
1867         if (!i915.enable_execlists) {
1868                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1869                 return 0;
1870         }
1871
1872         ret = mutex_lock_interruptible(&dev->struct_mutex);
1873         if (ret)
1874                 return ret;
1875
1876         intel_runtime_pm_get(dev_priv);
1877
1878         for_each_ring(ring, dev_priv, ring_id) {
1879                 struct intel_ctx_submit_request *head_req = NULL;
1880                 int count = 0;
1881                 unsigned long flags;
1882
1883                 seq_printf(m, "%s\n", ring->name);
1884
1885                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1886                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1887                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1888                            status, ctx_id);
1889
1890                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1891                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1892
1893                 read_pointer = ring->next_context_status_buffer;
1894                 write_pointer = status_pointer & 0x07;
1895                 if (read_pointer > write_pointer)
1896                         write_pointer += 6;
1897                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1898                            read_pointer, write_pointer);
1899
1900                 for (i = 0; i < 6; i++) {
1901                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1902                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1903
1904                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1905                                    i, status, ctx_id);
1906                 }
1907
1908                 spin_lock_irqsave(&ring->execlist_lock, flags);
1909                 list_for_each(cursor, &ring->execlist_queue)
1910                         count++;
1911                 head_req = list_first_entry_or_null(&ring->execlist_queue,
1912                                 struct intel_ctx_submit_request, execlist_link);
1913                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1914
1915                 seq_printf(m, "\t%d requests in queue\n", count);
1916                 if (head_req) {
1917                         struct drm_i915_gem_object *ctx_obj;
1918
1919                         ctx_obj = head_req->ctx->engine[ring_id].state;
1920                         seq_printf(m, "\tHead request id: %u\n",
1921                                    intel_execlists_ctx_id(ctx_obj));
1922                         seq_printf(m, "\tHead request tail: %u\n",
1923                                    head_req->tail);
1924                 }
1925
1926                 seq_putc(m, '\n');
1927         }
1928
1929         intel_runtime_pm_put(dev_priv);
1930         mutex_unlock(&dev->struct_mutex);
1931
1932         return 0;
1933 }
1934
1935 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1936 {
1937         struct drm_info_node *node = m->private;
1938         struct drm_device *dev = node->minor->dev;
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1941
1942         spin_lock_irq(&dev_priv->uncore.lock);
1943         if (IS_VALLEYVIEW(dev)) {
1944                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1945                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1946         } else
1947                 forcewake_count = dev_priv->uncore.forcewake_count;
1948         spin_unlock_irq(&dev_priv->uncore.lock);
1949
1950         if (IS_VALLEYVIEW(dev)) {
1951                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1952                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1953         } else
1954                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1955
1956         return 0;
1957 }
1958
1959 static const char *swizzle_string(unsigned swizzle)
1960 {
1961         switch (swizzle) {
1962         case I915_BIT_6_SWIZZLE_NONE:
1963                 return "none";
1964         case I915_BIT_6_SWIZZLE_9:
1965                 return "bit9";
1966         case I915_BIT_6_SWIZZLE_9_10:
1967                 return "bit9/bit10";
1968         case I915_BIT_6_SWIZZLE_9_11:
1969                 return "bit9/bit11";
1970         case I915_BIT_6_SWIZZLE_9_10_11:
1971                 return "bit9/bit10/bit11";
1972         case I915_BIT_6_SWIZZLE_9_17:
1973                 return "bit9/bit17";
1974         case I915_BIT_6_SWIZZLE_9_10_17:
1975                 return "bit9/bit10/bit17";
1976         case I915_BIT_6_SWIZZLE_UNKNOWN:
1977                 return "unknown";
1978         }
1979
1980         return "bug";
1981 }
1982
1983 static int i915_swizzle_info(struct seq_file *m, void *data)
1984 {
1985         struct drm_info_node *node = m->private;
1986         struct drm_device *dev = node->minor->dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         int ret;
1989
1990         ret = mutex_lock_interruptible(&dev->struct_mutex);
1991         if (ret)
1992                 return ret;
1993         intel_runtime_pm_get(dev_priv);
1994
1995         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1996                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1997         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1998                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1999
2000         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2001                 seq_printf(m, "DDC = 0x%08x\n",
2002                            I915_READ(DCC));
2003                 seq_printf(m, "DDC2 = 0x%08x\n",
2004                            I915_READ(DCC2));
2005                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2006                            I915_READ16(C0DRB3));
2007                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2008                            I915_READ16(C1DRB3));
2009         } else if (INTEL_INFO(dev)->gen >= 6) {
2010                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2011                            I915_READ(MAD_DIMM_C0));
2012                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2013                            I915_READ(MAD_DIMM_C1));
2014                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2015                            I915_READ(MAD_DIMM_C2));
2016                 seq_printf(m, "TILECTL = 0x%08x\n",
2017                            I915_READ(TILECTL));
2018                 if (INTEL_INFO(dev)->gen >= 8)
2019                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2020                                    I915_READ(GAMTARBMODE));
2021                 else
2022                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2023                                    I915_READ(ARB_MODE));
2024                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2025                            I915_READ(DISP_ARB_CTL));
2026         }
2027
2028         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2029                 seq_puts(m, "L-shaped memory detected\n");
2030
2031         intel_runtime_pm_put(dev_priv);
2032         mutex_unlock(&dev->struct_mutex);
2033
2034         return 0;
2035 }
2036
2037 static int per_file_ctx(int id, void *ptr, void *data)
2038 {
2039         struct intel_context *ctx = ptr;
2040         struct seq_file *m = data;
2041         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2042
2043         if (!ppgtt) {
2044                 seq_printf(m, "  no ppgtt for context %d\n",
2045                            ctx->user_handle);
2046                 return 0;
2047         }
2048
2049         if (i915_gem_context_is_default(ctx))
2050                 seq_puts(m, "  default context:\n");
2051         else
2052                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2053         ppgtt->debug_dump(ppgtt, m);
2054
2055         return 0;
2056 }
2057
2058 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2059 {
2060         struct drm_i915_private *dev_priv = dev->dev_private;
2061         struct intel_engine_cs *ring;
2062         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2063         int unused, i;
2064
2065         if (!ppgtt)
2066                 return;
2067
2068         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2069         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2070         for_each_ring(ring, dev_priv, unused) {
2071                 seq_printf(m, "%s\n", ring->name);
2072                 for (i = 0; i < 4; i++) {
2073                         u32 offset = 0x270 + i * 8;
2074                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2075                         pdp <<= 32;
2076                         pdp |= I915_READ(ring->mmio_base + offset);
2077                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2078                 }
2079         }
2080 }
2081
2082 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2083 {
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         struct intel_engine_cs *ring;
2086         struct drm_file *file;
2087         int i;
2088
2089         if (INTEL_INFO(dev)->gen == 6)
2090                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2091
2092         for_each_ring(ring, dev_priv, i) {
2093                 seq_printf(m, "%s\n", ring->name);
2094                 if (INTEL_INFO(dev)->gen == 7)
2095                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2096                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2097                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2098                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2099         }
2100         if (dev_priv->mm.aliasing_ppgtt) {
2101                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2102
2103                 seq_puts(m, "aliasing PPGTT:\n");
2104                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2105
2106                 ppgtt->debug_dump(ppgtt, m);
2107         }
2108
2109         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2110                 struct drm_i915_file_private *file_priv = file->driver_priv;
2111
2112                 seq_printf(m, "proc: %s\n",
2113                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2114                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2115         }
2116         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2117 }
2118
2119 static int i915_ppgtt_info(struct seq_file *m, void *data)
2120 {
2121         struct drm_info_node *node = m->private;
2122         struct drm_device *dev = node->minor->dev;
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124
2125         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2126         if (ret)
2127                 return ret;
2128         intel_runtime_pm_get(dev_priv);
2129
2130         if (INTEL_INFO(dev)->gen >= 8)
2131                 gen8_ppgtt_info(m, dev);
2132         else if (INTEL_INFO(dev)->gen >= 6)
2133                 gen6_ppgtt_info(m, dev);
2134
2135         intel_runtime_pm_put(dev_priv);
2136         mutex_unlock(&dev->struct_mutex);
2137
2138         return 0;
2139 }
2140
2141 static int i915_llc(struct seq_file *m, void *data)
2142 {
2143         struct drm_info_node *node = m->private;
2144         struct drm_device *dev = node->minor->dev;
2145         struct drm_i915_private *dev_priv = dev->dev_private;
2146
2147         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2148         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2149         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2150
2151         return 0;
2152 }
2153
2154 static int i915_edp_psr_status(struct seq_file *m, void *data)
2155 {
2156         struct drm_info_node *node = m->private;
2157         struct drm_device *dev = node->minor->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         u32 psrperf = 0;
2160         u32 stat[3];
2161         enum pipe pipe;
2162         bool enabled = false;
2163
2164         intel_runtime_pm_get(dev_priv);
2165
2166         mutex_lock(&dev_priv->psr.lock);
2167         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2168         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2169         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2170         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2171         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2172                    dev_priv->psr.busy_frontbuffer_bits);
2173         seq_printf(m, "Re-enable work scheduled: %s\n",
2174                    yesno(work_busy(&dev_priv->psr.work.work)));
2175
2176         if (HAS_PSR(dev)) {
2177                 if (HAS_DDI(dev))
2178                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2179                 else {
2180                         for_each_pipe(dev_priv, pipe) {
2181                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2182                                         VLV_EDP_PSR_CURR_STATE_MASK;
2183                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2184                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2185                                         enabled = true;
2186                         }
2187                 }
2188         }
2189         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2190
2191         if (!HAS_DDI(dev))
2192                 for_each_pipe(dev_priv, pipe) {
2193                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2194                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2195                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2196                 }
2197         seq_puts(m, "\n");
2198
2199         /* CHV PSR has no kind of performance counter */
2200         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2201                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2202                         EDP_PSR_PERF_CNT_MASK;
2203
2204                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2205         }
2206         mutex_unlock(&dev_priv->psr.lock);
2207
2208         intel_runtime_pm_put(dev_priv);
2209         return 0;
2210 }
2211
2212 static int i915_sink_crc(struct seq_file *m, void *data)
2213 {
2214         struct drm_info_node *node = m->private;
2215         struct drm_device *dev = node->minor->dev;
2216         struct intel_encoder *encoder;
2217         struct intel_connector *connector;
2218         struct intel_dp *intel_dp = NULL;
2219         int ret;
2220         u8 crc[6];
2221
2222         drm_modeset_lock_all(dev);
2223         list_for_each_entry(connector, &dev->mode_config.connector_list,
2224                             base.head) {
2225
2226                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2227                         continue;
2228
2229                 if (!connector->base.encoder)
2230                         continue;
2231
2232                 encoder = to_intel_encoder(connector->base.encoder);
2233                 if (encoder->type != INTEL_OUTPUT_EDP)
2234                         continue;
2235
2236                 intel_dp = enc_to_intel_dp(&encoder->base);
2237
2238                 ret = intel_dp_sink_crc(intel_dp, crc);
2239                 if (ret)
2240                         goto out;
2241
2242                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2243                            crc[0], crc[1], crc[2],
2244                            crc[3], crc[4], crc[5]);
2245                 goto out;
2246         }
2247         ret = -ENODEV;
2248 out:
2249         drm_modeset_unlock_all(dev);
2250         return ret;
2251 }
2252
2253 static int i915_energy_uJ(struct seq_file *m, void *data)
2254 {
2255         struct drm_info_node *node = m->private;
2256         struct drm_device *dev = node->minor->dev;
2257         struct drm_i915_private *dev_priv = dev->dev_private;
2258         u64 power;
2259         u32 units;
2260
2261         if (INTEL_INFO(dev)->gen < 6)
2262                 return -ENODEV;
2263
2264         intel_runtime_pm_get(dev_priv);
2265
2266         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2267         power = (power & 0x1f00) >> 8;
2268         units = 1000000 / (1 << power); /* convert to uJ */
2269         power = I915_READ(MCH_SECP_NRG_STTS);
2270         power *= units;
2271
2272         intel_runtime_pm_put(dev_priv);
2273
2274         seq_printf(m, "%llu", (long long unsigned)power);
2275
2276         return 0;
2277 }
2278
2279 static int i915_pc8_status(struct seq_file *m, void *unused)
2280 {
2281         struct drm_info_node *node = m->private;
2282         struct drm_device *dev = node->minor->dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284
2285         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2286                 seq_puts(m, "not supported\n");
2287                 return 0;
2288         }
2289
2290         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2291         seq_printf(m, "IRQs disabled: %s\n",
2292                    yesno(!intel_irqs_enabled(dev_priv)));
2293
2294         return 0;
2295 }
2296
2297 static const char *power_domain_str(enum intel_display_power_domain domain)
2298 {
2299         switch (domain) {
2300         case POWER_DOMAIN_PIPE_A:
2301                 return "PIPE_A";
2302         case POWER_DOMAIN_PIPE_B:
2303                 return "PIPE_B";
2304         case POWER_DOMAIN_PIPE_C:
2305                 return "PIPE_C";
2306         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2307                 return "PIPE_A_PANEL_FITTER";
2308         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2309                 return "PIPE_B_PANEL_FITTER";
2310         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2311                 return "PIPE_C_PANEL_FITTER";
2312         case POWER_DOMAIN_TRANSCODER_A:
2313                 return "TRANSCODER_A";
2314         case POWER_DOMAIN_TRANSCODER_B:
2315                 return "TRANSCODER_B";
2316         case POWER_DOMAIN_TRANSCODER_C:
2317                 return "TRANSCODER_C";
2318         case POWER_DOMAIN_TRANSCODER_EDP:
2319                 return "TRANSCODER_EDP";
2320         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2321                 return "PORT_DDI_A_2_LANES";
2322         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2323                 return "PORT_DDI_A_4_LANES";
2324         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2325                 return "PORT_DDI_B_2_LANES";
2326         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2327                 return "PORT_DDI_B_4_LANES";
2328         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2329                 return "PORT_DDI_C_2_LANES";
2330         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2331                 return "PORT_DDI_C_4_LANES";
2332         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2333                 return "PORT_DDI_D_2_LANES";
2334         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2335                 return "PORT_DDI_D_4_LANES";
2336         case POWER_DOMAIN_PORT_DSI:
2337                 return "PORT_DSI";
2338         case POWER_DOMAIN_PORT_CRT:
2339                 return "PORT_CRT";
2340         case POWER_DOMAIN_PORT_OTHER:
2341                 return "PORT_OTHER";
2342         case POWER_DOMAIN_VGA:
2343                 return "VGA";
2344         case POWER_DOMAIN_AUDIO:
2345                 return "AUDIO";
2346         case POWER_DOMAIN_PLLS:
2347                 return "PLLS";
2348         case POWER_DOMAIN_INIT:
2349                 return "INIT";
2350         default:
2351                 MISSING_CASE(domain);
2352                 return "?";
2353         }
2354 }
2355
2356 static int i915_power_domain_info(struct seq_file *m, void *unused)
2357 {
2358         struct drm_info_node *node = m->private;
2359         struct drm_device *dev = node->minor->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2362         int i;
2363
2364         mutex_lock(&power_domains->lock);
2365
2366         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2367         for (i = 0; i < power_domains->power_well_count; i++) {
2368                 struct i915_power_well *power_well;
2369                 enum intel_display_power_domain power_domain;
2370
2371                 power_well = &power_domains->power_wells[i];
2372                 seq_printf(m, "%-25s %d\n", power_well->name,
2373                            power_well->count);
2374
2375                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2376                      power_domain++) {
2377                         if (!(BIT(power_domain) & power_well->domains))
2378                                 continue;
2379
2380                         seq_printf(m, "  %-23s %d\n",
2381                                  power_domain_str(power_domain),
2382                                  power_domains->domain_use_count[power_domain]);
2383                 }
2384         }
2385
2386         mutex_unlock(&power_domains->lock);
2387
2388         return 0;
2389 }
2390
2391 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2392                                  struct drm_display_mode *mode)
2393 {
2394         int i;
2395
2396         for (i = 0; i < tabs; i++)
2397                 seq_putc(m, '\t');
2398
2399         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2400                    mode->base.id, mode->name,
2401                    mode->vrefresh, mode->clock,
2402                    mode->hdisplay, mode->hsync_start,
2403                    mode->hsync_end, mode->htotal,
2404                    mode->vdisplay, mode->vsync_start,
2405                    mode->vsync_end, mode->vtotal,
2406                    mode->type, mode->flags);
2407 }
2408
2409 static void intel_encoder_info(struct seq_file *m,
2410                                struct intel_crtc *intel_crtc,
2411                                struct intel_encoder *intel_encoder)
2412 {
2413         struct drm_info_node *node = m->private;
2414         struct drm_device *dev = node->minor->dev;
2415         struct drm_crtc *crtc = &intel_crtc->base;
2416         struct intel_connector *intel_connector;
2417         struct drm_encoder *encoder;
2418
2419         encoder = &intel_encoder->base;
2420         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2421                    encoder->base.id, encoder->name);
2422         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2423                 struct drm_connector *connector = &intel_connector->base;
2424                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2425                            connector->base.id,
2426                            connector->name,
2427                            drm_get_connector_status_name(connector->status));
2428                 if (connector->status == connector_status_connected) {
2429                         struct drm_display_mode *mode = &crtc->mode;
2430                         seq_printf(m, ", mode:\n");
2431                         intel_seq_print_mode(m, 2, mode);
2432                 } else {
2433                         seq_putc(m, '\n');
2434                 }
2435         }
2436 }
2437
2438 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2439 {
2440         struct drm_info_node *node = m->private;
2441         struct drm_device *dev = node->minor->dev;
2442         struct drm_crtc *crtc = &intel_crtc->base;
2443         struct intel_encoder *intel_encoder;
2444
2445         if (crtc->primary->fb)
2446                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2447                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2448                            crtc->primary->fb->width, crtc->primary->fb->height);
2449         else
2450                 seq_puts(m, "\tprimary plane disabled\n");
2451         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2452                 intel_encoder_info(m, intel_crtc, intel_encoder);
2453 }
2454
2455 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2456 {
2457         struct drm_display_mode *mode = panel->fixed_mode;
2458
2459         seq_printf(m, "\tfixed mode:\n");
2460         intel_seq_print_mode(m, 2, mode);
2461 }
2462
2463 static void intel_dp_info(struct seq_file *m,
2464                           struct intel_connector *intel_connector)
2465 {
2466         struct intel_encoder *intel_encoder = intel_connector->encoder;
2467         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2468
2469         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2470         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2471                    "no");
2472         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2473                 intel_panel_info(m, &intel_connector->panel);
2474 }
2475
2476 static void intel_hdmi_info(struct seq_file *m,
2477                             struct intel_connector *intel_connector)
2478 {
2479         struct intel_encoder *intel_encoder = intel_connector->encoder;
2480         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2481
2482         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2483                    "no");
2484 }
2485
2486 static void intel_lvds_info(struct seq_file *m,
2487                             struct intel_connector *intel_connector)
2488 {
2489         intel_panel_info(m, &intel_connector->panel);
2490 }
2491
2492 static void intel_connector_info(struct seq_file *m,
2493                                  struct drm_connector *connector)
2494 {
2495         struct intel_connector *intel_connector = to_intel_connector(connector);
2496         struct intel_encoder *intel_encoder = intel_connector->encoder;
2497         struct drm_display_mode *mode;
2498
2499         seq_printf(m, "connector %d: type %s, status: %s\n",
2500                    connector->base.id, connector->name,
2501                    drm_get_connector_status_name(connector->status));
2502         if (connector->status == connector_status_connected) {
2503                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2504                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2505                            connector->display_info.width_mm,
2506                            connector->display_info.height_mm);
2507                 seq_printf(m, "\tsubpixel order: %s\n",
2508                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2509                 seq_printf(m, "\tCEA rev: %d\n",
2510                            connector->display_info.cea_rev);
2511         }
2512         if (intel_encoder) {
2513                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2514                     intel_encoder->type == INTEL_OUTPUT_EDP)
2515                         intel_dp_info(m, intel_connector);
2516                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2517                         intel_hdmi_info(m, intel_connector);
2518                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2519                         intel_lvds_info(m, intel_connector);
2520         }
2521
2522         seq_printf(m, "\tmodes:\n");
2523         list_for_each_entry(mode, &connector->modes, head)
2524                 intel_seq_print_mode(m, 2, mode);
2525 }
2526
2527 static bool cursor_active(struct drm_device *dev, int pipe)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         u32 state;
2531
2532         if (IS_845G(dev) || IS_I865G(dev))
2533                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2534         else
2535                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2536
2537         return state;
2538 }
2539
2540 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2541 {
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         u32 pos;
2544
2545         pos = I915_READ(CURPOS(pipe));
2546
2547         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2548         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2549                 *x = -*x;
2550
2551         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2552         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2553                 *y = -*y;
2554
2555         return cursor_active(dev, pipe);
2556 }
2557
2558 static int i915_display_info(struct seq_file *m, void *unused)
2559 {
2560         struct drm_info_node *node = m->private;
2561         struct drm_device *dev = node->minor->dev;
2562         struct drm_i915_private *dev_priv = dev->dev_private;
2563         struct intel_crtc *crtc;
2564         struct drm_connector *connector;
2565
2566         intel_runtime_pm_get(dev_priv);
2567         drm_modeset_lock_all(dev);
2568         seq_printf(m, "CRTC info\n");
2569         seq_printf(m, "---------\n");
2570         for_each_intel_crtc(dev, crtc) {
2571                 bool active;
2572                 int x, y;
2573
2574                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2575                            crtc->base.base.id, pipe_name(crtc->pipe),
2576                            yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2577                 if (crtc->active) {
2578                         intel_crtc_info(m, crtc);
2579
2580                         active = cursor_position(dev, crtc->pipe, &x, &y);
2581                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2582                                    yesno(crtc->cursor_base),
2583                                    x, y, crtc->cursor_width, crtc->cursor_height,
2584                                    crtc->cursor_addr, yesno(active));
2585                 }
2586
2587                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2588                            yesno(!crtc->cpu_fifo_underrun_disabled),
2589                            yesno(!crtc->pch_fifo_underrun_disabled));
2590         }
2591
2592         seq_printf(m, "\n");
2593         seq_printf(m, "Connector info\n");
2594         seq_printf(m, "--------------\n");
2595         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2596                 intel_connector_info(m, connector);
2597         }
2598         drm_modeset_unlock_all(dev);
2599         intel_runtime_pm_put(dev_priv);
2600
2601         return 0;
2602 }
2603
2604 static int i915_semaphore_status(struct seq_file *m, void *unused)
2605 {
2606         struct drm_info_node *node = (struct drm_info_node *) m->private;
2607         struct drm_device *dev = node->minor->dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct intel_engine_cs *ring;
2610         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2611         int i, j, ret;
2612
2613         if (!i915_semaphore_is_enabled(dev)) {
2614                 seq_puts(m, "Semaphores are disabled\n");
2615                 return 0;
2616         }
2617
2618         ret = mutex_lock_interruptible(&dev->struct_mutex);
2619         if (ret)
2620                 return ret;
2621         intel_runtime_pm_get(dev_priv);
2622
2623         if (IS_BROADWELL(dev)) {
2624                 struct page *page;
2625                 uint64_t *seqno;
2626
2627                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2628
2629                 seqno = (uint64_t *)kmap_atomic(page);
2630                 for_each_ring(ring, dev_priv, i) {
2631                         uint64_t offset;
2632
2633                         seq_printf(m, "%s\n", ring->name);
2634
2635                         seq_puts(m, "  Last signal:");
2636                         for (j = 0; j < num_rings; j++) {
2637                                 offset = i * I915_NUM_RINGS + j;
2638                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2639                                            seqno[offset], offset * 8);
2640                         }
2641                         seq_putc(m, '\n');
2642
2643                         seq_puts(m, "  Last wait:  ");
2644                         for (j = 0; j < num_rings; j++) {
2645                                 offset = i + (j * I915_NUM_RINGS);
2646                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2647                                            seqno[offset], offset * 8);
2648                         }
2649                         seq_putc(m, '\n');
2650
2651                 }
2652                 kunmap_atomic(seqno);
2653         } else {
2654                 seq_puts(m, "  Last signal:");
2655                 for_each_ring(ring, dev_priv, i)
2656                         for (j = 0; j < num_rings; j++)
2657                                 seq_printf(m, "0x%08x\n",
2658                                            I915_READ(ring->semaphore.mbox.signal[j]));
2659                 seq_putc(m, '\n');
2660         }
2661
2662         seq_puts(m, "\nSync seqno:\n");
2663         for_each_ring(ring, dev_priv, i) {
2664                 for (j = 0; j < num_rings; j++) {
2665                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2666                 }
2667                 seq_putc(m, '\n');
2668         }
2669         seq_putc(m, '\n');
2670
2671         intel_runtime_pm_put(dev_priv);
2672         mutex_unlock(&dev->struct_mutex);
2673         return 0;
2674 }
2675
2676 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2677 {
2678         struct drm_info_node *node = (struct drm_info_node *) m->private;
2679         struct drm_device *dev = node->minor->dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         int i;
2682
2683         drm_modeset_lock_all(dev);
2684         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2685                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2686
2687                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2688                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2689                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2690                 seq_printf(m, " tracked hardware state:\n");
2691                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2692                 seq_printf(m, " dpll_md: 0x%08x\n",
2693                            pll->config.hw_state.dpll_md);
2694                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2695                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2696                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2697         }
2698         drm_modeset_unlock_all(dev);
2699
2700         return 0;
2701 }
2702
2703 static int i915_wa_registers(struct seq_file *m, void *unused)
2704 {
2705         int i;
2706         int ret;
2707         struct drm_info_node *node = (struct drm_info_node *) m->private;
2708         struct drm_device *dev = node->minor->dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710
2711         ret = mutex_lock_interruptible(&dev->struct_mutex);
2712         if (ret)
2713                 return ret;
2714
2715         intel_runtime_pm_get(dev_priv);
2716
2717         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2718         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2719                 u32 addr, mask, value, read;
2720                 bool ok;
2721
2722                 addr = dev_priv->workarounds.reg[i].addr;
2723                 mask = dev_priv->workarounds.reg[i].mask;
2724                 value = dev_priv->workarounds.reg[i].value;
2725                 read = I915_READ(addr);
2726                 ok = (value & mask) == (read & mask);
2727                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2728                            addr, value, mask, read, ok ? "OK" : "FAIL");
2729         }
2730
2731         intel_runtime_pm_put(dev_priv);
2732         mutex_unlock(&dev->struct_mutex);
2733
2734         return 0;
2735 }
2736
2737 static int i915_ddb_info(struct seq_file *m, void *unused)
2738 {
2739         struct drm_info_node *node = m->private;
2740         struct drm_device *dev = node->minor->dev;
2741         struct drm_i915_private *dev_priv = dev->dev_private;
2742         struct skl_ddb_allocation *ddb;
2743         struct skl_ddb_entry *entry;
2744         enum pipe pipe;
2745         int plane;
2746
2747         if (INTEL_INFO(dev)->gen < 9)
2748                 return 0;
2749
2750         drm_modeset_lock_all(dev);
2751
2752         ddb = &dev_priv->wm.skl_hw.ddb;
2753
2754         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2755
2756         for_each_pipe(dev_priv, pipe) {
2757                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2758
2759                 for_each_plane(pipe, plane) {
2760                         entry = &ddb->plane[pipe][plane];
2761                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2762                                    entry->start, entry->end,
2763                                    skl_ddb_entry_size(entry));
2764                 }
2765
2766                 entry = &ddb->cursor[pipe];
2767                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2768                            entry->end, skl_ddb_entry_size(entry));
2769         }
2770
2771         drm_modeset_unlock_all(dev);
2772
2773         return 0;
2774 }
2775
2776 struct pipe_crc_info {
2777         const char *name;
2778         struct drm_device *dev;
2779         enum pipe pipe;
2780 };
2781
2782 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2783 {
2784         struct drm_info_node *node = (struct drm_info_node *) m->private;
2785         struct drm_device *dev = node->minor->dev;
2786         struct drm_encoder *encoder;
2787         struct intel_encoder *intel_encoder;
2788         struct intel_digital_port *intel_dig_port;
2789         drm_modeset_lock_all(dev);
2790         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2791                 intel_encoder = to_intel_encoder(encoder);
2792                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2793                         continue;
2794                 intel_dig_port = enc_to_dig_port(encoder);
2795                 if (!intel_dig_port->dp.can_mst)
2796                         continue;
2797
2798                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2799         }
2800         drm_modeset_unlock_all(dev);
2801         return 0;
2802 }
2803
2804 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2805 {
2806         struct pipe_crc_info *info = inode->i_private;
2807         struct drm_i915_private *dev_priv = info->dev->dev_private;
2808         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2809
2810         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2811                 return -ENODEV;
2812
2813         spin_lock_irq(&pipe_crc->lock);
2814
2815         if (pipe_crc->opened) {
2816                 spin_unlock_irq(&pipe_crc->lock);
2817                 return -EBUSY; /* already open */
2818         }
2819
2820         pipe_crc->opened = true;
2821         filep->private_data = inode->i_private;
2822
2823         spin_unlock_irq(&pipe_crc->lock);
2824
2825         return 0;
2826 }
2827
2828 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2829 {
2830         struct pipe_crc_info *info = inode->i_private;
2831         struct drm_i915_private *dev_priv = info->dev->dev_private;
2832         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2833
2834         spin_lock_irq(&pipe_crc->lock);
2835         pipe_crc->opened = false;
2836         spin_unlock_irq(&pipe_crc->lock);
2837
2838         return 0;
2839 }
2840
2841 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2842 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2843 /* account for \'0' */
2844 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2845
2846 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2847 {
2848         assert_spin_locked(&pipe_crc->lock);
2849         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2850                         INTEL_PIPE_CRC_ENTRIES_NR);
2851 }
2852
2853 static ssize_t
2854 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2855                    loff_t *pos)
2856 {
2857         struct pipe_crc_info *info = filep->private_data;
2858         struct drm_device *dev = info->dev;
2859         struct drm_i915_private *dev_priv = dev->dev_private;
2860         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2861         char buf[PIPE_CRC_BUFFER_LEN];
2862         int n_entries;
2863         ssize_t bytes_read;
2864
2865         /*
2866          * Don't allow user space to provide buffers not big enough to hold
2867          * a line of data.
2868          */
2869         if (count < PIPE_CRC_LINE_LEN)
2870                 return -EINVAL;
2871
2872         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2873                 return 0;
2874
2875         /* nothing to read */
2876         spin_lock_irq(&pipe_crc->lock);
2877         while (pipe_crc_data_count(pipe_crc) == 0) {
2878                 int ret;
2879
2880                 if (filep->f_flags & O_NONBLOCK) {
2881                         spin_unlock_irq(&pipe_crc->lock);
2882                         return -EAGAIN;
2883                 }
2884
2885                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2886                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2887                 if (ret) {
2888                         spin_unlock_irq(&pipe_crc->lock);
2889                         return ret;
2890                 }
2891         }
2892
2893         /* We now have one or more entries to read */
2894         n_entries = count / PIPE_CRC_LINE_LEN;
2895
2896         bytes_read = 0;
2897         while (n_entries > 0) {
2898                 struct intel_pipe_crc_entry *entry =
2899                         &pipe_crc->entries[pipe_crc->tail];
2900                 int ret;
2901
2902                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2903                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2904                         break;
2905
2906                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2907                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2908
2909                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2910                                        "%8u %8x %8x %8x %8x %8x\n",
2911                                        entry->frame, entry->crc[0],
2912                                        entry->crc[1], entry->crc[2],
2913                                        entry->crc[3], entry->crc[4]);
2914
2915                 spin_unlock_irq(&pipe_crc->lock);
2916
2917                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
2918                 if (ret == PIPE_CRC_LINE_LEN)
2919                         return -EFAULT;
2920
2921                 user_buf += PIPE_CRC_LINE_LEN;
2922                 n_entries--;
2923
2924                 spin_lock_irq(&pipe_crc->lock);
2925         }
2926
2927         spin_unlock_irq(&pipe_crc->lock);
2928
2929         return bytes_read;
2930 }
2931
2932 static const struct file_operations i915_pipe_crc_fops = {
2933         .owner = THIS_MODULE,
2934         .open = i915_pipe_crc_open,
2935         .read = i915_pipe_crc_read,
2936         .release = i915_pipe_crc_release,
2937 };
2938
2939 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2940         {
2941                 .name = "i915_pipe_A_crc",
2942                 .pipe = PIPE_A,
2943         },
2944         {
2945                 .name = "i915_pipe_B_crc",
2946                 .pipe = PIPE_B,
2947         },
2948         {
2949                 .name = "i915_pipe_C_crc",
2950                 .pipe = PIPE_C,
2951         },
2952 };
2953
2954 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2955                                 enum pipe pipe)
2956 {
2957         struct drm_device *dev = minor->dev;
2958         struct dentry *ent;
2959         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2960
2961         info->dev = dev;
2962         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2963                                   &i915_pipe_crc_fops);
2964         if (!ent)
2965                 return -ENOMEM;
2966
2967         return drm_add_fake_info_node(minor, ent, info);
2968 }
2969
2970 static const char * const pipe_crc_sources[] = {
2971         "none",
2972         "plane1",
2973         "plane2",
2974         "pf",
2975         "pipe",
2976         "TV",
2977         "DP-B",
2978         "DP-C",
2979         "DP-D",
2980         "auto",
2981 };
2982
2983 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2984 {
2985         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2986         return pipe_crc_sources[source];
2987 }
2988
2989 static int display_crc_ctl_show(struct seq_file *m, void *data)
2990 {
2991         struct drm_device *dev = m->private;
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         int i;
2994
2995         for (i = 0; i < I915_MAX_PIPES; i++)
2996                 seq_printf(m, "%c %s\n", pipe_name(i),
2997                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2998
2999         return 0;
3000 }
3001
3002 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3003 {
3004         struct drm_device *dev = inode->i_private;
3005
3006         return single_open(file, display_crc_ctl_show, dev);
3007 }
3008
3009 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3010                                  uint32_t *val)
3011 {
3012         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3013                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3014
3015         switch (*source) {
3016         case INTEL_PIPE_CRC_SOURCE_PIPE:
3017                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3018                 break;
3019         case INTEL_PIPE_CRC_SOURCE_NONE:
3020                 *val = 0;
3021                 break;
3022         default:
3023                 return -EINVAL;
3024         }
3025
3026         return 0;
3027 }
3028
3029 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3030                                      enum intel_pipe_crc_source *source)
3031 {
3032         struct intel_encoder *encoder;
3033         struct intel_crtc *crtc;
3034         struct intel_digital_port *dig_port;
3035         int ret = 0;
3036
3037         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3038
3039         drm_modeset_lock_all(dev);
3040         for_each_intel_encoder(dev, encoder) {
3041                 if (!encoder->base.crtc)
3042                         continue;
3043
3044                 crtc = to_intel_crtc(encoder->base.crtc);
3045
3046                 if (crtc->pipe != pipe)
3047                         continue;
3048
3049                 switch (encoder->type) {
3050                 case INTEL_OUTPUT_TVOUT:
3051                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3052                         break;
3053                 case INTEL_OUTPUT_DISPLAYPORT:
3054                 case INTEL_OUTPUT_EDP:
3055                         dig_port = enc_to_dig_port(&encoder->base);
3056                         switch (dig_port->port) {
3057                         case PORT_B:
3058                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3059                                 break;
3060                         case PORT_C:
3061                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3062                                 break;
3063                         case PORT_D:
3064                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3065                                 break;
3066                         default:
3067                                 WARN(1, "nonexisting DP port %c\n",
3068                                      port_name(dig_port->port));
3069                                 break;
3070                         }
3071                         break;
3072                 default:
3073                         break;
3074                 }
3075         }
3076         drm_modeset_unlock_all(dev);
3077
3078         return ret;
3079 }
3080
3081 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3082                                 enum pipe pipe,
3083                                 enum intel_pipe_crc_source *source,
3084                                 uint32_t *val)
3085 {
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087         bool need_stable_symbols = false;
3088
3089         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3090                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3091                 if (ret)
3092                         return ret;
3093         }
3094
3095         switch (*source) {
3096         case INTEL_PIPE_CRC_SOURCE_PIPE:
3097                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3098                 break;
3099         case INTEL_PIPE_CRC_SOURCE_DP_B:
3100                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3101                 need_stable_symbols = true;
3102                 break;
3103         case INTEL_PIPE_CRC_SOURCE_DP_C:
3104                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3105                 need_stable_symbols = true;
3106                 break;
3107         case INTEL_PIPE_CRC_SOURCE_DP_D:
3108                 if (!IS_CHERRYVIEW(dev))
3109                         return -EINVAL;
3110                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3111                 need_stable_symbols = true;
3112                 break;
3113         case INTEL_PIPE_CRC_SOURCE_NONE:
3114                 *val = 0;
3115                 break;
3116         default:
3117                 return -EINVAL;
3118         }
3119
3120         /*
3121          * When the pipe CRC tap point is after the transcoders we need
3122          * to tweak symbol-level features to produce a deterministic series of
3123          * symbols for a given frame. We need to reset those features only once
3124          * a frame (instead of every nth symbol):
3125          *   - DC-balance: used to ensure a better clock recovery from the data
3126          *     link (SDVO)
3127          *   - DisplayPort scrambling: used for EMI reduction
3128          */
3129         if (need_stable_symbols) {
3130                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3131
3132                 tmp |= DC_BALANCE_RESET_VLV;
3133                 switch (pipe) {
3134                 case PIPE_A:
3135                         tmp |= PIPE_A_SCRAMBLE_RESET;
3136                         break;
3137                 case PIPE_B:
3138                         tmp |= PIPE_B_SCRAMBLE_RESET;
3139                         break;
3140                 case PIPE_C:
3141                         tmp |= PIPE_C_SCRAMBLE_RESET;
3142                         break;
3143                 default:
3144                         return -EINVAL;
3145                 }
3146                 I915_WRITE(PORT_DFT2_G4X, tmp);
3147         }
3148
3149         return 0;
3150 }
3151
3152 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3153                                  enum pipe pipe,
3154                                  enum intel_pipe_crc_source *source,
3155                                  uint32_t *val)
3156 {
3157         struct drm_i915_private *dev_priv = dev->dev_private;
3158         bool need_stable_symbols = false;
3159
3160         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3161                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3162                 if (ret)
3163                         return ret;
3164         }
3165
3166         switch (*source) {
3167         case INTEL_PIPE_CRC_SOURCE_PIPE:
3168                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3169                 break;
3170         case INTEL_PIPE_CRC_SOURCE_TV:
3171                 if (!SUPPORTS_TV(dev))
3172                         return -EINVAL;
3173                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3174                 break;
3175         case INTEL_PIPE_CRC_SOURCE_DP_B:
3176                 if (!IS_G4X(dev))
3177                         return -EINVAL;
3178                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3179                 need_stable_symbols = true;
3180                 break;
3181         case INTEL_PIPE_CRC_SOURCE_DP_C:
3182                 if (!IS_G4X(dev))
3183                         return -EINVAL;
3184                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3185                 need_stable_symbols = true;
3186                 break;
3187         case INTEL_PIPE_CRC_SOURCE_DP_D:
3188                 if (!IS_G4X(dev))
3189                         return -EINVAL;
3190                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3191                 need_stable_symbols = true;
3192                 break;
3193         case INTEL_PIPE_CRC_SOURCE_NONE:
3194                 *val = 0;
3195                 break;
3196         default:
3197                 return -EINVAL;
3198         }
3199
3200         /*
3201          * When the pipe CRC tap point is after the transcoders we need
3202          * to tweak symbol-level features to produce a deterministic series of
3203          * symbols for a given frame. We need to reset those features only once
3204          * a frame (instead of every nth symbol):
3205          *   - DC-balance: used to ensure a better clock recovery from the data
3206          *     link (SDVO)
3207          *   - DisplayPort scrambling: used for EMI reduction
3208          */
3209         if (need_stable_symbols) {
3210                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3211
3212                 WARN_ON(!IS_G4X(dev));
3213
3214                 I915_WRITE(PORT_DFT_I9XX,
3215                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3216
3217                 if (pipe == PIPE_A)
3218                         tmp |= PIPE_A_SCRAMBLE_RESET;
3219                 else
3220                         tmp |= PIPE_B_SCRAMBLE_RESET;
3221
3222                 I915_WRITE(PORT_DFT2_G4X, tmp);
3223         }
3224
3225         return 0;
3226 }
3227
3228 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3229                                          enum pipe pipe)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3233
3234         switch (pipe) {
3235         case PIPE_A:
3236                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3237                 break;
3238         case PIPE_B:
3239                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3240                 break;
3241         case PIPE_C:
3242                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3243                 break;
3244         default:
3245                 return;
3246         }
3247         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3248                 tmp &= ~DC_BALANCE_RESET_VLV;
3249         I915_WRITE(PORT_DFT2_G4X, tmp);
3250
3251 }
3252
3253 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3254                                          enum pipe pipe)
3255 {
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3258
3259         if (pipe == PIPE_A)
3260                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3261         else
3262                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3263         I915_WRITE(PORT_DFT2_G4X, tmp);
3264
3265         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3266                 I915_WRITE(PORT_DFT_I9XX,
3267                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3268         }
3269 }
3270
3271 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3272                                 uint32_t *val)
3273 {
3274         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3275                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3276
3277         switch (*source) {
3278         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3279                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3280                 break;
3281         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3282                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3283                 break;
3284         case INTEL_PIPE_CRC_SOURCE_PIPE:
3285                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3286                 break;
3287         case INTEL_PIPE_CRC_SOURCE_NONE:
3288                 *val = 0;
3289                 break;
3290         default:
3291                 return -EINVAL;
3292         }
3293
3294         return 0;
3295 }
3296
3297 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3298 {
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         struct intel_crtc *crtc =
3301                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3302
3303         drm_modeset_lock_all(dev);
3304         /*
3305          * If we use the eDP transcoder we need to make sure that we don't
3306          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3307          * relevant on hsw with pipe A when using the always-on power well
3308          * routing.
3309          */
3310         if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3311             !crtc->config.pch_pfit.enabled) {
3312                 crtc->config.pch_pfit.force_thru = true;
3313
3314                 intel_display_power_get(dev_priv,
3315                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3316
3317                 dev_priv->display.crtc_disable(&crtc->base);
3318                 dev_priv->display.crtc_enable(&crtc->base);
3319         }
3320         drm_modeset_unlock_all(dev);
3321 }
3322
3323 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3324 {
3325         struct drm_i915_private *dev_priv = dev->dev_private;
3326         struct intel_crtc *crtc =
3327                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3328
3329         drm_modeset_lock_all(dev);
3330         /*
3331          * If we use the eDP transcoder we need to make sure that we don't
3332          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3333          * relevant on hsw with pipe A when using the always-on power well
3334          * routing.
3335          */
3336         if (crtc->config.pch_pfit.force_thru) {
3337                 crtc->config.pch_pfit.force_thru = false;
3338
3339                 dev_priv->display.crtc_disable(&crtc->base);
3340                 dev_priv->display.crtc_enable(&crtc->base);
3341
3342                 intel_display_power_put(dev_priv,
3343                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3344         }
3345         drm_modeset_unlock_all(dev);
3346 }
3347
3348 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3349                                 enum pipe pipe,
3350                                 enum intel_pipe_crc_source *source,
3351                                 uint32_t *val)
3352 {
3353         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3354                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3355
3356         switch (*source) {
3357         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3358                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3359                 break;
3360         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3361                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3362                 break;
3363         case INTEL_PIPE_CRC_SOURCE_PF:
3364                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3365                         hsw_trans_edp_pipe_A_crc_wa(dev);
3366
3367                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3368                 break;
3369         case INTEL_PIPE_CRC_SOURCE_NONE:
3370                 *val = 0;
3371                 break;
3372         default:
3373                 return -EINVAL;
3374         }
3375
3376         return 0;
3377 }
3378
3379 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3380                                enum intel_pipe_crc_source source)
3381 {
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3384         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3385                                                                         pipe));
3386         u32 val = 0; /* shut up gcc */
3387         int ret;
3388
3389         if (pipe_crc->source == source)
3390                 return 0;
3391
3392         /* forbid changing the source without going back to 'none' */
3393         if (pipe_crc->source && source)
3394                 return -EINVAL;
3395
3396         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3397                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3398                 return -EIO;
3399         }
3400
3401         if (IS_GEN2(dev))
3402                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3403         else if (INTEL_INFO(dev)->gen < 5)
3404                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3405         else if (IS_VALLEYVIEW(dev))
3406                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3407         else if (IS_GEN5(dev) || IS_GEN6(dev))
3408                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3409         else
3410                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3411
3412         if (ret != 0)
3413                 return ret;
3414
3415         /* none -> real source transition */
3416         if (source) {
3417                 struct intel_pipe_crc_entry *entries;
3418
3419                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3420                                  pipe_name(pipe), pipe_crc_source_name(source));
3421
3422                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3423                                   sizeof(pipe_crc->entries[0]),
3424                                   GFP_KERNEL);
3425                 if (!entries)
3426                         return -ENOMEM;
3427
3428                 /*
3429                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3430                  * enabled and disabled dynamically based on package C states,
3431                  * user space can't make reliable use of the CRCs, so let's just
3432                  * completely disable it.
3433                  */
3434                 hsw_disable_ips(crtc);
3435
3436                 spin_lock_irq(&pipe_crc->lock);
3437                 kfree(pipe_crc->entries);
3438                 pipe_crc->entries = entries;
3439                 pipe_crc->head = 0;
3440                 pipe_crc->tail = 0;
3441                 spin_unlock_irq(&pipe_crc->lock);
3442         }
3443
3444         pipe_crc->source = source;
3445
3446         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3447         POSTING_READ(PIPE_CRC_CTL(pipe));
3448
3449         /* real source -> none transition */
3450         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3451                 struct intel_pipe_crc_entry *entries;
3452                 struct intel_crtc *crtc =
3453                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3454
3455                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3456                                  pipe_name(pipe));
3457
3458                 drm_modeset_lock(&crtc->base.mutex, NULL);
3459                 if (crtc->active)
3460                         intel_wait_for_vblank(dev, pipe);
3461                 drm_modeset_unlock(&crtc->base.mutex);
3462
3463                 spin_lock_irq(&pipe_crc->lock);
3464                 entries = pipe_crc->entries;
3465                 pipe_crc->entries = NULL;
3466                 pipe_crc->head = 0;
3467                 pipe_crc->tail = 0;
3468                 spin_unlock_irq(&pipe_crc->lock);
3469
3470                 kfree(entries);
3471
3472                 if (IS_G4X(dev))
3473                         g4x_undo_pipe_scramble_reset(dev, pipe);
3474                 else if (IS_VALLEYVIEW(dev))
3475                         vlv_undo_pipe_scramble_reset(dev, pipe);
3476                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3477                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3478
3479                 hsw_enable_ips(crtc);
3480         }
3481
3482         return 0;
3483 }
3484
3485 /*
3486  * Parse pipe CRC command strings:
3487  *   command: wsp* object wsp+ name wsp+ source wsp*
3488  *   object: 'pipe'
3489  *   name: (A | B | C)
3490  *   source: (none | plane1 | plane2 | pf)
3491  *   wsp: (#0x20 | #0x9 | #0xA)+
3492  *
3493  * eg.:
3494  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3495  *  "pipe A none"    ->  Stop CRC
3496  */
3497 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3498 {
3499         int n_words = 0;
3500
3501         while (*buf) {
3502                 char *end;
3503
3504                 /* skip leading white space */
3505                 buf = skip_spaces(buf);
3506                 if (!*buf)
3507                         break;  /* end of buffer */
3508
3509                 /* find end of word */
3510                 for (end = buf; *end && !isspace(*end); end++)
3511                         ;
3512
3513                 if (n_words == max_words) {
3514                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3515                                          max_words);
3516                         return -EINVAL; /* ran out of words[] before bytes */
3517                 }
3518
3519                 if (*end)
3520                         *end++ = '\0';
3521                 words[n_words++] = buf;
3522                 buf = end;
3523         }
3524
3525         return n_words;
3526 }
3527
3528 enum intel_pipe_crc_object {
3529         PIPE_CRC_OBJECT_PIPE,
3530 };
3531
3532 static const char * const pipe_crc_objects[] = {
3533         "pipe",
3534 };
3535
3536 static int
3537 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3538 {
3539         int i;
3540
3541         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3542                 if (!strcmp(buf, pipe_crc_objects[i])) {
3543                         *o = i;
3544                         return 0;
3545                     }
3546
3547         return -EINVAL;
3548 }
3549
3550 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3551 {
3552         const char name = buf[0];
3553
3554         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3555                 return -EINVAL;
3556
3557         *pipe = name - 'A';
3558
3559         return 0;
3560 }
3561
3562 static int
3563 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3564 {
3565         int i;
3566
3567         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3568                 if (!strcmp(buf, pipe_crc_sources[i])) {
3569                         *s = i;
3570                         return 0;
3571                     }
3572
3573         return -EINVAL;
3574 }
3575
3576 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3577 {
3578 #define N_WORDS 3
3579         int n_words;
3580         char *words[N_WORDS];
3581         enum pipe pipe;
3582         enum intel_pipe_crc_object object;
3583         enum intel_pipe_crc_source source;
3584
3585         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3586         if (n_words != N_WORDS) {
3587                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3588                                  N_WORDS);
3589                 return -EINVAL;
3590         }
3591
3592         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3593                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3594                 return -EINVAL;
3595         }
3596
3597         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3598                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3599                 return -EINVAL;
3600         }
3601
3602         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3603                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3604                 return -EINVAL;
3605         }
3606
3607         return pipe_crc_set_source(dev, pipe, source);
3608 }
3609
3610 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3611                                      size_t len, loff_t *offp)
3612 {
3613         struct seq_file *m = file->private_data;
3614         struct drm_device *dev = m->private;
3615         char *tmpbuf;
3616         int ret;
3617
3618         if (len == 0)
3619                 return 0;
3620
3621         if (len > PAGE_SIZE - 1) {
3622                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3623                                  PAGE_SIZE);
3624                 return -E2BIG;
3625         }
3626
3627         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3628         if (!tmpbuf)
3629                 return -ENOMEM;
3630
3631         if (copy_from_user(tmpbuf, ubuf, len)) {
3632                 ret = -EFAULT;
3633                 goto out;
3634         }
3635         tmpbuf[len] = '\0';
3636
3637         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3638
3639 out:
3640         kfree(tmpbuf);
3641         if (ret < 0)
3642                 return ret;
3643
3644         *offp += len;
3645         return len;
3646 }
3647
3648 static const struct file_operations i915_display_crc_ctl_fops = {
3649         .owner = THIS_MODULE,
3650         .open = display_crc_ctl_open,
3651         .read = seq_read,
3652         .llseek = seq_lseek,
3653         .release = single_release,
3654         .write = display_crc_ctl_write
3655 };
3656
3657 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3658 {
3659         struct drm_device *dev = m->private;
3660         int num_levels = ilk_wm_max_level(dev) + 1;
3661         int level;
3662
3663         drm_modeset_lock_all(dev);
3664
3665         for (level = 0; level < num_levels; level++) {
3666                 unsigned int latency = wm[level];
3667
3668                 /*
3669                  * - WM1+ latency values in 0.5us units
3670                  * - latencies are in us on gen9
3671                  */
3672                 if (INTEL_INFO(dev)->gen >= 9)
3673                         latency *= 10;
3674                 else if (level > 0)
3675                         latency *= 5;
3676
3677                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3678                            level, wm[level], latency / 10, latency % 10);
3679         }
3680
3681         drm_modeset_unlock_all(dev);
3682 }
3683
3684 static int pri_wm_latency_show(struct seq_file *m, void *data)
3685 {
3686         struct drm_device *dev = m->private;
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         const uint16_t *latencies;
3689
3690         if (INTEL_INFO(dev)->gen >= 9)
3691                 latencies = dev_priv->wm.skl_latency;
3692         else
3693                 latencies = to_i915(dev)->wm.pri_latency;
3694
3695         wm_latency_show(m, latencies);
3696
3697         return 0;
3698 }
3699
3700 static int spr_wm_latency_show(struct seq_file *m, void *data)
3701 {
3702         struct drm_device *dev = m->private;
3703         struct drm_i915_private *dev_priv = dev->dev_private;
3704         const uint16_t *latencies;
3705
3706         if (INTEL_INFO(dev)->gen >= 9)
3707                 latencies = dev_priv->wm.skl_latency;
3708         else
3709                 latencies = to_i915(dev)->wm.spr_latency;
3710
3711         wm_latency_show(m, latencies);
3712
3713         return 0;
3714 }
3715
3716 static int cur_wm_latency_show(struct seq_file *m, void *data)
3717 {
3718         struct drm_device *dev = m->private;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         const uint16_t *latencies;
3721
3722         if (INTEL_INFO(dev)->gen >= 9)
3723                 latencies = dev_priv->wm.skl_latency;
3724         else
3725                 latencies = to_i915(dev)->wm.cur_latency;
3726
3727         wm_latency_show(m, latencies);
3728
3729         return 0;
3730 }
3731
3732 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3733 {
3734         struct drm_device *dev = inode->i_private;
3735
3736         if (HAS_GMCH_DISPLAY(dev))
3737                 return -ENODEV;
3738
3739         return single_open(file, pri_wm_latency_show, dev);
3740 }
3741
3742 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3743 {
3744         struct drm_device *dev = inode->i_private;
3745
3746         if (HAS_GMCH_DISPLAY(dev))
3747                 return -ENODEV;
3748
3749         return single_open(file, spr_wm_latency_show, dev);
3750 }
3751
3752 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3753 {
3754         struct drm_device *dev = inode->i_private;
3755
3756         if (HAS_GMCH_DISPLAY(dev))
3757                 return -ENODEV;
3758
3759         return single_open(file, cur_wm_latency_show, dev);
3760 }
3761
3762 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3763                                 size_t len, loff_t *offp, uint16_t wm[8])
3764 {
3765         struct seq_file *m = file->private_data;
3766         struct drm_device *dev = m->private;
3767         uint16_t new[8] = { 0 };
3768         int num_levels = ilk_wm_max_level(dev) + 1;
3769         int level;
3770         int ret;
3771         char tmp[32];
3772
3773         if (len >= sizeof(tmp))
3774                 return -EINVAL;
3775
3776         if (copy_from_user(tmp, ubuf, len))
3777                 return -EFAULT;
3778
3779         tmp[len] = '\0';
3780
3781         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3782                      &new[0], &new[1], &new[2], &new[3],
3783                      &new[4], &new[5], &new[6], &new[7]);
3784         if (ret != num_levels)
3785                 return -EINVAL;
3786
3787         drm_modeset_lock_all(dev);
3788
3789         for (level = 0; level < num_levels; level++)
3790                 wm[level] = new[level];
3791
3792         drm_modeset_unlock_all(dev);
3793
3794         return len;
3795 }
3796
3797
3798 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3799                                     size_t len, loff_t *offp)
3800 {
3801         struct seq_file *m = file->private_data;
3802         struct drm_device *dev = m->private;
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         uint16_t *latencies;
3805
3806         if (INTEL_INFO(dev)->gen >= 9)
3807                 latencies = dev_priv->wm.skl_latency;
3808         else
3809                 latencies = to_i915(dev)->wm.pri_latency;
3810
3811         return wm_latency_write(file, ubuf, len, offp, latencies);
3812 }
3813
3814 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3815                                     size_t len, loff_t *offp)
3816 {
3817         struct seq_file *m = file->private_data;
3818         struct drm_device *dev = m->private;
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         uint16_t *latencies;
3821
3822         if (INTEL_INFO(dev)->gen >= 9)
3823                 latencies = dev_priv->wm.skl_latency;
3824         else
3825                 latencies = to_i915(dev)->wm.spr_latency;
3826
3827         return wm_latency_write(file, ubuf, len, offp, latencies);
3828 }
3829
3830 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3831                                     size_t len, loff_t *offp)
3832 {
3833         struct seq_file *m = file->private_data;
3834         struct drm_device *dev = m->private;
3835         struct drm_i915_private *dev_priv = dev->dev_private;
3836         uint16_t *latencies;
3837
3838         if (INTEL_INFO(dev)->gen >= 9)
3839                 latencies = dev_priv->wm.skl_latency;
3840         else
3841                 latencies = to_i915(dev)->wm.cur_latency;
3842
3843         return wm_latency_write(file, ubuf, len, offp, latencies);
3844 }
3845
3846 static const struct file_operations i915_pri_wm_latency_fops = {
3847         .owner = THIS_MODULE,
3848         .open = pri_wm_latency_open,
3849         .read = seq_read,
3850         .llseek = seq_lseek,
3851         .release = single_release,
3852         .write = pri_wm_latency_write
3853 };
3854
3855 static const struct file_operations i915_spr_wm_latency_fops = {
3856         .owner = THIS_MODULE,
3857         .open = spr_wm_latency_open,
3858         .read = seq_read,
3859         .llseek = seq_lseek,
3860         .release = single_release,
3861         .write = spr_wm_latency_write
3862 };
3863
3864 static const struct file_operations i915_cur_wm_latency_fops = {
3865         .owner = THIS_MODULE,
3866         .open = cur_wm_latency_open,
3867         .read = seq_read,
3868         .llseek = seq_lseek,
3869         .release = single_release,
3870         .write = cur_wm_latency_write
3871 };
3872
3873 static int
3874 i915_wedged_get(void *data, u64 *val)
3875 {
3876         struct drm_device *dev = data;
3877         struct drm_i915_private *dev_priv = dev->dev_private;
3878
3879         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3880
3881         return 0;
3882 }
3883
3884 static int
3885 i915_wedged_set(void *data, u64 val)
3886 {
3887         struct drm_device *dev = data;
3888         struct drm_i915_private *dev_priv = dev->dev_private;
3889
3890         intel_runtime_pm_get(dev_priv);
3891
3892         i915_handle_error(dev, val,
3893                           "Manually setting wedged to %llu", val);
3894
3895         intel_runtime_pm_put(dev_priv);
3896
3897         return 0;
3898 }
3899
3900 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3901                         i915_wedged_get, i915_wedged_set,
3902                         "%llu\n");
3903
3904 static int
3905 i915_ring_stop_get(void *data, u64 *val)
3906 {
3907         struct drm_device *dev = data;
3908         struct drm_i915_private *dev_priv = dev->dev_private;
3909
3910         *val = dev_priv->gpu_error.stop_rings;
3911
3912         return 0;
3913 }
3914
3915 static int
3916 i915_ring_stop_set(void *data, u64 val)
3917 {
3918         struct drm_device *dev = data;
3919         struct drm_i915_private *dev_priv = dev->dev_private;
3920         int ret;
3921
3922         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3923
3924         ret = mutex_lock_interruptible(&dev->struct_mutex);
3925         if (ret)
3926                 return ret;
3927
3928         dev_priv->gpu_error.stop_rings = val;
3929         mutex_unlock(&dev->struct_mutex);
3930
3931         return 0;
3932 }
3933
3934 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3935                         i915_ring_stop_get, i915_ring_stop_set,
3936                         "0x%08llx\n");
3937
3938 static int
3939 i915_ring_missed_irq_get(void *data, u64 *val)
3940 {
3941         struct drm_device *dev = data;
3942         struct drm_i915_private *dev_priv = dev->dev_private;
3943
3944         *val = dev_priv->gpu_error.missed_irq_rings;
3945         return 0;
3946 }
3947
3948 static int
3949 i915_ring_missed_irq_set(void *data, u64 val)
3950 {
3951         struct drm_device *dev = data;
3952         struct drm_i915_private *dev_priv = dev->dev_private;
3953         int ret;
3954
3955         /* Lock against concurrent debugfs callers */
3956         ret = mutex_lock_interruptible(&dev->struct_mutex);
3957         if (ret)
3958                 return ret;
3959         dev_priv->gpu_error.missed_irq_rings = val;
3960         mutex_unlock(&dev->struct_mutex);
3961
3962         return 0;
3963 }
3964
3965 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3966                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3967                         "0x%08llx\n");
3968
3969 static int
3970 i915_ring_test_irq_get(void *data, u64 *val)
3971 {
3972         struct drm_device *dev = data;
3973         struct drm_i915_private *dev_priv = dev->dev_private;
3974
3975         *val = dev_priv->gpu_error.test_irq_rings;
3976
3977         return 0;
3978 }
3979
3980 static int
3981 i915_ring_test_irq_set(void *data, u64 val)
3982 {
3983         struct drm_device *dev = data;
3984         struct drm_i915_private *dev_priv = dev->dev_private;
3985         int ret;
3986
3987         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3988
3989         /* Lock against concurrent debugfs callers */
3990         ret = mutex_lock_interruptible(&dev->struct_mutex);
3991         if (ret)
3992                 return ret;
3993
3994         dev_priv->gpu_error.test_irq_rings = val;
3995         mutex_unlock(&dev->struct_mutex);
3996
3997         return 0;
3998 }
3999
4000 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4001                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4002                         "0x%08llx\n");
4003
4004 #define DROP_UNBOUND 0x1
4005 #define DROP_BOUND 0x2
4006 #define DROP_RETIRE 0x4
4007 #define DROP_ACTIVE 0x8
4008 #define DROP_ALL (DROP_UNBOUND | \
4009                   DROP_BOUND | \
4010                   DROP_RETIRE | \
4011                   DROP_ACTIVE)
4012 static int
4013 i915_drop_caches_get(void *data, u64 *val)
4014 {
4015         *val = DROP_ALL;
4016
4017         return 0;
4018 }
4019
4020 static int
4021 i915_drop_caches_set(void *data, u64 val)
4022 {
4023         struct drm_device *dev = data;
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         int ret;
4026
4027         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4028
4029         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4030          * on ioctls on -EAGAIN. */
4031         ret = mutex_lock_interruptible(&dev->struct_mutex);
4032         if (ret)
4033                 return ret;
4034
4035         if (val & DROP_ACTIVE) {
4036                 ret = i915_gpu_idle(dev);
4037                 if (ret)
4038                         goto unlock;
4039         }
4040
4041         if (val & (DROP_RETIRE | DROP_ACTIVE))
4042                 i915_gem_retire_requests(dev);
4043
4044         if (val & DROP_BOUND)
4045                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4046
4047         if (val & DROP_UNBOUND)
4048                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4049
4050 unlock:
4051         mutex_unlock(&dev->struct_mutex);
4052
4053         return ret;
4054 }
4055
4056 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4057                         i915_drop_caches_get, i915_drop_caches_set,
4058                         "0x%08llx\n");
4059
4060 static int
4061 i915_max_freq_get(void *data, u64 *val)
4062 {
4063         struct drm_device *dev = data;
4064         struct drm_i915_private *dev_priv = dev->dev_private;
4065         int ret;
4066
4067         if (INTEL_INFO(dev)->gen < 6)
4068                 return -ENODEV;
4069
4070         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4071
4072         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4073         if (ret)
4074                 return ret;
4075
4076         if (IS_VALLEYVIEW(dev))
4077                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4078         else
4079                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4080         mutex_unlock(&dev_priv->rps.hw_lock);
4081
4082         return 0;
4083 }
4084
4085 static int
4086 i915_max_freq_set(void *data, u64 val)
4087 {
4088         struct drm_device *dev = data;
4089         struct drm_i915_private *dev_priv = dev->dev_private;
4090         u32 rp_state_cap, hw_max, hw_min;
4091         int ret;
4092
4093         if (INTEL_INFO(dev)->gen < 6)
4094                 return -ENODEV;
4095
4096         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4097
4098         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4099
4100         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4101         if (ret)
4102                 return ret;
4103
4104         /*
4105          * Turbo will still be enabled, but won't go above the set value.
4106          */
4107         if (IS_VALLEYVIEW(dev)) {
4108                 val = vlv_freq_opcode(dev_priv, val);
4109
4110                 hw_max = dev_priv->rps.max_freq;
4111                 hw_min = dev_priv->rps.min_freq;
4112         } else {
4113                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4114
4115                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4116                 hw_max = dev_priv->rps.max_freq;
4117                 hw_min = (rp_state_cap >> 16) & 0xff;
4118         }
4119
4120         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4121                 mutex_unlock(&dev_priv->rps.hw_lock);
4122                 return -EINVAL;
4123         }
4124
4125         dev_priv->rps.max_freq_softlimit = val;
4126
4127         if (IS_VALLEYVIEW(dev))
4128                 valleyview_set_rps(dev, val);
4129         else
4130                 gen6_set_rps(dev, val);
4131
4132         mutex_unlock(&dev_priv->rps.hw_lock);
4133
4134         return 0;
4135 }
4136
4137 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4138                         i915_max_freq_get, i915_max_freq_set,
4139                         "%llu\n");
4140
4141 static int
4142 i915_min_freq_get(void *data, u64 *val)
4143 {
4144         struct drm_device *dev = data;
4145         struct drm_i915_private *dev_priv = dev->dev_private;
4146         int ret;
4147
4148         if (INTEL_INFO(dev)->gen < 6)
4149                 return -ENODEV;
4150
4151         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4152
4153         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4154         if (ret)
4155                 return ret;
4156
4157         if (IS_VALLEYVIEW(dev))
4158                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4159         else
4160                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4161         mutex_unlock(&dev_priv->rps.hw_lock);
4162
4163         return 0;
4164 }
4165
4166 static int
4167 i915_min_freq_set(void *data, u64 val)
4168 {
4169         struct drm_device *dev = data;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         u32 rp_state_cap, hw_max, hw_min;
4172         int ret;
4173
4174         if (INTEL_INFO(dev)->gen < 6)
4175                 return -ENODEV;
4176
4177         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4178
4179         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4180
4181         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4182         if (ret)
4183                 return ret;
4184
4185         /*
4186          * Turbo will still be enabled, but won't go below the set value.
4187          */
4188         if (IS_VALLEYVIEW(dev)) {
4189                 val = vlv_freq_opcode(dev_priv, val);
4190
4191                 hw_max = dev_priv->rps.max_freq;
4192                 hw_min = dev_priv->rps.min_freq;
4193         } else {
4194                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4195
4196                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4197                 hw_max = dev_priv->rps.max_freq;
4198                 hw_min = (rp_state_cap >> 16) & 0xff;
4199         }
4200
4201         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4202                 mutex_unlock(&dev_priv->rps.hw_lock);
4203                 return -EINVAL;
4204         }
4205
4206         dev_priv->rps.min_freq_softlimit = val;
4207
4208         if (IS_VALLEYVIEW(dev))
4209                 valleyview_set_rps(dev, val);
4210         else
4211                 gen6_set_rps(dev, val);
4212
4213         mutex_unlock(&dev_priv->rps.hw_lock);
4214
4215         return 0;
4216 }
4217
4218 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4219                         i915_min_freq_get, i915_min_freq_set,
4220                         "%llu\n");
4221
4222 static int
4223 i915_cache_sharing_get(void *data, u64 *val)
4224 {
4225         struct drm_device *dev = data;
4226         struct drm_i915_private *dev_priv = dev->dev_private;
4227         u32 snpcr;
4228         int ret;
4229
4230         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4231                 return -ENODEV;
4232
4233         ret = mutex_lock_interruptible(&dev->struct_mutex);
4234         if (ret)
4235                 return ret;
4236         intel_runtime_pm_get(dev_priv);
4237
4238         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4239
4240         intel_runtime_pm_put(dev_priv);
4241         mutex_unlock(&dev_priv->dev->struct_mutex);
4242
4243         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4244
4245         return 0;
4246 }
4247
4248 static int
4249 i915_cache_sharing_set(void *data, u64 val)
4250 {
4251         struct drm_device *dev = data;
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         u32 snpcr;
4254
4255         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4256                 return -ENODEV;
4257
4258         if (val > 3)
4259                 return -EINVAL;
4260
4261         intel_runtime_pm_get(dev_priv);
4262         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4263
4264         /* Update the cache sharing policy here as well */
4265         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4266         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4267         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4268         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4269
4270         intel_runtime_pm_put(dev_priv);
4271         return 0;
4272 }
4273
4274 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4275                         i915_cache_sharing_get, i915_cache_sharing_set,
4276                         "%llu\n");
4277
4278 static int i915_forcewake_open(struct inode *inode, struct file *file)
4279 {
4280         struct drm_device *dev = inode->i_private;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282
4283         if (INTEL_INFO(dev)->gen < 6)
4284                 return 0;
4285
4286         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4287
4288         return 0;
4289 }
4290
4291 static int i915_forcewake_release(struct inode *inode, struct file *file)
4292 {
4293         struct drm_device *dev = inode->i_private;
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295
4296         if (INTEL_INFO(dev)->gen < 6)
4297                 return 0;
4298
4299         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4300
4301         return 0;
4302 }
4303
4304 static const struct file_operations i915_forcewake_fops = {
4305         .owner = THIS_MODULE,
4306         .open = i915_forcewake_open,
4307         .release = i915_forcewake_release,
4308 };
4309
4310 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4311 {
4312         struct drm_device *dev = minor->dev;
4313         struct dentry *ent;
4314
4315         ent = debugfs_create_file("i915_forcewake_user",
4316                                   S_IRUSR,
4317                                   root, dev,
4318                                   &i915_forcewake_fops);
4319         if (!ent)
4320                 return -ENOMEM;
4321
4322         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4323 }
4324
4325 static int i915_debugfs_create(struct dentry *root,
4326                                struct drm_minor *minor,
4327                                const char *name,
4328                                const struct file_operations *fops)
4329 {
4330         struct drm_device *dev = minor->dev;
4331         struct dentry *ent;
4332
4333         ent = debugfs_create_file(name,
4334                                   S_IRUGO | S_IWUSR,
4335                                   root, dev,
4336                                   fops);
4337         if (!ent)
4338                 return -ENOMEM;
4339
4340         return drm_add_fake_info_node(minor, ent, fops);
4341 }
4342
4343 static const struct drm_info_list i915_debugfs_list[] = {
4344         {"i915_capabilities", i915_capabilities, 0},
4345         {"i915_gem_objects", i915_gem_object_info, 0},
4346         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4347         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4348         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4349         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4350         {"i915_gem_stolen", i915_gem_stolen_list_info },
4351         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4352         {"i915_gem_request", i915_gem_request_info, 0},
4353         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4354         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4355         {"i915_gem_interrupt", i915_interrupt_info, 0},
4356         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4357         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4358         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4359         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4360         {"i915_frequency_info", i915_frequency_info, 0},
4361         {"i915_drpc_info", i915_drpc_info, 0},
4362         {"i915_emon_status", i915_emon_status, 0},
4363         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4364         {"i915_fbc_status", i915_fbc_status, 0},
4365         {"i915_ips_status", i915_ips_status, 0},
4366         {"i915_sr_status", i915_sr_status, 0},
4367         {"i915_opregion", i915_opregion, 0},
4368         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4369         {"i915_context_status", i915_context_status, 0},
4370         {"i915_dump_lrc", i915_dump_lrc, 0},
4371         {"i915_execlists", i915_execlists, 0},
4372         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4373         {"i915_swizzle_info", i915_swizzle_info, 0},
4374         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4375         {"i915_llc", i915_llc, 0},
4376         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4377         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4378         {"i915_energy_uJ", i915_energy_uJ, 0},
4379         {"i915_pc8_status", i915_pc8_status, 0},
4380         {"i915_power_domain_info", i915_power_domain_info, 0},
4381         {"i915_display_info", i915_display_info, 0},
4382         {"i915_semaphore_status", i915_semaphore_status, 0},
4383         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4384         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4385         {"i915_wa_registers", i915_wa_registers, 0},
4386         {"i915_ddb_info", i915_ddb_info, 0},
4387 };
4388 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4389
4390 static const struct i915_debugfs_files {
4391         const char *name;
4392         const struct file_operations *fops;
4393 } i915_debugfs_files[] = {
4394         {"i915_wedged", &i915_wedged_fops},
4395         {"i915_max_freq", &i915_max_freq_fops},
4396         {"i915_min_freq", &i915_min_freq_fops},
4397         {"i915_cache_sharing", &i915_cache_sharing_fops},
4398         {"i915_ring_stop", &i915_ring_stop_fops},
4399         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4400         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4401         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4402         {"i915_error_state", &i915_error_state_fops},
4403         {"i915_next_seqno", &i915_next_seqno_fops},
4404         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4405         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4406         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4407         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4408         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4409 };
4410
4411 void intel_display_crc_init(struct drm_device *dev)
4412 {
4413         struct drm_i915_private *dev_priv = dev->dev_private;
4414         enum pipe pipe;
4415
4416         for_each_pipe(dev_priv, pipe) {
4417                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4418
4419                 pipe_crc->opened = false;
4420                 spin_lock_init(&pipe_crc->lock);
4421                 init_waitqueue_head(&pipe_crc->wq);
4422         }
4423 }
4424
4425 int i915_debugfs_init(struct drm_minor *minor)
4426 {
4427         int ret, i;
4428
4429         ret = i915_forcewake_create(minor->debugfs_root, minor);
4430         if (ret)
4431                 return ret;
4432
4433         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4434                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4435                 if (ret)
4436                         return ret;
4437         }
4438
4439         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4440                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4441                                           i915_debugfs_files[i].name,
4442                                           i915_debugfs_files[i].fops);
4443                 if (ret)
4444                         return ret;
4445         }
4446
4447         return drm_debugfs_create_files(i915_debugfs_list,
4448                                         I915_DEBUGFS_ENTRIES,
4449                                         minor->debugfs_root, minor);
4450 }
4451
4452 void i915_debugfs_cleanup(struct drm_minor *minor)
4453 {
4454         int i;
4455
4456         drm_debugfs_remove_files(i915_debugfs_list,
4457                                  I915_DEBUGFS_ENTRIES, minor);
4458
4459         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4460                                  1, minor);
4461
4462         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4463                 struct drm_info_list *info_list =
4464                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4465
4466                 drm_debugfs_remove_files(info_list, 1, minor);
4467         }
4468
4469         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4470                 struct drm_info_list *info_list =
4471                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4472
4473                 drm_debugfs_remove_files(info_list, 1, minor);
4474         }
4475 }