drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->user_pin_count > 0)
 100                 return "P";
 101         else if (i915_gem_obj_is_pinned(obj))
 102                 return "p";
 103         else
 104                 return " ";
 105 }
 106
 107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 108 {
 109         switch (obj->tiling_mode) {
 110         default:
 111         case I915_TILING_NONE: return " ";
 112         case I915_TILING_X: return "X";
 113         case I915_TILING_Y: return "Y";
 114         }
 115 }
 116
 117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->has_global_gtt_mapping ? "g" : " ";
 120 }
 121
 122 static void
 123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 124 {
 125         struct i915_vma *vma;
 126         int pin_count = 0;
 127
 128         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 129                    &obj->base,
 130                    get_pin_flag(obj),
 131                    get_tiling_flag(obj),
 132                    get_global_flag(obj),
 133                    obj->base.size / 1024,
 134                    obj->base.read_domains,
 135                    obj->base.write_domain,
 136                    obj->last_read_seqno,
 137                    obj->last_write_seqno,
 138                    obj->last_fenced_seqno,
 139                    i915_cache_level_str(obj->cache_level),
 140                    obj->dirty ? " dirty" : "",
 141                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 142         if (obj->base.name)
 143                 seq_printf(m, " (name: %d)", obj->base.name);
 144         list_for_each_entry(vma, &obj->vma_list, vma_link)
 145                 if (vma->pin_count > 0)
 146                         pin_count++;
 147                 seq_printf(m, " (pinned x %d)", pin_count);
 148         if (obj->pin_display)
 149                 seq_printf(m, " (display)");
 150         if (obj->fence_reg != I915_FENCE_REG_NONE)
 151                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 152         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 153                 if (!i915_is_ggtt(vma->vm))
 154                         seq_puts(m, " (pp");
 155                 else
 156                         seq_puts(m, " (g");
 157                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 158                            vma->node.start, vma->node.size);
 159         }
 160         if (obj->stolen)
 161                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 162         if (obj->pin_mappable || obj->fault_mappable) {
 163                 char s[3], *t = s;
 164                 if (obj->pin_mappable)
 165                         *t++ = 'p';
 166                 if (obj->fault_mappable)
 167                         *t++ = 'f';
 168                 *t = '\0';
 169                 seq_printf(m, " (%s mappable)", s);
 170         }
 171         if (obj->ring != NULL)
 172                 seq_printf(m, " (%s)", obj->ring->name);
 173 }
 174
 175 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 176 {
 177         seq_putc(m, ctx->is_initialized ? 'I' : 'i');
 178         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 179         seq_putc(m, ' ');
 180 }
 181
 182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 183 {
 184         struct drm_info_node *node = m->private;
 185         uintptr_t list = (uintptr_t) node->info_ent->data;
 186         struct list_head *head;
 187         struct drm_device *dev = node->minor->dev;
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         struct i915_address_space *vm = &dev_priv->gtt.base;
 190         struct i915_vma *vma;
 191         size_t total_obj_size, total_gtt_size;
 192         int count, ret;
 193
 194         ret = mutex_lock_interruptible(&dev->struct_mutex);
 195         if (ret)
 196                 return ret;
 197
 198         /* FIXME: the user of this interface might want more than just GGTT */
 199         switch (list) {
 200         case ACTIVE_LIST:
 201                 seq_puts(m, "Active:\n");
 202                 head = &vm->active_list;
 203                 break;
 204         case INACTIVE_LIST:
 205                 seq_puts(m, "Inactive:\n");
 206                 head = &vm->inactive_list;
 207                 break;
 208         default:
 209                 mutex_unlock(&dev->struct_mutex);
 210                 return -EINVAL;
 211         }
 212
 213         total_obj_size = total_gtt_size = count = 0;
 214         list_for_each_entry(vma, head, mm_list) {
 215                 seq_printf(m, "   ");
 216                 describe_obj(m, vma->obj);
 217                 seq_printf(m, "\n");
 218                 total_obj_size += vma->obj->base.size;
 219                 total_gtt_size += vma->node.size;
 220                 count++;
 221         }
 222         mutex_unlock(&dev->struct_mutex);
 223
 224         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 225                    count, total_obj_size, total_gtt_size);
 226         return 0;
 227 }
 228
 229 static int obj_rank_by_stolen(void *priv,
 230                               struct list_head *A, struct list_head *B)
 231 {
 232         struct drm_i915_gem_object *a =
 233                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 234         struct drm_i915_gem_object *b =
 235                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 236
 237         return a->stolen->start - b->stolen->start;
 238 }
 239
 240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 241 {
 242         struct drm_info_node *node = m->private;
 243         struct drm_device *dev = node->minor->dev;
 244         struct drm_i915_private *dev_priv = dev->dev_private;
 245         struct drm_i915_gem_object *obj;
 246         size_t total_obj_size, total_gtt_size;
 247         LIST_HEAD(stolen);
 248         int count, ret;
 249
 250         ret = mutex_lock_interruptible(&dev->struct_mutex);
 251         if (ret)
 252                 return ret;
 253
 254         total_obj_size = total_gtt_size = count = 0;
 255         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 256                 if (obj->stolen == NULL)
 257                         continue;
 258
 259                 list_add(&obj->obj_exec_link, &stolen);
 260
 261                 total_obj_size += obj->base.size;
 262                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 263                 count++;
 264         }
 265         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 266                 if (obj->stolen == NULL)
 267                         continue;
 268
 269                 list_add(&obj->obj_exec_link, &stolen);
 270
 271                 total_obj_size += obj->base.size;
 272                 count++;
 273         }
 274         list_sort(NULL, &stolen, obj_rank_by_stolen);
 275         seq_puts(m, "Stolen:\n");
 276         while (!list_empty(&stolen)) {
 277                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 278                 seq_puts(m, "   ");
 279                 describe_obj(m, obj);
 280                 seq_putc(m, '\n');
 281                 list_del_init(&obj->obj_exec_link);
 282         }
 283         mutex_unlock(&dev->struct_mutex);
 284
 285         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 286                    count, total_obj_size, total_gtt_size);
 287         return 0;
 288 }
 289
 290 #define count_objects(list, member) do { \
 291         list_for_each_entry(obj, list, member) { \
 292                 size += i915_gem_obj_ggtt_size(obj); \
 293                 ++count; \
 294                 if (obj->map_and_fenceable) { \
 295                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 296                         ++mappable_count; \
 297                 } \
 298         } \
 299 } while (0)
 300
 301 struct file_stats {
 302         struct drm_i915_file_private *file_priv;
 303         int count;
 304         size_t total, unbound;
 305         size_t global, shared;
 306         size_t active, inactive;
 307 };
 308
 309 static int per_file_stats(int id, void *ptr, void *data)
 310 {
 311         struct drm_i915_gem_object *obj = ptr;
 312         struct file_stats *stats = data;
 313         struct i915_vma *vma;
 314
 315         stats->count++;
 316         stats->total += obj->base.size;
 317
 318         if (obj->base.name || obj->base.dma_buf)
 319                 stats->shared += obj->base.size;
 320
 321         if (USES_FULL_PPGTT(obj->base.dev)) {
 322                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 323                         struct i915_hw_ppgtt *ppgtt;
 324
 325                         if (!drm_mm_node_allocated(&vma->node))
 326                                 continue;
 327
 328                         if (i915_is_ggtt(vma->vm)) {
 329                                 stats->global += obj->base.size;
 330                                 continue;
 331                         }
 332
 333                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 334                         if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
 335                                 continue;
 336
 337                         if (obj->ring) /* XXX per-vma statistic */
 338                                 stats->active += obj->base.size;
 339                         else
 340                                 stats->inactive += obj->base.size;
 341
 342                         return 0;
 343                 }
 344         } else {
 345                 if (i915_gem_obj_ggtt_bound(obj)) {
 346                         stats->global += obj->base.size;
 347                         if (obj->ring)
 348                                 stats->active += obj->base.size;
 349                         else
 350                                 stats->inactive += obj->base.size;
 351                         return 0;
 352                 }
 353         }
 354
 355         if (!list_empty(&obj->global_list))
 356                 stats->unbound += obj->base.size;
 357
 358         return 0;
 359 }
 360
 361 #define count_vmas(list, member) do { \
 362         list_for_each_entry(vma, list, member) { \
 363                 size += i915_gem_obj_ggtt_size(vma->obj); \
 364                 ++count; \
 365                 if (vma->obj->map_and_fenceable) { \
 366                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 367                         ++mappable_count; \
 368                 } \
 369         } \
 370 } while (0)
 371
 372 static int i915_gem_object_info(struct seq_file *m, void* data)
 373 {
 374         struct drm_info_node *node = m->private;
 375         struct drm_device *dev = node->minor->dev;
 376         struct drm_i915_private *dev_priv = dev->dev_private;
 377         u32 count, mappable_count, purgeable_count;
 378         size_t size, mappable_size, purgeable_size;
 379         struct drm_i915_gem_object *obj;
 380         struct i915_address_space *vm = &dev_priv->gtt.base;
 381         struct drm_file *file;
 382         struct i915_vma *vma;
 383         int ret;
 384
 385         ret = mutex_lock_interruptible(&dev->struct_mutex);
 386         if (ret)
 387                 return ret;
 388
 389         seq_printf(m, "%u objects, %zu bytes\n",
 390                    dev_priv->mm.object_count,
 391                    dev_priv->mm.object_memory);
 392
 393         size = count = mappable_size = mappable_count = 0;
 394         count_objects(&dev_priv->mm.bound_list, global_list);
 395         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 396                    count, mappable_count, size, mappable_size);
 397
 398         size = count = mappable_size = mappable_count = 0;
 399         count_vmas(&vm->active_list, mm_list);
 400         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 401                    count, mappable_count, size, mappable_size);
 402
 403         size = count = mappable_size = mappable_count = 0;
 404         count_vmas(&vm->inactive_list, mm_list);
 405         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 406                    count, mappable_count, size, mappable_size);
 407
 408         size = count = purgeable_size = purgeable_count = 0;
 409         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 410                 size += obj->base.size, ++count;
 411                 if (obj->madv == I915_MADV_DONTNEED)
 412                         purgeable_size += obj->base.size, ++purgeable_count;
 413         }
 414         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 415
 416         size = count = mappable_size = mappable_count = 0;
 417         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 418                 if (obj->fault_mappable) {
 419                         size += i915_gem_obj_ggtt_size(obj);
 420                         ++count;
 421                 }
 422                 if (obj->pin_mappable) {
 423                         mappable_size += i915_gem_obj_ggtt_size(obj);
 424                         ++mappable_count;
 425                 }
 426                 if (obj->madv == I915_MADV_DONTNEED) {
 427                         purgeable_size += obj->base.size;
 428                         ++purgeable_count;
 429                 }
 430         }
 431         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 432                    purgeable_count, purgeable_size);
 433         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 434                    mappable_count, mappable_size);
 435         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 436                    count, size);
 437
 438         seq_printf(m, "%zu [%lu] gtt total\n",
 439                    dev_priv->gtt.base.total,
 440                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 441
 442         seq_putc(m, '\n');
 443         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 444                 struct file_stats stats;
 445                 struct task_struct *task;
 446
 447                 memset(&stats, 0, sizeof(stats));
 448                 stats.file_priv = file->driver_priv;
 449                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 450                 /*
 451                  * Although we have a valid reference on file->pid, that does
 452                  * not guarantee that the task_struct who called get_pid() is
 453                  * still alive (e.g. get_pid(current) => fork() => exit()).
 454                  * Therefore, we need to protect this ->comm access using RCU.
 455                  */
 456                 rcu_read_lock();
 457                 task = pid_task(file->pid, PIDTYPE_PID);
 458                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
 459                            task ? task->comm : "<unknown>",
 460                            stats.count,
 461                            stats.total,
 462                            stats.active,
 463                            stats.inactive,
 464                            stats.global,
 465                            stats.shared,
 466                            stats.unbound);
 467                 rcu_read_unlock();
 468         }
 469
 470         mutex_unlock(&dev->struct_mutex);
 471
 472         return 0;
 473 }
 474
 475 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 476 {
 477         struct drm_info_node *node = m->private;
 478         struct drm_device *dev = node->minor->dev;
 479         uintptr_t list = (uintptr_t) node->info_ent->data;
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         struct drm_i915_gem_object *obj;
 482         size_t total_obj_size, total_gtt_size;
 483         int count, ret;
 484
 485         ret = mutex_lock_interruptible(&dev->struct_mutex);
 486         if (ret)
 487                 return ret;
 488
 489         total_obj_size = total_gtt_size = count = 0;
 490         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 491                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 492                         continue;
 493
 494                 seq_puts(m, "   ");
 495                 describe_obj(m, obj);
 496                 seq_putc(m, '\n');
 497                 total_obj_size += obj->base.size;
 498                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 499                 count++;
 500         }
 501
 502         mutex_unlock(&dev->struct_mutex);
 503
 504         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 505                    count, total_obj_size, total_gtt_size);
 506
 507         return 0;
 508 }
 509
 510 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 511 {
 512         struct drm_info_node *node = m->private;
 513         struct drm_device *dev = node->minor->dev;
 514         unsigned long flags;
 515         struct intel_crtc *crtc;
 516
 517         for_each_intel_crtc(dev, crtc) {
 518                 const char pipe = pipe_name(crtc->pipe);
 519                 const char plane = plane_name(crtc->plane);
 520                 struct intel_unpin_work *work;
 521
 522                 spin_lock_irqsave(&dev->event_lock, flags);
 523                 work = crtc->unpin_work;
 524                 if (work == NULL) {
 525                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 526                                    pipe, plane);
 527                 } else {
 528                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 529                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 530                                            pipe, plane);
 531                         } else {
 532                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 533                                            pipe, plane);
 534                         }
 535                         if (work->enable_stall_check)
 536                                 seq_puts(m, "Stall check enabled, ");
 537                         else
 538                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 539                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 540
 541                         if (work->old_fb_obj) {
 542                                 struct drm_i915_gem_object *obj = work->old_fb_obj;
 543                                 if (obj)
 544                                         seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
 545                                                    i915_gem_obj_ggtt_offset(obj));
 546                         }
 547                         if (work->pending_flip_obj) {
 548                                 struct drm_i915_gem_object *obj = work->pending_flip_obj;
 549                                 if (obj)
 550                                         seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
 551                                                    i915_gem_obj_ggtt_offset(obj));
 552                         }
 553                 }
 554                 spin_unlock_irqrestore(&dev->event_lock, flags);
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int i915_gem_request_info(struct seq_file *m, void *data)
 561 {
 562         struct drm_info_node *node = m->private;
 563         struct drm_device *dev = node->minor->dev;
 564         struct drm_i915_private *dev_priv = dev->dev_private;
 565         struct intel_engine_cs *ring;
 566         struct drm_i915_gem_request *gem_request;
 567         int ret, count, i;
 568
 569         ret = mutex_lock_interruptible(&dev->struct_mutex);
 570         if (ret)
 571                 return ret;
 572
 573         count = 0;
 574         for_each_ring(ring, dev_priv, i) {
 575                 if (list_empty(&ring->request_list))
 576                         continue;
 577
 578                 seq_printf(m, "%s requests:\n", ring->name);
 579                 list_for_each_entry(gem_request,
 580                                     &ring->request_list,
 581                                     list) {
 582                         seq_printf(m, "    %d @ %d\n",
 583                                    gem_request->seqno,
 584                                    (int) (jiffies - gem_request->emitted_jiffies));
 585                 }
 586                 count++;
 587         }
 588         mutex_unlock(&dev->struct_mutex);
 589
 590         if (count == 0)
 591                 seq_puts(m, "No requests\n");
 592
 593         return 0;
 594 }
 595
 596 static void i915_ring_seqno_info(struct seq_file *m,
 597                                  struct intel_engine_cs *ring)
 598 {
 599         if (ring->get_seqno) {
 600                 seq_printf(m, "Current sequence (%s): %u\n",
 601                            ring->name, ring->get_seqno(ring, false));
 602         }
 603 }
 604
 605 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 606 {
 607         struct drm_info_node *node = m->private;
 608         struct drm_device *dev = node->minor->dev;
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610         struct intel_engine_cs *ring;
 611         int ret, i;
 612
 613         ret = mutex_lock_interruptible(&dev->struct_mutex);
 614         if (ret)
 615                 return ret;
 616         intel_runtime_pm_get(dev_priv);
 617
 618         for_each_ring(ring, dev_priv, i)
 619                 i915_ring_seqno_info(m, ring);
 620
 621         intel_runtime_pm_put(dev_priv);
 622         mutex_unlock(&dev->struct_mutex);
 623
 624         return 0;
 625 }
 626
 627
 628 static int i915_interrupt_info(struct seq_file *m, void *data)
 629 {
 630         struct drm_info_node *node = m->private;
 631         struct drm_device *dev = node->minor->dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         struct intel_engine_cs *ring;
 634         int ret, i, pipe;
 635
 636         ret = mutex_lock_interruptible(&dev->struct_mutex);
 637         if (ret)
 638                 return ret;
 639         intel_runtime_pm_get(dev_priv);
 640
 641         if (IS_CHERRYVIEW(dev)) {
 642                 int i;
 643                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 644                            I915_READ(GEN8_MASTER_IRQ));
 645
 646                 seq_printf(m, "Display IER:\t%08x\n",
 647                            I915_READ(VLV_IER));
 648                 seq_printf(m, "Display IIR:\t%08x\n",
 649                            I915_READ(VLV_IIR));
 650                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 651                            I915_READ(VLV_IIR_RW));
 652                 seq_printf(m, "Display IMR:\t%08x\n",
 653                            I915_READ(VLV_IMR));
 654                 for_each_pipe(pipe)
 655                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 656                                    pipe_name(pipe),
 657                                    I915_READ(PIPESTAT(pipe)));
 658
 659                 seq_printf(m, "Port hotplug:\t%08x\n",
 660                            I915_READ(PORT_HOTPLUG_EN));
 661                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 662                            I915_READ(VLV_DPFLIPSTAT));
 663                 seq_printf(m, "DPINVGTT:\t%08x\n",
 664                            I915_READ(DPINVGTT));
 665
 666                 for (i = 0; i < 4; i++) {
 667                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 668                                    i, I915_READ(GEN8_GT_IMR(i)));
 669                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 670                                    i, I915_READ(GEN8_GT_IIR(i)));
 671                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 672                                    i, I915_READ(GEN8_GT_IER(i)));
 673                 }
 674
 675                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 676                            I915_READ(GEN8_PCU_IMR));
 677                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 678                            I915_READ(GEN8_PCU_IIR));
 679                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 680                            I915_READ(GEN8_PCU_IER));
 681         } else if (INTEL_INFO(dev)->gen >= 8) {
 682                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 683                            I915_READ(GEN8_MASTER_IRQ));
 684
 685                 for (i = 0; i < 4; i++) {
 686                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 687                                    i, I915_READ(GEN8_GT_IMR(i)));
 688                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 689                                    i, I915_READ(GEN8_GT_IIR(i)));
 690                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 691                                    i, I915_READ(GEN8_GT_IER(i)));
 692                 }
 693
 694                 for_each_pipe(pipe) {
 695                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 696                                    pipe_name(pipe),
 697                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 698                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 699                                    pipe_name(pipe),
 700                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 701                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 702                                    pipe_name(pipe),
 703                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 704                 }
 705
 706                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 707                            I915_READ(GEN8_DE_PORT_IMR));
 708                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 709                            I915_READ(GEN8_DE_PORT_IIR));
 710                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 711                            I915_READ(GEN8_DE_PORT_IER));
 712
 713                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 714                            I915_READ(GEN8_DE_MISC_IMR));
 715                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 716                            I915_READ(GEN8_DE_MISC_IIR));
 717                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 718                            I915_READ(GEN8_DE_MISC_IER));
 719
 720                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 721                            I915_READ(GEN8_PCU_IMR));
 722                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 723                            I915_READ(GEN8_PCU_IIR));
 724                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 725                            I915_READ(GEN8_PCU_IER));
 726         } else if (IS_VALLEYVIEW(dev)) {
 727                 seq_printf(m, "Display IER:\t%08x\n",
 728                            I915_READ(VLV_IER));
 729                 seq_printf(m, "Display IIR:\t%08x\n",
 730                            I915_READ(VLV_IIR));
 731                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 732                            I915_READ(VLV_IIR_RW));
 733                 seq_printf(m, "Display IMR:\t%08x\n",
 734                            I915_READ(VLV_IMR));
 735                 for_each_pipe(pipe)
 736                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 737                                    pipe_name(pipe),
 738                                    I915_READ(PIPESTAT(pipe)));
 739
 740                 seq_printf(m, "Master IER:\t%08x\n",
 741                            I915_READ(VLV_MASTER_IER));
 742
 743                 seq_printf(m, "Render IER:\t%08x\n",
 744                            I915_READ(GTIER));
 745                 seq_printf(m, "Render IIR:\t%08x\n",
 746                            I915_READ(GTIIR));
 747                 seq_printf(m, "Render IMR:\t%08x\n",
 748                            I915_READ(GTIMR));
 749
 750                 seq_printf(m, "PM IER:\t\t%08x\n",
 751                            I915_READ(GEN6_PMIER));
 752                 seq_printf(m, "PM IIR:\t\t%08x\n",
 753                            I915_READ(GEN6_PMIIR));
 754                 seq_printf(m, "PM IMR:\t\t%08x\n",
 755                            I915_READ(GEN6_PMIMR));
 756
 757                 seq_printf(m, "Port hotplug:\t%08x\n",
 758                            I915_READ(PORT_HOTPLUG_EN));
 759                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 760                            I915_READ(VLV_DPFLIPSTAT));
 761                 seq_printf(m, "DPINVGTT:\t%08x\n",
 762                            I915_READ(DPINVGTT));
 763
 764         } else if (!HAS_PCH_SPLIT(dev)) {
 765                 seq_printf(m, "Interrupt enable:    %08x\n",
 766                            I915_READ(IER));
 767                 seq_printf(m, "Interrupt identity:  %08x\n",
 768                            I915_READ(IIR));
 769                 seq_printf(m, "Interrupt mask:      %08x\n",
 770                            I915_READ(IMR));
 771                 for_each_pipe(pipe)
 772                         seq_printf(m, "Pipe %c stat:         %08x\n",
 773                                    pipe_name(pipe),
 774                                    I915_READ(PIPESTAT(pipe)));
 775         } else {
 776                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 777                            I915_READ(DEIER));
 778                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 779                            I915_READ(DEIIR));
 780                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 781                            I915_READ(DEIMR));
 782                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 783                            I915_READ(SDEIER));
 784                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 785                            I915_READ(SDEIIR));
 786                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 787                            I915_READ(SDEIMR));
 788                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 789                            I915_READ(GTIER));
 790                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 791                            I915_READ(GTIIR));
 792                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 793                            I915_READ(GTIMR));
 794         }
 795         for_each_ring(ring, dev_priv, i) {
 796                 if (INTEL_INFO(dev)->gen >= 6) {
 797                         seq_printf(m,
 798                                    "Graphics Interrupt mask (%s):       %08x\n",
 799                                    ring->name, I915_READ_IMR(ring));
 800                 }
 801                 i915_ring_seqno_info(m, ring);
 802         }
 803         intel_runtime_pm_put(dev_priv);
 804         mutex_unlock(&dev->struct_mutex);
 805
 806         return 0;
 807 }
 808
 809 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 810 {
 811         struct drm_info_node *node = m->private;
 812         struct drm_device *dev = node->minor->dev;
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         int i, ret;
 815
 816         ret = mutex_lock_interruptible(&dev->struct_mutex);
 817         if (ret)
 818                 return ret;
 819
 820         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 821         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 822         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 823                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 824
 825                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 826                            i, dev_priv->fence_regs[i].pin_count);
 827                 if (obj == NULL)
 828                         seq_puts(m, "unused");
 829                 else
 830                         describe_obj(m, obj);
 831                 seq_putc(m, '\n');
 832         }
 833
 834         mutex_unlock(&dev->struct_mutex);
 835         return 0;
 836 }
 837
 838 static int i915_hws_info(struct seq_file *m, void *data)
 839 {
 840         struct drm_info_node *node = m->private;
 841         struct drm_device *dev = node->minor->dev;
 842         struct drm_i915_private *dev_priv = dev->dev_private;
 843         struct intel_engine_cs *ring;
 844         const u32 *hws;
 845         int i;
 846
 847         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 848         hws = ring->status_page.page_addr;
 849         if (hws == NULL)
 850                 return 0;
 851
 852         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 853                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 854                            i * 4,
 855                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 856         }
 857         return 0;
 858 }
 859
 860 static ssize_t
 861 i915_error_state_write(struct file *filp,
 862                        const char __user *ubuf,
 863                        size_t cnt,
 864                        loff_t *ppos)
 865 {
 866         struct i915_error_state_file_priv *error_priv = filp->private_data;
 867         struct drm_device *dev = error_priv->dev;
 868         int ret;
 869
 870         DRM_DEBUG_DRIVER("Resetting error state\n");
 871
 872         ret = mutex_lock_interruptible(&dev->struct_mutex);
 873         if (ret)
 874                 return ret;
 875
 876         i915_destroy_error_state(dev);
 877         mutex_unlock(&dev->struct_mutex);
 878
 879         return cnt;
 880 }
 881
 882 static int i915_error_state_open(struct inode *inode, struct file *file)
 883 {
 884         struct drm_device *dev = inode->i_private;
 885         struct i915_error_state_file_priv *error_priv;
 886
 887         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 888         if (!error_priv)
 889                 return -ENOMEM;
 890
 891         error_priv->dev = dev;
 892
 893         i915_error_state_get(dev, error_priv);
 894
 895         file->private_data = error_priv;
 896
 897         return 0;
 898 }
 899
 900 static int i915_error_state_release(struct inode *inode, struct file *file)
 901 {
 902         struct i915_error_state_file_priv *error_priv = file->private_data;
 903
 904         i915_error_state_put(error_priv);
 905         kfree(error_priv);
 906
 907         return 0;
 908 }
 909
 910 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 911                                      size_t count, loff_t *pos)
 912 {
 913         struct i915_error_state_file_priv *error_priv = file->private_data;
 914         struct drm_i915_error_state_buf error_str;
 915         loff_t tmp_pos = 0;
 916         ssize_t ret_count = 0;
 917         int ret;
 918
 919         ret = i915_error_state_buf_init(&error_str, count, *pos);
 920         if (ret)
 921                 return ret;
 922
 923         ret = i915_error_state_to_str(&error_str, error_priv);
 924         if (ret)
 925                 goto out;
 926
 927         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 928                                             error_str.buf,
 929                                             error_str.bytes);
 930
 931         if (ret_count < 0)
 932                 ret = ret_count;
 933         else
 934                 *pos = error_str.start + ret_count;
 935 out:
 936         i915_error_state_buf_release(&error_str);
 937         return ret ?: ret_count;
 938 }
 939
 940 static const struct file_operations i915_error_state_fops = {
 941         .owner = THIS_MODULE,
 942         .open = i915_error_state_open,
 943         .read = i915_error_state_read,
 944         .write = i915_error_state_write,
 945         .llseek = default_llseek,
 946         .release = i915_error_state_release,
 947 };
 948
 949 static int
 950 i915_next_seqno_get(void *data, u64 *val)
 951 {
 952         struct drm_device *dev = data;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         int ret;
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         *val = dev_priv->next_seqno;
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return 0;
 964 }
 965
 966 static int
 967 i915_next_seqno_set(void *data, u64 val)
 968 {
 969         struct drm_device *dev = data;
 970         int ret;
 971
 972         ret = mutex_lock_interruptible(&dev->struct_mutex);
 973         if (ret)
 974                 return ret;
 975
 976         ret = i915_gem_set_seqno(dev, val);
 977         mutex_unlock(&dev->struct_mutex);
 978
 979         return ret;
 980 }
 981
 982 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 983                         i915_next_seqno_get, i915_next_seqno_set,
 984                         "0x%llx\n");
 985
 986 static int i915_rstdby_delays(struct seq_file *m, void *unused)
 987 {
 988         struct drm_info_node *node = m->private;
 989         struct drm_device *dev = node->minor->dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         u16 crstanddelay;
 992         int ret;
 993
 994         ret = mutex_lock_interruptible(&dev->struct_mutex);
 995         if (ret)
 996                 return ret;
 997         intel_runtime_pm_get(dev_priv);
 998
 999         crstanddelay = I915_READ16(CRSTANDVID);
1000
1001         intel_runtime_pm_put(dev_priv);
1002         mutex_unlock(&dev->struct_mutex);
1003
1004         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1005
1006         return 0;
1007 }
1008
1009 static int i915_frequency_info(struct seq_file *m, void *unused)
1010 {
1011         struct drm_info_node *node = m->private;
1012         struct drm_device *dev = node->minor->dev;
1013         struct drm_i915_private *dev_priv = dev->dev_private;
1014         int ret = 0;
1015
1016         intel_runtime_pm_get(dev_priv);
1017
1018         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1019
1020         if (IS_GEN5(dev)) {
1021                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1022                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1023
1024                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1025                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1026                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1027                            MEMSTAT_VID_SHIFT);
1028                 seq_printf(m, "Current P-state: %d\n",
1029                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1030         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1031                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1032                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1033                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1034                 u32 rpmodectl, rpinclimit, rpdeclimit;
1035                 u32 rpstat, cagf, reqf;
1036                 u32 rpupei, rpcurup, rpprevup;
1037                 u32 rpdownei, rpcurdown, rpprevdown;
1038                 int max_freq;
1039
1040                 /* RPSTAT1 is in the GT power well */
1041                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1042                 if (ret)
1043                         goto out;
1044
1045                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1046
1047                 reqf = I915_READ(GEN6_RPNSWREQ);
1048                 reqf &= ~GEN6_TURBO_DISABLE;
1049                 if (IS_HASWELL(dev))
1050                         reqf >>= 24;
1051                 else
1052                         reqf >>= 25;
1053                 reqf *= GT_FREQUENCY_MULTIPLIER;
1054
1055                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1056                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1057                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1058
1059                 rpstat = I915_READ(GEN6_RPSTAT1);
1060                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1061                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1062                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1063                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1064                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1065                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1066                 if (IS_HASWELL(dev))
1067                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1068                 else
1069                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1070                 cagf *= GT_FREQUENCY_MULTIPLIER;
1071
1072                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1073                 mutex_unlock(&dev->struct_mutex);
1074
1075                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1076                            I915_READ(GEN6_PMIER),
1077                            I915_READ(GEN6_PMIMR),
1078                            I915_READ(GEN6_PMISR),
1079                            I915_READ(GEN6_PMIIR),
1080                            I915_READ(GEN6_PMINTRMSK));
1081                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1082                 seq_printf(m, "Render p-state ratio: %d\n",
1083                            (gt_perf_status & 0xff00) >> 8);
1084                 seq_printf(m, "Render p-state VID: %d\n",
1085                            gt_perf_status & 0xff);
1086                 seq_printf(m, "Render p-state limit: %d\n",
1087                            rp_state_limits & 0xff);
1088                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1089                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1090                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1091                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1092                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1093                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1094                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1095                            GEN6_CURICONT_MASK);
1096                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1097                            GEN6_CURBSYTAVG_MASK);
1098                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1099                            GEN6_CURBSYTAVG_MASK);
1100                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1101                            GEN6_CURIAVG_MASK);
1102                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1103                            GEN6_CURBSYTAVG_MASK);
1104                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1105                            GEN6_CURBSYTAVG_MASK);
1106
1107                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1108                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1109                            max_freq * GT_FREQUENCY_MULTIPLIER);
1110
1111                 max_freq = (rp_state_cap & 0xff00) >> 8;
1112                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1113                            max_freq * GT_FREQUENCY_MULTIPLIER);
1114
1115                 max_freq = rp_state_cap & 0xff;
1116                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1117                            max_freq * GT_FREQUENCY_MULTIPLIER);
1118
1119                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1120                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1121         } else if (IS_VALLEYVIEW(dev)) {
1122                 u32 freq_sts, val;
1123
1124                 mutex_lock(&dev_priv->rps.hw_lock);
1125                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1126                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1127                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1128
1129                 val = valleyview_rps_max_freq(dev_priv);
1130                 seq_printf(m, "max GPU freq: %d MHz\n",
1131                            vlv_gpu_freq(dev_priv, val));
1132
1133                 val = valleyview_rps_min_freq(dev_priv);
1134                 seq_printf(m, "min GPU freq: %d MHz\n",
1135                            vlv_gpu_freq(dev_priv, val));
1136
1137                 seq_printf(m, "current GPU freq: %d MHz\n",
1138                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1139                 mutex_unlock(&dev_priv->rps.hw_lock);
1140         } else {
1141                 seq_puts(m, "no P-state info available\n");
1142         }
1143
1144 out:
1145         intel_runtime_pm_put(dev_priv);
1146         return ret;
1147 }
1148
1149 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1150 {
1151         struct drm_info_node *node = m->private;
1152         struct drm_device *dev = node->minor->dev;
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         u32 delayfreq;
1155         int ret, i;
1156
1157         ret = mutex_lock_interruptible(&dev->struct_mutex);
1158         if (ret)
1159                 return ret;
1160         intel_runtime_pm_get(dev_priv);
1161
1162         for (i = 0; i < 16; i++) {
1163                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1164                 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1165                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1166         }
1167
1168         intel_runtime_pm_put(dev_priv);
1169
1170         mutex_unlock(&dev->struct_mutex);
1171
1172         return 0;
1173 }
1174
1175 static inline int MAP_TO_MV(int map)
1176 {
1177         return 1250 - (map * 25);
1178 }
1179
1180 static int i915_inttoext_table(struct seq_file *m, void *unused)
1181 {
1182         struct drm_info_node *node = m->private;
1183         struct drm_device *dev = node->minor->dev;
1184         struct drm_i915_private *dev_priv = dev->dev_private;
1185         u32 inttoext;
1186         int ret, i;
1187
1188         ret = mutex_lock_interruptible(&dev->struct_mutex);
1189         if (ret)
1190                 return ret;
1191         intel_runtime_pm_get(dev_priv);
1192
1193         for (i = 1; i <= 32; i++) {
1194                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1195                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1196         }
1197
1198         intel_runtime_pm_put(dev_priv);
1199         mutex_unlock(&dev->struct_mutex);
1200
1201         return 0;
1202 }
1203
1204 static int ironlake_drpc_info(struct seq_file *m)
1205 {
1206         struct drm_info_node *node = m->private;
1207         struct drm_device *dev = node->minor->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         u32 rgvmodectl, rstdbyctl;
1210         u16 crstandvid;
1211         int ret;
1212
1213         ret = mutex_lock_interruptible(&dev->struct_mutex);
1214         if (ret)
1215                 return ret;
1216         intel_runtime_pm_get(dev_priv);
1217
1218         rgvmodectl = I915_READ(MEMMODECTL);
1219         rstdbyctl = I915_READ(RSTDBYCTL);
1220         crstandvid = I915_READ16(CRSTANDVID);
1221
1222         intel_runtime_pm_put(dev_priv);
1223         mutex_unlock(&dev->struct_mutex);
1224
1225         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1226                    "yes" : "no");
1227         seq_printf(m, "Boost freq: %d\n",
1228                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1229                    MEMMODE_BOOST_FREQ_SHIFT);
1230         seq_printf(m, "HW control enabled: %s\n",
1231                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1232         seq_printf(m, "SW control enabled: %s\n",
1233                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1234         seq_printf(m, "Gated voltage change: %s\n",
1235                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1236         seq_printf(m, "Starting frequency: P%d\n",
1237                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1238         seq_printf(m, "Max P-state: P%d\n",
1239                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1240         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1241         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1242         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1243         seq_printf(m, "Render standby enabled: %s\n",
1244                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1245         seq_puts(m, "Current RS state: ");
1246         switch (rstdbyctl & RSX_STATUS_MASK) {
1247         case RSX_STATUS_ON:
1248                 seq_puts(m, "on\n");
1249                 break;
1250         case RSX_STATUS_RC1:
1251                 seq_puts(m, "RC1\n");
1252                 break;
1253         case RSX_STATUS_RC1E:
1254                 seq_puts(m, "RC1E\n");
1255                 break;
1256         case RSX_STATUS_RS1:
1257                 seq_puts(m, "RS1\n");
1258                 break;
1259         case RSX_STATUS_RS2:
1260                 seq_puts(m, "RS2 (RC6)\n");
1261                 break;
1262         case RSX_STATUS_RS3:
1263                 seq_puts(m, "RC3 (RC6+)\n");
1264                 break;
1265         default:
1266                 seq_puts(m, "unknown\n");
1267                 break;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static int vlv_drpc_info(struct seq_file *m)
1274 {
1275
1276         struct drm_info_node *node = m->private;
1277         struct drm_device *dev = node->minor->dev;
1278         struct drm_i915_private *dev_priv = dev->dev_private;
1279         u32 rpmodectl1, rcctl1;
1280         unsigned fw_rendercount = 0, fw_mediacount = 0;
1281
1282         intel_runtime_pm_get(dev_priv);
1283
1284         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1285         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1286
1287         intel_runtime_pm_put(dev_priv);
1288
1289         seq_printf(m, "Video Turbo Mode: %s\n",
1290                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1291         seq_printf(m, "Turbo enabled: %s\n",
1292                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1293         seq_printf(m, "HW control enabled: %s\n",
1294                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1295         seq_printf(m, "SW control enabled: %s\n",
1296                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1297                           GEN6_RP_MEDIA_SW_MODE));
1298         seq_printf(m, "RC6 Enabled: %s\n",
1299                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1300                                         GEN6_RC_CTL_EI_MODE(1))));
1301         seq_printf(m, "Render Power Well: %s\n",
1302                         (I915_READ(VLV_GTLC_PW_STATUS) &
1303                                 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1304         seq_printf(m, "Media Power Well: %s\n",
1305                         (I915_READ(VLV_GTLC_PW_STATUS) &
1306                                 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1307
1308         seq_printf(m, "Render RC6 residency since boot: %u\n",
1309                    I915_READ(VLV_GT_RENDER_RC6));
1310         seq_printf(m, "Media RC6 residency since boot: %u\n",
1311                    I915_READ(VLV_GT_MEDIA_RC6));
1312
1313         spin_lock_irq(&dev_priv->uncore.lock);
1314         fw_rendercount = dev_priv->uncore.fw_rendercount;
1315         fw_mediacount = dev_priv->uncore.fw_mediacount;
1316         spin_unlock_irq(&dev_priv->uncore.lock);
1317
1318         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1319         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1320
1321
1322         return 0;
1323 }
1324
1325
1326 static int gen6_drpc_info(struct seq_file *m)
1327 {
1328
1329         struct drm_info_node *node = m->private;
1330         struct drm_device *dev = node->minor->dev;
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1333         unsigned forcewake_count;
1334         int count = 0, ret;
1335
1336         ret = mutex_lock_interruptible(&dev->struct_mutex);
1337         if (ret)
1338                 return ret;
1339         intel_runtime_pm_get(dev_priv);
1340
1341         spin_lock_irq(&dev_priv->uncore.lock);
1342         forcewake_count = dev_priv->uncore.forcewake_count;
1343         spin_unlock_irq(&dev_priv->uncore.lock);
1344
1345         if (forcewake_count) {
1346                 seq_puts(m, "RC information inaccurate because somebody "
1347                             "holds a forcewake reference \n");
1348         } else {
1349                 /* NB: we cannot use forcewake, else we read the wrong values */
1350                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1351                         udelay(10);
1352                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1353         }
1354
1355         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1356         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1357
1358         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1359         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1360         mutex_unlock(&dev->struct_mutex);
1361         mutex_lock(&dev_priv->rps.hw_lock);
1362         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1363         mutex_unlock(&dev_priv->rps.hw_lock);
1364
1365         intel_runtime_pm_put(dev_priv);
1366
1367         seq_printf(m, "Video Turbo Mode: %s\n",
1368                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1369         seq_printf(m, "HW control enabled: %s\n",
1370                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1371         seq_printf(m, "SW control enabled: %s\n",
1372                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1373                           GEN6_RP_MEDIA_SW_MODE));
1374         seq_printf(m, "RC1e Enabled: %s\n",
1375                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1376         seq_printf(m, "RC6 Enabled: %s\n",
1377                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1378         seq_printf(m, "Deep RC6 Enabled: %s\n",
1379                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1380         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1381                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1382         seq_puts(m, "Current RC state: ");
1383         switch (gt_core_status & GEN6_RCn_MASK) {
1384         case GEN6_RC0:
1385                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1386                         seq_puts(m, "Core Power Down\n");
1387                 else
1388                         seq_puts(m, "on\n");
1389                 break;
1390         case GEN6_RC3:
1391                 seq_puts(m, "RC3\n");
1392                 break;
1393         case GEN6_RC6:
1394                 seq_puts(m, "RC6\n");
1395                 break;
1396         case GEN6_RC7:
1397                 seq_puts(m, "RC7\n");
1398                 break;
1399         default:
1400                 seq_puts(m, "Unknown\n");
1401                 break;
1402         }
1403
1404         seq_printf(m, "Core Power Down: %s\n",
1405                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1406
1407         /* Not exactly sure what this is */
1408         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1409                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1410         seq_printf(m, "RC6 residency since boot: %u\n",
1411                    I915_READ(GEN6_GT_GFX_RC6));
1412         seq_printf(m, "RC6+ residency since boot: %u\n",
1413                    I915_READ(GEN6_GT_GFX_RC6p));
1414         seq_printf(m, "RC6++ residency since boot: %u\n",
1415                    I915_READ(GEN6_GT_GFX_RC6pp));
1416
1417         seq_printf(m, "RC6   voltage: %dmV\n",
1418                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1419         seq_printf(m, "RC6+  voltage: %dmV\n",
1420                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1421         seq_printf(m, "RC6++ voltage: %dmV\n",
1422                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1423         return 0;
1424 }
1425
1426 static int i915_drpc_info(struct seq_file *m, void *unused)
1427 {
1428         struct drm_info_node *node = m->private;
1429         struct drm_device *dev = node->minor->dev;
1430
1431         if (IS_VALLEYVIEW(dev))
1432                 return vlv_drpc_info(m);
1433         else if (IS_GEN6(dev) || IS_GEN7(dev))
1434                 return gen6_drpc_info(m);
1435         else
1436                 return ironlake_drpc_info(m);
1437 }
1438
1439 static int i915_fbc_status(struct seq_file *m, void *unused)
1440 {
1441         struct drm_info_node *node = m->private;
1442         struct drm_device *dev = node->minor->dev;
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444
1445         if (!HAS_FBC(dev)) {
1446                 seq_puts(m, "FBC unsupported on this chipset\n");
1447                 return 0;
1448         }
1449
1450         intel_runtime_pm_get(dev_priv);
1451
1452         if (intel_fbc_enabled(dev)) {
1453                 seq_puts(m, "FBC enabled\n");
1454         } else {
1455                 seq_puts(m, "FBC disabled: ");
1456                 switch (dev_priv->fbc.no_fbc_reason) {
1457                 case FBC_OK:
1458                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1459                         break;
1460                 case FBC_UNSUPPORTED:
1461                         seq_puts(m, "unsupported by this chipset");
1462                         break;
1463                 case FBC_NO_OUTPUT:
1464                         seq_puts(m, "no outputs");
1465                         break;
1466                 case FBC_STOLEN_TOO_SMALL:
1467                         seq_puts(m, "not enough stolen memory");
1468                         break;
1469                 case FBC_UNSUPPORTED_MODE:
1470                         seq_puts(m, "mode not supported");
1471                         break;
1472                 case FBC_MODE_TOO_LARGE:
1473                         seq_puts(m, "mode too large");
1474                         break;
1475                 case FBC_BAD_PLANE:
1476                         seq_puts(m, "FBC unsupported on plane");
1477                         break;
1478                 case FBC_NOT_TILED:
1479                         seq_puts(m, "scanout buffer not tiled");
1480                         break;
1481                 case FBC_MULTIPLE_PIPES:
1482                         seq_puts(m, "multiple pipes are enabled");
1483                         break;
1484                 case FBC_MODULE_PARAM:
1485                         seq_puts(m, "disabled per module param (default off)");
1486                         break;
1487                 case FBC_CHIP_DEFAULT:
1488                         seq_puts(m, "disabled per chip default");
1489                         break;
1490                 default:
1491                         seq_puts(m, "unknown reason");
1492                 }
1493                 seq_putc(m, '\n');
1494         }
1495
1496         intel_runtime_pm_put(dev_priv);
1497
1498         return 0;
1499 }
1500
1501 static int i915_ips_status(struct seq_file *m, void *unused)
1502 {
1503         struct drm_info_node *node = m->private;
1504         struct drm_device *dev = node->minor->dev;
1505         struct drm_i915_private *dev_priv = dev->dev_private;
1506
1507         if (!HAS_IPS(dev)) {
1508                 seq_puts(m, "not supported\n");
1509                 return 0;
1510         }
1511
1512         intel_runtime_pm_get(dev_priv);
1513
1514         if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1515                 seq_puts(m, "enabled\n");
1516         else
1517                 seq_puts(m, "disabled\n");
1518
1519         intel_runtime_pm_put(dev_priv);
1520
1521         return 0;
1522 }
1523
1524 static int i915_sr_status(struct seq_file *m, void *unused)
1525 {
1526         struct drm_info_node *node = m->private;
1527         struct drm_device *dev = node->minor->dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         bool sr_enabled = false;
1530
1531         intel_runtime_pm_get(dev_priv);
1532
1533         if (HAS_PCH_SPLIT(dev))
1534                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1535         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1536                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1537         else if (IS_I915GM(dev))
1538                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1539         else if (IS_PINEVIEW(dev))
1540                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1541
1542         intel_runtime_pm_put(dev_priv);
1543
1544         seq_printf(m, "self-refresh: %s\n",
1545                    sr_enabled ? "enabled" : "disabled");
1546
1547         return 0;
1548 }
1549
1550 static int i915_emon_status(struct seq_file *m, void *unused)
1551 {
1552         struct drm_info_node *node = m->private;
1553         struct drm_device *dev = node->minor->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         unsigned long temp, chipset, gfx;
1556         int ret;
1557
1558         if (!IS_GEN5(dev))
1559                 return -ENODEV;
1560
1561         ret = mutex_lock_interruptible(&dev->struct_mutex);
1562         if (ret)
1563                 return ret;
1564
1565         temp = i915_mch_val(dev_priv);
1566         chipset = i915_chipset_val(dev_priv);
1567         gfx = i915_gfx_val(dev_priv);
1568         mutex_unlock(&dev->struct_mutex);
1569
1570         seq_printf(m, "GMCH temp: %ld\n", temp);
1571         seq_printf(m, "Chipset power: %ld\n", chipset);
1572         seq_printf(m, "GFX power: %ld\n", gfx);
1573         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1574
1575         return 0;
1576 }
1577
1578 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1579 {
1580         struct drm_info_node *node = m->private;
1581         struct drm_device *dev = node->minor->dev;
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         int ret = 0;
1584         int gpu_freq, ia_freq;
1585
1586         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1587                 seq_puts(m, "unsupported on this chipset\n");
1588                 return 0;
1589         }
1590
1591         intel_runtime_pm_get(dev_priv);
1592
1593         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1594
1595         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1596         if (ret)
1597                 goto out;
1598
1599         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1600
1601         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1602              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1603              gpu_freq++) {
1604                 ia_freq = gpu_freq;
1605                 sandybridge_pcode_read(dev_priv,
1606                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1607                                        &ia_freq);
1608                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1609                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1610                            ((ia_freq >> 0) & 0xff) * 100,
1611                            ((ia_freq >> 8) & 0xff) * 100);
1612         }
1613
1614         mutex_unlock(&dev_priv->rps.hw_lock);
1615
1616 out:
1617         intel_runtime_pm_put(dev_priv);
1618         return ret;
1619 }
1620
1621 static int i915_gfxec(struct seq_file *m, void *unused)
1622 {
1623         struct drm_info_node *node = m->private;
1624         struct drm_device *dev = node->minor->dev;
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         int ret;
1627
1628         ret = mutex_lock_interruptible(&dev->struct_mutex);
1629         if (ret)
1630                 return ret;
1631         intel_runtime_pm_get(dev_priv);
1632
1633         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1634         intel_runtime_pm_put(dev_priv);
1635
1636         mutex_unlock(&dev->struct_mutex);
1637
1638         return 0;
1639 }
1640
1641 static int i915_opregion(struct seq_file *m, void *unused)
1642 {
1643         struct drm_info_node *node = m->private;
1644         struct drm_device *dev = node->minor->dev;
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         struct intel_opregion *opregion = &dev_priv->opregion;
1647         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1648         int ret;
1649
1650         if (data == NULL)
1651                 return -ENOMEM;
1652
1653         ret = mutex_lock_interruptible(&dev->struct_mutex);
1654         if (ret)
1655                 goto out;
1656
1657         if (opregion->header) {
1658                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1659                 seq_write(m, data, OPREGION_SIZE);
1660         }
1661
1662         mutex_unlock(&dev->struct_mutex);
1663
1664 out:
1665         kfree(data);
1666         return 0;
1667 }
1668
1669 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1670 {
1671         struct drm_info_node *node = m->private;
1672         struct drm_device *dev = node->minor->dev;
1673         struct intel_fbdev *ifbdev = NULL;
1674         struct intel_framebuffer *fb;
1675
1676 #ifdef CONFIG_DRM_I915_FBDEV
1677         struct drm_i915_private *dev_priv = dev->dev_private;
1678
1679         ifbdev = dev_priv->fbdev;
1680         fb = to_intel_framebuffer(ifbdev->helper.fb);
1681
1682         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1683                    fb->base.width,
1684                    fb->base.height,
1685                    fb->base.depth,
1686                    fb->base.bits_per_pixel,
1687                    atomic_read(&fb->base.refcount.refcount));
1688         describe_obj(m, fb->obj);
1689         seq_putc(m, '\n');
1690 #endif
1691
1692         mutex_lock(&dev->mode_config.fb_lock);
1693         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1694                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1695                         continue;
1696
1697                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1698                            fb->base.width,
1699                            fb->base.height,
1700                            fb->base.depth,
1701                            fb->base.bits_per_pixel,
1702                            atomic_read(&fb->base.refcount.refcount));
1703                 describe_obj(m, fb->obj);
1704                 seq_putc(m, '\n');
1705         }
1706         mutex_unlock(&dev->mode_config.fb_lock);
1707
1708         return 0;
1709 }
1710
1711 static int i915_context_status(struct seq_file *m, void *unused)
1712 {
1713         struct drm_info_node *node = m->private;
1714         struct drm_device *dev = node->minor->dev;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716         struct intel_engine_cs *ring;
1717         struct intel_context *ctx;
1718         int ret, i;
1719
1720         ret = mutex_lock_interruptible(&dev->struct_mutex);
1721         if (ret)
1722                 return ret;
1723
1724         if (dev_priv->ips.pwrctx) {
1725                 seq_puts(m, "power context ");
1726                 describe_obj(m, dev_priv->ips.pwrctx);
1727                 seq_putc(m, '\n');
1728         }
1729
1730         if (dev_priv->ips.renderctx) {
1731                 seq_puts(m, "render context ");
1732                 describe_obj(m, dev_priv->ips.renderctx);
1733                 seq_putc(m, '\n');
1734         }
1735
1736         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1737                 if (ctx->obj == NULL)
1738                         continue;
1739
1740                 seq_puts(m, "HW context ");
1741                 describe_ctx(m, ctx);
1742                 for_each_ring(ring, dev_priv, i)
1743                         if (ring->default_context == ctx)
1744                                 seq_printf(m, "(default context %s) ", ring->name);
1745
1746                 describe_obj(m, ctx->obj);
1747                 seq_putc(m, '\n');
1748         }
1749
1750         mutex_unlock(&dev->struct_mutex);
1751
1752         return 0;
1753 }
1754
1755 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1756 {
1757         struct drm_info_node *node = m->private;
1758         struct drm_device *dev = node->minor->dev;
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1761
1762         spin_lock_irq(&dev_priv->uncore.lock);
1763         if (IS_VALLEYVIEW(dev)) {
1764                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1765                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1766         } else
1767                 forcewake_count = dev_priv->uncore.forcewake_count;
1768         spin_unlock_irq(&dev_priv->uncore.lock);
1769
1770         if (IS_VALLEYVIEW(dev)) {
1771                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1772                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1773         } else
1774                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1775
1776         return 0;
1777 }
1778
1779 static const char *swizzle_string(unsigned swizzle)
1780 {
1781         switch (swizzle) {
1782         case I915_BIT_6_SWIZZLE_NONE:
1783                 return "none";
1784         case I915_BIT_6_SWIZZLE_9:
1785                 return "bit9";
1786         case I915_BIT_6_SWIZZLE_9_10:
1787                 return "bit9/bit10";
1788         case I915_BIT_6_SWIZZLE_9_11:
1789                 return "bit9/bit11";
1790         case I915_BIT_6_SWIZZLE_9_10_11:
1791                 return "bit9/bit10/bit11";
1792         case I915_BIT_6_SWIZZLE_9_17:
1793                 return "bit9/bit17";
1794         case I915_BIT_6_SWIZZLE_9_10_17:
1795                 return "bit9/bit10/bit17";
1796         case I915_BIT_6_SWIZZLE_UNKNOWN:
1797                 return "unknown";
1798         }
1799
1800         return "bug";
1801 }
1802
1803 static int i915_swizzle_info(struct seq_file *m, void *data)
1804 {
1805         struct drm_info_node *node = m->private;
1806         struct drm_device *dev = node->minor->dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808         int ret;
1809
1810         ret = mutex_lock_interruptible(&dev->struct_mutex);
1811         if (ret)
1812                 return ret;
1813         intel_runtime_pm_get(dev_priv);
1814
1815         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1816                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1817         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1818                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1819
1820         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1821                 seq_printf(m, "DDC = 0x%08x\n",
1822                            I915_READ(DCC));
1823                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1824                            I915_READ16(C0DRB3));
1825                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1826                            I915_READ16(C1DRB3));
1827         } else if (INTEL_INFO(dev)->gen >= 6) {
1828                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1829                            I915_READ(MAD_DIMM_C0));
1830                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1831                            I915_READ(MAD_DIMM_C1));
1832                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1833                            I915_READ(MAD_DIMM_C2));
1834                 seq_printf(m, "TILECTL = 0x%08x\n",
1835                            I915_READ(TILECTL));
1836                 if (IS_GEN8(dev))
1837                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1838                                    I915_READ(GAMTARBMODE));
1839                 else
1840                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1841                                    I915_READ(ARB_MODE));
1842                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1843                            I915_READ(DISP_ARB_CTL));
1844         }
1845         intel_runtime_pm_put(dev_priv);
1846         mutex_unlock(&dev->struct_mutex);
1847
1848         return 0;
1849 }
1850
1851 static int per_file_ctx(int id, void *ptr, void *data)
1852 {
1853         struct intel_context *ctx = ptr;
1854         struct seq_file *m = data;
1855         struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1856
1857         if (i915_gem_context_is_default(ctx))
1858                 seq_puts(m, "  default context:\n");
1859         else
1860                 seq_printf(m, "  context %d:\n", ctx->id);
1861         ppgtt->debug_dump(ppgtt, m);
1862
1863         return 0;
1864 }
1865
1866 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1867 {
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_engine_cs *ring;
1870         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1871         int unused, i;
1872
1873         if (!ppgtt)
1874                 return;
1875
1876         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1877         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1878         for_each_ring(ring, dev_priv, unused) {
1879                 seq_printf(m, "%s\n", ring->name);
1880                 for (i = 0; i < 4; i++) {
1881                         u32 offset = 0x270 + i * 8;
1882                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1883                         pdp <<= 32;
1884                         pdp |= I915_READ(ring->mmio_base + offset);
1885                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1886                 }
1887         }
1888 }
1889
1890 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1891 {
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         struct intel_engine_cs *ring;
1894         struct drm_file *file;
1895         int i;
1896
1897         if (INTEL_INFO(dev)->gen == 6)
1898                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1899
1900         for_each_ring(ring, dev_priv, i) {
1901                 seq_printf(m, "%s\n", ring->name);
1902                 if (INTEL_INFO(dev)->gen == 7)
1903                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1904                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1905                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1906                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1907         }
1908         if (dev_priv->mm.aliasing_ppgtt) {
1909                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1910
1911                 seq_puts(m, "aliasing PPGTT:\n");
1912                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1913
1914                 ppgtt->debug_dump(ppgtt, m);
1915         } else
1916                 return;
1917
1918         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1919                 struct drm_i915_file_private *file_priv = file->driver_priv;
1920
1921                 seq_printf(m, "proc: %s\n",
1922                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
1923                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1924         }
1925         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1926 }
1927
1928 static int i915_ppgtt_info(struct seq_file *m, void *data)
1929 {
1930         struct drm_info_node *node = m->private;
1931         struct drm_device *dev = node->minor->dev;
1932         struct drm_i915_private *dev_priv = dev->dev_private;
1933
1934         int ret = mutex_lock_interruptible(&dev->struct_mutex);
1935         if (ret)
1936                 return ret;
1937         intel_runtime_pm_get(dev_priv);
1938
1939         if (INTEL_INFO(dev)->gen >= 8)
1940                 gen8_ppgtt_info(m, dev);
1941         else if (INTEL_INFO(dev)->gen >= 6)
1942                 gen6_ppgtt_info(m, dev);
1943
1944         intel_runtime_pm_put(dev_priv);
1945         mutex_unlock(&dev->struct_mutex);
1946
1947         return 0;
1948 }
1949
1950 static int i915_llc(struct seq_file *m, void *data)
1951 {
1952         struct drm_info_node *node = m->private;
1953         struct drm_device *dev = node->minor->dev;
1954         struct drm_i915_private *dev_priv = dev->dev_private;
1955
1956         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1957         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1958         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1959
1960         return 0;
1961 }
1962
1963 static int i915_edp_psr_status(struct seq_file *m, void *data)
1964 {
1965         struct drm_info_node *node = m->private;
1966         struct drm_device *dev = node->minor->dev;
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         u32 psrperf = 0;
1969         bool enabled = false;
1970
1971         intel_runtime_pm_get(dev_priv);
1972
1973         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1974         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1975
1976         enabled = HAS_PSR(dev) &&
1977                 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1978         seq_printf(m, "Enabled: %s\n", yesno(enabled));
1979
1980         if (HAS_PSR(dev))
1981                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1982                         EDP_PSR_PERF_CNT_MASK;
1983         seq_printf(m, "Performance_Counter: %u\n", psrperf);
1984
1985         intel_runtime_pm_put(dev_priv);
1986         return 0;
1987 }
1988
1989 static int i915_sink_crc(struct seq_file *m, void *data)
1990 {
1991         struct drm_info_node *node = m->private;
1992         struct drm_device *dev = node->minor->dev;
1993         struct intel_encoder *encoder;
1994         struct intel_connector *connector;
1995         struct intel_dp *intel_dp = NULL;
1996         int ret;
1997         u8 crc[6];
1998
1999         drm_modeset_lock_all(dev);
2000         list_for_each_entry(connector, &dev->mode_config.connector_list,
2001                             base.head) {
2002
2003                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2004                         continue;
2005
2006                 if (!connector->base.encoder)
2007                         continue;
2008
2009                 encoder = to_intel_encoder(connector->base.encoder);
2010                 if (encoder->type != INTEL_OUTPUT_EDP)
2011                         continue;
2012
2013                 intel_dp = enc_to_intel_dp(&encoder->base);
2014
2015                 ret = intel_dp_sink_crc(intel_dp, crc);
2016                 if (ret)
2017                         goto out;
2018
2019                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2020                            crc[0], crc[1], crc[2],
2021                            crc[3], crc[4], crc[5]);
2022                 goto out;
2023         }
2024         ret = -ENODEV;
2025 out:
2026         drm_modeset_unlock_all(dev);
2027         return ret;
2028 }
2029
2030 static int i915_energy_uJ(struct seq_file *m, void *data)
2031 {
2032         struct drm_info_node *node = m->private;
2033         struct drm_device *dev = node->minor->dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         u64 power;
2036         u32 units;
2037
2038         if (INTEL_INFO(dev)->gen < 6)
2039                 return -ENODEV;
2040
2041         intel_runtime_pm_get(dev_priv);
2042
2043         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2044         power = (power & 0x1f00) >> 8;
2045         units = 1000000 / (1 << power); /* convert to uJ */
2046         power = I915_READ(MCH_SECP_NRG_STTS);
2047         power *= units;
2048
2049         intel_runtime_pm_put(dev_priv);
2050
2051         seq_printf(m, "%llu", (long long unsigned)power);
2052
2053         return 0;
2054 }
2055
2056 static int i915_pc8_status(struct seq_file *m, void *unused)
2057 {
2058         struct drm_info_node *node = m->private;
2059         struct drm_device *dev = node->minor->dev;
2060         struct drm_i915_private *dev_priv = dev->dev_private;
2061
2062         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2063                 seq_puts(m, "not supported\n");
2064                 return 0;
2065         }
2066
2067         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2068         seq_printf(m, "IRQs disabled: %s\n",
2069                    yesno(dev_priv->pm.irqs_disabled));
2070
2071         return 0;
2072 }
2073
2074 static const char *power_domain_str(enum intel_display_power_domain domain)
2075 {
2076         switch (domain) {
2077         case POWER_DOMAIN_PIPE_A:
2078                 return "PIPE_A";
2079         case POWER_DOMAIN_PIPE_B:
2080                 return "PIPE_B";
2081         case POWER_DOMAIN_PIPE_C:
2082                 return "PIPE_C";
2083         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2084                 return "PIPE_A_PANEL_FITTER";
2085         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2086                 return "PIPE_B_PANEL_FITTER";
2087         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2088                 return "PIPE_C_PANEL_FITTER";
2089         case POWER_DOMAIN_TRANSCODER_A:
2090                 return "TRANSCODER_A";
2091         case POWER_DOMAIN_TRANSCODER_B:
2092                 return "TRANSCODER_B";
2093         case POWER_DOMAIN_TRANSCODER_C:
2094                 return "TRANSCODER_C";
2095         case POWER_DOMAIN_TRANSCODER_EDP:
2096                 return "TRANSCODER_EDP";
2097         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2098                 return "PORT_DDI_A_2_LANES";
2099         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2100                 return "PORT_DDI_A_4_LANES";
2101         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2102                 return "PORT_DDI_B_2_LANES";
2103         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2104                 return "PORT_DDI_B_4_LANES";
2105         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2106                 return "PORT_DDI_C_2_LANES";
2107         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2108                 return "PORT_DDI_C_4_LANES";
2109         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2110                 return "PORT_DDI_D_2_LANES";
2111         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2112                 return "PORT_DDI_D_4_LANES";
2113         case POWER_DOMAIN_PORT_DSI:
2114                 return "PORT_DSI";
2115         case POWER_DOMAIN_PORT_CRT:
2116                 return "PORT_CRT";
2117         case POWER_DOMAIN_PORT_OTHER:
2118                 return "PORT_OTHER";
2119         case POWER_DOMAIN_VGA:
2120                 return "VGA";
2121         case POWER_DOMAIN_AUDIO:
2122                 return "AUDIO";
2123         case POWER_DOMAIN_INIT:
2124                 return "INIT";
2125         default:
2126                 WARN_ON(1);
2127                 return "?";
2128         }
2129 }
2130
2131 static int i915_power_domain_info(struct seq_file *m, void *unused)
2132 {
2133         struct drm_info_node *node = m->private;
2134         struct drm_device *dev = node->minor->dev;
2135         struct drm_i915_private *dev_priv = dev->dev_private;
2136         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2137         int i;
2138
2139         mutex_lock(&power_domains->lock);
2140
2141         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2142         for (i = 0; i < power_domains->power_well_count; i++) {
2143                 struct i915_power_well *power_well;
2144                 enum intel_display_power_domain power_domain;
2145
2146                 power_well = &power_domains->power_wells[i];
2147                 seq_printf(m, "%-25s %d\n", power_well->name,
2148                            power_well->count);
2149
2150                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2151                      power_domain++) {
2152                         if (!(BIT(power_domain) & power_well->domains))
2153                                 continue;
2154
2155                         seq_printf(m, "  %-23s %d\n",
2156                                  power_domain_str(power_domain),
2157                                  power_domains->domain_use_count[power_domain]);
2158                 }
2159         }
2160
2161         mutex_unlock(&power_domains->lock);
2162
2163         return 0;
2164 }
2165
2166 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2167                                  struct drm_display_mode *mode)
2168 {
2169         int i;
2170
2171         for (i = 0; i < tabs; i++)
2172                 seq_putc(m, '\t');
2173
2174         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2175                    mode->base.id, mode->name,
2176                    mode->vrefresh, mode->clock,
2177                    mode->hdisplay, mode->hsync_start,
2178                    mode->hsync_end, mode->htotal,
2179                    mode->vdisplay, mode->vsync_start,
2180                    mode->vsync_end, mode->vtotal,
2181                    mode->type, mode->flags);
2182 }
2183
2184 static void intel_encoder_info(struct seq_file *m,
2185                                struct intel_crtc *intel_crtc,
2186                                struct intel_encoder *intel_encoder)
2187 {
2188         struct drm_info_node *node = m->private;
2189         struct drm_device *dev = node->minor->dev;
2190         struct drm_crtc *crtc = &intel_crtc->base;
2191         struct intel_connector *intel_connector;
2192         struct drm_encoder *encoder;
2193
2194         encoder = &intel_encoder->base;
2195         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2196                    encoder->base.id, encoder->name);
2197         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2198                 struct drm_connector *connector = &intel_connector->base;
2199                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2200                            connector->base.id,
2201                            connector->name,
2202                            drm_get_connector_status_name(connector->status));
2203                 if (connector->status == connector_status_connected) {
2204                         struct drm_display_mode *mode = &crtc->mode;
2205                         seq_printf(m, ", mode:\n");
2206                         intel_seq_print_mode(m, 2, mode);
2207                 } else {
2208                         seq_putc(m, '\n');
2209                 }
2210         }
2211 }
2212
2213 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2214 {
2215         struct drm_info_node *node = m->private;
2216         struct drm_device *dev = node->minor->dev;
2217         struct drm_crtc *crtc = &intel_crtc->base;
2218         struct intel_encoder *intel_encoder;
2219
2220         seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2221                    crtc->primary->fb->base.id, crtc->x, crtc->y,
2222                    crtc->primary->fb->width, crtc->primary->fb->height);
2223         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2224                 intel_encoder_info(m, intel_crtc, intel_encoder);
2225 }
2226
2227 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2228 {
2229         struct drm_display_mode *mode = panel->fixed_mode;
2230
2231         seq_printf(m, "\tfixed mode:\n");
2232         intel_seq_print_mode(m, 2, mode);
2233 }
2234
2235 static void intel_dp_info(struct seq_file *m,
2236                           struct intel_connector *intel_connector)
2237 {
2238         struct intel_encoder *intel_encoder = intel_connector->encoder;
2239         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2240
2241         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2242         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2243                    "no");
2244         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2245                 intel_panel_info(m, &intel_connector->panel);
2246 }
2247
2248 static void intel_hdmi_info(struct seq_file *m,
2249                             struct intel_connector *intel_connector)
2250 {
2251         struct intel_encoder *intel_encoder = intel_connector->encoder;
2252         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2253
2254         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2255                    "no");
2256 }
2257
2258 static void intel_lvds_info(struct seq_file *m,
2259                             struct intel_connector *intel_connector)
2260 {
2261         intel_panel_info(m, &intel_connector->panel);
2262 }
2263
2264 static void intel_connector_info(struct seq_file *m,
2265                                  struct drm_connector *connector)
2266 {
2267         struct intel_connector *intel_connector = to_intel_connector(connector);
2268         struct intel_encoder *intel_encoder = intel_connector->encoder;
2269         struct drm_display_mode *mode;
2270
2271         seq_printf(m, "connector %d: type %s, status: %s\n",
2272                    connector->base.id, connector->name,
2273                    drm_get_connector_status_name(connector->status));
2274         if (connector->status == connector_status_connected) {
2275                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2276                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2277                            connector->display_info.width_mm,
2278                            connector->display_info.height_mm);
2279                 seq_printf(m, "\tsubpixel order: %s\n",
2280                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2281                 seq_printf(m, "\tCEA rev: %d\n",
2282                            connector->display_info.cea_rev);
2283         }
2284         if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2285             intel_encoder->type == INTEL_OUTPUT_EDP)
2286                 intel_dp_info(m, intel_connector);
2287         else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2288                 intel_hdmi_info(m, intel_connector);
2289         else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2290                 intel_lvds_info(m, intel_connector);
2291
2292         seq_printf(m, "\tmodes:\n");
2293         list_for_each_entry(mode, &connector->modes, head)
2294                 intel_seq_print_mode(m, 2, mode);
2295 }
2296
2297 static bool cursor_active(struct drm_device *dev, int pipe)
2298 {
2299         struct drm_i915_private *dev_priv = dev->dev_private;
2300         u32 state;
2301
2302         if (IS_845G(dev) || IS_I865G(dev))
2303                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2304         else
2305                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2306
2307         return state;
2308 }
2309
2310 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2311 {
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         u32 pos;
2314
2315         pos = I915_READ(CURPOS(pipe));
2316
2317         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2318         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2319                 *x = -*x;
2320
2321         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2322         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2323                 *y = -*y;
2324
2325         return cursor_active(dev, pipe);
2326 }
2327
2328 static int i915_display_info(struct seq_file *m, void *unused)
2329 {
2330         struct drm_info_node *node = m->private;
2331         struct drm_device *dev = node->minor->dev;
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *crtc;
2334         struct drm_connector *connector;
2335
2336         intel_runtime_pm_get(dev_priv);
2337         drm_modeset_lock_all(dev);
2338         seq_printf(m, "CRTC info\n");
2339         seq_printf(m, "---------\n");
2340         for_each_intel_crtc(dev, crtc) {
2341                 bool active;
2342                 int x, y;
2343
2344                 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2345                            crtc->base.base.id, pipe_name(crtc->pipe),
2346                            yesno(crtc->active));
2347                 if (crtc->active) {
2348                         intel_crtc_info(m, crtc);
2349
2350                         active = cursor_position(dev, crtc->pipe, &x, &y);
2351                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2352                                    yesno(crtc->cursor_base),
2353                                    x, y, crtc->cursor_addr,
2354                                    yesno(active));
2355                 }
2356
2357                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2358                            yesno(!crtc->cpu_fifo_underrun_disabled),
2359                            yesno(!crtc->pch_fifo_underrun_disabled));
2360         }
2361
2362         seq_printf(m, "\n");
2363         seq_printf(m, "Connector info\n");
2364         seq_printf(m, "--------------\n");
2365         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2366                 intel_connector_info(m, connector);
2367         }
2368         drm_modeset_unlock_all(dev);
2369         intel_runtime_pm_put(dev_priv);
2370
2371         return 0;
2372 }
2373
2374 struct pipe_crc_info {
2375         const char *name;
2376         struct drm_device *dev;
2377         enum pipe pipe;
2378 };
2379
2380 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2381 {
2382         struct pipe_crc_info *info = inode->i_private;
2383         struct drm_i915_private *dev_priv = info->dev->dev_private;
2384         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2385
2386         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2387                 return -ENODEV;
2388
2389         spin_lock_irq(&pipe_crc->lock);
2390
2391         if (pipe_crc->opened) {
2392                 spin_unlock_irq(&pipe_crc->lock);
2393                 return -EBUSY; /* already open */
2394         }
2395
2396         pipe_crc->opened = true;
2397         filep->private_data = inode->i_private;
2398
2399         spin_unlock_irq(&pipe_crc->lock);
2400
2401         return 0;
2402 }
2403
2404 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2405 {
2406         struct pipe_crc_info *info = inode->i_private;
2407         struct drm_i915_private *dev_priv = info->dev->dev_private;
2408         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2409
2410         spin_lock_irq(&pipe_crc->lock);
2411         pipe_crc->opened = false;
2412         spin_unlock_irq(&pipe_crc->lock);
2413
2414         return 0;
2415 }
2416
2417 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2418 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2419 /* account for \'0' */
2420 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2421
2422 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2423 {
2424         assert_spin_locked(&pipe_crc->lock);
2425         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2426                         INTEL_PIPE_CRC_ENTRIES_NR);
2427 }
2428
2429 static ssize_t
2430 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2431                    loff_t *pos)
2432 {
2433         struct pipe_crc_info *info = filep->private_data;
2434         struct drm_device *dev = info->dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2437         char buf[PIPE_CRC_BUFFER_LEN];
2438         int head, tail, n_entries, n;
2439         ssize_t bytes_read;
2440
2441         /*
2442          * Don't allow user space to provide buffers not big enough to hold
2443          * a line of data.
2444          */
2445         if (count < PIPE_CRC_LINE_LEN)
2446                 return -EINVAL;
2447
2448         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2449                 return 0;
2450
2451         /* nothing to read */
2452         spin_lock_irq(&pipe_crc->lock);
2453         while (pipe_crc_data_count(pipe_crc) == 0) {
2454                 int ret;
2455
2456                 if (filep->f_flags & O_NONBLOCK) {
2457                         spin_unlock_irq(&pipe_crc->lock);
2458                         return -EAGAIN;
2459                 }
2460
2461                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2462                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2463                 if (ret) {
2464                         spin_unlock_irq(&pipe_crc->lock);
2465                         return ret;
2466                 }
2467         }
2468
2469         /* We now have one or more entries to read */
2470         head = pipe_crc->head;
2471         tail = pipe_crc->tail;
2472         n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2473                         count / PIPE_CRC_LINE_LEN);
2474         spin_unlock_irq(&pipe_crc->lock);
2475
2476         bytes_read = 0;
2477         n = 0;
2478         do {
2479                 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2480                 int ret;
2481
2482                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2483                                        "%8u %8x %8x %8x %8x %8x\n",
2484                                        entry->frame, entry->crc[0],
2485                                        entry->crc[1], entry->crc[2],
2486                                        entry->crc[3], entry->crc[4]);
2487
2488                 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2489                                    buf, PIPE_CRC_LINE_LEN);
2490                 if (ret == PIPE_CRC_LINE_LEN)
2491                         return -EFAULT;
2492
2493                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2494                 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2495                 n++;
2496         } while (--n_entries);
2497
2498         spin_lock_irq(&pipe_crc->lock);
2499         pipe_crc->tail = tail;
2500         spin_unlock_irq(&pipe_crc->lock);
2501
2502         return bytes_read;
2503 }
2504
2505 static const struct file_operations i915_pipe_crc_fops = {
2506         .owner = THIS_MODULE,
2507         .open = i915_pipe_crc_open,
2508         .read = i915_pipe_crc_read,
2509         .release = i915_pipe_crc_release,
2510 };
2511
2512 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2513         {
2514                 .name = "i915_pipe_A_crc",
2515                 .pipe = PIPE_A,
2516         },
2517         {
2518                 .name = "i915_pipe_B_crc",
2519                 .pipe = PIPE_B,
2520         },
2521         {
2522                 .name = "i915_pipe_C_crc",
2523                 .pipe = PIPE_C,
2524         },
2525 };
2526
2527 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2528                                 enum pipe pipe)
2529 {
2530         struct drm_device *dev = minor->dev;
2531         struct dentry *ent;
2532         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2533
2534         info->dev = dev;
2535         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2536                                   &i915_pipe_crc_fops);
2537         if (!ent)
2538                 return -ENOMEM;
2539
2540         return drm_add_fake_info_node(minor, ent, info);
2541 }
2542
2543 static const char * const pipe_crc_sources[] = {
2544         "none",
2545         "plane1",
2546         "plane2",
2547         "pf",
2548         "pipe",
2549         "TV",
2550         "DP-B",
2551         "DP-C",
2552         "DP-D",
2553         "auto",
2554 };
2555
2556 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2557 {
2558         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2559         return pipe_crc_sources[source];
2560 }
2561
2562 static int display_crc_ctl_show(struct seq_file *m, void *data)
2563 {
2564         struct drm_device *dev = m->private;
2565         struct drm_i915_private *dev_priv = dev->dev_private;
2566         int i;
2567
2568         for (i = 0; i < I915_MAX_PIPES; i++)
2569                 seq_printf(m, "%c %s\n", pipe_name(i),
2570                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2571
2572         return 0;
2573 }
2574
2575 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2576 {
2577         struct drm_device *dev = inode->i_private;
2578
2579         return single_open(file, display_crc_ctl_show, dev);
2580 }
2581
2582 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2583                                  uint32_t *val)
2584 {
2585         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2586                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2587
2588         switch (*source) {
2589         case INTEL_PIPE_CRC_SOURCE_PIPE:
2590                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2591                 break;
2592         case INTEL_PIPE_CRC_SOURCE_NONE:
2593                 *val = 0;
2594                 break;
2595         default:
2596                 return -EINVAL;
2597         }
2598
2599         return 0;
2600 }
2601
2602 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2603                                      enum intel_pipe_crc_source *source)
2604 {
2605         struct intel_encoder *encoder;
2606         struct intel_crtc *crtc;
2607         struct intel_digital_port *dig_port;
2608         int ret = 0;
2609
2610         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2611
2612         drm_modeset_lock_all(dev);
2613         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2614                             base.head) {
2615                 if (!encoder->base.crtc)
2616                         continue;
2617
2618                 crtc = to_intel_crtc(encoder->base.crtc);
2619
2620                 if (crtc->pipe != pipe)
2621                         continue;
2622
2623                 switch (encoder->type) {
2624                 case INTEL_OUTPUT_TVOUT:
2625                         *source = INTEL_PIPE_CRC_SOURCE_TV;
2626                         break;
2627                 case INTEL_OUTPUT_DISPLAYPORT:
2628                 case INTEL_OUTPUT_EDP:
2629                         dig_port = enc_to_dig_port(&encoder->base);
2630                         switch (dig_port->port) {
2631                         case PORT_B:
2632                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2633                                 break;
2634                         case PORT_C:
2635                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2636                                 break;
2637                         case PORT_D:
2638                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2639                                 break;
2640                         default:
2641                                 WARN(1, "nonexisting DP port %c\n",
2642                                      port_name(dig_port->port));
2643                                 break;
2644                         }
2645                         break;
2646                 }
2647         }
2648         drm_modeset_unlock_all(dev);
2649
2650         return ret;
2651 }
2652
2653 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2654                                 enum pipe pipe,
2655                                 enum intel_pipe_crc_source *source,
2656                                 uint32_t *val)
2657 {
2658         struct drm_i915_private *dev_priv = dev->dev_private;
2659         bool need_stable_symbols = false;
2660
2661         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2662                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2663                 if (ret)
2664                         return ret;
2665         }
2666
2667         switch (*source) {
2668         case INTEL_PIPE_CRC_SOURCE_PIPE:
2669                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2670                 break;
2671         case INTEL_PIPE_CRC_SOURCE_DP_B:
2672                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2673                 need_stable_symbols = true;
2674                 break;
2675         case INTEL_PIPE_CRC_SOURCE_DP_C:
2676                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2677                 need_stable_symbols = true;
2678                 break;
2679         case INTEL_PIPE_CRC_SOURCE_NONE:
2680                 *val = 0;
2681                 break;
2682         default:
2683                 return -EINVAL;
2684         }
2685
2686         /*
2687          * When the pipe CRC tap point is after the transcoders we need
2688          * to tweak symbol-level features to produce a deterministic series of
2689          * symbols for a given frame. We need to reset those features only once
2690          * a frame (instead of every nth symbol):
2691          *   - DC-balance: used to ensure a better clock recovery from the data
2692          *     link (SDVO)
2693          *   - DisplayPort scrambling: used for EMI reduction
2694          */
2695         if (need_stable_symbols) {
2696                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2697
2698                 tmp |= DC_BALANCE_RESET_VLV;
2699                 if (pipe == PIPE_A)
2700                         tmp |= PIPE_A_SCRAMBLE_RESET;
2701                 else
2702                         tmp |= PIPE_B_SCRAMBLE_RESET;
2703
2704                 I915_WRITE(PORT_DFT2_G4X, tmp);
2705         }
2706
2707         return 0;
2708 }
2709
2710 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2711                                  enum pipe pipe,
2712                                  enum intel_pipe_crc_source *source,
2713                                  uint32_t *val)
2714 {
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         bool need_stable_symbols = false;
2717
2718         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2719                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2720                 if (ret)
2721                         return ret;
2722         }
2723
2724         switch (*source) {
2725         case INTEL_PIPE_CRC_SOURCE_PIPE:
2726                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2727                 break;
2728         case INTEL_PIPE_CRC_SOURCE_TV:
2729                 if (!SUPPORTS_TV(dev))
2730                         return -EINVAL;
2731                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2732                 break;
2733         case INTEL_PIPE_CRC_SOURCE_DP_B:
2734                 if (!IS_G4X(dev))
2735                         return -EINVAL;
2736                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2737                 need_stable_symbols = true;
2738                 break;
2739         case INTEL_PIPE_CRC_SOURCE_DP_C:
2740                 if (!IS_G4X(dev))
2741                         return -EINVAL;
2742                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2743                 need_stable_symbols = true;
2744                 break;
2745         case INTEL_PIPE_CRC_SOURCE_DP_D:
2746                 if (!IS_G4X(dev))
2747                         return -EINVAL;
2748                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2749                 need_stable_symbols = true;
2750                 break;
2751         case INTEL_PIPE_CRC_SOURCE_NONE:
2752                 *val = 0;
2753                 break;
2754         default:
2755                 return -EINVAL;
2756         }
2757
2758         /*
2759          * When the pipe CRC tap point is after the transcoders we need
2760          * to tweak symbol-level features to produce a deterministic series of
2761          * symbols for a given frame. We need to reset those features only once
2762          * a frame (instead of every nth symbol):
2763          *   - DC-balance: used to ensure a better clock recovery from the data
2764          *     link (SDVO)
2765          *   - DisplayPort scrambling: used for EMI reduction
2766          */
2767         if (need_stable_symbols) {
2768                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2769
2770                 WARN_ON(!IS_G4X(dev));
2771
2772                 I915_WRITE(PORT_DFT_I9XX,
2773                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2774
2775                 if (pipe == PIPE_A)
2776                         tmp |= PIPE_A_SCRAMBLE_RESET;
2777                 else
2778                         tmp |= PIPE_B_SCRAMBLE_RESET;
2779
2780                 I915_WRITE(PORT_DFT2_G4X, tmp);
2781         }
2782
2783         return 0;
2784 }
2785
2786 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2787                                          enum pipe pipe)
2788 {
2789         struct drm_i915_private *dev_priv = dev->dev_private;
2790         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2791
2792         if (pipe == PIPE_A)
2793                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2794         else
2795                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2796         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2797                 tmp &= ~DC_BALANCE_RESET_VLV;
2798         I915_WRITE(PORT_DFT2_G4X, tmp);
2799
2800 }
2801
2802 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2803                                          enum pipe pipe)
2804 {
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2807
2808         if (pipe == PIPE_A)
2809                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2810         else
2811                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2812         I915_WRITE(PORT_DFT2_G4X, tmp);
2813
2814         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2815                 I915_WRITE(PORT_DFT_I9XX,
2816                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2817         }
2818 }
2819
2820 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2821                                 uint32_t *val)
2822 {
2823         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2824                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2825
2826         switch (*source) {
2827         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2828                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2829                 break;
2830         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2831                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2832                 break;
2833         case INTEL_PIPE_CRC_SOURCE_PIPE:
2834                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2835                 break;
2836         case INTEL_PIPE_CRC_SOURCE_NONE:
2837                 *val = 0;
2838                 break;
2839         default:
2840                 return -EINVAL;
2841         }
2842
2843         return 0;
2844 }
2845
2846 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2847                                 uint32_t *val)
2848 {
2849         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2850                 *source = INTEL_PIPE_CRC_SOURCE_PF;
2851
2852         switch (*source) {
2853         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2854                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2855                 break;
2856         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2857                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2858                 break;
2859         case INTEL_PIPE_CRC_SOURCE_PF:
2860                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2861                 break;
2862         case INTEL_PIPE_CRC_SOURCE_NONE:
2863                 *val = 0;
2864                 break;
2865         default:
2866                 return -EINVAL;
2867         }
2868
2869         return 0;
2870 }
2871
2872 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2873                                enum intel_pipe_crc_source source)
2874 {
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2877         u32 val = 0; /* shut up gcc */
2878         int ret;
2879
2880         if (pipe_crc->source == source)
2881                 return 0;
2882
2883         /* forbid changing the source without going back to 'none' */
2884         if (pipe_crc->source && source)
2885                 return -EINVAL;
2886
2887         if (IS_GEN2(dev))
2888                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2889         else if (INTEL_INFO(dev)->gen < 5)
2890                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2891         else if (IS_VALLEYVIEW(dev))
2892                 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2893         else if (IS_GEN5(dev) || IS_GEN6(dev))
2894                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2895         else
2896                 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2897
2898         if (ret != 0)
2899                 return ret;
2900
2901         /* none -> real source transition */
2902         if (source) {
2903                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2904                                  pipe_name(pipe), pipe_crc_source_name(source));
2905
2906                 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2907                                             INTEL_PIPE_CRC_ENTRIES_NR,
2908                                             GFP_KERNEL);
2909                 if (!pipe_crc->entries)
2910                         return -ENOMEM;
2911
2912                 spin_lock_irq(&pipe_crc->lock);
2913                 pipe_crc->head = 0;
2914                 pipe_crc->tail = 0;
2915                 spin_unlock_irq(&pipe_crc->lock);
2916         }
2917
2918         pipe_crc->source = source;
2919
2920         I915_WRITE(PIPE_CRC_CTL(pipe), val);
2921         POSTING_READ(PIPE_CRC_CTL(pipe));
2922
2923         /* real source -> none transition */
2924         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2925                 struct intel_pipe_crc_entry *entries;
2926
2927                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2928                                  pipe_name(pipe));
2929
2930                 intel_wait_for_vblank(dev, pipe);
2931
2932                 spin_lock_irq(&pipe_crc->lock);
2933                 entries = pipe_crc->entries;
2934                 pipe_crc->entries = NULL;
2935                 spin_unlock_irq(&pipe_crc->lock);
2936
2937                 kfree(entries);
2938
2939                 if (IS_G4X(dev))
2940                         g4x_undo_pipe_scramble_reset(dev, pipe);
2941                 else if (IS_VALLEYVIEW(dev))
2942                         vlv_undo_pipe_scramble_reset(dev, pipe);
2943         }
2944
2945         return 0;
2946 }
2947
2948 /*
2949  * Parse pipe CRC command strings:
2950  *   command: wsp* object wsp+ name wsp+ source wsp*
2951  *   object: 'pipe'
2952  *   name: (A | B | C)
2953  *   source: (none | plane1 | plane2 | pf)
2954  *   wsp: (#0x20 | #0x9 | #0xA)+
2955  *
2956  * eg.:
2957  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
2958  *  "pipe A none"    ->  Stop CRC
2959  */
2960 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2961 {
2962         int n_words = 0;
2963
2964         while (*buf) {
2965                 char *end;
2966
2967                 /* skip leading white space */
2968                 buf = skip_spaces(buf);
2969                 if (!*buf)
2970                         break;  /* end of buffer */
2971
2972                 /* find end of word */
2973                 for (end = buf; *end && !isspace(*end); end++)
2974                         ;
2975
2976                 if (n_words == max_words) {
2977                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2978                                          max_words);
2979                         return -EINVAL; /* ran out of words[] before bytes */
2980                 }
2981
2982                 if (*end)
2983                         *end++ = '\0';
2984                 words[n_words++] = buf;
2985                 buf = end;
2986         }
2987
2988         return n_words;
2989 }
2990
2991 enum intel_pipe_crc_object {
2992         PIPE_CRC_OBJECT_PIPE,
2993 };
2994
2995 static const char * const pipe_crc_objects[] = {
2996         "pipe",
2997 };
2998
2999 static int
3000 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3001 {
3002         int i;
3003
3004         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3005                 if (!strcmp(buf, pipe_crc_objects[i])) {
3006                         *o = i;
3007                         return 0;
3008                     }
3009
3010         return -EINVAL;
3011 }
3012
3013 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3014 {
3015         const char name = buf[0];
3016
3017         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3018                 return -EINVAL;
3019
3020         *pipe = name - 'A';
3021
3022         return 0;
3023 }
3024
3025 static int
3026 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3027 {
3028         int i;
3029
3030         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3031                 if (!strcmp(buf, pipe_crc_sources[i])) {
3032                         *s = i;
3033                         return 0;
3034                     }
3035
3036         return -EINVAL;
3037 }
3038
3039 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3040 {
3041 #define N_WORDS 3
3042         int n_words;
3043         char *words[N_WORDS];
3044         enum pipe pipe;
3045         enum intel_pipe_crc_object object;
3046         enum intel_pipe_crc_source source;
3047
3048         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3049         if (n_words != N_WORDS) {
3050                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3051                                  N_WORDS);
3052                 return -EINVAL;
3053         }
3054
3055         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3056                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3057                 return -EINVAL;
3058         }
3059
3060         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3061                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3062                 return -EINVAL;
3063         }
3064
3065         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3066                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3067                 return -EINVAL;
3068         }
3069
3070         return pipe_crc_set_source(dev, pipe, source);
3071 }
3072
3073 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3074                                      size_t len, loff_t *offp)
3075 {
3076         struct seq_file *m = file->private_data;
3077         struct drm_device *dev = m->private;
3078         char *tmpbuf;
3079         int ret;
3080
3081         if (len == 0)
3082                 return 0;
3083
3084         if (len > PAGE_SIZE - 1) {
3085                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3086                                  PAGE_SIZE);
3087                 return -E2BIG;
3088         }
3089
3090         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3091         if (!tmpbuf)
3092                 return -ENOMEM;
3093
3094         if (copy_from_user(tmpbuf, ubuf, len)) {
3095                 ret = -EFAULT;
3096                 goto out;
3097         }
3098         tmpbuf[len] = '\0';
3099
3100         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3101
3102 out:
3103         kfree(tmpbuf);
3104         if (ret < 0)
3105                 return ret;
3106
3107         *offp += len;
3108         return len;
3109 }
3110
3111 static const struct file_operations i915_display_crc_ctl_fops = {
3112         .owner = THIS_MODULE,
3113         .open = display_crc_ctl_open,
3114         .read = seq_read,
3115         .llseek = seq_lseek,
3116         .release = single_release,
3117         .write = display_crc_ctl_write
3118 };
3119
3120 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3121 {
3122         struct drm_device *dev = m->private;
3123         int num_levels = ilk_wm_max_level(dev) + 1;
3124         int level;
3125
3126         drm_modeset_lock_all(dev);
3127
3128         for (level = 0; level < num_levels; level++) {
3129                 unsigned int latency = wm[level];
3130
3131                 /* WM1+ latency values in 0.5us units */
3132                 if (level > 0)
3133                         latency *= 5;
3134
3135                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3136                            level, wm[level],
3137                            latency / 10, latency % 10);
3138         }
3139
3140         drm_modeset_unlock_all(dev);
3141 }
3142
3143 static int pri_wm_latency_show(struct seq_file *m, void *data)
3144 {
3145         struct drm_device *dev = m->private;
3146
3147         wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3148
3149         return 0;
3150 }
3151
3152 static int spr_wm_latency_show(struct seq_file *m, void *data)
3153 {
3154         struct drm_device *dev = m->private;
3155
3156         wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3157
3158         return 0;
3159 }
3160
3161 static int cur_wm_latency_show(struct seq_file *m, void *data)
3162 {
3163         struct drm_device *dev = m->private;
3164
3165         wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3166
3167         return 0;
3168 }
3169
3170 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3171 {
3172         struct drm_device *dev = inode->i_private;
3173
3174         if (!HAS_PCH_SPLIT(dev))
3175                 return -ENODEV;
3176
3177         return single_open(file, pri_wm_latency_show, dev);
3178 }
3179
3180 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3181 {
3182         struct drm_device *dev = inode->i_private;
3183
3184         if (!HAS_PCH_SPLIT(dev))
3185                 return -ENODEV;
3186
3187         return single_open(file, spr_wm_latency_show, dev);
3188 }
3189
3190 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3191 {
3192         struct drm_device *dev = inode->i_private;
3193
3194         if (!HAS_PCH_SPLIT(dev))
3195                 return -ENODEV;
3196
3197         return single_open(file, cur_wm_latency_show, dev);
3198 }
3199
3200 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3201                                 size_t len, loff_t *offp, uint16_t wm[5])
3202 {
3203         struct seq_file *m = file->private_data;
3204         struct drm_device *dev = m->private;
3205         uint16_t new[5] = { 0 };
3206         int num_levels = ilk_wm_max_level(dev) + 1;
3207         int level;
3208         int ret;
3209         char tmp[32];
3210
3211         if (len >= sizeof(tmp))
3212                 return -EINVAL;
3213
3214         if (copy_from_user(tmp, ubuf, len))
3215                 return -EFAULT;
3216
3217         tmp[len] = '\0';
3218
3219         ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3220         if (ret != num_levels)
3221                 return -EINVAL;
3222
3223         drm_modeset_lock_all(dev);
3224
3225         for (level = 0; level < num_levels; level++)
3226                 wm[level] = new[level];
3227
3228         drm_modeset_unlock_all(dev);
3229
3230         return len;
3231 }
3232
3233
3234 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3235                                     size_t len, loff_t *offp)
3236 {
3237         struct seq_file *m = file->private_data;
3238         struct drm_device *dev = m->private;
3239
3240         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3241 }
3242
3243 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3244                                     size_t len, loff_t *offp)
3245 {
3246         struct seq_file *m = file->private_data;
3247         struct drm_device *dev = m->private;
3248
3249         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3250 }
3251
3252 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3253                                     size_t len, loff_t *offp)
3254 {
3255         struct seq_file *m = file->private_data;
3256         struct drm_device *dev = m->private;
3257
3258         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3259 }
3260
3261 static const struct file_operations i915_pri_wm_latency_fops = {
3262         .owner = THIS_MODULE,
3263         .open = pri_wm_latency_open,
3264         .read = seq_read,
3265         .llseek = seq_lseek,
3266         .release = single_release,
3267         .write = pri_wm_latency_write
3268 };
3269
3270 static const struct file_operations i915_spr_wm_latency_fops = {
3271         .owner = THIS_MODULE,
3272         .open = spr_wm_latency_open,
3273         .read = seq_read,
3274         .llseek = seq_lseek,
3275         .release = single_release,
3276         .write = spr_wm_latency_write
3277 };
3278
3279 static const struct file_operations i915_cur_wm_latency_fops = {
3280         .owner = THIS_MODULE,
3281         .open = cur_wm_latency_open,
3282         .read = seq_read,
3283         .llseek = seq_lseek,
3284         .release = single_release,
3285         .write = cur_wm_latency_write
3286 };
3287
3288 static int
3289 i915_wedged_get(void *data, u64 *val)
3290 {
3291         struct drm_device *dev = data;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293
3294         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3295
3296         return 0;
3297 }
3298
3299 static int
3300 i915_wedged_set(void *data, u64 val)
3301 {
3302         struct drm_device *dev = data;
3303         struct drm_i915_private *dev_priv = dev->dev_private;
3304
3305         intel_runtime_pm_get(dev_priv);
3306
3307         i915_handle_error(dev, val,
3308                           "Manually setting wedged to %llu", val);
3309
3310         intel_runtime_pm_put(dev_priv);
3311
3312         return 0;
3313 }
3314
3315 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3316                         i915_wedged_get, i915_wedged_set,
3317                         "%llu\n");
3318
3319 static int
3320 i915_ring_stop_get(void *data, u64 *val)
3321 {
3322         struct drm_device *dev = data;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324
3325         *val = dev_priv->gpu_error.stop_rings;
3326
3327         return 0;
3328 }
3329
3330 static int
3331 i915_ring_stop_set(void *data, u64 val)
3332 {
3333         struct drm_device *dev = data;
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335         int ret;
3336
3337         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3338
3339         ret = mutex_lock_interruptible(&dev->struct_mutex);
3340         if (ret)
3341                 return ret;
3342
3343         dev_priv->gpu_error.stop_rings = val;
3344         mutex_unlock(&dev->struct_mutex);
3345
3346         return 0;
3347 }
3348
3349 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3350                         i915_ring_stop_get, i915_ring_stop_set,
3351                         "0x%08llx\n");
3352
3353 static int
3354 i915_ring_missed_irq_get(void *data, u64 *val)
3355 {
3356         struct drm_device *dev = data;
3357         struct drm_i915_private *dev_priv = dev->dev_private;
3358
3359         *val = dev_priv->gpu_error.missed_irq_rings;
3360         return 0;
3361 }
3362
3363 static int
3364 i915_ring_missed_irq_set(void *data, u64 val)
3365 {
3366         struct drm_device *dev = data;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         int ret;
3369
3370         /* Lock against concurrent debugfs callers */
3371         ret = mutex_lock_interruptible(&dev->struct_mutex);
3372         if (ret)
3373                 return ret;
3374         dev_priv->gpu_error.missed_irq_rings = val;
3375         mutex_unlock(&dev->struct_mutex);
3376
3377         return 0;
3378 }
3379
3380 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3381                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3382                         "0x%08llx\n");
3383
3384 static int
3385 i915_ring_test_irq_get(void *data, u64 *val)
3386 {
3387         struct drm_device *dev = data;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389
3390         *val = dev_priv->gpu_error.test_irq_rings;
3391
3392         return 0;
3393 }
3394
3395 static int
3396 i915_ring_test_irq_set(void *data, u64 val)
3397 {
3398         struct drm_device *dev = data;
3399         struct drm_i915_private *dev_priv = dev->dev_private;
3400         int ret;
3401
3402         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3403
3404         /* Lock against concurrent debugfs callers */
3405         ret = mutex_lock_interruptible(&dev->struct_mutex);
3406         if (ret)
3407                 return ret;
3408
3409         dev_priv->gpu_error.test_irq_rings = val;
3410         mutex_unlock(&dev->struct_mutex);
3411
3412         return 0;
3413 }
3414
3415 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3416                         i915_ring_test_irq_get, i915_ring_test_irq_set,
3417                         "0x%08llx\n");
3418
3419 #define DROP_UNBOUND 0x1
3420 #define DROP_BOUND 0x2
3421 #define DROP_RETIRE 0x4
3422 #define DROP_ACTIVE 0x8
3423 #define DROP_ALL (DROP_UNBOUND | \
3424                   DROP_BOUND | \
3425                   DROP_RETIRE | \
3426                   DROP_ACTIVE)
3427 static int
3428 i915_drop_caches_get(void *data, u64 *val)
3429 {
3430         *val = DROP_ALL;
3431
3432         return 0;
3433 }
3434
3435 static int
3436 i915_drop_caches_set(void *data, u64 val)
3437 {
3438         struct drm_device *dev = data;
3439         struct drm_i915_private *dev_priv = dev->dev_private;
3440         struct drm_i915_gem_object *obj, *next;
3441         struct i915_address_space *vm;
3442         struct i915_vma *vma, *x;
3443         int ret;
3444
3445         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3446
3447         /* No need to check and wait for gpu resets, only libdrm auto-restarts
3448          * on ioctls on -EAGAIN. */
3449         ret = mutex_lock_interruptible(&dev->struct_mutex);
3450         if (ret)
3451                 return ret;
3452
3453         if (val & DROP_ACTIVE) {
3454                 ret = i915_gpu_idle(dev);
3455                 if (ret)
3456                         goto unlock;
3457         }
3458
3459         if (val & (DROP_RETIRE | DROP_ACTIVE))
3460                 i915_gem_retire_requests(dev);
3461
3462         if (val & DROP_BOUND) {
3463                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3464                         list_for_each_entry_safe(vma, x, &vm->inactive_list,
3465                                                  mm_list) {
3466                                 if (vma->pin_count)
3467                                         continue;
3468
3469                                 ret = i915_vma_unbind(vma);
3470                                 if (ret)
3471                                         goto unlock;
3472                         }
3473                 }
3474         }
3475
3476         if (val & DROP_UNBOUND) {
3477                 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3478                                          global_list)
3479                         if (obj->pages_pin_count == 0) {
3480                                 ret = i915_gem_object_put_pages(obj);
3481                                 if (ret)
3482                                         goto unlock;
3483                         }
3484         }
3485
3486 unlock:
3487         mutex_unlock(&dev->struct_mutex);
3488
3489         return ret;
3490 }
3491
3492 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3493                         i915_drop_caches_get, i915_drop_caches_set,
3494                         "0x%08llx\n");
3495
3496 static int
3497 i915_max_freq_get(void *data, u64 *val)
3498 {
3499         struct drm_device *dev = data;
3500         struct drm_i915_private *dev_priv = dev->dev_private;
3501         int ret;
3502
3503         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3504                 return -ENODEV;
3505
3506         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3507
3508         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3509         if (ret)
3510                 return ret;
3511
3512         if (IS_VALLEYVIEW(dev))
3513                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3514         else
3515                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3516         mutex_unlock(&dev_priv->rps.hw_lock);
3517
3518         return 0;
3519 }
3520
3521 static int
3522 i915_max_freq_set(void *data, u64 val)
3523 {
3524         struct drm_device *dev = data;
3525         struct drm_i915_private *dev_priv = dev->dev_private;
3526         u32 rp_state_cap, hw_max, hw_min;
3527         int ret;
3528
3529         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3530                 return -ENODEV;
3531
3532         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3533
3534         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3535
3536         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3537         if (ret)
3538                 return ret;
3539
3540         /*
3541          * Turbo will still be enabled, but won't go above the set value.
3542          */
3543         if (IS_VALLEYVIEW(dev)) {
3544                 val = vlv_freq_opcode(dev_priv, val);
3545
3546                 hw_max = valleyview_rps_max_freq(dev_priv);
3547                 hw_min = valleyview_rps_min_freq(dev_priv);
3548         } else {
3549                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3550
3551                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3552                 hw_max = dev_priv->rps.max_freq;
3553                 hw_min = (rp_state_cap >> 16) & 0xff;
3554         }
3555
3556         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3557                 mutex_unlock(&dev_priv->rps.hw_lock);
3558                 return -EINVAL;
3559         }
3560
3561         dev_priv->rps.max_freq_softlimit = val;
3562
3563         if (IS_VALLEYVIEW(dev))
3564                 valleyview_set_rps(dev, val);
3565         else
3566                 gen6_set_rps(dev, val);
3567
3568         mutex_unlock(&dev_priv->rps.hw_lock);
3569
3570         return 0;
3571 }
3572
3573 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3574                         i915_max_freq_get, i915_max_freq_set,
3575                         "%llu\n");
3576
3577 static int
3578 i915_min_freq_get(void *data, u64 *val)
3579 {
3580         struct drm_device *dev = data;
3581         struct drm_i915_private *dev_priv = dev->dev_private;
3582         int ret;
3583
3584         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3585                 return -ENODEV;
3586
3587         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3588
3589         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3590         if (ret)
3591                 return ret;
3592
3593         if (IS_VALLEYVIEW(dev))
3594                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3595         else
3596                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3597         mutex_unlock(&dev_priv->rps.hw_lock);
3598
3599         return 0;
3600 }
3601
3602 static int
3603 i915_min_freq_set(void *data, u64 val)
3604 {
3605         struct drm_device *dev = data;
3606         struct drm_i915_private *dev_priv = dev->dev_private;
3607         u32 rp_state_cap, hw_max, hw_min;
3608         int ret;
3609
3610         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3611                 return -ENODEV;
3612
3613         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3614
3615         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3616
3617         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3618         if (ret)
3619                 return ret;
3620
3621         /*
3622          * Turbo will still be enabled, but won't go below the set value.
3623          */
3624         if (IS_VALLEYVIEW(dev)) {
3625                 val = vlv_freq_opcode(dev_priv, val);
3626
3627                 hw_max = valleyview_rps_max_freq(dev_priv);
3628                 hw_min = valleyview_rps_min_freq(dev_priv);
3629         } else {
3630                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3631
3632                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3633                 hw_max = dev_priv->rps.max_freq;
3634                 hw_min = (rp_state_cap >> 16) & 0xff;
3635         }
3636
3637         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3638                 mutex_unlock(&dev_priv->rps.hw_lock);
3639                 return -EINVAL;
3640         }
3641
3642         dev_priv->rps.min_freq_softlimit = val;
3643
3644         if (IS_VALLEYVIEW(dev))
3645                 valleyview_set_rps(dev, val);
3646         else
3647                 gen6_set_rps(dev, val);
3648
3649         mutex_unlock(&dev_priv->rps.hw_lock);
3650
3651         return 0;
3652 }
3653
3654 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3655                         i915_min_freq_get, i915_min_freq_set,
3656                         "%llu\n");
3657
3658 static int
3659 i915_cache_sharing_get(void *data, u64 *val)
3660 {
3661         struct drm_device *dev = data;
3662         struct drm_i915_private *dev_priv = dev->dev_private;
3663         u32 snpcr;
3664         int ret;
3665
3666         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3667                 return -ENODEV;
3668
3669         ret = mutex_lock_interruptible(&dev->struct_mutex);
3670         if (ret)
3671                 return ret;
3672         intel_runtime_pm_get(dev_priv);
3673
3674         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3675
3676         intel_runtime_pm_put(dev_priv);
3677         mutex_unlock(&dev_priv->dev->struct_mutex);
3678
3679         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3680
3681         return 0;
3682 }
3683
3684 static int
3685 i915_cache_sharing_set(void *data, u64 val)
3686 {
3687         struct drm_device *dev = data;
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         u32 snpcr;
3690
3691         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3692                 return -ENODEV;
3693
3694         if (val > 3)
3695                 return -EINVAL;
3696
3697         intel_runtime_pm_get(dev_priv);
3698         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3699
3700         /* Update the cache sharing policy here as well */
3701         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3702         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3703         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3704         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3705
3706         intel_runtime_pm_put(dev_priv);
3707         return 0;
3708 }
3709
3710 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3711                         i915_cache_sharing_get, i915_cache_sharing_set,
3712                         "%llu\n");
3713
3714 static int i915_forcewake_open(struct inode *inode, struct file *file)
3715 {
3716         struct drm_device *dev = inode->i_private;
3717         struct drm_i915_private *dev_priv = dev->dev_private;
3718
3719         if (INTEL_INFO(dev)->gen < 6)
3720                 return 0;
3721
3722         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3723
3724         return 0;
3725 }
3726
3727 static int i915_forcewake_release(struct inode *inode, struct file *file)
3728 {
3729         struct drm_device *dev = inode->i_private;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731
3732         if (INTEL_INFO(dev)->gen < 6)
3733                 return 0;
3734
3735         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3736
3737         return 0;
3738 }
3739
3740 static const struct file_operations i915_forcewake_fops = {
3741         .owner = THIS_MODULE,
3742         .open = i915_forcewake_open,
3743         .release = i915_forcewake_release,
3744 };
3745
3746 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3747 {
3748         struct drm_device *dev = minor->dev;
3749         struct dentry *ent;
3750
3751         ent = debugfs_create_file("i915_forcewake_user",
3752                                   S_IRUSR,
3753                                   root, dev,
3754                                   &i915_forcewake_fops);
3755         if (!ent)
3756                 return -ENOMEM;
3757
3758         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3759 }
3760
3761 static int i915_debugfs_create(struct dentry *root,
3762                                struct drm_minor *minor,
3763                                const char *name,
3764                                const struct file_operations *fops)
3765 {
3766         struct drm_device *dev = minor->dev;
3767         struct dentry *ent;
3768
3769         ent = debugfs_create_file(name,
3770                                   S_IRUGO | S_IWUSR,
3771                                   root, dev,
3772                                   fops);
3773         if (!ent)
3774                 return -ENOMEM;
3775
3776         return drm_add_fake_info_node(minor, ent, fops);
3777 }
3778
3779 static const struct drm_info_list i915_debugfs_list[] = {
3780         {"i915_capabilities", i915_capabilities, 0},
3781         {"i915_gem_objects", i915_gem_object_info, 0},
3782         {"i915_gem_gtt", i915_gem_gtt_info, 0},
3783         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3784         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3785         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3786         {"i915_gem_stolen", i915_gem_stolen_list_info },
3787         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3788         {"i915_gem_request", i915_gem_request_info, 0},
3789         {"i915_gem_seqno", i915_gem_seqno_info, 0},
3790         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3791         {"i915_gem_interrupt", i915_interrupt_info, 0},
3792         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3793         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3794         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3795         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3796         {"i915_rstdby_delays", i915_rstdby_delays, 0},
3797         {"i915_frequency_info", i915_frequency_info, 0},
3798         {"i915_delayfreq_table", i915_delayfreq_table, 0},
3799         {"i915_inttoext_table", i915_inttoext_table, 0},
3800         {"i915_drpc_info", i915_drpc_info, 0},
3801         {"i915_emon_status", i915_emon_status, 0},
3802         {"i915_ring_freq_table", i915_ring_freq_table, 0},
3803         {"i915_gfxec", i915_gfxec, 0},
3804         {"i915_fbc_status", i915_fbc_status, 0},
3805         {"i915_ips_status", i915_ips_status, 0},
3806         {"i915_sr_status", i915_sr_status, 0},
3807         {"i915_opregion", i915_opregion, 0},
3808         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3809         {"i915_context_status", i915_context_status, 0},
3810         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3811         {"i915_swizzle_info", i915_swizzle_info, 0},
3812         {"i915_ppgtt_info", i915_ppgtt_info, 0},
3813         {"i915_llc", i915_llc, 0},
3814         {"i915_edp_psr_status", i915_edp_psr_status, 0},
3815         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3816         {"i915_energy_uJ", i915_energy_uJ, 0},
3817         {"i915_pc8_status", i915_pc8_status, 0},
3818         {"i915_power_domain_info", i915_power_domain_info, 0},
3819         {"i915_display_info", i915_display_info, 0},
3820 };
3821 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3822
3823 static const struct i915_debugfs_files {
3824         const char *name;
3825         const struct file_operations *fops;
3826 } i915_debugfs_files[] = {
3827         {"i915_wedged", &i915_wedged_fops},
3828         {"i915_max_freq", &i915_max_freq_fops},
3829         {"i915_min_freq", &i915_min_freq_fops},
3830         {"i915_cache_sharing", &i915_cache_sharing_fops},
3831         {"i915_ring_stop", &i915_ring_stop_fops},
3832         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3833         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3834         {"i915_gem_drop_caches", &i915_drop_caches_fops},
3835         {"i915_error_state", &i915_error_state_fops},
3836         {"i915_next_seqno", &i915_next_seqno_fops},
3837         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3838         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3839         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3840         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3841 };
3842
3843 void intel_display_crc_init(struct drm_device *dev)
3844 {
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         enum pipe pipe;
3847
3848         for_each_pipe(pipe) {
3849                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3850
3851                 pipe_crc->opened = false;
3852                 spin_lock_init(&pipe_crc->lock);
3853                 init_waitqueue_head(&pipe_crc->wq);
3854         }
3855 }
3856
3857 int i915_debugfs_init(struct drm_minor *minor)
3858 {
3859         int ret, i;
3860
3861         ret = i915_forcewake_create(minor->debugfs_root, minor);
3862         if (ret)
3863                 return ret;
3864
3865         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3866                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3867                 if (ret)
3868                         return ret;
3869         }
3870
3871         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3872                 ret = i915_debugfs_create(minor->debugfs_root, minor,
3873                                           i915_debugfs_files[i].name,
3874                                           i915_debugfs_files[i].fops);
3875                 if (ret)
3876                         return ret;
3877         }
3878
3879         return drm_debugfs_create_files(i915_debugfs_list,
3880                                         I915_DEBUGFS_ENTRIES,
3881                                         minor->debugfs_root, minor);
3882 }
3883
3884 void i915_debugfs_cleanup(struct drm_minor *minor)
3885 {
3886         int i;
3887
3888         drm_debugfs_remove_files(i915_debugfs_list,
3889                                  I915_DEBUGFS_ENTRIES, minor);
3890
3891         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3892                                  1, minor);
3893
3894         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3895                 struct drm_info_list *info_list =
3896                         (struct drm_info_list *)&i915_pipe_crc_data[i];
3897
3898                 drm_debugfs_remove_files(info_list, 1, minor);
3899         }
3900
3901         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3902                 struct drm_info_list *info_list =
3903                         (struct drm_info_list *) i915_debugfs_files[i].fops;
3904
3905                 drm_debugfs_remove_files(info_list, 1, minor);
3906         }
3907 }