drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_of.h>
  29 #include <drm/i2c/tda998x.h>
  30
  31 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  32
  33 struct tda998x_priv {
  34         struct i2c_client *cec;
  35         struct i2c_client *hdmi;
  36         struct mutex mutex;
  37         u16 rev;
  38         u8 current_page;
  39         int dpms;
  40         bool is_hdmi_sink;
  41         u8 vip_cntrl_0;
  42         u8 vip_cntrl_1;
  43         u8 vip_cntrl_2;
  44         struct tda998x_encoder_params params;
  45
  46         wait_queue_head_t wq_edid;
  47         volatile int wq_edid_wait;
  48         struct drm_encoder *encoder;
  49
  50         struct work_struct detect_work;
  51         struct timer_list edid_delay_timer;
  52         wait_queue_head_t edid_delay_waitq;
  53         bool edid_delay_active;
  54 };
  55
  56 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
  57
  58 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  59  * things we encode the page # in upper bits of the register #.  To read/
  60  * write a given register, we need to make sure CURPAGE register is set
  61  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  62  */
  63
  64 #define REG(page, addr) (((page) << 8) | (addr))
  65 #define REG2ADDR(reg)   ((reg) & 0xff)
  66 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  67
  68 #define REG_CURPAGE               0xff                /* write */
  69
  70
  71 /* Page 00h: General Control */
  72 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  73 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  74 # define MAIN_CNTRL0_SR           (1 << 0)
  75 # define MAIN_CNTRL0_DECS         (1 << 1)
  76 # define MAIN_CNTRL0_DEHS         (1 << 2)
  77 # define MAIN_CNTRL0_CECS         (1 << 3)
  78 # define MAIN_CNTRL0_CEHS         (1 << 4)
  79 # define MAIN_CNTRL0_SCALER       (1 << 7)
  80 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  81 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  82 # define SOFTRESET_AUDIO          (1 << 0)
  83 # define SOFTRESET_I2C_MASTER     (1 << 1)
  84 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  85 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  86 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  87 # define I2C_MASTER_DIS_MM        (1 << 0)
  88 # define I2C_MASTER_DIS_FILT      (1 << 1)
  89 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  90 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  91 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  92 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  93 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  94 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  95 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  96 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  97 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  98 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  99 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 100 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 101 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 102 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 103 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 104 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 105 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 106 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 107 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 108 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 109 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 110 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 111 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 112 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 113 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 114 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 115 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 116 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 117 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 118 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 119 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 120 # define VIP_CNTRL_3_EMB          (1 << 3)
 121 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 122 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 123 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 124 # define VIP_CNTRL_3_EDGE         (1 << 7)
 125 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 126 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 127 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 128 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 129 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 130 # define VIP_CNTRL_4_TST_656      (1 << 6)
 131 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 132 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 133 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 134 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 135 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 136 # define MUX_AP_SELECT_I2S        0x64
 137 # define MUX_AP_SELECT_SPDIF      0x40
 138 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 139 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 140 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 141 # define MAT_CONTRL_MAT_BP        (1 << 2)
 142 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 143 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 144 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 145 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 146 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 147 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 148 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 149 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 150 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 151 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 152 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 153 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 154 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 155 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 156 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 157 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 158 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 159 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 160 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 161 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 162 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 163 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 164 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 165 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 166 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 167 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 168 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 169 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 170 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 171 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 172 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 173 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 174 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 175 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 176 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 177 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 178 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 179 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 180 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 181 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 182 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 183 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 184 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 185 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 186 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 187 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 188 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 189 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 190 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 191 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 192 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 193 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 194 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 195 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 196 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 197 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 198 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 199 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 200 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 201 # define HVF_CNTRL_0_SM           (1 << 7)
 202 # define HVF_CNTRL_0_RWB          (1 << 6)
 203 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 204 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 205 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 206 # define HVF_CNTRL_1_FOR          (1 << 0)
 207 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 208 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 209 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 210 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 211 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 212 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 213 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 214 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 215 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 216 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 217 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 218 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 219 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 220
 221 /* Page 02h: PLL settings */
 222 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 223 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 224 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 225 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 226 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 227 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 228 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 229 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 230 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 231 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 232 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 233 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 234 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 235 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 236 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 237 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 238 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 239 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 240 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 241 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 242 # define AUDIO_DIV_SERCLK_1       0
 243 # define AUDIO_DIV_SERCLK_2       1
 244 # define AUDIO_DIV_SERCLK_4       2
 245 # define AUDIO_DIV_SERCLK_8       3
 246 # define AUDIO_DIV_SERCLK_16      4
 247 # define AUDIO_DIV_SERCLK_32      5
 248 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 249 # define SEL_CLK_SEL_CLK1         (1 << 0)
 250 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 251 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 252 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 253
 254
 255 /* Page 09h: EDID Control */
 256 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 257 /* next 127 successive registers are the EDID block */
 258 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 259 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 260 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 261 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 262 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 263
 264
 265 /* Page 10h: information frames and packets */
 266 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 267 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 268 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 269 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 270 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 271
 272
 273 /* Page 11h: audio settings and content info packets */
 274 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 275 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 276 # define AIP_CNTRL_0_SWAP         (1 << 1)
 277 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 278 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 279 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 280 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 281 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 282 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 283 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 284 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 285 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 286 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 287 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 288 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 289 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 290 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 291 # define CTS_N_K(x)               (((x) & 7) << 0)
 292 # define CTS_N_M(x)               (((x) & 3) << 4)
 293 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 294 # define ENC_CNTRL_RST_ENC        (1 << 0)
 295 # define ENC_CNTRL_RST_SEL        (1 << 1)
 296 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 297 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 298 # define DIP_FLAGS_ACR            (1 << 0)
 299 # define DIP_FLAGS_GC             (1 << 1)
 300 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 301 # define DIP_IF_FLAGS_IF1         (1 << 1)
 302 # define DIP_IF_FLAGS_IF2         (1 << 2)
 303 # define DIP_IF_FLAGS_IF3         (1 << 3)
 304 # define DIP_IF_FLAGS_IF4         (1 << 4)
 305 # define DIP_IF_FLAGS_IF5         (1 << 5)
 306 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 307
 308
 309 /* Page 12h: HDCP and OTP */
 310 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 311 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 312 # define TX4_PD_RAM               (1 << 1)
 313 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 314 # define TX33_HDMI                (1 << 1)
 315
 316
 317 /* Page 13h: Gamut related metadata packets */
 318
 319
 320
 321 /* CEC registers: (not paged)
 322  */
 323 #define REG_CEC_INTSTATUS         0xee                /* read */
 324 # define CEC_INTSTATUS_CEC        (1 << 0)
 325 # define CEC_INTSTATUS_HDMI       (1 << 1)
 326 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 327 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 328 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 329 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 330 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 331 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 332 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 333 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 334 # define CEC_RXSHPDINT_HPD        BIT(1)
 335 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 336 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 337 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 338
 339 #define REG_CEC_ENAMODS           0xff                /* read/write */
 340 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 341 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 342 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 343 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 344 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 345
 346
 347 /* Device versions: */
 348 #define TDA9989N2                 0x0101
 349 #define TDA19989                  0x0201
 350 #define TDA19989N2                0x0202
 351 #define TDA19988                  0x0301
 352
 353 static void
 354 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 355 {
 356         struct i2c_client *client = priv->cec;
 357         u8 buf[] = {addr, val};
 358         int ret;
 359
 360         ret = i2c_master_send(client, buf, sizeof(buf));
 361         if (ret < 0)
 362                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 363 }
 364
 365 static u8
 366 cec_read(struct tda998x_priv *priv, u8 addr)
 367 {
 368         struct i2c_client *client = priv->cec;
 369         u8 val;
 370         int ret;
 371
 372         ret = i2c_master_send(client, &addr, sizeof(addr));
 373         if (ret < 0)
 374                 goto fail;
 375
 376         ret = i2c_master_recv(client, &val, sizeof(val));
 377         if (ret < 0)
 378                 goto fail;
 379
 380         return val;
 381
 382 fail:
 383         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 384         return 0;
 385 }
 386
 387 static int
 388 set_page(struct tda998x_priv *priv, u16 reg)
 389 {
 390         if (REG2PAGE(reg) != priv->current_page) {
 391                 struct i2c_client *client = priv->hdmi;
 392                 u8 buf[] = {
 393                                 REG_CURPAGE, REG2PAGE(reg)
 394                 };
 395                 int ret = i2c_master_send(client, buf, sizeof(buf));
 396                 if (ret < 0) {
 397                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 398                                         reg, ret);
 399                         return ret;
 400                 }
 401
 402                 priv->current_page = REG2PAGE(reg);
 403         }
 404         return 0;
 405 }
 406
 407 static int
 408 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 409 {
 410         struct i2c_client *client = priv->hdmi;
 411         u8 addr = REG2ADDR(reg);
 412         int ret;
 413
 414         mutex_lock(&priv->mutex);
 415         ret = set_page(priv, reg);
 416         if (ret < 0)
 417                 goto out;
 418
 419         ret = i2c_master_send(client, &addr, sizeof(addr));
 420         if (ret < 0)
 421                 goto fail;
 422
 423         ret = i2c_master_recv(client, buf, cnt);
 424         if (ret < 0)
 425                 goto fail;
 426
 427         goto out;
 428
 429 fail:
 430         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 431 out:
 432         mutex_unlock(&priv->mutex);
 433         return ret;
 434 }
 435
 436 static void
 437 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 438 {
 439         struct i2c_client *client = priv->hdmi;
 440         u8 buf[cnt+1];
 441         int ret;
 442
 443         buf[0] = REG2ADDR(reg);
 444         memcpy(&buf[1], p, cnt);
 445
 446         mutex_lock(&priv->mutex);
 447         ret = set_page(priv, reg);
 448         if (ret < 0)
 449                 goto out;
 450
 451         ret = i2c_master_send(client, buf, cnt + 1);
 452         if (ret < 0)
 453                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 454 out:
 455         mutex_unlock(&priv->mutex);
 456 }
 457
 458 static int
 459 reg_read(struct tda998x_priv *priv, u16 reg)
 460 {
 461         u8 val = 0;
 462         int ret;
 463
 464         ret = reg_read_range(priv, reg, &val, sizeof(val));
 465         if (ret < 0)
 466                 return ret;
 467         return val;
 468 }
 469
 470 static void
 471 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 472 {
 473         struct i2c_client *client = priv->hdmi;
 474         u8 buf[] = {REG2ADDR(reg), val};
 475         int ret;
 476
 477         mutex_lock(&priv->mutex);
 478         ret = set_page(priv, reg);
 479         if (ret < 0)
 480                 goto out;
 481
 482         ret = i2c_master_send(client, buf, sizeof(buf));
 483         if (ret < 0)
 484                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 485 out:
 486         mutex_unlock(&priv->mutex);
 487 }
 488
 489 static void
 490 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 491 {
 492         struct i2c_client *client = priv->hdmi;
 493         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 494         int ret;
 495
 496         mutex_lock(&priv->mutex);
 497         ret = set_page(priv, reg);
 498         if (ret < 0)
 499                 goto out;
 500
 501         ret = i2c_master_send(client, buf, sizeof(buf));
 502         if (ret < 0)
 503                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 504 out:
 505         mutex_unlock(&priv->mutex);
 506 }
 507
 508 static void
 509 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 510 {
 511         int old_val;
 512
 513         old_val = reg_read(priv, reg);
 514         if (old_val >= 0)
 515                 reg_write(priv, reg, old_val | val);
 516 }
 517
 518 static void
 519 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 520 {
 521         int old_val;
 522
 523         old_val = reg_read(priv, reg);
 524         if (old_val >= 0)
 525                 reg_write(priv, reg, old_val & ~val);
 526 }
 527
 528 static void
 529 tda998x_reset(struct tda998x_priv *priv)
 530 {
 531         /* reset audio and i2c master: */
 532         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 533         msleep(50);
 534         reg_write(priv, REG_SOFTRESET, 0);
 535         msleep(50);
 536
 537         /* reset transmitter: */
 538         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 539         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 540
 541         /* PLL registers common configuration */
 542         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 543         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 544         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 545         reg_write(priv, REG_SERIALIZER,   0x00);
 546         reg_write(priv, REG_BUFFER_OUT,   0x00);
 547         reg_write(priv, REG_PLL_SCG1,     0x00);
 548         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 549         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 550         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 551         reg_write(priv, REG_PLL_SCGN2,    0x00);
 552         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 553         reg_write(priv, REG_PLL_SCGR2,    0x00);
 554         reg_write(priv, REG_PLL_SCG2,     0x10);
 555
 556         /* Write the default value MUX register */
 557         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 558 }
 559
 560 /*
 561  * The TDA998x has a problem when trying to read the EDID close to a
 562  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 563  * trying to read EDID data.
 564  *
 565  * However, tda998x_encoder_get_modes() may be called at any moment
 566  * after tda998x_encoder_detect() indicates that we are connected, so
 567  * we need to delay probing modes in tda998x_encoder_get_modes() after
 568  * we have seen a HPD inactive->active transition.  This code implements
 569  * that delay.
 570  */
 571 static void tda998x_edid_delay_done(unsigned long data)
 572 {
 573         struct tda998x_priv *priv = (struct tda998x_priv *)data;
 574
 575         priv->edid_delay_active = false;
 576         wake_up(&priv->edid_delay_waitq);
 577         schedule_work(&priv->detect_work);
 578 }
 579
 580 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 581 {
 582         priv->edid_delay_active = true;
 583         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 584 }
 585
 586 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 587 {
 588         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 589 }
 590
 591 /*
 592  * We need to run the KMS hotplug event helper outside of our threaded
 593  * interrupt routine as this can call back into our get_modes method,
 594  * which will want to make use of interrupts.
 595  */
 596 static void tda998x_detect_work(struct work_struct *work)
 597 {
 598         struct tda998x_priv *priv =
 599                 container_of(work, struct tda998x_priv, detect_work);
 600         struct drm_device *dev = priv->encoder->dev;
 601
 602         if (dev)
 603                 drm_kms_helper_hotplug_event(dev);
 604 }
 605
 606 /*
 607  * only 2 interrupts may occur: screen plug/unplug and EDID read
 608  */
 609 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 610 {
 611         struct tda998x_priv *priv = data;
 612         u8 sta, cec, lvl, flag0, flag1, flag2;
 613         bool handled = false;
 614
 615         sta = cec_read(priv, REG_CEC_INTSTATUS);
 616         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 617         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 618         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 619         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 620         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 621         DRM_DEBUG_DRIVER(
 622                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 623                 sta, cec, lvl, flag0, flag1, flag2);
 624
 625         if (cec & CEC_RXSHPDINT_HPD) {
 626                 if (lvl & CEC_RXSHPDLEV_HPD)
 627                         tda998x_edid_delay_start(priv);
 628                 else
 629                         schedule_work(&priv->detect_work);
 630
 631                 handled = true;
 632         }
 633
 634         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 635                 priv->wq_edid_wait = 0;
 636                 wake_up(&priv->wq_edid);
 637                 handled = true;
 638         }
 639
 640         return IRQ_RETVAL(handled);
 641 }
 642
 643 static u8 tda998x_cksum(u8 *buf, size_t bytes)
 644 {
 645         int sum = 0;
 646
 647         while (bytes--)
 648                 sum -= *buf++;
 649         return sum;
 650 }
 651
 652 #define HB(x) (x)
 653 #define PB(x) (HB(2) + 1 + (x))
 654
 655 static void
 656 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 657                  u8 *buf, size_t size)
 658 {
 659         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 660         reg_write_range(priv, addr, buf, size);
 661         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 662 }
 663
 664 static void
 665 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 666 {
 667         u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
 668
 669         memset(buf, 0, sizeof(buf));
 670         buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
 671         buf[HB(1)] = 0x01;
 672         buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
 673         buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
 674         buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
 675         buf[PB(4)] = p->audio_frame[4];
 676         buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
 677
 678         buf[PB(0)] = tda998x_cksum(buf, sizeof(buf));
 679
 680         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
 681                          sizeof(buf));
 682 }
 683
 684 static void
 685 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 686 {
 687         struct hdmi_avi_infoframe frame;
 688         u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 689         ssize_t len;
 690
 691         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 692
 693         frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 694
 695         len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
 696         if (len < 0) {
 697                 dev_err(&priv->hdmi->dev,
 698                         "hdmi_avi_infoframe_pack() failed: %zd\n", len);
 699                 return;
 700         }
 701
 702         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len);
 703 }
 704
 705 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 706 {
 707         if (on) {
 708                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 709                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 710                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 711         } else {
 712                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 713         }
 714 }
 715
 716 static void
 717 tda998x_configure_audio(struct tda998x_priv *priv,
 718                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 719 {
 720         u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 721         u32 n;
 722
 723         /* Enable audio ports */
 724         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 725         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 726
 727         /* Set audio input source */
 728         switch (p->audio_format) {
 729         case AFMT_SPDIF:
 730                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 731                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 732                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 733                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 734                 break;
 735
 736         case AFMT_I2S:
 737                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 738                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 739                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 740                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 741                 break;
 742
 743         default:
 744                 BUG();
 745                 return;
 746         }
 747
 748         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 749         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 750                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 751         reg_write(priv, REG_CTS_N, cts_n);
 752
 753         /*
 754          * Audio input somehow depends on HDMI line rate which is
 755          * related to pixclk. Testing showed that modes with pixclk
 756          * >100MHz need a larger divider while <40MHz need the default.
 757          * There is no detailed info in the datasheet, so we just
 758          * assume 100MHz requires larger divider.
 759          */
 760         adiv = AUDIO_DIV_SERCLK_8;
 761         if (mode->clock > 100000)
 762                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 763
 764         /* S/PDIF asks for a larger divider */
 765         if (p->audio_format == AFMT_SPDIF)
 766                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 767
 768         reg_write(priv, REG_AUDIO_DIV, adiv);
 769
 770         /*
 771          * This is the approximate value of N, which happens to be
 772          * the recommended values for non-coherent clocks.
 773          */
 774         n = 128 * p->audio_sample_rate / 1000;
 775
 776         /* Write the CTS and N values */
 777         buf[0] = 0x44;
 778         buf[1] = 0x42;
 779         buf[2] = 0x01;
 780         buf[3] = n;
 781         buf[4] = n >> 8;
 782         buf[5] = n >> 16;
 783         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 784
 785         /* Set CTS clock reference */
 786         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 787
 788         /* Reset CTS generator */
 789         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 790         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 791
 792         /* Write the channel status */
 793         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 794         buf[1] = 0x00;
 795         buf[2] = IEC958_AES3_CON_FS_NOTID;
 796         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 797                         IEC958_AES4_CON_MAX_WORDLEN_24;
 798         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 799
 800         tda998x_audio_mute(priv, true);
 801         msleep(20);
 802         tda998x_audio_mute(priv, false);
 803
 804         /* Write the audio information packet */
 805         tda998x_write_aif(priv, p);
 806 }
 807
 808 /* DRM encoder functions */
 809
 810 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 811                                        const struct tda998x_encoder_params *p)
 812 {
 813         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 814                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 815                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 816                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 817         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 818                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 819                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 820                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 821         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 822                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 823                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 824                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 825
 826         priv->params = *p;
 827 }
 828
 829 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 830 {
 831         /* we only care about on or off: */
 832         if (mode != DRM_MODE_DPMS_ON)
 833                 mode = DRM_MODE_DPMS_OFF;
 834
 835         if (mode == priv->dpms)
 836                 return;
 837
 838         switch (mode) {
 839         case DRM_MODE_DPMS_ON:
 840                 /* enable video ports, audio will be enabled later */
 841                 reg_write(priv, REG_ENA_VP_0, 0xff);
 842                 reg_write(priv, REG_ENA_VP_1, 0xff);
 843                 reg_write(priv, REG_ENA_VP_2, 0xff);
 844                 /* set muxing after enabling ports: */
 845                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 846                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 847                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 848                 break;
 849         case DRM_MODE_DPMS_OFF:
 850                 /* disable video ports */
 851                 reg_write(priv, REG_ENA_VP_0, 0x00);
 852                 reg_write(priv, REG_ENA_VP_1, 0x00);
 853                 reg_write(priv, REG_ENA_VP_2, 0x00);
 854                 break;
 855         }
 856
 857         priv->dpms = mode;
 858 }
 859
 860 static void
 861 tda998x_encoder_save(struct drm_encoder *encoder)
 862 {
 863         DBG("");
 864 }
 865
 866 static void
 867 tda998x_encoder_restore(struct drm_encoder *encoder)
 868 {
 869         DBG("");
 870 }
 871
 872 static bool
 873 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 874                           const struct drm_display_mode *mode,
 875                           struct drm_display_mode *adjusted_mode)
 876 {
 877         return true;
 878 }
 879
 880 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 881                                       struct drm_display_mode *mode)
 882 {
 883         if (mode->clock > 150000)
 884                 return MODE_CLOCK_HIGH;
 885         if (mode->htotal >= BIT(13))
 886                 return MODE_BAD_HVALUE;
 887         if (mode->vtotal >= BIT(11))
 888                 return MODE_BAD_VVALUE;
 889         return MODE_OK;
 890 }
 891
 892 static void
 893 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 894                          struct drm_display_mode *mode,
 895                          struct drm_display_mode *adjusted_mode)
 896 {
 897         u16 ref_pix, ref_line, n_pix, n_line;
 898         u16 hs_pix_s, hs_pix_e;
 899         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 900         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 901         u16 vwin1_line_s, vwin1_line_e;
 902         u16 vwin2_line_s, vwin2_line_e;
 903         u16 de_pix_s, de_pix_e;
 904         u8 reg, div, rep;
 905
 906         /*
 907          * Internally TDA998x is using ITU-R BT.656 style sync but
 908          * we get VESA style sync. TDA998x is using a reference pixel
 909          * relative to ITU to sync to the input frame and for output
 910          * sync generation. Currently, we are using reference detection
 911          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 912          * which is position of rising VS with coincident rising HS.
 913          *
 914          * Now there is some issues to take care of:
 915          * - HDMI data islands require sync-before-active
 916          * - TDA998x register values must be > 0 to be enabled
 917          * - REFLINE needs an additional offset of +1
 918          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 919          *
 920          * So we add +1 to all horizontal and vertical register values,
 921          * plus an additional +3 for REFPIX as we are using RGB input only.
 922          */
 923         n_pix        = mode->htotal;
 924         n_line       = mode->vtotal;
 925
 926         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 927         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 928         de_pix_e     = mode->htotal;
 929         de_pix_s     = mode->htotal - mode->hdisplay;
 930         ref_pix      = 3 + hs_pix_s;
 931
 932         /*
 933          * Attached LCD controllers may generate broken sync. Allow
 934          * those to adjust the position of the rising VS edge by adding
 935          * HSKEW to ref_pix.
 936          */
 937         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 938                 ref_pix += adjusted_mode->hskew;
 939
 940         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 941                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 942                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 943                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 944                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 945                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 946                 vs1_line_e   = vs1_line_s +
 947                                mode->vsync_end - mode->vsync_start;
 948                 vwin2_line_s = vwin2_line_e = 0;
 949                 vs2_pix_s    = vs2_pix_e  = 0;
 950                 vs2_line_s   = vs2_line_e = 0;
 951         } else {
 952                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 953                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 954                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 955                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 956                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 957                 vs1_line_e   = vs1_line_s +
 958                                (mode->vsync_end - mode->vsync_start)/2;
 959                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 960                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 961                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 962                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 963                 vs2_line_e   = vs2_line_s +
 964                                (mode->vsync_end - mode->vsync_start)/2;
 965         }
 966
 967         div = 148500 / mode->clock;
 968         if (div != 0) {
 969                 div--;
 970                 if (div > 3)
 971                         div = 3;
 972         }
 973
 974         /* mute the audio FIFO: */
 975         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 976
 977         /* set HDMI HDCP mode off: */
 978         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 979         reg_clear(priv, REG_TX33, TX33_HDMI);
 980         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 981
 982         /* no pre-filter or interpolator: */
 983         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 984                         HVF_CNTRL_0_INTPOL(0));
 985         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 986         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 987                         VIP_CNTRL_4_BLC(0));
 988
 989         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 990         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 991                                           PLL_SERIAL_3_SRL_DE);
 992         reg_write(priv, REG_SERIALIZER, 0);
 993         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 994
 995         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 996         rep = 0;
 997         reg_write(priv, REG_RPT_CNTRL, 0);
 998         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 999                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1000
1001         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1002                         PLL_SERIAL_2_SRL_PR(rep));
1003
1004         /* set color matrix bypass flag: */
1005         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1006                                 MAT_CONTRL_MAT_SC(1));
1007
1008         /* set BIAS tmds value: */
1009         reg_write(priv, REG_ANA_GENERAL, 0x09);
1010
1011         /*
1012          * Sync on rising HSYNC/VSYNC
1013          */
1014         reg = VIP_CNTRL_3_SYNC_HS;
1015
1016         /*
1017          * TDA19988 requires high-active sync at input stage,
1018          * so invert low-active sync provided by master encoder here
1019          */
1020         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1021                 reg |= VIP_CNTRL_3_H_TGL;
1022         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1023                 reg |= VIP_CNTRL_3_V_TGL;
1024         reg_write(priv, REG_VIP_CNTRL_3, reg);
1025
1026         reg_write(priv, REG_VIDFORMAT, 0x00);
1027         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1028         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1029         reg_write16(priv, REG_NPIX_MSB, n_pix);
1030         reg_write16(priv, REG_NLINE_MSB, n_line);
1031         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1032         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1033         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1034         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1035         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1036         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1037         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1038         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1039         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1040         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1041         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1042         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1043         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1044         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1045         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1046         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1047
1048         if (priv->rev == TDA19988) {
1049                 /* let incoming pixels fill the active space (if any) */
1050                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1051         }
1052
1053         /*
1054          * Always generate sync polarity relative to input sync and
1055          * revert input stage toggled sync at output stage
1056          */
1057         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1058         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1059                 reg |= TBG_CNTRL_1_H_TGL;
1060         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1061                 reg |= TBG_CNTRL_1_V_TGL;
1062         reg_write(priv, REG_TBG_CNTRL_1, reg);
1063
1064         /* must be last register set: */
1065         reg_write(priv, REG_TBG_CNTRL_0, 0);
1066
1067         /* Only setup the info frames if the sink is HDMI */
1068         if (priv->is_hdmi_sink) {
1069                 /* We need to turn HDMI HDCP stuff on to get audio through */
1070                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1071                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1072                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1073                 reg_set(priv, REG_TX33, TX33_HDMI);
1074
1075                 tda998x_write_avi(priv, adjusted_mode);
1076
1077                 if (priv->params.audio_cfg)
1078                         tda998x_configure_audio(priv, adjusted_mode,
1079                                                 &priv->params);
1080         }
1081 }
1082
1083 static enum drm_connector_status
1084 tda998x_encoder_detect(struct tda998x_priv *priv)
1085 {
1086         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1087
1088         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1089                         connector_status_disconnected;
1090 }
1091
1092 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1093 {
1094         struct tda998x_priv *priv = data;
1095         u8 offset, segptr;
1096         int ret, i;
1097
1098         offset = (blk & 1) ? 128 : 0;
1099         segptr = blk / 2;
1100
1101         reg_write(priv, REG_DDC_ADDR, 0xa0);
1102         reg_write(priv, REG_DDC_OFFS, offset);
1103         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1104         reg_write(priv, REG_DDC_SEGM, segptr);
1105
1106         /* enable reading EDID: */
1107         priv->wq_edid_wait = 1;
1108         reg_write(priv, REG_EDID_CTRL, 0x1);
1109
1110         /* flag must be cleared by sw: */
1111         reg_write(priv, REG_EDID_CTRL, 0x0);
1112
1113         /* wait for block read to complete: */
1114         if (priv->hdmi->irq) {
1115                 i = wait_event_timeout(priv->wq_edid,
1116                                         !priv->wq_edid_wait,
1117                                         msecs_to_jiffies(100));
1118                 if (i < 0) {
1119                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1120                         return i;
1121                 }
1122         } else {
1123                 for (i = 100; i > 0; i--) {
1124                         msleep(1);
1125                         ret = reg_read(priv, REG_INT_FLAGS_2);
1126                         if (ret < 0)
1127                                 return ret;
1128                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1129                                 break;
1130                 }
1131         }
1132
1133         if (i == 0) {
1134                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1135                 return -ETIMEDOUT;
1136         }
1137
1138         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1139         if (ret != length) {
1140                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1141                         blk, ret);
1142                 return ret;
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int
1149 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1150                           struct drm_connector *connector)
1151 {
1152         struct edid *edid;
1153         int n;
1154
1155         /*
1156          * If we get killed while waiting for the HPD timeout, return
1157          * no modes found: we are not in a restartable path, so we
1158          * can't handle signals gracefully.
1159          */
1160         if (tda998x_edid_delay_wait(priv))
1161                 return 0;
1162
1163         if (priv->rev == TDA19988)
1164                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1165
1166         edid = drm_do_get_edid(connector, read_edid_block, priv);
1167
1168         if (priv->rev == TDA19988)
1169                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1170
1171         if (!edid) {
1172                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1173                 return 0;
1174         }
1175
1176         drm_mode_connector_update_edid_property(connector, edid);
1177         n = drm_add_edid_modes(connector, edid);
1178         priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1179         kfree(edid);
1180
1181         return n;
1182 }
1183
1184 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1185                                         struct drm_connector *connector)
1186 {
1187         if (priv->hdmi->irq)
1188                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1189         else
1190                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1191                         DRM_CONNECTOR_POLL_DISCONNECT;
1192 }
1193
1194 static int
1195 tda998x_encoder_set_property(struct drm_encoder *encoder,
1196                             struct drm_connector *connector,
1197                             struct drm_property *property,
1198                             uint64_t val)
1199 {
1200         DBG("");
1201         return 0;
1202 }
1203
1204 static void tda998x_destroy(struct tda998x_priv *priv)
1205 {
1206         /* disable all IRQs and free the IRQ handler */
1207         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1208         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1209
1210         if (priv->hdmi->irq)
1211                 free_irq(priv->hdmi->irq, priv);
1212
1213         del_timer_sync(&priv->edid_delay_timer);
1214         cancel_work_sync(&priv->detect_work);
1215
1216         i2c_unregister_device(priv->cec);
1217 }
1218
1219 /* Slave encoder support */
1220
1221 static void
1222 tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1223 {
1224         tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1225 }
1226
1227 static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1228 {
1229         struct tda998x_priv *priv = to_tda998x_priv(encoder);
1230
1231         tda998x_destroy(priv);
1232         drm_i2c_encoder_destroy(encoder);
1233         kfree(priv);
1234 }
1235
1236 static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1237 {
1238         tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1239 }
1240
1241 static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1242                                             struct drm_display_mode *mode)
1243 {
1244         return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1245 }
1246
1247 static void
1248 tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1249                                struct drm_display_mode *mode,
1250                                struct drm_display_mode *adjusted_mode)
1251 {
1252         tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1253 }
1254
1255 static enum drm_connector_status
1256 tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1257                              struct drm_connector *connector)
1258 {
1259         return tda998x_encoder_detect(to_tda998x_priv(encoder));
1260 }
1261
1262 static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1263                                            struct drm_connector *connector)
1264 {
1265         return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
1266 }
1267
1268 static int
1269 tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1270                                        struct drm_connector *connector)
1271 {
1272         tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
1273         return 0;
1274 }
1275
1276 static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1277         .set_config = tda998x_encoder_slave_set_config,
1278         .destroy = tda998x_encoder_slave_destroy,
1279         .dpms = tda998x_encoder_slave_dpms,
1280         .save = tda998x_encoder_save,
1281         .restore = tda998x_encoder_restore,
1282         .mode_fixup = tda998x_encoder_mode_fixup,
1283         .mode_valid = tda998x_encoder_slave_mode_valid,
1284         .mode_set = tda998x_encoder_slave_mode_set,
1285         .detect = tda998x_encoder_slave_detect,
1286         .get_modes = tda998x_encoder_slave_get_modes,
1287         .create_resources = tda998x_encoder_slave_create_resources,
1288         .set_property = tda998x_encoder_set_property,
1289 };
1290
1291 /* I2C driver functions */
1292
1293 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1294 {
1295         struct device_node *np = client->dev.of_node;
1296         u32 video;
1297         int rev_lo, rev_hi, ret;
1298         unsigned short cec_addr;
1299
1300         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1301         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1302         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1303
1304         priv->current_page = 0xff;
1305         priv->hdmi = client;
1306         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1307         cec_addr = 0x34 + (client->addr & 0x03);
1308         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1309         if (!priv->cec)
1310                 return -ENODEV;
1311
1312         priv->dpms = DRM_MODE_DPMS_OFF;
1313
1314         mutex_init(&priv->mutex);       /* protect the page access */
1315         init_waitqueue_head(&priv->edid_delay_waitq);
1316         setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1317                     (unsigned long)priv);
1318         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1319
1320         /* wake up the device: */
1321         cec_write(priv, REG_CEC_ENAMODS,
1322                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1323
1324         tda998x_reset(priv);
1325
1326         /* read version: */
1327         rev_lo = reg_read(priv, REG_VERSION_LSB);
1328         rev_hi = reg_read(priv, REG_VERSION_MSB);
1329         if (rev_lo < 0 || rev_hi < 0) {
1330                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1331                 goto fail;
1332         }
1333
1334         priv->rev = rev_lo | rev_hi << 8;
1335
1336         /* mask off feature bits: */
1337         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1338
1339         switch (priv->rev) {
1340         case TDA9989N2:
1341                 dev_info(&client->dev, "found TDA9989 n2");
1342                 break;
1343         case TDA19989:
1344                 dev_info(&client->dev, "found TDA19989");
1345                 break;
1346         case TDA19989N2:
1347                 dev_info(&client->dev, "found TDA19989 n2");
1348                 break;
1349         case TDA19988:
1350                 dev_info(&client->dev, "found TDA19988");
1351                 break;
1352         default:
1353                 dev_err(&client->dev, "found unsupported device: %04x\n",
1354                         priv->rev);
1355                 goto fail;
1356         }
1357
1358         /* after reset, enable DDC: */
1359         reg_write(priv, REG_DDC_DISABLE, 0x00);
1360
1361         /* set clock on DDC channel: */
1362         reg_write(priv, REG_TX3, 39);
1363
1364         /* if necessary, disable multi-master: */
1365         if (priv->rev == TDA19989)
1366                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1367
1368         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1369                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1370
1371         /* initialize the optional IRQ */
1372         if (client->irq) {
1373                 int irqf_trigger;
1374
1375                 /* init read EDID waitqueue and HDP work */
1376                 init_waitqueue_head(&priv->wq_edid);
1377
1378                 /* clear pending interrupts */
1379                 reg_read(priv, REG_INT_FLAGS_0);
1380                 reg_read(priv, REG_INT_FLAGS_1);
1381                 reg_read(priv, REG_INT_FLAGS_2);
1382
1383                 irqf_trigger =
1384                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1385                 ret = request_threaded_irq(client->irq, NULL,
1386                                            tda998x_irq_thread,
1387                                            irqf_trigger | IRQF_ONESHOT,
1388                                            "tda998x", priv);
1389                 if (ret) {
1390                         dev_err(&client->dev,
1391                                 "failed to request IRQ#%u: %d\n",
1392                                 client->irq, ret);
1393                         goto fail;
1394                 }
1395
1396                 /* enable HPD irq */
1397                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1398         }
1399
1400         /* enable EDID read irq: */
1401         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1402
1403         if (!np)
1404                 return 0;               /* non-DT */
1405
1406         /* get the optional video properties */
1407         ret = of_property_read_u32(np, "video-ports", &video);
1408         if (ret == 0) {
1409                 priv->vip_cntrl_0 = video >> 16;
1410                 priv->vip_cntrl_1 = video >> 8;
1411                 priv->vip_cntrl_2 = video;
1412         }
1413
1414         return 0;
1415
1416 fail:
1417         /* if encoder_init fails, the encoder slave is never registered,
1418          * so cleanup here:
1419          */
1420         if (priv->cec)
1421                 i2c_unregister_device(priv->cec);
1422         return -ENXIO;
1423 }
1424
1425 static int tda998x_encoder_init(struct i2c_client *client,
1426                                 struct drm_device *dev,
1427                                 struct drm_encoder_slave *encoder_slave)
1428 {
1429         struct tda998x_priv *priv;
1430         int ret;
1431
1432         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1433         if (!priv)
1434                 return -ENOMEM;
1435
1436         priv->encoder = &encoder_slave->base;
1437
1438         ret = tda998x_create(client, priv);
1439         if (ret) {
1440                 kfree(priv);
1441                 return ret;
1442         }
1443
1444         encoder_slave->slave_priv = priv;
1445         encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1446
1447         return 0;
1448 }
1449
1450 struct tda998x_priv2 {
1451         struct tda998x_priv base;
1452         struct drm_encoder encoder;
1453         struct drm_connector connector;
1454 };
1455
1456 #define conn_to_tda998x_priv2(x) \
1457         container_of(x, struct tda998x_priv2, connector);
1458
1459 #define enc_to_tda998x_priv2(x) \
1460         container_of(x, struct tda998x_priv2, encoder);
1461
1462 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1463 {
1464         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1465
1466         tda998x_encoder_dpms(&priv->base, mode);
1467 }
1468
1469 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1470 {
1471         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1472 }
1473
1474 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1475 {
1476         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1477 }
1478
1479 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1480                                       struct drm_display_mode *mode,
1481                                       struct drm_display_mode *adjusted_mode)
1482 {
1483         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1484
1485         tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1486 }
1487
1488 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1489         .dpms = tda998x_encoder2_dpms,
1490         .save = tda998x_encoder_save,
1491         .restore = tda998x_encoder_restore,
1492         .mode_fixup = tda998x_encoder_mode_fixup,
1493         .prepare = tda998x_encoder_prepare,
1494         .commit = tda998x_encoder_commit,
1495         .mode_set = tda998x_encoder2_mode_set,
1496 };
1497
1498 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1499 {
1500         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1501
1502         tda998x_destroy(&priv->base);
1503         drm_encoder_cleanup(encoder);
1504 }
1505
1506 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1507         .destroy = tda998x_encoder_destroy,
1508 };
1509
1510 static int tda998x_connector_get_modes(struct drm_connector *connector)
1511 {
1512         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1513
1514         return tda998x_encoder_get_modes(&priv->base, connector);
1515 }
1516
1517 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1518                                         struct drm_display_mode *mode)
1519 {
1520         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1521
1522         return tda998x_encoder_mode_valid(&priv->base, mode);
1523 }
1524
1525 static struct drm_encoder *
1526 tda998x_connector_best_encoder(struct drm_connector *connector)
1527 {
1528         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1529
1530         return &priv->encoder;
1531 }
1532
1533 static
1534 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1535         .get_modes = tda998x_connector_get_modes,
1536         .mode_valid = tda998x_connector_mode_valid,
1537         .best_encoder = tda998x_connector_best_encoder,
1538 };
1539
1540 static enum drm_connector_status
1541 tda998x_connector_detect(struct drm_connector *connector, bool force)
1542 {
1543         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1544
1545         return tda998x_encoder_detect(&priv->base);
1546 }
1547
1548 static void tda998x_connector_destroy(struct drm_connector *connector)
1549 {
1550         drm_connector_unregister(connector);
1551         drm_connector_cleanup(connector);
1552 }
1553
1554 static const struct drm_connector_funcs tda998x_connector_funcs = {
1555         .dpms = drm_helper_connector_dpms,
1556         .fill_modes = drm_helper_probe_single_connector_modes,
1557         .detect = tda998x_connector_detect,
1558         .destroy = tda998x_connector_destroy,
1559 };
1560
1561 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1562 {
1563         struct tda998x_encoder_params *params = dev->platform_data;
1564         struct i2c_client *client = to_i2c_client(dev);
1565         struct drm_device *drm = data;
1566         struct tda998x_priv2 *priv;
1567         u32 crtcs = 0;
1568         int ret;
1569
1570         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1571         if (!priv)
1572                 return -ENOMEM;
1573
1574         dev_set_drvdata(dev, priv);
1575
1576         if (dev->of_node)
1577                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1578
1579         /* If no CRTCs were found, fall back to our old behaviour */
1580         if (crtcs == 0) {
1581                 dev_warn(dev, "Falling back to first CRTC\n");
1582                 crtcs = 1 << 0;
1583         }
1584
1585         priv->base.encoder = &priv->encoder;
1586         priv->connector.interlace_allowed = 1;
1587         priv->encoder.possible_crtcs = crtcs;
1588
1589         ret = tda998x_create(client, &priv->base);
1590         if (ret)
1591                 return ret;
1592
1593         if (!dev->of_node && params)
1594                 tda998x_encoder_set_config(&priv->base, params);
1595
1596         tda998x_encoder_set_polling(&priv->base, &priv->connector);
1597
1598         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1599         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1600                                DRM_MODE_ENCODER_TMDS);
1601         if (ret)
1602                 goto err_encoder;
1603
1604         drm_connector_helper_add(&priv->connector,
1605                                  &tda998x_connector_helper_funcs);
1606         ret = drm_connector_init(drm, &priv->connector,
1607                                  &tda998x_connector_funcs,
1608                                  DRM_MODE_CONNECTOR_HDMIA);
1609         if (ret)
1610                 goto err_connector;
1611
1612         ret = drm_connector_register(&priv->connector);
1613         if (ret)
1614                 goto err_sysfs;
1615
1616         priv->connector.encoder = &priv->encoder;
1617         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1618
1619         return 0;
1620
1621 err_sysfs:
1622         drm_connector_cleanup(&priv->connector);
1623 err_connector:
1624         drm_encoder_cleanup(&priv->encoder);
1625 err_encoder:
1626         tda998x_destroy(&priv->base);
1627         return ret;
1628 }
1629
1630 static void tda998x_unbind(struct device *dev, struct device *master,
1631                            void *data)
1632 {
1633         struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1634
1635         drm_connector_cleanup(&priv->connector);
1636         drm_encoder_cleanup(&priv->encoder);
1637         tda998x_destroy(&priv->base);
1638 }
1639
1640 static const struct component_ops tda998x_ops = {
1641         .bind = tda998x_bind,
1642         .unbind = tda998x_unbind,
1643 };
1644
1645 static int
1646 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1647 {
1648         return component_add(&client->dev, &tda998x_ops);
1649 }
1650
1651 static int tda998x_remove(struct i2c_client *client)
1652 {
1653         component_del(&client->dev, &tda998x_ops);
1654         return 0;
1655 }
1656
1657 #ifdef CONFIG_OF
1658 static const struct of_device_id tda998x_dt_ids[] = {
1659         { .compatible = "nxp,tda998x", },
1660         { }
1661 };
1662 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1663 #endif
1664
1665 static struct i2c_device_id tda998x_ids[] = {
1666         { "tda998x", 0 },
1667         { }
1668 };
1669 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1670
1671 static struct drm_i2c_encoder_driver tda998x_driver = {
1672         .i2c_driver = {
1673                 .probe = tda998x_probe,
1674                 .remove = tda998x_remove,
1675                 .driver = {
1676                         .name = "tda998x",
1677                         .of_match_table = of_match_ptr(tda998x_dt_ids),
1678                 },
1679                 .id_table = tda998x_ids,
1680         },
1681         .encoder_init = tda998x_encoder_init,
1682 };
1683
1684 /* Module initialization */
1685
1686 static int __init
1687 tda998x_init(void)
1688 {
1689         DBG("");
1690         return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1691 }
1692
1693 static void __exit
1694 tda998x_exit(void)
1695 {
1696         DBG("");
1697         drm_i2c_encoder_unregister(&tda998x_driver);
1698 }
1699
1700 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1701 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1702 MODULE_LICENSE("GPL");
1703
1704 module_init(tda998x_init);
1705 module_exit(tda998x_exit);