drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_of.h>
  29 #include <drm/i2c/tda998x.h>
  30
  31 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  32
  33 struct tda998x_priv {
  34         struct i2c_client *cec;
  35         struct i2c_client *hdmi;
  36         struct mutex mutex;
  37         u16 rev;
  38         u8 current_page;
  39         int dpms;
  40         bool is_hdmi_sink;
  41         u8 vip_cntrl_0;
  42         u8 vip_cntrl_1;
  43         u8 vip_cntrl_2;
  44         struct tda998x_encoder_params params;
  45
  46         wait_queue_head_t wq_edid;
  47         volatile int wq_edid_wait;
  48         struct drm_encoder *encoder;
  49
  50         struct work_struct detect_work;
  51         struct timer_list edid_delay_timer;
  52         wait_queue_head_t edid_delay_waitq;
  53         bool edid_delay_active;
  54 };
  55
  56 #define to_tda998x_priv(x)  ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
  57
  58 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  59  * things we encode the page # in upper bits of the register #.  To read/
  60  * write a given register, we need to make sure CURPAGE register is set
  61  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  62  */
  63
  64 #define REG(page, addr) (((page) << 8) | (addr))
  65 #define REG2ADDR(reg)   ((reg) & 0xff)
  66 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  67
  68 #define REG_CURPAGE               0xff                /* write */
  69
  70
  71 /* Page 00h: General Control */
  72 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  73 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  74 # define MAIN_CNTRL0_SR           (1 << 0)
  75 # define MAIN_CNTRL0_DECS         (1 << 1)
  76 # define MAIN_CNTRL0_DEHS         (1 << 2)
  77 # define MAIN_CNTRL0_CECS         (1 << 3)
  78 # define MAIN_CNTRL0_CEHS         (1 << 4)
  79 # define MAIN_CNTRL0_SCALER       (1 << 7)
  80 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  81 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  82 # define SOFTRESET_AUDIO          (1 << 0)
  83 # define SOFTRESET_I2C_MASTER     (1 << 1)
  84 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  85 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  86 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  87 # define I2C_MASTER_DIS_MM        (1 << 0)
  88 # define I2C_MASTER_DIS_FILT      (1 << 1)
  89 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  90 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  91 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  92 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  93 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  94 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  95 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  96 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  97 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  98 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  99 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 100 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 101 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 102 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 103 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 104 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 105 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 106 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 107 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 108 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 109 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 110 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 111 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 112 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 113 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 114 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 115 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 116 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 117 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 118 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 119 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 120 # define VIP_CNTRL_3_EMB          (1 << 3)
 121 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 122 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 123 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 124 # define VIP_CNTRL_3_EDGE         (1 << 7)
 125 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 126 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 127 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 128 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 129 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 130 # define VIP_CNTRL_4_TST_656      (1 << 6)
 131 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 132 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 133 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 134 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 135 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 136 # define MUX_AP_SELECT_I2S        0x64
 137 # define MUX_AP_SELECT_SPDIF      0x40
 138 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 139 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 140 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 141 # define MAT_CONTRL_MAT_BP        (1 << 2)
 142 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 143 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 144 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 145 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 146 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 147 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 148 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 149 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 150 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 151 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 152 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 153 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 154 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 155 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 156 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 157 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 158 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 159 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 160 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 161 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 162 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 163 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 164 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 165 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 166 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 167 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 168 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 169 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 170 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 171 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 172 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 173 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 174 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 175 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 176 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 177 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 178 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 179 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 180 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 181 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 182 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 183 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 184 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 185 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 186 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 187 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 188 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 189 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 190 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 191 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 192 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 193 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 194 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 195 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 196 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 197 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 198 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 199 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 200 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 201 # define HVF_CNTRL_0_SM           (1 << 7)
 202 # define HVF_CNTRL_0_RWB          (1 << 6)
 203 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 204 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 205 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 206 # define HVF_CNTRL_1_FOR          (1 << 0)
 207 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 208 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 209 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 210 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 211 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 212 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 213 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 214 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 215 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 216 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 217 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 218 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 219 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 220
 221 /* Page 02h: PLL settings */
 222 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 223 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 224 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 225 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 226 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 227 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 228 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 229 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 230 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 231 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 232 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 233 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 234 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 235 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 236 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 237 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 238 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 239 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 240 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 241 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 242 # define AUDIO_DIV_SERCLK_1       0
 243 # define AUDIO_DIV_SERCLK_2       1
 244 # define AUDIO_DIV_SERCLK_4       2
 245 # define AUDIO_DIV_SERCLK_8       3
 246 # define AUDIO_DIV_SERCLK_16      4
 247 # define AUDIO_DIV_SERCLK_32      5
 248 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 249 # define SEL_CLK_SEL_CLK1         (1 << 0)
 250 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 251 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 252 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 253
 254
 255 /* Page 09h: EDID Control */
 256 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 257 /* next 127 successive registers are the EDID block */
 258 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 259 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 260 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 261 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 262 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 263
 264
 265 /* Page 10h: information frames and packets */
 266 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 267 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 268 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 269 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 270 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 271
 272
 273 /* Page 11h: audio settings and content info packets */
 274 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 275 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 276 # define AIP_CNTRL_0_SWAP         (1 << 1)
 277 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 278 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 279 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 280 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 281 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 282 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 283 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 284 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 285 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 286 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 287 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 288 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 289 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 290 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 291 # define CTS_N_K(x)               (((x) & 7) << 0)
 292 # define CTS_N_M(x)               (((x) & 3) << 4)
 293 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 294 # define ENC_CNTRL_RST_ENC        (1 << 0)
 295 # define ENC_CNTRL_RST_SEL        (1 << 1)
 296 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 297 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 298 # define DIP_FLAGS_ACR            (1 << 0)
 299 # define DIP_FLAGS_GC             (1 << 1)
 300 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 301 # define DIP_IF_FLAGS_IF1         (1 << 1)
 302 # define DIP_IF_FLAGS_IF2         (1 << 2)
 303 # define DIP_IF_FLAGS_IF3         (1 << 3)
 304 # define DIP_IF_FLAGS_IF4         (1 << 4)
 305 # define DIP_IF_FLAGS_IF5         (1 << 5)
 306 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 307
 308
 309 /* Page 12h: HDCP and OTP */
 310 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 311 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 312 # define TX4_PD_RAM               (1 << 1)
 313 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 314 # define TX33_HDMI                (1 << 1)
 315
 316
 317 /* Page 13h: Gamut related metadata packets */
 318
 319
 320
 321 /* CEC registers: (not paged)
 322  */
 323 #define REG_CEC_INTSTATUS         0xee                /* read */
 324 # define CEC_INTSTATUS_CEC        (1 << 0)
 325 # define CEC_INTSTATUS_HDMI       (1 << 1)
 326 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 327 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 328 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 329 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 330 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 331 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 332 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 333 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 334 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 335 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 336
 337 #define REG_CEC_ENAMODS           0xff                /* read/write */
 338 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 339 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 340 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 341 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 342 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 343
 344
 345 /* Device versions: */
 346 #define TDA9989N2                 0x0101
 347 #define TDA19989                  0x0201
 348 #define TDA19989N2                0x0202
 349 #define TDA19988                  0x0301
 350
 351 static void
 352 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 353 {
 354         struct i2c_client *client = priv->cec;
 355         u8 buf[] = {addr, val};
 356         int ret;
 357
 358         ret = i2c_master_send(client, buf, sizeof(buf));
 359         if (ret < 0)
 360                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 361 }
 362
 363 static u8
 364 cec_read(struct tda998x_priv *priv, u8 addr)
 365 {
 366         struct i2c_client *client = priv->cec;
 367         u8 val;
 368         int ret;
 369
 370         ret = i2c_master_send(client, &addr, sizeof(addr));
 371         if (ret < 0)
 372                 goto fail;
 373
 374         ret = i2c_master_recv(client, &val, sizeof(val));
 375         if (ret < 0)
 376                 goto fail;
 377
 378         return val;
 379
 380 fail:
 381         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 382         return 0;
 383 }
 384
 385 static int
 386 set_page(struct tda998x_priv *priv, u16 reg)
 387 {
 388         if (REG2PAGE(reg) != priv->current_page) {
 389                 struct i2c_client *client = priv->hdmi;
 390                 u8 buf[] = {
 391                                 REG_CURPAGE, REG2PAGE(reg)
 392                 };
 393                 int ret = i2c_master_send(client, buf, sizeof(buf));
 394                 if (ret < 0) {
 395                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 396                                         reg, ret);
 397                         return ret;
 398                 }
 399
 400                 priv->current_page = REG2PAGE(reg);
 401         }
 402         return 0;
 403 }
 404
 405 static int
 406 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 407 {
 408         struct i2c_client *client = priv->hdmi;
 409         u8 addr = REG2ADDR(reg);
 410         int ret;
 411
 412         mutex_lock(&priv->mutex);
 413         ret = set_page(priv, reg);
 414         if (ret < 0)
 415                 goto out;
 416
 417         ret = i2c_master_send(client, &addr, sizeof(addr));
 418         if (ret < 0)
 419                 goto fail;
 420
 421         ret = i2c_master_recv(client, buf, cnt);
 422         if (ret < 0)
 423                 goto fail;
 424
 425         goto out;
 426
 427 fail:
 428         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 429 out:
 430         mutex_unlock(&priv->mutex);
 431         return ret;
 432 }
 433
 434 static void
 435 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 436 {
 437         struct i2c_client *client = priv->hdmi;
 438         u8 buf[cnt+1];
 439         int ret;
 440
 441         buf[0] = REG2ADDR(reg);
 442         memcpy(&buf[1], p, cnt);
 443
 444         mutex_lock(&priv->mutex);
 445         ret = set_page(priv, reg);
 446         if (ret < 0)
 447                 goto out;
 448
 449         ret = i2c_master_send(client, buf, cnt + 1);
 450         if (ret < 0)
 451                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 452 out:
 453         mutex_unlock(&priv->mutex);
 454 }
 455
 456 static int
 457 reg_read(struct tda998x_priv *priv, u16 reg)
 458 {
 459         u8 val = 0;
 460         int ret;
 461
 462         ret = reg_read_range(priv, reg, &val, sizeof(val));
 463         if (ret < 0)
 464                 return ret;
 465         return val;
 466 }
 467
 468 static void
 469 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 470 {
 471         struct i2c_client *client = priv->hdmi;
 472         u8 buf[] = {REG2ADDR(reg), val};
 473         int ret;
 474
 475         mutex_lock(&priv->mutex);
 476         ret = set_page(priv, reg);
 477         if (ret < 0)
 478                 goto out;
 479
 480         ret = i2c_master_send(client, buf, sizeof(buf));
 481         if (ret < 0)
 482                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 483 out:
 484         mutex_unlock(&priv->mutex);
 485 }
 486
 487 static void
 488 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 489 {
 490         struct i2c_client *client = priv->hdmi;
 491         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 492         int ret;
 493
 494         mutex_lock(&priv->mutex);
 495         ret = set_page(priv, reg);
 496         if (ret < 0)
 497                 goto out;
 498
 499         ret = i2c_master_send(client, buf, sizeof(buf));
 500         if (ret < 0)
 501                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 502 out:
 503         mutex_unlock(&priv->mutex);
 504 }
 505
 506 static void
 507 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 508 {
 509         int old_val;
 510
 511         old_val = reg_read(priv, reg);
 512         if (old_val >= 0)
 513                 reg_write(priv, reg, old_val | val);
 514 }
 515
 516 static void
 517 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 518 {
 519         int old_val;
 520
 521         old_val = reg_read(priv, reg);
 522         if (old_val >= 0)
 523                 reg_write(priv, reg, old_val & ~val);
 524 }
 525
 526 static void
 527 tda998x_reset(struct tda998x_priv *priv)
 528 {
 529         /* reset audio and i2c master: */
 530         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 531         msleep(50);
 532         reg_write(priv, REG_SOFTRESET, 0);
 533         msleep(50);
 534
 535         /* reset transmitter: */
 536         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 537         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 538
 539         /* PLL registers common configuration */
 540         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 541         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 542         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 543         reg_write(priv, REG_SERIALIZER,   0x00);
 544         reg_write(priv, REG_BUFFER_OUT,   0x00);
 545         reg_write(priv, REG_PLL_SCG1,     0x00);
 546         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 547         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 548         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 549         reg_write(priv, REG_PLL_SCGN2,    0x00);
 550         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 551         reg_write(priv, REG_PLL_SCGR2,    0x00);
 552         reg_write(priv, REG_PLL_SCG2,     0x10);
 553
 554         /* Write the default value MUX register */
 555         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 556 }
 557
 558 /*
 559  * The TDA998x has a problem when trying to read the EDID close to a
 560  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 561  * trying to read EDID data.
 562  *
 563  * However, tda998x_encoder_get_modes() may be called at any moment
 564  * after tda998x_encoder_detect() indicates that we are connected, so
 565  * we need to delay probing modes in tda998x_encoder_get_modes() after
 566  * we have seen a HPD inactive->active transition.  This code implements
 567  * that delay.
 568  */
 569 static void tda998x_edid_delay_done(unsigned long data)
 570 {
 571         struct tda998x_priv *priv = (struct tda998x_priv *)data;
 572
 573         priv->edid_delay_active = false;
 574         wake_up(&priv->edid_delay_waitq);
 575         schedule_work(&priv->detect_work);
 576 }
 577
 578 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 579 {
 580         priv->edid_delay_active = true;
 581         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 582 }
 583
 584 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 585 {
 586         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 587 }
 588
 589 /*
 590  * We need to run the KMS hotplug event helper outside of our threaded
 591  * interrupt routine as this can call back into our get_modes method,
 592  * which will want to make use of interrupts.
 593  */
 594 static void tda998x_detect_work(struct work_struct *work)
 595 {
 596         struct tda998x_priv *priv =
 597                 container_of(work, struct tda998x_priv, detect_work);
 598         struct drm_device *dev = priv->encoder->dev;
 599
 600         if (dev)
 601                 drm_kms_helper_hotplug_event(dev);
 602 }
 603
 604 /*
 605  * only 2 interrupts may occur: screen plug/unplug and EDID read
 606  */
 607 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 608 {
 609         struct tda998x_priv *priv = data;
 610         u8 sta, cec, lvl, flag0, flag1, flag2;
 611         bool handled = false;
 612
 613         sta = cec_read(priv, REG_CEC_INTSTATUS);
 614         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 615         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 616         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 617         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 618         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 619         DRM_DEBUG_DRIVER(
 620                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 621                 sta, cec, lvl, flag0, flag1, flag2);
 622         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 623                 priv->wq_edid_wait = 0;
 624                 wake_up(&priv->wq_edid);
 625                 handled = true;
 626         } else if (cec != 0) {                  /* HPD change */
 627                 if (lvl & CEC_RXSHPDLEV_HPD)
 628                         tda998x_edid_delay_start(priv);
 629                 else
 630                         schedule_work(&priv->detect_work);
 631
 632                 handled = true;
 633         }
 634         return IRQ_RETVAL(handled);
 635 }
 636
 637 static u8 tda998x_cksum(u8 *buf, size_t bytes)
 638 {
 639         int sum = 0;
 640
 641         while (bytes--)
 642                 sum -= *buf++;
 643         return sum;
 644 }
 645
 646 #define HB(x) (x)
 647 #define PB(x) (HB(2) + 1 + (x))
 648
 649 static void
 650 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 651                  u8 *buf, size_t size)
 652 {
 653         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 654         reg_write_range(priv, addr, buf, size);
 655         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 656 }
 657
 658 static void
 659 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 660 {
 661         u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
 662
 663         memset(buf, 0, sizeof(buf));
 664         buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
 665         buf[HB(1)] = 0x01;
 666         buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
 667         buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
 668         buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
 669         buf[PB(4)] = p->audio_frame[4];
 670         buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
 671
 672         buf[PB(0)] = tda998x_cksum(buf, sizeof(buf));
 673
 674         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
 675                          sizeof(buf));
 676 }
 677
 678 static void
 679 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 680 {
 681         struct hdmi_avi_infoframe frame;
 682         u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 683         ssize_t len;
 684
 685         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 686
 687         frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 688
 689         len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
 690         if (len < 0) {
 691                 dev_err(&priv->hdmi->dev,
 692                         "hdmi_avi_infoframe_pack() failed: %zd\n", len);
 693                 return;
 694         }
 695
 696         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len);
 697 }
 698
 699 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 700 {
 701         if (on) {
 702                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 703                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 704                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 705         } else {
 706                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 707         }
 708 }
 709
 710 static void
 711 tda998x_configure_audio(struct tda998x_priv *priv,
 712                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 713 {
 714         u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 715         u32 n;
 716
 717         /* Enable audio ports */
 718         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 719         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 720
 721         /* Set audio input source */
 722         switch (p->audio_format) {
 723         case AFMT_SPDIF:
 724                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 725                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 726                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 727                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 728                 break;
 729
 730         case AFMT_I2S:
 731                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 732                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 733                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 734                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 735                 break;
 736
 737         default:
 738                 BUG();
 739                 return;
 740         }
 741
 742         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 743         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 744                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 745         reg_write(priv, REG_CTS_N, cts_n);
 746
 747         /*
 748          * Audio input somehow depends on HDMI line rate which is
 749          * related to pixclk. Testing showed that modes with pixclk
 750          * >100MHz need a larger divider while <40MHz need the default.
 751          * There is no detailed info in the datasheet, so we just
 752          * assume 100MHz requires larger divider.
 753          */
 754         adiv = AUDIO_DIV_SERCLK_8;
 755         if (mode->clock > 100000)
 756                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 757
 758         /* S/PDIF asks for a larger divider */
 759         if (p->audio_format == AFMT_SPDIF)
 760                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 761
 762         reg_write(priv, REG_AUDIO_DIV, adiv);
 763
 764         /*
 765          * This is the approximate value of N, which happens to be
 766          * the recommended values for non-coherent clocks.
 767          */
 768         n = 128 * p->audio_sample_rate / 1000;
 769
 770         /* Write the CTS and N values */
 771         buf[0] = 0x44;
 772         buf[1] = 0x42;
 773         buf[2] = 0x01;
 774         buf[3] = n;
 775         buf[4] = n >> 8;
 776         buf[5] = n >> 16;
 777         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 778
 779         /* Set CTS clock reference */
 780         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 781
 782         /* Reset CTS generator */
 783         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 784         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 785
 786         /* Write the channel status */
 787         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 788         buf[1] = 0x00;
 789         buf[2] = IEC958_AES3_CON_FS_NOTID;
 790         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 791                         IEC958_AES4_CON_MAX_WORDLEN_24;
 792         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 793
 794         tda998x_audio_mute(priv, true);
 795         msleep(20);
 796         tda998x_audio_mute(priv, false);
 797
 798         /* Write the audio information packet */
 799         tda998x_write_aif(priv, p);
 800 }
 801
 802 /* DRM encoder functions */
 803
 804 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 805                                        const struct tda998x_encoder_params *p)
 806 {
 807         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 808                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 809                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 810                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 811         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 812                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 813                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 814                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 815         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 816                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 817                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 818                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 819
 820         priv->params = *p;
 821 }
 822
 823 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 824 {
 825         /* we only care about on or off: */
 826         if (mode != DRM_MODE_DPMS_ON)
 827                 mode = DRM_MODE_DPMS_OFF;
 828
 829         if (mode == priv->dpms)
 830                 return;
 831
 832         switch (mode) {
 833         case DRM_MODE_DPMS_ON:
 834                 /* enable video ports, audio will be enabled later */
 835                 reg_write(priv, REG_ENA_VP_0, 0xff);
 836                 reg_write(priv, REG_ENA_VP_1, 0xff);
 837                 reg_write(priv, REG_ENA_VP_2, 0xff);
 838                 /* set muxing after enabling ports: */
 839                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 840                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 841                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 842                 break;
 843         case DRM_MODE_DPMS_OFF:
 844                 /* disable video ports */
 845                 reg_write(priv, REG_ENA_VP_0, 0x00);
 846                 reg_write(priv, REG_ENA_VP_1, 0x00);
 847                 reg_write(priv, REG_ENA_VP_2, 0x00);
 848                 break;
 849         }
 850
 851         priv->dpms = mode;
 852 }
 853
 854 static void
 855 tda998x_encoder_save(struct drm_encoder *encoder)
 856 {
 857         DBG("");
 858 }
 859
 860 static void
 861 tda998x_encoder_restore(struct drm_encoder *encoder)
 862 {
 863         DBG("");
 864 }
 865
 866 static bool
 867 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 868                           const struct drm_display_mode *mode,
 869                           struct drm_display_mode *adjusted_mode)
 870 {
 871         return true;
 872 }
 873
 874 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 875                                       struct drm_display_mode *mode)
 876 {
 877         if (mode->clock > 150000)
 878                 return MODE_CLOCK_HIGH;
 879         if (mode->htotal >= BIT(13))
 880                 return MODE_BAD_HVALUE;
 881         if (mode->vtotal >= BIT(11))
 882                 return MODE_BAD_VVALUE;
 883         return MODE_OK;
 884 }
 885
 886 static void
 887 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 888                          struct drm_display_mode *mode,
 889                          struct drm_display_mode *adjusted_mode)
 890 {
 891         u16 ref_pix, ref_line, n_pix, n_line;
 892         u16 hs_pix_s, hs_pix_e;
 893         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 894         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 895         u16 vwin1_line_s, vwin1_line_e;
 896         u16 vwin2_line_s, vwin2_line_e;
 897         u16 de_pix_s, de_pix_e;
 898         u8 reg, div, rep;
 899
 900         /*
 901          * Internally TDA998x is using ITU-R BT.656 style sync but
 902          * we get VESA style sync. TDA998x is using a reference pixel
 903          * relative to ITU to sync to the input frame and for output
 904          * sync generation. Currently, we are using reference detection
 905          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 906          * which is position of rising VS with coincident rising HS.
 907          *
 908          * Now there is some issues to take care of:
 909          * - HDMI data islands require sync-before-active
 910          * - TDA998x register values must be > 0 to be enabled
 911          * - REFLINE needs an additional offset of +1
 912          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 913          *
 914          * So we add +1 to all horizontal and vertical register values,
 915          * plus an additional +3 for REFPIX as we are using RGB input only.
 916          */
 917         n_pix        = mode->htotal;
 918         n_line       = mode->vtotal;
 919
 920         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 921         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 922         de_pix_e     = mode->htotal;
 923         de_pix_s     = mode->htotal - mode->hdisplay;
 924         ref_pix      = 3 + hs_pix_s;
 925
 926         /*
 927          * Attached LCD controllers may generate broken sync. Allow
 928          * those to adjust the position of the rising VS edge by adding
 929          * HSKEW to ref_pix.
 930          */
 931         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 932                 ref_pix += adjusted_mode->hskew;
 933
 934         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 935                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 936                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 937                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 938                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 939                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 940                 vs1_line_e   = vs1_line_s +
 941                                mode->vsync_end - mode->vsync_start;
 942                 vwin2_line_s = vwin2_line_e = 0;
 943                 vs2_pix_s    = vs2_pix_e  = 0;
 944                 vs2_line_s   = vs2_line_e = 0;
 945         } else {
 946                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 947                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 948                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 949                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 950                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 951                 vs1_line_e   = vs1_line_s +
 952                                (mode->vsync_end - mode->vsync_start)/2;
 953                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 954                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 955                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 956                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 957                 vs2_line_e   = vs2_line_s +
 958                                (mode->vsync_end - mode->vsync_start)/2;
 959         }
 960
 961         div = 148500 / mode->clock;
 962         if (div != 0) {
 963                 div--;
 964                 if (div > 3)
 965                         div = 3;
 966         }
 967
 968         /* mute the audio FIFO: */
 969         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 970
 971         /* set HDMI HDCP mode off: */
 972         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 973         reg_clear(priv, REG_TX33, TX33_HDMI);
 974         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 975
 976         /* no pre-filter or interpolator: */
 977         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 978                         HVF_CNTRL_0_INTPOL(0));
 979         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 980         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 981                         VIP_CNTRL_4_BLC(0));
 982
 983         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 984         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 985                                           PLL_SERIAL_3_SRL_DE);
 986         reg_write(priv, REG_SERIALIZER, 0);
 987         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 988
 989         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 990         rep = 0;
 991         reg_write(priv, REG_RPT_CNTRL, 0);
 992         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 993                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 994
 995         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
 996                         PLL_SERIAL_2_SRL_PR(rep));
 997
 998         /* set color matrix bypass flag: */
 999         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1000                                 MAT_CONTRL_MAT_SC(1));
1001
1002         /* set BIAS tmds value: */
1003         reg_write(priv, REG_ANA_GENERAL, 0x09);
1004
1005         /*
1006          * Sync on rising HSYNC/VSYNC
1007          */
1008         reg = VIP_CNTRL_3_SYNC_HS;
1009
1010         /*
1011          * TDA19988 requires high-active sync at input stage,
1012          * so invert low-active sync provided by master encoder here
1013          */
1014         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1015                 reg |= VIP_CNTRL_3_H_TGL;
1016         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1017                 reg |= VIP_CNTRL_3_V_TGL;
1018         reg_write(priv, REG_VIP_CNTRL_3, reg);
1019
1020         reg_write(priv, REG_VIDFORMAT, 0x00);
1021         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1022         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1023         reg_write16(priv, REG_NPIX_MSB, n_pix);
1024         reg_write16(priv, REG_NLINE_MSB, n_line);
1025         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1026         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1027         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1028         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1029         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1030         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1031         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1032         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1033         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1034         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1035         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1036         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1037         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1038         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1039         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1040         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1041
1042         if (priv->rev == TDA19988) {
1043                 /* let incoming pixels fill the active space (if any) */
1044                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1045         }
1046
1047         /*
1048          * Always generate sync polarity relative to input sync and
1049          * revert input stage toggled sync at output stage
1050          */
1051         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1052         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1053                 reg |= TBG_CNTRL_1_H_TGL;
1054         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1055                 reg |= TBG_CNTRL_1_V_TGL;
1056         reg_write(priv, REG_TBG_CNTRL_1, reg);
1057
1058         /* must be last register set: */
1059         reg_write(priv, REG_TBG_CNTRL_0, 0);
1060
1061         /* Only setup the info frames if the sink is HDMI */
1062         if (priv->is_hdmi_sink) {
1063                 /* We need to turn HDMI HDCP stuff on to get audio through */
1064                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1065                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1066                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1067                 reg_set(priv, REG_TX33, TX33_HDMI);
1068
1069                 tda998x_write_avi(priv, adjusted_mode);
1070
1071                 if (priv->params.audio_cfg)
1072                         tda998x_configure_audio(priv, adjusted_mode,
1073                                                 &priv->params);
1074         }
1075 }
1076
1077 static enum drm_connector_status
1078 tda998x_encoder_detect(struct tda998x_priv *priv)
1079 {
1080         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1081
1082         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1083                         connector_status_disconnected;
1084 }
1085
1086 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1087 {
1088         struct tda998x_priv *priv = data;
1089         u8 offset, segptr;
1090         int ret, i;
1091
1092         offset = (blk & 1) ? 128 : 0;
1093         segptr = blk / 2;
1094
1095         reg_write(priv, REG_DDC_ADDR, 0xa0);
1096         reg_write(priv, REG_DDC_OFFS, offset);
1097         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1098         reg_write(priv, REG_DDC_SEGM, segptr);
1099
1100         /* enable reading EDID: */
1101         priv->wq_edid_wait = 1;
1102         reg_write(priv, REG_EDID_CTRL, 0x1);
1103
1104         /* flag must be cleared by sw: */
1105         reg_write(priv, REG_EDID_CTRL, 0x0);
1106
1107         /* wait for block read to complete: */
1108         if (priv->hdmi->irq) {
1109                 i = wait_event_timeout(priv->wq_edid,
1110                                         !priv->wq_edid_wait,
1111                                         msecs_to_jiffies(100));
1112                 if (i < 0) {
1113                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1114                         return i;
1115                 }
1116         } else {
1117                 for (i = 100; i > 0; i--) {
1118                         msleep(1);
1119                         ret = reg_read(priv, REG_INT_FLAGS_2);
1120                         if (ret < 0)
1121                                 return ret;
1122                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1123                                 break;
1124                 }
1125         }
1126
1127         if (i == 0) {
1128                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1129                 return -ETIMEDOUT;
1130         }
1131
1132         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1133         if (ret != length) {
1134                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1135                         blk, ret);
1136                 return ret;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int
1143 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1144                           struct drm_connector *connector)
1145 {
1146         struct edid *edid;
1147         int n;
1148
1149         /*
1150          * If we get killed while waiting for the HPD timeout, return
1151          * no modes found: we are not in a restartable path, so we
1152          * can't handle signals gracefully.
1153          */
1154         if (tda998x_edid_delay_wait(priv))
1155                 return 0;
1156
1157         if (priv->rev == TDA19988)
1158                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1159
1160         edid = drm_do_get_edid(connector, read_edid_block, priv);
1161
1162         if (priv->rev == TDA19988)
1163                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1164
1165         if (!edid) {
1166                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1167                 return 0;
1168         }
1169
1170         drm_mode_connector_update_edid_property(connector, edid);
1171         n = drm_add_edid_modes(connector, edid);
1172         priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1173         kfree(edid);
1174
1175         return n;
1176 }
1177
1178 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1179                                         struct drm_connector *connector)
1180 {
1181         if (priv->hdmi->irq)
1182                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1183         else
1184                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1185                         DRM_CONNECTOR_POLL_DISCONNECT;
1186 }
1187
1188 static int
1189 tda998x_encoder_set_property(struct drm_encoder *encoder,
1190                             struct drm_connector *connector,
1191                             struct drm_property *property,
1192                             uint64_t val)
1193 {
1194         DBG("");
1195         return 0;
1196 }
1197
1198 static void tda998x_destroy(struct tda998x_priv *priv)
1199 {
1200         /* disable all IRQs and free the IRQ handler */
1201         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1202         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1203
1204         if (priv->hdmi->irq)
1205                 free_irq(priv->hdmi->irq, priv);
1206
1207         del_timer_sync(&priv->edid_delay_timer);
1208         cancel_work_sync(&priv->detect_work);
1209
1210         i2c_unregister_device(priv->cec);
1211 }
1212
1213 /* Slave encoder support */
1214
1215 static void
1216 tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1217 {
1218         tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1219 }
1220
1221 static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1222 {
1223         struct tda998x_priv *priv = to_tda998x_priv(encoder);
1224
1225         tda998x_destroy(priv);
1226         drm_i2c_encoder_destroy(encoder);
1227         kfree(priv);
1228 }
1229
1230 static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1231 {
1232         tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1233 }
1234
1235 static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1236                                             struct drm_display_mode *mode)
1237 {
1238         return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1239 }
1240
1241 static void
1242 tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1243                                struct drm_display_mode *mode,
1244                                struct drm_display_mode *adjusted_mode)
1245 {
1246         tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1247 }
1248
1249 static enum drm_connector_status
1250 tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1251                              struct drm_connector *connector)
1252 {
1253         return tda998x_encoder_detect(to_tda998x_priv(encoder));
1254 }
1255
1256 static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1257                                            struct drm_connector *connector)
1258 {
1259         return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
1260 }
1261
1262 static int
1263 tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1264                                        struct drm_connector *connector)
1265 {
1266         tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
1267         return 0;
1268 }
1269
1270 static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1271         .set_config = tda998x_encoder_slave_set_config,
1272         .destroy = tda998x_encoder_slave_destroy,
1273         .dpms = tda998x_encoder_slave_dpms,
1274         .save = tda998x_encoder_save,
1275         .restore = tda998x_encoder_restore,
1276         .mode_fixup = tda998x_encoder_mode_fixup,
1277         .mode_valid = tda998x_encoder_slave_mode_valid,
1278         .mode_set = tda998x_encoder_slave_mode_set,
1279         .detect = tda998x_encoder_slave_detect,
1280         .get_modes = tda998x_encoder_slave_get_modes,
1281         .create_resources = tda998x_encoder_slave_create_resources,
1282         .set_property = tda998x_encoder_set_property,
1283 };
1284
1285 /* I2C driver functions */
1286
1287 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1288 {
1289         struct device_node *np = client->dev.of_node;
1290         u32 video;
1291         int rev_lo, rev_hi, ret;
1292         unsigned short cec_addr;
1293
1294         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1295         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1296         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1297
1298         priv->current_page = 0xff;
1299         priv->hdmi = client;
1300         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1301         cec_addr = 0x34 + (client->addr & 0x03);
1302         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1303         if (!priv->cec)
1304                 return -ENODEV;
1305
1306         priv->dpms = DRM_MODE_DPMS_OFF;
1307
1308         mutex_init(&priv->mutex);       /* protect the page access */
1309         init_waitqueue_head(&priv->edid_delay_waitq);
1310         setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1311                     (unsigned long)priv);
1312         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1313
1314         /* wake up the device: */
1315         cec_write(priv, REG_CEC_ENAMODS,
1316                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1317
1318         tda998x_reset(priv);
1319
1320         /* read version: */
1321         rev_lo = reg_read(priv, REG_VERSION_LSB);
1322         rev_hi = reg_read(priv, REG_VERSION_MSB);
1323         if (rev_lo < 0 || rev_hi < 0) {
1324                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1325                 goto fail;
1326         }
1327
1328         priv->rev = rev_lo | rev_hi << 8;
1329
1330         /* mask off feature bits: */
1331         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1332
1333         switch (priv->rev) {
1334         case TDA9989N2:
1335                 dev_info(&client->dev, "found TDA9989 n2");
1336                 break;
1337         case TDA19989:
1338                 dev_info(&client->dev, "found TDA19989");
1339                 break;
1340         case TDA19989N2:
1341                 dev_info(&client->dev, "found TDA19989 n2");
1342                 break;
1343         case TDA19988:
1344                 dev_info(&client->dev, "found TDA19988");
1345                 break;
1346         default:
1347                 dev_err(&client->dev, "found unsupported device: %04x\n",
1348                         priv->rev);
1349                 goto fail;
1350         }
1351
1352         /* after reset, enable DDC: */
1353         reg_write(priv, REG_DDC_DISABLE, 0x00);
1354
1355         /* set clock on DDC channel: */
1356         reg_write(priv, REG_TX3, 39);
1357
1358         /* if necessary, disable multi-master: */
1359         if (priv->rev == TDA19989)
1360                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1361
1362         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1363                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1364
1365         /* initialize the optional IRQ */
1366         if (client->irq) {
1367                 int irqf_trigger;
1368
1369                 /* init read EDID waitqueue and HDP work */
1370                 init_waitqueue_head(&priv->wq_edid);
1371
1372                 /* clear pending interrupts */
1373                 reg_read(priv, REG_INT_FLAGS_0);
1374                 reg_read(priv, REG_INT_FLAGS_1);
1375                 reg_read(priv, REG_INT_FLAGS_2);
1376
1377                 irqf_trigger =
1378                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1379                 ret = request_threaded_irq(client->irq, NULL,
1380                                            tda998x_irq_thread,
1381                                            irqf_trigger | IRQF_ONESHOT,
1382                                            "tda998x", priv);
1383                 if (ret) {
1384                         dev_err(&client->dev,
1385                                 "failed to request IRQ#%u: %d\n",
1386                                 client->irq, ret);
1387                         goto fail;
1388                 }
1389
1390                 /* enable HPD irq */
1391                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1392         }
1393
1394         /* enable EDID read irq: */
1395         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1396
1397         if (!np)
1398                 return 0;               /* non-DT */
1399
1400         /* get the optional video properties */
1401         ret = of_property_read_u32(np, "video-ports", &video);
1402         if (ret == 0) {
1403                 priv->vip_cntrl_0 = video >> 16;
1404                 priv->vip_cntrl_1 = video >> 8;
1405                 priv->vip_cntrl_2 = video;
1406         }
1407
1408         return 0;
1409
1410 fail:
1411         /* if encoder_init fails, the encoder slave is never registered,
1412          * so cleanup here:
1413          */
1414         if (priv->cec)
1415                 i2c_unregister_device(priv->cec);
1416         return -ENXIO;
1417 }
1418
1419 static int tda998x_encoder_init(struct i2c_client *client,
1420                                 struct drm_device *dev,
1421                                 struct drm_encoder_slave *encoder_slave)
1422 {
1423         struct tda998x_priv *priv;
1424         int ret;
1425
1426         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1427         if (!priv)
1428                 return -ENOMEM;
1429
1430         priv->encoder = &encoder_slave->base;
1431
1432         ret = tda998x_create(client, priv);
1433         if (ret) {
1434                 kfree(priv);
1435                 return ret;
1436         }
1437
1438         encoder_slave->slave_priv = priv;
1439         encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1440
1441         return 0;
1442 }
1443
1444 struct tda998x_priv2 {
1445         struct tda998x_priv base;
1446         struct drm_encoder encoder;
1447         struct drm_connector connector;
1448 };
1449
1450 #define conn_to_tda998x_priv2(x) \
1451         container_of(x, struct tda998x_priv2, connector);
1452
1453 #define enc_to_tda998x_priv2(x) \
1454         container_of(x, struct tda998x_priv2, encoder);
1455
1456 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1457 {
1458         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1459
1460         tda998x_encoder_dpms(&priv->base, mode);
1461 }
1462
1463 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1464 {
1465         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1466 }
1467
1468 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1469 {
1470         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1471 }
1472
1473 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1474                                       struct drm_display_mode *mode,
1475                                       struct drm_display_mode *adjusted_mode)
1476 {
1477         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1478
1479         tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1480 }
1481
1482 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1483         .dpms = tda998x_encoder2_dpms,
1484         .save = tda998x_encoder_save,
1485         .restore = tda998x_encoder_restore,
1486         .mode_fixup = tda998x_encoder_mode_fixup,
1487         .prepare = tda998x_encoder_prepare,
1488         .commit = tda998x_encoder_commit,
1489         .mode_set = tda998x_encoder2_mode_set,
1490 };
1491
1492 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1493 {
1494         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1495
1496         tda998x_destroy(&priv->base);
1497         drm_encoder_cleanup(encoder);
1498 }
1499
1500 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1501         .destroy = tda998x_encoder_destroy,
1502 };
1503
1504 static int tda998x_connector_get_modes(struct drm_connector *connector)
1505 {
1506         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1507
1508         return tda998x_encoder_get_modes(&priv->base, connector);
1509 }
1510
1511 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1512                                         struct drm_display_mode *mode)
1513 {
1514         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1515
1516         return tda998x_encoder_mode_valid(&priv->base, mode);
1517 }
1518
1519 static struct drm_encoder *
1520 tda998x_connector_best_encoder(struct drm_connector *connector)
1521 {
1522         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1523
1524         return &priv->encoder;
1525 }
1526
1527 static
1528 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1529         .get_modes = tda998x_connector_get_modes,
1530         .mode_valid = tda998x_connector_mode_valid,
1531         .best_encoder = tda998x_connector_best_encoder,
1532 };
1533
1534 static enum drm_connector_status
1535 tda998x_connector_detect(struct drm_connector *connector, bool force)
1536 {
1537         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1538
1539         return tda998x_encoder_detect(&priv->base);
1540 }
1541
1542 static void tda998x_connector_destroy(struct drm_connector *connector)
1543 {
1544         drm_connector_unregister(connector);
1545         drm_connector_cleanup(connector);
1546 }
1547
1548 static const struct drm_connector_funcs tda998x_connector_funcs = {
1549         .dpms = drm_helper_connector_dpms,
1550         .fill_modes = drm_helper_probe_single_connector_modes,
1551         .detect = tda998x_connector_detect,
1552         .destroy = tda998x_connector_destroy,
1553 };
1554
1555 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1556 {
1557         struct tda998x_encoder_params *params = dev->platform_data;
1558         struct i2c_client *client = to_i2c_client(dev);
1559         struct drm_device *drm = data;
1560         struct tda998x_priv2 *priv;
1561         u32 crtcs = 0;
1562         int ret;
1563
1564         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1565         if (!priv)
1566                 return -ENOMEM;
1567
1568         dev_set_drvdata(dev, priv);
1569
1570         if (dev->of_node)
1571                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1572
1573         /* If no CRTCs were found, fall back to our old behaviour */
1574         if (crtcs == 0) {
1575                 dev_warn(dev, "Falling back to first CRTC\n");
1576                 crtcs = 1 << 0;
1577         }
1578
1579         priv->base.encoder = &priv->encoder;
1580         priv->connector.interlace_allowed = 1;
1581         priv->encoder.possible_crtcs = crtcs;
1582
1583         ret = tda998x_create(client, &priv->base);
1584         if (ret)
1585                 return ret;
1586
1587         if (!dev->of_node && params)
1588                 tda998x_encoder_set_config(&priv->base, params);
1589
1590         tda998x_encoder_set_polling(&priv->base, &priv->connector);
1591
1592         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1593         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1594                                DRM_MODE_ENCODER_TMDS);
1595         if (ret)
1596                 goto err_encoder;
1597
1598         drm_connector_helper_add(&priv->connector,
1599                                  &tda998x_connector_helper_funcs);
1600         ret = drm_connector_init(drm, &priv->connector,
1601                                  &tda998x_connector_funcs,
1602                                  DRM_MODE_CONNECTOR_HDMIA);
1603         if (ret)
1604                 goto err_connector;
1605
1606         ret = drm_connector_register(&priv->connector);
1607         if (ret)
1608                 goto err_sysfs;
1609
1610         priv->connector.encoder = &priv->encoder;
1611         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1612
1613         return 0;
1614
1615 err_sysfs:
1616         drm_connector_cleanup(&priv->connector);
1617 err_connector:
1618         drm_encoder_cleanup(&priv->encoder);
1619 err_encoder:
1620         tda998x_destroy(&priv->base);
1621         return ret;
1622 }
1623
1624 static void tda998x_unbind(struct device *dev, struct device *master,
1625                            void *data)
1626 {
1627         struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1628
1629         drm_connector_cleanup(&priv->connector);
1630         drm_encoder_cleanup(&priv->encoder);
1631         tda998x_destroy(&priv->base);
1632 }
1633
1634 static const struct component_ops tda998x_ops = {
1635         .bind = tda998x_bind,
1636         .unbind = tda998x_unbind,
1637 };
1638
1639 static int
1640 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1641 {
1642         return component_add(&client->dev, &tda998x_ops);
1643 }
1644
1645 static int tda998x_remove(struct i2c_client *client)
1646 {
1647         component_del(&client->dev, &tda998x_ops);
1648         return 0;
1649 }
1650
1651 #ifdef CONFIG_OF
1652 static const struct of_device_id tda998x_dt_ids[] = {
1653         { .compatible = "nxp,tda998x", },
1654         { }
1655 };
1656 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1657 #endif
1658
1659 static struct i2c_device_id tda998x_ids[] = {
1660         { "tda998x", 0 },
1661         { }
1662 };
1663 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1664
1665 static struct drm_i2c_encoder_driver tda998x_driver = {
1666         .i2c_driver = {
1667                 .probe = tda998x_probe,
1668                 .remove = tda998x_remove,
1669                 .driver = {
1670                         .name = "tda998x",
1671                         .of_match_table = of_match_ptr(tda998x_dt_ids),
1672                 },
1673                 .id_table = tda998x_ids,
1674         },
1675         .encoder_init = tda998x_encoder_init,
1676 };
1677
1678 /* Module initialization */
1679
1680 static int __init
1681 tda998x_init(void)
1682 {
1683         DBG("");
1684         return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1685 }
1686
1687 static void __exit
1688 tda998x_exit(void)
1689 {
1690         DBG("");
1691         drm_i2c_encoder_unregister(&tda998x_driver);
1692 }
1693
1694 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1695 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1696 MODULE_LICENSE("GPL");
1697
1698 module_init(tda998x_init);
1699 module_exit(tda998x_exit);