drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_of.h>
  28 #include <drm/i2c/tda998x.h>
  29
  30 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  31
  32 struct tda998x_priv {
  33         struct i2c_client *cec;
  34         struct i2c_client *hdmi;
  35         struct mutex mutex;
  36         u16 rev;
  37         u8 current_page;
  38         int dpms;
  39         bool is_hdmi_sink;
  40         u8 vip_cntrl_0;
  41         u8 vip_cntrl_1;
  42         u8 vip_cntrl_2;
  43         struct tda998x_encoder_params params;
  44
  45         wait_queue_head_t wq_edid;
  46         volatile int wq_edid_wait;
  47
  48         struct work_struct detect_work;
  49         struct timer_list edid_delay_timer;
  50         wait_queue_head_t edid_delay_waitq;
  51         bool edid_delay_active;
  52
  53         struct drm_encoder encoder;
  54         struct drm_connector connector;
  55 };
  56
  57 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  58  * things we encode the page # in upper bits of the register #.  To read/
  59  * write a given register, we need to make sure CURPAGE register is set
  60  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  61  */
  62
  63 #define REG(page, addr) (((page) << 8) | (addr))
  64 #define REG2ADDR(reg)   ((reg) & 0xff)
  65 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  66
  67 #define REG_CURPAGE               0xff                /* write */
  68
  69
  70 /* Page 00h: General Control */
  71 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  72 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  73 # define MAIN_CNTRL0_SR           (1 << 0)
  74 # define MAIN_CNTRL0_DECS         (1 << 1)
  75 # define MAIN_CNTRL0_DEHS         (1 << 2)
  76 # define MAIN_CNTRL0_CECS         (1 << 3)
  77 # define MAIN_CNTRL0_CEHS         (1 << 4)
  78 # define MAIN_CNTRL0_SCALER       (1 << 7)
  79 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  80 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  81 # define SOFTRESET_AUDIO          (1 << 0)
  82 # define SOFTRESET_I2C_MASTER     (1 << 1)
  83 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  84 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  85 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  86 # define I2C_MASTER_DIS_MM        (1 << 0)
  87 # define I2C_MASTER_DIS_FILT      (1 << 1)
  88 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  89 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  90 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  91 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  92 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  93 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  94 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  95 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  96 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  97 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  98 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
  99 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 100 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 101 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 102 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 103 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 104 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 105 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 106 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 107 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 108 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 109 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 110 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 111 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 112 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 113 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 114 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 115 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 116 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 117 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 118 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 119 # define VIP_CNTRL_3_EMB          (1 << 3)
 120 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 121 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 122 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 123 # define VIP_CNTRL_3_EDGE         (1 << 7)
 124 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 125 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 126 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 127 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 128 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 129 # define VIP_CNTRL_4_TST_656      (1 << 6)
 130 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 131 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 132 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 133 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 134 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 135 # define MUX_AP_SELECT_I2S        0x64
 136 # define MUX_AP_SELECT_SPDIF      0x40
 137 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 138 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 139 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 140 # define MAT_CONTRL_MAT_BP        (1 << 2)
 141 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 142 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 143 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 144 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 145 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 146 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 147 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 148 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 149 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 150 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 151 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 152 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 153 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 154 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 155 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 156 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 157 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 158 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 159 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 160 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 161 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 162 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 163 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 164 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 165 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 166 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 167 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 168 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 169 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 170 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 171 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 172 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 173 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 174 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 175 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 176 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 177 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 178 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 179 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 180 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 181 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 182 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 183 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 184 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 185 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 186 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 187 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 188 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 189 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 190 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 191 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 192 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 193 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 194 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 195 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 196 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 197 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 198 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 199 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 200 # define HVF_CNTRL_0_SM           (1 << 7)
 201 # define HVF_CNTRL_0_RWB          (1 << 6)
 202 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 203 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 204 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 205 # define HVF_CNTRL_1_FOR          (1 << 0)
 206 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 207 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 208 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 209 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 210 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 211 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 212 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 213 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 214 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 215 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 216 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 217 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 218 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 219
 220 /* Page 02h: PLL settings */
 221 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 222 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 223 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 224 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 225 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 226 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 227 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 228 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 229 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 230 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 231 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 232 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 233 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 234 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 235 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 236 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 237 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 238 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 239 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 240 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 241 # define AUDIO_DIV_SERCLK_1       0
 242 # define AUDIO_DIV_SERCLK_2       1
 243 # define AUDIO_DIV_SERCLK_4       2
 244 # define AUDIO_DIV_SERCLK_8       3
 245 # define AUDIO_DIV_SERCLK_16      4
 246 # define AUDIO_DIV_SERCLK_32      5
 247 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 248 # define SEL_CLK_SEL_CLK1         (1 << 0)
 249 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 250 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 251 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 252
 253
 254 /* Page 09h: EDID Control */
 255 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 256 /* next 127 successive registers are the EDID block */
 257 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 258 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 259 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 260 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 261 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 262
 263
 264 /* Page 10h: information frames and packets */
 265 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 266 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 267 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 268 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 269 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 270
 271
 272 /* Page 11h: audio settings and content info packets */
 273 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 274 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 275 # define AIP_CNTRL_0_SWAP         (1 << 1)
 276 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 277 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 278 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 279 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 280 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 281 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 282 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 283 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 284 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 285 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 286 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 287 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 288 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 289 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 290 # define CTS_N_K(x)               (((x) & 7) << 0)
 291 # define CTS_N_M(x)               (((x) & 3) << 4)
 292 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 293 # define ENC_CNTRL_RST_ENC        (1 << 0)
 294 # define ENC_CNTRL_RST_SEL        (1 << 1)
 295 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 296 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 297 # define DIP_FLAGS_ACR            (1 << 0)
 298 # define DIP_FLAGS_GC             (1 << 1)
 299 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 300 # define DIP_IF_FLAGS_IF1         (1 << 1)
 301 # define DIP_IF_FLAGS_IF2         (1 << 2)
 302 # define DIP_IF_FLAGS_IF3         (1 << 3)
 303 # define DIP_IF_FLAGS_IF4         (1 << 4)
 304 # define DIP_IF_FLAGS_IF5         (1 << 5)
 305 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 306
 307
 308 /* Page 12h: HDCP and OTP */
 309 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 310 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 311 # define TX4_PD_RAM               (1 << 1)
 312 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 313 # define TX33_HDMI                (1 << 1)
 314
 315
 316 /* Page 13h: Gamut related metadata packets */
 317
 318
 319
 320 /* CEC registers: (not paged)
 321  */
 322 #define REG_CEC_INTSTATUS         0xee                /* read */
 323 # define CEC_INTSTATUS_CEC        (1 << 0)
 324 # define CEC_INTSTATUS_HDMI       (1 << 1)
 325 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 326 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 327 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 328 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 329 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 330 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 331 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 332 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 333 # define CEC_RXSHPDINT_HPD        BIT(1)
 334 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 335 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 336 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 337
 338 #define REG_CEC_ENAMODS           0xff                /* read/write */
 339 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 340 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 341 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 342 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 343 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 344
 345
 346 /* Device versions: */
 347 #define TDA9989N2                 0x0101
 348 #define TDA19989                  0x0201
 349 #define TDA19989N2                0x0202
 350 #define TDA19988                  0x0301
 351
 352 static void
 353 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 354 {
 355         struct i2c_client *client = priv->cec;
 356         u8 buf[] = {addr, val};
 357         int ret;
 358
 359         ret = i2c_master_send(client, buf, sizeof(buf));
 360         if (ret < 0)
 361                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 362 }
 363
 364 static u8
 365 cec_read(struct tda998x_priv *priv, u8 addr)
 366 {
 367         struct i2c_client *client = priv->cec;
 368         u8 val;
 369         int ret;
 370
 371         ret = i2c_master_send(client, &addr, sizeof(addr));
 372         if (ret < 0)
 373                 goto fail;
 374
 375         ret = i2c_master_recv(client, &val, sizeof(val));
 376         if (ret < 0)
 377                 goto fail;
 378
 379         return val;
 380
 381 fail:
 382         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 383         return 0;
 384 }
 385
 386 static int
 387 set_page(struct tda998x_priv *priv, u16 reg)
 388 {
 389         if (REG2PAGE(reg) != priv->current_page) {
 390                 struct i2c_client *client = priv->hdmi;
 391                 u8 buf[] = {
 392                                 REG_CURPAGE, REG2PAGE(reg)
 393                 };
 394                 int ret = i2c_master_send(client, buf, sizeof(buf));
 395                 if (ret < 0) {
 396                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 397                                         reg, ret);
 398                         return ret;
 399                 }
 400
 401                 priv->current_page = REG2PAGE(reg);
 402         }
 403         return 0;
 404 }
 405
 406 static int
 407 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 408 {
 409         struct i2c_client *client = priv->hdmi;
 410         u8 addr = REG2ADDR(reg);
 411         int ret;
 412
 413         mutex_lock(&priv->mutex);
 414         ret = set_page(priv, reg);
 415         if (ret < 0)
 416                 goto out;
 417
 418         ret = i2c_master_send(client, &addr, sizeof(addr));
 419         if (ret < 0)
 420                 goto fail;
 421
 422         ret = i2c_master_recv(client, buf, cnt);
 423         if (ret < 0)
 424                 goto fail;
 425
 426         goto out;
 427
 428 fail:
 429         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 430 out:
 431         mutex_unlock(&priv->mutex);
 432         return ret;
 433 }
 434
 435 static void
 436 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 437 {
 438         struct i2c_client *client = priv->hdmi;
 439         u8 buf[cnt+1];
 440         int ret;
 441
 442         buf[0] = REG2ADDR(reg);
 443         memcpy(&buf[1], p, cnt);
 444
 445         mutex_lock(&priv->mutex);
 446         ret = set_page(priv, reg);
 447         if (ret < 0)
 448                 goto out;
 449
 450         ret = i2c_master_send(client, buf, cnt + 1);
 451         if (ret < 0)
 452                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 453 out:
 454         mutex_unlock(&priv->mutex);
 455 }
 456
 457 static int
 458 reg_read(struct tda998x_priv *priv, u16 reg)
 459 {
 460         u8 val = 0;
 461         int ret;
 462
 463         ret = reg_read_range(priv, reg, &val, sizeof(val));
 464         if (ret < 0)
 465                 return ret;
 466         return val;
 467 }
 468
 469 static void
 470 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 471 {
 472         struct i2c_client *client = priv->hdmi;
 473         u8 buf[] = {REG2ADDR(reg), val};
 474         int ret;
 475
 476         mutex_lock(&priv->mutex);
 477         ret = set_page(priv, reg);
 478         if (ret < 0)
 479                 goto out;
 480
 481         ret = i2c_master_send(client, buf, sizeof(buf));
 482         if (ret < 0)
 483                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 484 out:
 485         mutex_unlock(&priv->mutex);
 486 }
 487
 488 static void
 489 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 490 {
 491         struct i2c_client *client = priv->hdmi;
 492         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 493         int ret;
 494
 495         mutex_lock(&priv->mutex);
 496         ret = set_page(priv, reg);
 497         if (ret < 0)
 498                 goto out;
 499
 500         ret = i2c_master_send(client, buf, sizeof(buf));
 501         if (ret < 0)
 502                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 503 out:
 504         mutex_unlock(&priv->mutex);
 505 }
 506
 507 static void
 508 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 509 {
 510         int old_val;
 511
 512         old_val = reg_read(priv, reg);
 513         if (old_val >= 0)
 514                 reg_write(priv, reg, old_val | val);
 515 }
 516
 517 static void
 518 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 519 {
 520         int old_val;
 521
 522         old_val = reg_read(priv, reg);
 523         if (old_val >= 0)
 524                 reg_write(priv, reg, old_val & ~val);
 525 }
 526
 527 static void
 528 tda998x_reset(struct tda998x_priv *priv)
 529 {
 530         /* reset audio and i2c master: */
 531         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 532         msleep(50);
 533         reg_write(priv, REG_SOFTRESET, 0);
 534         msleep(50);
 535
 536         /* reset transmitter: */
 537         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 538         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 539
 540         /* PLL registers common configuration */
 541         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 542         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 543         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 544         reg_write(priv, REG_SERIALIZER,   0x00);
 545         reg_write(priv, REG_BUFFER_OUT,   0x00);
 546         reg_write(priv, REG_PLL_SCG1,     0x00);
 547         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 548         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 549         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 550         reg_write(priv, REG_PLL_SCGN2,    0x00);
 551         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 552         reg_write(priv, REG_PLL_SCGR2,    0x00);
 553         reg_write(priv, REG_PLL_SCG2,     0x10);
 554
 555         /* Write the default value MUX register */
 556         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 557 }
 558
 559 /*
 560  * The TDA998x has a problem when trying to read the EDID close to a
 561  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 562  * trying to read EDID data.
 563  *
 564  * However, tda998x_encoder_get_modes() may be called at any moment
 565  * after tda998x_encoder_detect() indicates that we are connected, so
 566  * we need to delay probing modes in tda998x_encoder_get_modes() after
 567  * we have seen a HPD inactive->active transition.  This code implements
 568  * that delay.
 569  */
 570 static void tda998x_edid_delay_done(unsigned long data)
 571 {
 572         struct tda998x_priv *priv = (struct tda998x_priv *)data;
 573
 574         priv->edid_delay_active = false;
 575         wake_up(&priv->edid_delay_waitq);
 576         schedule_work(&priv->detect_work);
 577 }
 578
 579 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 580 {
 581         priv->edid_delay_active = true;
 582         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 583 }
 584
 585 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 586 {
 587         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 588 }
 589
 590 /*
 591  * We need to run the KMS hotplug event helper outside of our threaded
 592  * interrupt routine as this can call back into our get_modes method,
 593  * which will want to make use of interrupts.
 594  */
 595 static void tda998x_detect_work(struct work_struct *work)
 596 {
 597         struct tda998x_priv *priv =
 598                 container_of(work, struct tda998x_priv, detect_work);
 599         struct drm_device *dev = priv->encoder.dev;
 600
 601         if (dev)
 602                 drm_kms_helper_hotplug_event(dev);
 603 }
 604
 605 /*
 606  * only 2 interrupts may occur: screen plug/unplug and EDID read
 607  */
 608 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 609 {
 610         struct tda998x_priv *priv = data;
 611         u8 sta, cec, lvl, flag0, flag1, flag2;
 612         bool handled = false;
 613
 614         sta = cec_read(priv, REG_CEC_INTSTATUS);
 615         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 616         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 617         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 618         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 619         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 620         DRM_DEBUG_DRIVER(
 621                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 622                 sta, cec, lvl, flag0, flag1, flag2);
 623
 624         if (cec & CEC_RXSHPDINT_HPD) {
 625                 if (lvl & CEC_RXSHPDLEV_HPD)
 626                         tda998x_edid_delay_start(priv);
 627                 else
 628                         schedule_work(&priv->detect_work);
 629
 630                 handled = true;
 631         }
 632
 633         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 634                 priv->wq_edid_wait = 0;
 635                 wake_up(&priv->wq_edid);
 636                 handled = true;
 637         }
 638
 639         return IRQ_RETVAL(handled);
 640 }
 641
 642 static void
 643 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 644                  union hdmi_infoframe *frame)
 645 {
 646         u8 buf[32];
 647         ssize_t len;
 648
 649         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 650         if (len < 0) {
 651                 dev_err(&priv->hdmi->dev,
 652                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 653                         frame->any.type, len);
 654                 return;
 655         }
 656
 657         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 658         reg_write_range(priv, addr, buf, len);
 659         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 660 }
 661
 662 static void
 663 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 664 {
 665         union hdmi_infoframe frame;
 666
 667         hdmi_audio_infoframe_init(&frame.audio);
 668
 669         frame.audio.channels = p->audio_frame[1] & 0x07;
 670         frame.audio.channel_allocation = p->audio_frame[4];
 671         frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
 672         frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
 673
 674         /*
 675          * L-PCM and IEC61937 compressed audio shall always set sample
 676          * frequency to "refer to stream".  For others, see the HDMI
 677          * specification.
 678          */
 679         frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
 680
 681         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 682 }
 683
 684 static void
 685 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 686 {
 687         union hdmi_infoframe frame;
 688
 689         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
 690         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 691
 692         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 693 }
 694
 695 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 696 {
 697         if (on) {
 698                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 699                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 700                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 701         } else {
 702                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 703         }
 704 }
 705
 706 static void
 707 tda998x_configure_audio(struct tda998x_priv *priv,
 708                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 709 {
 710         u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 711         u32 n;
 712
 713         /* Enable audio ports */
 714         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 715         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 716
 717         /* Set audio input source */
 718         switch (p->audio_format) {
 719         case AFMT_SPDIF:
 720                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 721                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 722                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 723                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 724                 break;
 725
 726         case AFMT_I2S:
 727                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 728                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 729                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 730                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 731                 break;
 732
 733         default:
 734                 BUG();
 735                 return;
 736         }
 737
 738         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 739         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 740                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 741         reg_write(priv, REG_CTS_N, cts_n);
 742
 743         /*
 744          * Audio input somehow depends on HDMI line rate which is
 745          * related to pixclk. Testing showed that modes with pixclk
 746          * >100MHz need a larger divider while <40MHz need the default.
 747          * There is no detailed info in the datasheet, so we just
 748          * assume 100MHz requires larger divider.
 749          */
 750         adiv = AUDIO_DIV_SERCLK_8;
 751         if (mode->clock > 100000)
 752                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 753
 754         /* S/PDIF asks for a larger divider */
 755         if (p->audio_format == AFMT_SPDIF)
 756                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 757
 758         reg_write(priv, REG_AUDIO_DIV, adiv);
 759
 760         /*
 761          * This is the approximate value of N, which happens to be
 762          * the recommended values for non-coherent clocks.
 763          */
 764         n = 128 * p->audio_sample_rate / 1000;
 765
 766         /* Write the CTS and N values */
 767         buf[0] = 0x44;
 768         buf[1] = 0x42;
 769         buf[2] = 0x01;
 770         buf[3] = n;
 771         buf[4] = n >> 8;
 772         buf[5] = n >> 16;
 773         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 774
 775         /* Set CTS clock reference */
 776         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 777
 778         /* Reset CTS generator */
 779         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 780         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 781
 782         /* Write the channel status */
 783         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 784         buf[1] = 0x00;
 785         buf[2] = IEC958_AES3_CON_FS_NOTID;
 786         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 787                         IEC958_AES4_CON_MAX_WORDLEN_24;
 788         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 789
 790         tda998x_audio_mute(priv, true);
 791         msleep(20);
 792         tda998x_audio_mute(priv, false);
 793
 794         /* Write the audio information packet */
 795         tda998x_write_aif(priv, p);
 796 }
 797
 798 /* DRM encoder functions */
 799
 800 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 801                                        const struct tda998x_encoder_params *p)
 802 {
 803         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 804                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 805                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 806                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 807         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 808                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 809                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 810                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 811         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 812                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 813                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 814                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 815
 816         priv->params = *p;
 817 }
 818
 819 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 820 {
 821         /* we only care about on or off: */
 822         if (mode != DRM_MODE_DPMS_ON)
 823                 mode = DRM_MODE_DPMS_OFF;
 824
 825         if (mode == priv->dpms)
 826                 return;
 827
 828         switch (mode) {
 829         case DRM_MODE_DPMS_ON:
 830                 /* enable video ports, audio will be enabled later */
 831                 reg_write(priv, REG_ENA_VP_0, 0xff);
 832                 reg_write(priv, REG_ENA_VP_1, 0xff);
 833                 reg_write(priv, REG_ENA_VP_2, 0xff);
 834                 /* set muxing after enabling ports: */
 835                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 836                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 837                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 838                 break;
 839         case DRM_MODE_DPMS_OFF:
 840                 /* disable video ports */
 841                 reg_write(priv, REG_ENA_VP_0, 0x00);
 842                 reg_write(priv, REG_ENA_VP_1, 0x00);
 843                 reg_write(priv, REG_ENA_VP_2, 0x00);
 844                 break;
 845         }
 846
 847         priv->dpms = mode;
 848 }
 849
 850 static void
 851 tda998x_encoder_save(struct drm_encoder *encoder)
 852 {
 853         DBG("");
 854 }
 855
 856 static void
 857 tda998x_encoder_restore(struct drm_encoder *encoder)
 858 {
 859         DBG("");
 860 }
 861
 862 static bool
 863 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 864                           const struct drm_display_mode *mode,
 865                           struct drm_display_mode *adjusted_mode)
 866 {
 867         return true;
 868 }
 869
 870 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 871                                       struct drm_display_mode *mode)
 872 {
 873         if (mode->clock > 150000)
 874                 return MODE_CLOCK_HIGH;
 875         if (mode->htotal >= BIT(13))
 876                 return MODE_BAD_HVALUE;
 877         if (mode->vtotal >= BIT(11))
 878                 return MODE_BAD_VVALUE;
 879         return MODE_OK;
 880 }
 881
 882 static void
 883 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 884                          struct drm_display_mode *mode,
 885                          struct drm_display_mode *adjusted_mode)
 886 {
 887         u16 ref_pix, ref_line, n_pix, n_line;
 888         u16 hs_pix_s, hs_pix_e;
 889         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 890         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 891         u16 vwin1_line_s, vwin1_line_e;
 892         u16 vwin2_line_s, vwin2_line_e;
 893         u16 de_pix_s, de_pix_e;
 894         u8 reg, div, rep;
 895
 896         /*
 897          * Internally TDA998x is using ITU-R BT.656 style sync but
 898          * we get VESA style sync. TDA998x is using a reference pixel
 899          * relative to ITU to sync to the input frame and for output
 900          * sync generation. Currently, we are using reference detection
 901          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 902          * which is position of rising VS with coincident rising HS.
 903          *
 904          * Now there is some issues to take care of:
 905          * - HDMI data islands require sync-before-active
 906          * - TDA998x register values must be > 0 to be enabled
 907          * - REFLINE needs an additional offset of +1
 908          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 909          *
 910          * So we add +1 to all horizontal and vertical register values,
 911          * plus an additional +3 for REFPIX as we are using RGB input only.
 912          */
 913         n_pix        = mode->htotal;
 914         n_line       = mode->vtotal;
 915
 916         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 917         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 918         de_pix_e     = mode->htotal;
 919         de_pix_s     = mode->htotal - mode->hdisplay;
 920         ref_pix      = 3 + hs_pix_s;
 921
 922         /*
 923          * Attached LCD controllers may generate broken sync. Allow
 924          * those to adjust the position of the rising VS edge by adding
 925          * HSKEW to ref_pix.
 926          */
 927         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 928                 ref_pix += adjusted_mode->hskew;
 929
 930         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 931                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 932                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 933                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 934                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 935                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 936                 vs1_line_e   = vs1_line_s +
 937                                mode->vsync_end - mode->vsync_start;
 938                 vwin2_line_s = vwin2_line_e = 0;
 939                 vs2_pix_s    = vs2_pix_e  = 0;
 940                 vs2_line_s   = vs2_line_e = 0;
 941         } else {
 942                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 943                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 944                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 945                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 946                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 947                 vs1_line_e   = vs1_line_s +
 948                                (mode->vsync_end - mode->vsync_start)/2;
 949                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 950                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 951                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 952                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 953                 vs2_line_e   = vs2_line_s +
 954                                (mode->vsync_end - mode->vsync_start)/2;
 955         }
 956
 957         div = 148500 / mode->clock;
 958         if (div != 0) {
 959                 div--;
 960                 if (div > 3)
 961                         div = 3;
 962         }
 963
 964         /* mute the audio FIFO: */
 965         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 966
 967         /* set HDMI HDCP mode off: */
 968         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 969         reg_clear(priv, REG_TX33, TX33_HDMI);
 970         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 971
 972         /* no pre-filter or interpolator: */
 973         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 974                         HVF_CNTRL_0_INTPOL(0));
 975         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 976         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 977                         VIP_CNTRL_4_BLC(0));
 978
 979         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 980         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 981                                           PLL_SERIAL_3_SRL_DE);
 982         reg_write(priv, REG_SERIALIZER, 0);
 983         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 984
 985         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 986         rep = 0;
 987         reg_write(priv, REG_RPT_CNTRL, 0);
 988         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 989                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 990
 991         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
 992                         PLL_SERIAL_2_SRL_PR(rep));
 993
 994         /* set color matrix bypass flag: */
 995         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
 996                                 MAT_CONTRL_MAT_SC(1));
 997
 998         /* set BIAS tmds value: */
 999         reg_write(priv, REG_ANA_GENERAL, 0x09);
1000
1001         /*
1002          * Sync on rising HSYNC/VSYNC
1003          */
1004         reg = VIP_CNTRL_3_SYNC_HS;
1005
1006         /*
1007          * TDA19988 requires high-active sync at input stage,
1008          * so invert low-active sync provided by master encoder here
1009          */
1010         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1011                 reg |= VIP_CNTRL_3_H_TGL;
1012         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1013                 reg |= VIP_CNTRL_3_V_TGL;
1014         reg_write(priv, REG_VIP_CNTRL_3, reg);
1015
1016         reg_write(priv, REG_VIDFORMAT, 0x00);
1017         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1018         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1019         reg_write16(priv, REG_NPIX_MSB, n_pix);
1020         reg_write16(priv, REG_NLINE_MSB, n_line);
1021         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1022         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1023         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1024         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1025         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1026         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1027         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1028         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1029         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1030         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1031         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1032         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1033         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1034         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1035         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1036         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1037
1038         if (priv->rev == TDA19988) {
1039                 /* let incoming pixels fill the active space (if any) */
1040                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1041         }
1042
1043         /*
1044          * Always generate sync polarity relative to input sync and
1045          * revert input stage toggled sync at output stage
1046          */
1047         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1048         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1049                 reg |= TBG_CNTRL_1_H_TGL;
1050         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1051                 reg |= TBG_CNTRL_1_V_TGL;
1052         reg_write(priv, REG_TBG_CNTRL_1, reg);
1053
1054         /* must be last register set: */
1055         reg_write(priv, REG_TBG_CNTRL_0, 0);
1056
1057         /* Only setup the info frames if the sink is HDMI */
1058         if (priv->is_hdmi_sink) {
1059                 /* We need to turn HDMI HDCP stuff on to get audio through */
1060                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1061                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1062                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1063                 reg_set(priv, REG_TX33, TX33_HDMI);
1064
1065                 tda998x_write_avi(priv, adjusted_mode);
1066
1067                 if (priv->params.audio_cfg)
1068                         tda998x_configure_audio(priv, adjusted_mode,
1069                                                 &priv->params);
1070         }
1071 }
1072
1073 static enum drm_connector_status
1074 tda998x_encoder_detect(struct tda998x_priv *priv)
1075 {
1076         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1077
1078         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1079                         connector_status_disconnected;
1080 }
1081
1082 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1083 {
1084         struct tda998x_priv *priv = data;
1085         u8 offset, segptr;
1086         int ret, i;
1087
1088         offset = (blk & 1) ? 128 : 0;
1089         segptr = blk / 2;
1090
1091         reg_write(priv, REG_DDC_ADDR, 0xa0);
1092         reg_write(priv, REG_DDC_OFFS, offset);
1093         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1094         reg_write(priv, REG_DDC_SEGM, segptr);
1095
1096         /* enable reading EDID: */
1097         priv->wq_edid_wait = 1;
1098         reg_write(priv, REG_EDID_CTRL, 0x1);
1099
1100         /* flag must be cleared by sw: */
1101         reg_write(priv, REG_EDID_CTRL, 0x0);
1102
1103         /* wait for block read to complete: */
1104         if (priv->hdmi->irq) {
1105                 i = wait_event_timeout(priv->wq_edid,
1106                                         !priv->wq_edid_wait,
1107                                         msecs_to_jiffies(100));
1108                 if (i < 0) {
1109                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1110                         return i;
1111                 }
1112         } else {
1113                 for (i = 100; i > 0; i--) {
1114                         msleep(1);
1115                         ret = reg_read(priv, REG_INT_FLAGS_2);
1116                         if (ret < 0)
1117                                 return ret;
1118                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1119                                 break;
1120                 }
1121         }
1122
1123         if (i == 0) {
1124                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1125                 return -ETIMEDOUT;
1126         }
1127
1128         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1129         if (ret != length) {
1130                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1131                         blk, ret);
1132                 return ret;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int
1139 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1140                           struct drm_connector *connector)
1141 {
1142         struct edid *edid;
1143         int n;
1144
1145         /*
1146          * If we get killed while waiting for the HPD timeout, return
1147          * no modes found: we are not in a restartable path, so we
1148          * can't handle signals gracefully.
1149          */
1150         if (tda998x_edid_delay_wait(priv))
1151                 return 0;
1152
1153         if (priv->rev == TDA19988)
1154                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1155
1156         edid = drm_do_get_edid(connector, read_edid_block, priv);
1157
1158         if (priv->rev == TDA19988)
1159                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1160
1161         if (!edid) {
1162                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1163                 return 0;
1164         }
1165
1166         drm_mode_connector_update_edid_property(connector, edid);
1167         n = drm_add_edid_modes(connector, edid);
1168         priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1169         kfree(edid);
1170
1171         return n;
1172 }
1173
1174 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1175                                         struct drm_connector *connector)
1176 {
1177         if (priv->hdmi->irq)
1178                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1179         else
1180                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1181                         DRM_CONNECTOR_POLL_DISCONNECT;
1182 }
1183
1184 static void tda998x_destroy(struct tda998x_priv *priv)
1185 {
1186         /* disable all IRQs and free the IRQ handler */
1187         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1188         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1189
1190         if (priv->hdmi->irq)
1191                 free_irq(priv->hdmi->irq, priv);
1192
1193         del_timer_sync(&priv->edid_delay_timer);
1194         cancel_work_sync(&priv->detect_work);
1195
1196         i2c_unregister_device(priv->cec);
1197 }
1198
1199 /* I2C driver functions */
1200
1201 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1202 {
1203         struct device_node *np = client->dev.of_node;
1204         u32 video;
1205         int rev_lo, rev_hi, ret;
1206         unsigned short cec_addr;
1207
1208         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1209         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1210         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1211
1212         priv->current_page = 0xff;
1213         priv->hdmi = client;
1214         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1215         cec_addr = 0x34 + (client->addr & 0x03);
1216         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1217         if (!priv->cec)
1218                 return -ENODEV;
1219
1220         priv->dpms = DRM_MODE_DPMS_OFF;
1221
1222         mutex_init(&priv->mutex);       /* protect the page access */
1223         init_waitqueue_head(&priv->edid_delay_waitq);
1224         setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1225                     (unsigned long)priv);
1226         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1227
1228         /* wake up the device: */
1229         cec_write(priv, REG_CEC_ENAMODS,
1230                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1231
1232         tda998x_reset(priv);
1233
1234         /* read version: */
1235         rev_lo = reg_read(priv, REG_VERSION_LSB);
1236         rev_hi = reg_read(priv, REG_VERSION_MSB);
1237         if (rev_lo < 0 || rev_hi < 0) {
1238                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1239                 goto fail;
1240         }
1241
1242         priv->rev = rev_lo | rev_hi << 8;
1243
1244         /* mask off feature bits: */
1245         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1246
1247         switch (priv->rev) {
1248         case TDA9989N2:
1249                 dev_info(&client->dev, "found TDA9989 n2");
1250                 break;
1251         case TDA19989:
1252                 dev_info(&client->dev, "found TDA19989");
1253                 break;
1254         case TDA19989N2:
1255                 dev_info(&client->dev, "found TDA19989 n2");
1256                 break;
1257         case TDA19988:
1258                 dev_info(&client->dev, "found TDA19988");
1259                 break;
1260         default:
1261                 dev_err(&client->dev, "found unsupported device: %04x\n",
1262                         priv->rev);
1263                 goto fail;
1264         }
1265
1266         /* after reset, enable DDC: */
1267         reg_write(priv, REG_DDC_DISABLE, 0x00);
1268
1269         /* set clock on DDC channel: */
1270         reg_write(priv, REG_TX3, 39);
1271
1272         /* if necessary, disable multi-master: */
1273         if (priv->rev == TDA19989)
1274                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1275
1276         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1277                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1278
1279         /* initialize the optional IRQ */
1280         if (client->irq) {
1281                 int irqf_trigger;
1282
1283                 /* init read EDID waitqueue and HDP work */
1284                 init_waitqueue_head(&priv->wq_edid);
1285
1286                 /* clear pending interrupts */
1287                 reg_read(priv, REG_INT_FLAGS_0);
1288                 reg_read(priv, REG_INT_FLAGS_1);
1289                 reg_read(priv, REG_INT_FLAGS_2);
1290
1291                 irqf_trigger =
1292                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1293                 ret = request_threaded_irq(client->irq, NULL,
1294                                            tda998x_irq_thread,
1295                                            irqf_trigger | IRQF_ONESHOT,
1296                                            "tda998x", priv);
1297                 if (ret) {
1298                         dev_err(&client->dev,
1299                                 "failed to request IRQ#%u: %d\n",
1300                                 client->irq, ret);
1301                         goto fail;
1302                 }
1303
1304                 /* enable HPD irq */
1305                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1306         }
1307
1308         /* enable EDID read irq: */
1309         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1310
1311         if (!np)
1312                 return 0;               /* non-DT */
1313
1314         /* get the optional video properties */
1315         ret = of_property_read_u32(np, "video-ports", &video);
1316         if (ret == 0) {
1317                 priv->vip_cntrl_0 = video >> 16;
1318                 priv->vip_cntrl_1 = video >> 8;
1319                 priv->vip_cntrl_2 = video;
1320         }
1321
1322         return 0;
1323
1324 fail:
1325         /* if encoder_init fails, the encoder slave is never registered,
1326          * so cleanup here:
1327          */
1328         if (priv->cec)
1329                 i2c_unregister_device(priv->cec);
1330         return -ENXIO;
1331 }
1332
1333 #define conn_to_tda998x_priv(x) \
1334         container_of(x, struct tda998x_priv, connector);
1335
1336 #define enc_to_tda998x_priv(x) \
1337         container_of(x, struct tda998x_priv, encoder);
1338
1339 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1340 {
1341         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1342
1343         tda998x_encoder_dpms(priv, mode);
1344 }
1345
1346 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1347 {
1348         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1349 }
1350
1351 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1352 {
1353         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1354 }
1355
1356 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1357                                       struct drm_display_mode *mode,
1358                                       struct drm_display_mode *adjusted_mode)
1359 {
1360         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1361
1362         tda998x_encoder_mode_set(priv, mode, adjusted_mode);
1363 }
1364
1365 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1366         .dpms = tda998x_encoder2_dpms,
1367         .save = tda998x_encoder_save,
1368         .restore = tda998x_encoder_restore,
1369         .mode_fixup = tda998x_encoder_mode_fixup,
1370         .prepare = tda998x_encoder_prepare,
1371         .commit = tda998x_encoder_commit,
1372         .mode_set = tda998x_encoder2_mode_set,
1373 };
1374
1375 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1376 {
1377         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1378
1379         tda998x_destroy(priv);
1380         drm_encoder_cleanup(encoder);
1381 }
1382
1383 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1384         .destroy = tda998x_encoder_destroy,
1385 };
1386
1387 static int tda998x_connector_get_modes(struct drm_connector *connector)
1388 {
1389         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1390
1391         return tda998x_encoder_get_modes(priv, connector);
1392 }
1393
1394 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1395                                         struct drm_display_mode *mode)
1396 {
1397         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1398
1399         return tda998x_encoder_mode_valid(priv, mode);
1400 }
1401
1402 static struct drm_encoder *
1403 tda998x_connector_best_encoder(struct drm_connector *connector)
1404 {
1405         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1406
1407         return &priv->encoder;
1408 }
1409
1410 static
1411 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1412         .get_modes = tda998x_connector_get_modes,
1413         .mode_valid = tda998x_connector_mode_valid,
1414         .best_encoder = tda998x_connector_best_encoder,
1415 };
1416
1417 static enum drm_connector_status
1418 tda998x_connector_detect(struct drm_connector *connector, bool force)
1419 {
1420         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1421
1422         return tda998x_encoder_detect(priv);
1423 }
1424
1425 static void tda998x_connector_destroy(struct drm_connector *connector)
1426 {
1427         drm_connector_unregister(connector);
1428         drm_connector_cleanup(connector);
1429 }
1430
1431 static const struct drm_connector_funcs tda998x_connector_funcs = {
1432         .dpms = drm_helper_connector_dpms,
1433         .fill_modes = drm_helper_probe_single_connector_modes,
1434         .detect = tda998x_connector_detect,
1435         .destroy = tda998x_connector_destroy,
1436 };
1437
1438 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1439 {
1440         struct tda998x_encoder_params *params = dev->platform_data;
1441         struct i2c_client *client = to_i2c_client(dev);
1442         struct drm_device *drm = data;
1443         struct tda998x_priv *priv;
1444         u32 crtcs = 0;
1445         int ret;
1446
1447         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1448         if (!priv)
1449                 return -ENOMEM;
1450
1451         dev_set_drvdata(dev, priv);
1452
1453         if (dev->of_node)
1454                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1455
1456         /* If no CRTCs were found, fall back to our old behaviour */
1457         if (crtcs == 0) {
1458                 dev_warn(dev, "Falling back to first CRTC\n");
1459                 crtcs = 1 << 0;
1460         }
1461
1462         priv->connector.interlace_allowed = 1;
1463         priv->encoder.possible_crtcs = crtcs;
1464
1465         ret = tda998x_create(client, priv);
1466         if (ret)
1467                 return ret;
1468
1469         if (!dev->of_node && params)
1470                 tda998x_encoder_set_config(priv, params);
1471
1472         tda998x_encoder_set_polling(priv, &priv->connector);
1473
1474         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1475         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1476                                DRM_MODE_ENCODER_TMDS);
1477         if (ret)
1478                 goto err_encoder;
1479
1480         drm_connector_helper_add(&priv->connector,
1481                                  &tda998x_connector_helper_funcs);
1482         ret = drm_connector_init(drm, &priv->connector,
1483                                  &tda998x_connector_funcs,
1484                                  DRM_MODE_CONNECTOR_HDMIA);
1485         if (ret)
1486                 goto err_connector;
1487
1488         ret = drm_connector_register(&priv->connector);
1489         if (ret)
1490                 goto err_sysfs;
1491
1492         priv->connector.encoder = &priv->encoder;
1493         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1494
1495         return 0;
1496
1497 err_sysfs:
1498         drm_connector_cleanup(&priv->connector);
1499 err_connector:
1500         drm_encoder_cleanup(&priv->encoder);
1501 err_encoder:
1502         tda998x_destroy(priv);
1503         return ret;
1504 }
1505
1506 static void tda998x_unbind(struct device *dev, struct device *master,
1507                            void *data)
1508 {
1509         struct tda998x_priv *priv = dev_get_drvdata(dev);
1510
1511         drm_connector_cleanup(&priv->connector);
1512         drm_encoder_cleanup(&priv->encoder);
1513         tda998x_destroy(priv);
1514 }
1515
1516 static const struct component_ops tda998x_ops = {
1517         .bind = tda998x_bind,
1518         .unbind = tda998x_unbind,
1519 };
1520
1521 static int
1522 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1523 {
1524         return component_add(&client->dev, &tda998x_ops);
1525 }
1526
1527 static int tda998x_remove(struct i2c_client *client)
1528 {
1529         component_del(&client->dev, &tda998x_ops);
1530         return 0;
1531 }
1532
1533 #ifdef CONFIG_OF
1534 static const struct of_device_id tda998x_dt_ids[] = {
1535         { .compatible = "nxp,tda998x", },
1536         { }
1537 };
1538 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1539 #endif
1540
1541 static struct i2c_device_id tda998x_ids[] = {
1542         { "tda998x", 0 },
1543         { }
1544 };
1545 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1546
1547 static struct i2c_driver tda998x_driver = {
1548         .probe = tda998x_probe,
1549         .remove = tda998x_remove,
1550         .driver = {
1551                 .name = "tda998x",
1552                 .of_match_table = of_match_ptr(tda998x_dt_ids),
1553         },
1554         .id_table = tda998x_ids,
1555 };
1556
1557 module_i2c_driver(tda998x_driver);
1558
1559 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1560 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1561 MODULE_LICENSE("GPL");