drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <sound/asoundef.h>
  23
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_of.h>
  28 #include <drm/i2c/tda998x.h>
  29
  30 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  31
  32 struct tda998x_priv {
  33         struct i2c_client *cec;
  34         struct i2c_client *hdmi;
  35         struct mutex mutex;
  36         u16 rev;
  37         u8 current_page;
  38         int dpms;
  39         bool is_hdmi_sink;
  40         u8 vip_cntrl_0;
  41         u8 vip_cntrl_1;
  42         u8 vip_cntrl_2;
  43         struct tda998x_encoder_params params;
  44
  45         wait_queue_head_t wq_edid;
  46         volatile int wq_edid_wait;
  47         struct drm_encoder *encoder;
  48
  49         struct work_struct detect_work;
  50         struct timer_list edid_delay_timer;
  51         wait_queue_head_t edid_delay_waitq;
  52         bool edid_delay_active;
  53 };
  54
  55 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  56  * things we encode the page # in upper bits of the register #.  To read/
  57  * write a given register, we need to make sure CURPAGE register is set
  58  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  59  */
  60
  61 #define REG(page, addr) (((page) << 8) | (addr))
  62 #define REG2ADDR(reg)   ((reg) & 0xff)
  63 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  64
  65 #define REG_CURPAGE               0xff                /* write */
  66
  67
  68 /* Page 00h: General Control */
  69 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
  70 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
  71 # define MAIN_CNTRL0_SR           (1 << 0)
  72 # define MAIN_CNTRL0_DECS         (1 << 1)
  73 # define MAIN_CNTRL0_DEHS         (1 << 2)
  74 # define MAIN_CNTRL0_CECS         (1 << 3)
  75 # define MAIN_CNTRL0_CEHS         (1 << 4)
  76 # define MAIN_CNTRL0_SCALER       (1 << 7)
  77 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
  78 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
  79 # define SOFTRESET_AUDIO          (1 << 0)
  80 # define SOFTRESET_I2C_MASTER     (1 << 1)
  81 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
  82 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
  83 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
  84 # define I2C_MASTER_DIS_MM        (1 << 0)
  85 # define I2C_MASTER_DIS_FILT      (1 << 1)
  86 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
  87 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
  88 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
  89 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
  90 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
  91 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
  92 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
  93 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
  94 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
  95 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
  96 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
  97 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
  98 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
  99 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 100 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 101 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 102 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 103 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 104 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 105 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 106 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 107 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 108 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 109 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 110 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 111 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 112 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 113 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 114 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 115 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 116 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 117 # define VIP_CNTRL_3_EMB          (1 << 3)
 118 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 119 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 120 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 121 # define VIP_CNTRL_3_EDGE         (1 << 7)
 122 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 123 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 124 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 125 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 126 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 127 # define VIP_CNTRL_4_TST_656      (1 << 6)
 128 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 129 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 130 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 131 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 132 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 133 # define MUX_AP_SELECT_I2S        0x64
 134 # define MUX_AP_SELECT_SPDIF      0x40
 135 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 136 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 137 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 138 # define MAT_CONTRL_MAT_BP        (1 << 2)
 139 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 140 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 141 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 142 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 143 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 144 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 145 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 146 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 147 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 148 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 149 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 150 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 151 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 152 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 153 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 154 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 155 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 156 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 157 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 158 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 159 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 160 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 161 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 162 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 163 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 164 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 165 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 166 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 167 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 168 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 169 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 170 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 171 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 172 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 173 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 174 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 175 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 176 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 177 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 178 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 179 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 180 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 181 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 182 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 183 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 184 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 185 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 186 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 187 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 188 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 189 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 190 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 191 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 192 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 193 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 194 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 195 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 196 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 197 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 198 # define HVF_CNTRL_0_SM           (1 << 7)
 199 # define HVF_CNTRL_0_RWB          (1 << 6)
 200 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 201 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 202 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 203 # define HVF_CNTRL_1_FOR          (1 << 0)
 204 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 205 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 206 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 207 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 208 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 209 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 210 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 211 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 212 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 213 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 214 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 215 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 216 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 217
 218 /* Page 02h: PLL settings */
 219 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 220 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 221 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 222 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 223 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 224 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 225 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 226 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 227 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 228 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 229 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 230 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 231 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 232 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 233 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 234 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 235 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 236 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 237 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 238 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 239 # define AUDIO_DIV_SERCLK_1       0
 240 # define AUDIO_DIV_SERCLK_2       1
 241 # define AUDIO_DIV_SERCLK_4       2
 242 # define AUDIO_DIV_SERCLK_8       3
 243 # define AUDIO_DIV_SERCLK_16      4
 244 # define AUDIO_DIV_SERCLK_32      5
 245 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 246 # define SEL_CLK_SEL_CLK1         (1 << 0)
 247 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 248 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 249 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 250
 251
 252 /* Page 09h: EDID Control */
 253 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 254 /* next 127 successive registers are the EDID block */
 255 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 256 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 257 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 258 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 259 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 260
 261
 262 /* Page 10h: information frames and packets */
 263 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 264 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 265 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 266 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 267 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 268
 269
 270 /* Page 11h: audio settings and content info packets */
 271 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 272 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 273 # define AIP_CNTRL_0_SWAP         (1 << 1)
 274 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 275 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 276 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 277 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 278 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 279 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 280 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 281 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 282 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 283 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 284 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 285 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 286 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 287 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 288 # define CTS_N_K(x)               (((x) & 7) << 0)
 289 # define CTS_N_M(x)               (((x) & 3) << 4)
 290 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 291 # define ENC_CNTRL_RST_ENC        (1 << 0)
 292 # define ENC_CNTRL_RST_SEL        (1 << 1)
 293 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 294 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 295 # define DIP_FLAGS_ACR            (1 << 0)
 296 # define DIP_FLAGS_GC             (1 << 1)
 297 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 298 # define DIP_IF_FLAGS_IF1         (1 << 1)
 299 # define DIP_IF_FLAGS_IF2         (1 << 2)
 300 # define DIP_IF_FLAGS_IF3         (1 << 3)
 301 # define DIP_IF_FLAGS_IF4         (1 << 4)
 302 # define DIP_IF_FLAGS_IF5         (1 << 5)
 303 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 304
 305
 306 /* Page 12h: HDCP and OTP */
 307 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 308 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 309 # define TX4_PD_RAM               (1 << 1)
 310 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 311 # define TX33_HDMI                (1 << 1)
 312
 313
 314 /* Page 13h: Gamut related metadata packets */
 315
 316
 317
 318 /* CEC registers: (not paged)
 319  */
 320 #define REG_CEC_INTSTATUS         0xee                /* read */
 321 # define CEC_INTSTATUS_CEC        (1 << 0)
 322 # define CEC_INTSTATUS_HDMI       (1 << 1)
 323 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 324 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 325 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 326 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 327 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 328 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 329 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 330 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 331 # define CEC_RXSHPDINT_HPD        BIT(1)
 332 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 333 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 334 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 335
 336 #define REG_CEC_ENAMODS           0xff                /* read/write */
 337 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 338 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 339 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 340 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 341 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 342
 343
 344 /* Device versions: */
 345 #define TDA9989N2                 0x0101
 346 #define TDA19989                  0x0201
 347 #define TDA19989N2                0x0202
 348 #define TDA19988                  0x0301
 349
 350 static void
 351 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 352 {
 353         struct i2c_client *client = priv->cec;
 354         u8 buf[] = {addr, val};
 355         int ret;
 356
 357         ret = i2c_master_send(client, buf, sizeof(buf));
 358         if (ret < 0)
 359                 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
 360 }
 361
 362 static u8
 363 cec_read(struct tda998x_priv *priv, u8 addr)
 364 {
 365         struct i2c_client *client = priv->cec;
 366         u8 val;
 367         int ret;
 368
 369         ret = i2c_master_send(client, &addr, sizeof(addr));
 370         if (ret < 0)
 371                 goto fail;
 372
 373         ret = i2c_master_recv(client, &val, sizeof(val));
 374         if (ret < 0)
 375                 goto fail;
 376
 377         return val;
 378
 379 fail:
 380         dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
 381         return 0;
 382 }
 383
 384 static int
 385 set_page(struct tda998x_priv *priv, u16 reg)
 386 {
 387         if (REG2PAGE(reg) != priv->current_page) {
 388                 struct i2c_client *client = priv->hdmi;
 389                 u8 buf[] = {
 390                                 REG_CURPAGE, REG2PAGE(reg)
 391                 };
 392                 int ret = i2c_master_send(client, buf, sizeof(buf));
 393                 if (ret < 0) {
 394                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 395                                         reg, ret);
 396                         return ret;
 397                 }
 398
 399                 priv->current_page = REG2PAGE(reg);
 400         }
 401         return 0;
 402 }
 403
 404 static int
 405 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 406 {
 407         struct i2c_client *client = priv->hdmi;
 408         u8 addr = REG2ADDR(reg);
 409         int ret;
 410
 411         mutex_lock(&priv->mutex);
 412         ret = set_page(priv, reg);
 413         if (ret < 0)
 414                 goto out;
 415
 416         ret = i2c_master_send(client, &addr, sizeof(addr));
 417         if (ret < 0)
 418                 goto fail;
 419
 420         ret = i2c_master_recv(client, buf, cnt);
 421         if (ret < 0)
 422                 goto fail;
 423
 424         goto out;
 425
 426 fail:
 427         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 428 out:
 429         mutex_unlock(&priv->mutex);
 430         return ret;
 431 }
 432
 433 static void
 434 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 435 {
 436         struct i2c_client *client = priv->hdmi;
 437         u8 buf[cnt+1];
 438         int ret;
 439
 440         buf[0] = REG2ADDR(reg);
 441         memcpy(&buf[1], p, cnt);
 442
 443         mutex_lock(&priv->mutex);
 444         ret = set_page(priv, reg);
 445         if (ret < 0)
 446                 goto out;
 447
 448         ret = i2c_master_send(client, buf, cnt + 1);
 449         if (ret < 0)
 450                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 451 out:
 452         mutex_unlock(&priv->mutex);
 453 }
 454
 455 static int
 456 reg_read(struct tda998x_priv *priv, u16 reg)
 457 {
 458         u8 val = 0;
 459         int ret;
 460
 461         ret = reg_read_range(priv, reg, &val, sizeof(val));
 462         if (ret < 0)
 463                 return ret;
 464         return val;
 465 }
 466
 467 static void
 468 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 469 {
 470         struct i2c_client *client = priv->hdmi;
 471         u8 buf[] = {REG2ADDR(reg), val};
 472         int ret;
 473
 474         mutex_lock(&priv->mutex);
 475         ret = set_page(priv, reg);
 476         if (ret < 0)
 477                 goto out;
 478
 479         ret = i2c_master_send(client, buf, sizeof(buf));
 480         if (ret < 0)
 481                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 482 out:
 483         mutex_unlock(&priv->mutex);
 484 }
 485
 486 static void
 487 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 488 {
 489         struct i2c_client *client = priv->hdmi;
 490         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 491         int ret;
 492
 493         mutex_lock(&priv->mutex);
 494         ret = set_page(priv, reg);
 495         if (ret < 0)
 496                 goto out;
 497
 498         ret = i2c_master_send(client, buf, sizeof(buf));
 499         if (ret < 0)
 500                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 501 out:
 502         mutex_unlock(&priv->mutex);
 503 }
 504
 505 static void
 506 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 507 {
 508         int old_val;
 509
 510         old_val = reg_read(priv, reg);
 511         if (old_val >= 0)
 512                 reg_write(priv, reg, old_val | val);
 513 }
 514
 515 static void
 516 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 517 {
 518         int old_val;
 519
 520         old_val = reg_read(priv, reg);
 521         if (old_val >= 0)
 522                 reg_write(priv, reg, old_val & ~val);
 523 }
 524
 525 static void
 526 tda998x_reset(struct tda998x_priv *priv)
 527 {
 528         /* reset audio and i2c master: */
 529         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 530         msleep(50);
 531         reg_write(priv, REG_SOFTRESET, 0);
 532         msleep(50);
 533
 534         /* reset transmitter: */
 535         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 536         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 537
 538         /* PLL registers common configuration */
 539         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 540         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 541         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 542         reg_write(priv, REG_SERIALIZER,   0x00);
 543         reg_write(priv, REG_BUFFER_OUT,   0x00);
 544         reg_write(priv, REG_PLL_SCG1,     0x00);
 545         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 546         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 547         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 548         reg_write(priv, REG_PLL_SCGN2,    0x00);
 549         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 550         reg_write(priv, REG_PLL_SCGR2,    0x00);
 551         reg_write(priv, REG_PLL_SCG2,     0x10);
 552
 553         /* Write the default value MUX register */
 554         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 555 }
 556
 557 /*
 558  * The TDA998x has a problem when trying to read the EDID close to a
 559  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 560  * trying to read EDID data.
 561  *
 562  * However, tda998x_encoder_get_modes() may be called at any moment
 563  * after tda998x_encoder_detect() indicates that we are connected, so
 564  * we need to delay probing modes in tda998x_encoder_get_modes() after
 565  * we have seen a HPD inactive->active transition.  This code implements
 566  * that delay.
 567  */
 568 static void tda998x_edid_delay_done(unsigned long data)
 569 {
 570         struct tda998x_priv *priv = (struct tda998x_priv *)data;
 571
 572         priv->edid_delay_active = false;
 573         wake_up(&priv->edid_delay_waitq);
 574         schedule_work(&priv->detect_work);
 575 }
 576
 577 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 578 {
 579         priv->edid_delay_active = true;
 580         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 581 }
 582
 583 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 584 {
 585         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 586 }
 587
 588 /*
 589  * We need to run the KMS hotplug event helper outside of our threaded
 590  * interrupt routine as this can call back into our get_modes method,
 591  * which will want to make use of interrupts.
 592  */
 593 static void tda998x_detect_work(struct work_struct *work)
 594 {
 595         struct tda998x_priv *priv =
 596                 container_of(work, struct tda998x_priv, detect_work);
 597         struct drm_device *dev = priv->encoder->dev;
 598
 599         if (dev)
 600                 drm_kms_helper_hotplug_event(dev);
 601 }
 602
 603 /*
 604  * only 2 interrupts may occur: screen plug/unplug and EDID read
 605  */
 606 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 607 {
 608         struct tda998x_priv *priv = data;
 609         u8 sta, cec, lvl, flag0, flag1, flag2;
 610         bool handled = false;
 611
 612         sta = cec_read(priv, REG_CEC_INTSTATUS);
 613         cec = cec_read(priv, REG_CEC_RXSHPDINT);
 614         lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 615         flag0 = reg_read(priv, REG_INT_FLAGS_0);
 616         flag1 = reg_read(priv, REG_INT_FLAGS_1);
 617         flag2 = reg_read(priv, REG_INT_FLAGS_2);
 618         DRM_DEBUG_DRIVER(
 619                 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 620                 sta, cec, lvl, flag0, flag1, flag2);
 621
 622         if (cec & CEC_RXSHPDINT_HPD) {
 623                 if (lvl & CEC_RXSHPDLEV_HPD)
 624                         tda998x_edid_delay_start(priv);
 625                 else
 626                         schedule_work(&priv->detect_work);
 627
 628                 handled = true;
 629         }
 630
 631         if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 632                 priv->wq_edid_wait = 0;
 633                 wake_up(&priv->wq_edid);
 634                 handled = true;
 635         }
 636
 637         return IRQ_RETVAL(handled);
 638 }
 639
 640 static void
 641 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 642                  union hdmi_infoframe *frame)
 643 {
 644         u8 buf[32];
 645         ssize_t len;
 646
 647         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 648         if (len < 0) {
 649                 dev_err(&priv->hdmi->dev,
 650                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 651                         frame->any.type, len);
 652                 return;
 653         }
 654
 655         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 656         reg_write_range(priv, addr, buf, len);
 657         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 658 }
 659
 660 static void
 661 tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
 662 {
 663         union hdmi_infoframe frame;
 664
 665         hdmi_audio_infoframe_init(&frame.audio);
 666
 667         frame.audio.channels = p->audio_frame[1] & 0x07;
 668         frame.audio.channel_allocation = p->audio_frame[4];
 669         frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
 670         frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
 671
 672         /*
 673          * L-PCM and IEC61937 compressed audio shall always set sample
 674          * frequency to "refer to stream".  For others, see the HDMI
 675          * specification.
 676          */
 677         frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
 678
 679         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 680 }
 681
 682 static void
 683 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 684 {
 685         union hdmi_infoframe frame;
 686
 687         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
 688         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 689
 690         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 691 }
 692
 693 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 694 {
 695         if (on) {
 696                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 697                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 698                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 699         } else {
 700                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 701         }
 702 }
 703
 704 static void
 705 tda998x_configure_audio(struct tda998x_priv *priv,
 706                 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
 707 {
 708         u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 709         u32 n;
 710
 711         /* Enable audio ports */
 712         reg_write(priv, REG_ENA_AP, p->audio_cfg);
 713         reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
 714
 715         /* Set audio input source */
 716         switch (p->audio_format) {
 717         case AFMT_SPDIF:
 718                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 719                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 720                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 721                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 722                 break;
 723
 724         case AFMT_I2S:
 725                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 726                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 727                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 728                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 729                 break;
 730
 731         default:
 732                 BUG();
 733                 return;
 734         }
 735
 736         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 737         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 738                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 739         reg_write(priv, REG_CTS_N, cts_n);
 740
 741         /*
 742          * Audio input somehow depends on HDMI line rate which is
 743          * related to pixclk. Testing showed that modes with pixclk
 744          * >100MHz need a larger divider while <40MHz need the default.
 745          * There is no detailed info in the datasheet, so we just
 746          * assume 100MHz requires larger divider.
 747          */
 748         adiv = AUDIO_DIV_SERCLK_8;
 749         if (mode->clock > 100000)
 750                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 751
 752         /* S/PDIF asks for a larger divider */
 753         if (p->audio_format == AFMT_SPDIF)
 754                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 755
 756         reg_write(priv, REG_AUDIO_DIV, adiv);
 757
 758         /*
 759          * This is the approximate value of N, which happens to be
 760          * the recommended values for non-coherent clocks.
 761          */
 762         n = 128 * p->audio_sample_rate / 1000;
 763
 764         /* Write the CTS and N values */
 765         buf[0] = 0x44;
 766         buf[1] = 0x42;
 767         buf[2] = 0x01;
 768         buf[3] = n;
 769         buf[4] = n >> 8;
 770         buf[5] = n >> 16;
 771         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 772
 773         /* Set CTS clock reference */
 774         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 775
 776         /* Reset CTS generator */
 777         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 778         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 779
 780         /* Write the channel status */
 781         buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 782         buf[1] = 0x00;
 783         buf[2] = IEC958_AES3_CON_FS_NOTID;
 784         buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
 785                         IEC958_AES4_CON_MAX_WORDLEN_24;
 786         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 787
 788         tda998x_audio_mute(priv, true);
 789         msleep(20);
 790         tda998x_audio_mute(priv, false);
 791
 792         /* Write the audio information packet */
 793         tda998x_write_aif(priv, p);
 794 }
 795
 796 /* DRM encoder functions */
 797
 798 static void tda998x_encoder_set_config(struct tda998x_priv *priv,
 799                                        const struct tda998x_encoder_params *p)
 800 {
 801         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
 802                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
 803                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
 804                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
 805         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
 806                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
 807                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
 808                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
 809         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
 810                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
 811                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
 812                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
 813
 814         priv->params = *p;
 815 }
 816
 817 static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
 818 {
 819         /* we only care about on or off: */
 820         if (mode != DRM_MODE_DPMS_ON)
 821                 mode = DRM_MODE_DPMS_OFF;
 822
 823         if (mode == priv->dpms)
 824                 return;
 825
 826         switch (mode) {
 827         case DRM_MODE_DPMS_ON:
 828                 /* enable video ports, audio will be enabled later */
 829                 reg_write(priv, REG_ENA_VP_0, 0xff);
 830                 reg_write(priv, REG_ENA_VP_1, 0xff);
 831                 reg_write(priv, REG_ENA_VP_2, 0xff);
 832                 /* set muxing after enabling ports: */
 833                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
 834                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
 835                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
 836                 break;
 837         case DRM_MODE_DPMS_OFF:
 838                 /* disable video ports */
 839                 reg_write(priv, REG_ENA_VP_0, 0x00);
 840                 reg_write(priv, REG_ENA_VP_1, 0x00);
 841                 reg_write(priv, REG_ENA_VP_2, 0x00);
 842                 break;
 843         }
 844
 845         priv->dpms = mode;
 846 }
 847
 848 static void
 849 tda998x_encoder_save(struct drm_encoder *encoder)
 850 {
 851         DBG("");
 852 }
 853
 854 static void
 855 tda998x_encoder_restore(struct drm_encoder *encoder)
 856 {
 857         DBG("");
 858 }
 859
 860 static bool
 861 tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
 862                           const struct drm_display_mode *mode,
 863                           struct drm_display_mode *adjusted_mode)
 864 {
 865         return true;
 866 }
 867
 868 static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
 869                                       struct drm_display_mode *mode)
 870 {
 871         if (mode->clock > 150000)
 872                 return MODE_CLOCK_HIGH;
 873         if (mode->htotal >= BIT(13))
 874                 return MODE_BAD_HVALUE;
 875         if (mode->vtotal >= BIT(11))
 876                 return MODE_BAD_VVALUE;
 877         return MODE_OK;
 878 }
 879
 880 static void
 881 tda998x_encoder_mode_set(struct tda998x_priv *priv,
 882                          struct drm_display_mode *mode,
 883                          struct drm_display_mode *adjusted_mode)
 884 {
 885         u16 ref_pix, ref_line, n_pix, n_line;
 886         u16 hs_pix_s, hs_pix_e;
 887         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
 888         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
 889         u16 vwin1_line_s, vwin1_line_e;
 890         u16 vwin2_line_s, vwin2_line_e;
 891         u16 de_pix_s, de_pix_e;
 892         u8 reg, div, rep;
 893
 894         /*
 895          * Internally TDA998x is using ITU-R BT.656 style sync but
 896          * we get VESA style sync. TDA998x is using a reference pixel
 897          * relative to ITU to sync to the input frame and for output
 898          * sync generation. Currently, we are using reference detection
 899          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
 900          * which is position of rising VS with coincident rising HS.
 901          *
 902          * Now there is some issues to take care of:
 903          * - HDMI data islands require sync-before-active
 904          * - TDA998x register values must be > 0 to be enabled
 905          * - REFLINE needs an additional offset of +1
 906          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
 907          *
 908          * So we add +1 to all horizontal and vertical register values,
 909          * plus an additional +3 for REFPIX as we are using RGB input only.
 910          */
 911         n_pix        = mode->htotal;
 912         n_line       = mode->vtotal;
 913
 914         hs_pix_e     = mode->hsync_end - mode->hdisplay;
 915         hs_pix_s     = mode->hsync_start - mode->hdisplay;
 916         de_pix_e     = mode->htotal;
 917         de_pix_s     = mode->htotal - mode->hdisplay;
 918         ref_pix      = 3 + hs_pix_s;
 919
 920         /*
 921          * Attached LCD controllers may generate broken sync. Allow
 922          * those to adjust the position of the rising VS edge by adding
 923          * HSKEW to ref_pix.
 924          */
 925         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
 926                 ref_pix += adjusted_mode->hskew;
 927
 928         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
 929                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
 930                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
 931                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
 932                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 933                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
 934                 vs1_line_e   = vs1_line_s +
 935                                mode->vsync_end - mode->vsync_start;
 936                 vwin2_line_s = vwin2_line_e = 0;
 937                 vs2_pix_s    = vs2_pix_e  = 0;
 938                 vs2_line_s   = vs2_line_e = 0;
 939         } else {
 940                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
 941                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
 942                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
 943                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
 944                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
 945                 vs1_line_e   = vs1_line_s +
 946                                (mode->vsync_end - mode->vsync_start)/2;
 947                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
 948                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
 949                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
 950                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
 951                 vs2_line_e   = vs2_line_s +
 952                                (mode->vsync_end - mode->vsync_start)/2;
 953         }
 954
 955         div = 148500 / mode->clock;
 956         if (div != 0) {
 957                 div--;
 958                 if (div > 3)
 959                         div = 3;
 960         }
 961
 962         /* mute the audio FIFO: */
 963         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 964
 965         /* set HDMI HDCP mode off: */
 966         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
 967         reg_clear(priv, REG_TX33, TX33_HDMI);
 968         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
 969
 970         /* no pre-filter or interpolator: */
 971         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
 972                         HVF_CNTRL_0_INTPOL(0));
 973         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
 974         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
 975                         VIP_CNTRL_4_BLC(0));
 976
 977         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
 978         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
 979                                           PLL_SERIAL_3_SRL_DE);
 980         reg_write(priv, REG_SERIALIZER, 0);
 981         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
 982
 983         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
 984         rep = 0;
 985         reg_write(priv, REG_RPT_CNTRL, 0);
 986         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
 987                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 988
 989         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
 990                         PLL_SERIAL_2_SRL_PR(rep));
 991
 992         /* set color matrix bypass flag: */
 993         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
 994                                 MAT_CONTRL_MAT_SC(1));
 995
 996         /* set BIAS tmds value: */
 997         reg_write(priv, REG_ANA_GENERAL, 0x09);
 998
 999         /*
1000          * Sync on rising HSYNC/VSYNC
1001          */
1002         reg = VIP_CNTRL_3_SYNC_HS;
1003
1004         /*
1005          * TDA19988 requires high-active sync at input stage,
1006          * so invert low-active sync provided by master encoder here
1007          */
1008         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1009                 reg |= VIP_CNTRL_3_H_TGL;
1010         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1011                 reg |= VIP_CNTRL_3_V_TGL;
1012         reg_write(priv, REG_VIP_CNTRL_3, reg);
1013
1014         reg_write(priv, REG_VIDFORMAT, 0x00);
1015         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1016         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1017         reg_write16(priv, REG_NPIX_MSB, n_pix);
1018         reg_write16(priv, REG_NLINE_MSB, n_line);
1019         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1020         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1021         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1022         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1023         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1024         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1025         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1026         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1027         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1028         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1029         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1030         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1031         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1032         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1033         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1034         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1035
1036         if (priv->rev == TDA19988) {
1037                 /* let incoming pixels fill the active space (if any) */
1038                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1039         }
1040
1041         /*
1042          * Always generate sync polarity relative to input sync and
1043          * revert input stage toggled sync at output stage
1044          */
1045         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1046         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1047                 reg |= TBG_CNTRL_1_H_TGL;
1048         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1049                 reg |= TBG_CNTRL_1_V_TGL;
1050         reg_write(priv, REG_TBG_CNTRL_1, reg);
1051
1052         /* must be last register set: */
1053         reg_write(priv, REG_TBG_CNTRL_0, 0);
1054
1055         /* Only setup the info frames if the sink is HDMI */
1056         if (priv->is_hdmi_sink) {
1057                 /* We need to turn HDMI HDCP stuff on to get audio through */
1058                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1059                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1060                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1061                 reg_set(priv, REG_TX33, TX33_HDMI);
1062
1063                 tda998x_write_avi(priv, adjusted_mode);
1064
1065                 if (priv->params.audio_cfg)
1066                         tda998x_configure_audio(priv, adjusted_mode,
1067                                                 &priv->params);
1068         }
1069 }
1070
1071 static enum drm_connector_status
1072 tda998x_encoder_detect(struct tda998x_priv *priv)
1073 {
1074         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1075
1076         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1077                         connector_status_disconnected;
1078 }
1079
1080 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1081 {
1082         struct tda998x_priv *priv = data;
1083         u8 offset, segptr;
1084         int ret, i;
1085
1086         offset = (blk & 1) ? 128 : 0;
1087         segptr = blk / 2;
1088
1089         reg_write(priv, REG_DDC_ADDR, 0xa0);
1090         reg_write(priv, REG_DDC_OFFS, offset);
1091         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1092         reg_write(priv, REG_DDC_SEGM, segptr);
1093
1094         /* enable reading EDID: */
1095         priv->wq_edid_wait = 1;
1096         reg_write(priv, REG_EDID_CTRL, 0x1);
1097
1098         /* flag must be cleared by sw: */
1099         reg_write(priv, REG_EDID_CTRL, 0x0);
1100
1101         /* wait for block read to complete: */
1102         if (priv->hdmi->irq) {
1103                 i = wait_event_timeout(priv->wq_edid,
1104                                         !priv->wq_edid_wait,
1105                                         msecs_to_jiffies(100));
1106                 if (i < 0) {
1107                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1108                         return i;
1109                 }
1110         } else {
1111                 for (i = 100; i > 0; i--) {
1112                         msleep(1);
1113                         ret = reg_read(priv, REG_INT_FLAGS_2);
1114                         if (ret < 0)
1115                                 return ret;
1116                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1117                                 break;
1118                 }
1119         }
1120
1121         if (i == 0) {
1122                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1123                 return -ETIMEDOUT;
1124         }
1125
1126         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1127         if (ret != length) {
1128                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1129                         blk, ret);
1130                 return ret;
1131         }
1132
1133         return 0;
1134 }
1135
1136 static int
1137 tda998x_encoder_get_modes(struct tda998x_priv *priv,
1138                           struct drm_connector *connector)
1139 {
1140         struct edid *edid;
1141         int n;
1142
1143         /*
1144          * If we get killed while waiting for the HPD timeout, return
1145          * no modes found: we are not in a restartable path, so we
1146          * can't handle signals gracefully.
1147          */
1148         if (tda998x_edid_delay_wait(priv))
1149                 return 0;
1150
1151         if (priv->rev == TDA19988)
1152                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1153
1154         edid = drm_do_get_edid(connector, read_edid_block, priv);
1155
1156         if (priv->rev == TDA19988)
1157                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1158
1159         if (!edid) {
1160                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1161                 return 0;
1162         }
1163
1164         drm_mode_connector_update_edid_property(connector, edid);
1165         n = drm_add_edid_modes(connector, edid);
1166         priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1167         kfree(edid);
1168
1169         return n;
1170 }
1171
1172 static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1173                                         struct drm_connector *connector)
1174 {
1175         if (priv->hdmi->irq)
1176                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1177         else
1178                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1179                         DRM_CONNECTOR_POLL_DISCONNECT;
1180 }
1181
1182 static void tda998x_destroy(struct tda998x_priv *priv)
1183 {
1184         /* disable all IRQs and free the IRQ handler */
1185         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1186         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1187
1188         if (priv->hdmi->irq)
1189                 free_irq(priv->hdmi->irq, priv);
1190
1191         del_timer_sync(&priv->edid_delay_timer);
1192         cancel_work_sync(&priv->detect_work);
1193
1194         i2c_unregister_device(priv->cec);
1195 }
1196
1197 /* I2C driver functions */
1198
1199 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1200 {
1201         struct device_node *np = client->dev.of_node;
1202         u32 video;
1203         int rev_lo, rev_hi, ret;
1204         unsigned short cec_addr;
1205
1206         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1207         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1208         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1209
1210         priv->current_page = 0xff;
1211         priv->hdmi = client;
1212         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1213         cec_addr = 0x34 + (client->addr & 0x03);
1214         priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1215         if (!priv->cec)
1216                 return -ENODEV;
1217
1218         priv->dpms = DRM_MODE_DPMS_OFF;
1219
1220         mutex_init(&priv->mutex);       /* protect the page access */
1221         init_waitqueue_head(&priv->edid_delay_waitq);
1222         setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1223                     (unsigned long)priv);
1224         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1225
1226         /* wake up the device: */
1227         cec_write(priv, REG_CEC_ENAMODS,
1228                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1229
1230         tda998x_reset(priv);
1231
1232         /* read version: */
1233         rev_lo = reg_read(priv, REG_VERSION_LSB);
1234         rev_hi = reg_read(priv, REG_VERSION_MSB);
1235         if (rev_lo < 0 || rev_hi < 0) {
1236                 ret = rev_lo < 0 ? rev_lo : rev_hi;
1237                 goto fail;
1238         }
1239
1240         priv->rev = rev_lo | rev_hi << 8;
1241
1242         /* mask off feature bits: */
1243         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1244
1245         switch (priv->rev) {
1246         case TDA9989N2:
1247                 dev_info(&client->dev, "found TDA9989 n2");
1248                 break;
1249         case TDA19989:
1250                 dev_info(&client->dev, "found TDA19989");
1251                 break;
1252         case TDA19989N2:
1253                 dev_info(&client->dev, "found TDA19989 n2");
1254                 break;
1255         case TDA19988:
1256                 dev_info(&client->dev, "found TDA19988");
1257                 break;
1258         default:
1259                 dev_err(&client->dev, "found unsupported device: %04x\n",
1260                         priv->rev);
1261                 goto fail;
1262         }
1263
1264         /* after reset, enable DDC: */
1265         reg_write(priv, REG_DDC_DISABLE, 0x00);
1266
1267         /* set clock on DDC channel: */
1268         reg_write(priv, REG_TX3, 39);
1269
1270         /* if necessary, disable multi-master: */
1271         if (priv->rev == TDA19989)
1272                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1273
1274         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1275                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1276
1277         /* initialize the optional IRQ */
1278         if (client->irq) {
1279                 int irqf_trigger;
1280
1281                 /* init read EDID waitqueue and HDP work */
1282                 init_waitqueue_head(&priv->wq_edid);
1283
1284                 /* clear pending interrupts */
1285                 reg_read(priv, REG_INT_FLAGS_0);
1286                 reg_read(priv, REG_INT_FLAGS_1);
1287                 reg_read(priv, REG_INT_FLAGS_2);
1288
1289                 irqf_trigger =
1290                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1291                 ret = request_threaded_irq(client->irq, NULL,
1292                                            tda998x_irq_thread,
1293                                            irqf_trigger | IRQF_ONESHOT,
1294                                            "tda998x", priv);
1295                 if (ret) {
1296                         dev_err(&client->dev,
1297                                 "failed to request IRQ#%u: %d\n",
1298                                 client->irq, ret);
1299                         goto fail;
1300                 }
1301
1302                 /* enable HPD irq */
1303                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1304         }
1305
1306         /* enable EDID read irq: */
1307         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1308
1309         if (!np)
1310                 return 0;               /* non-DT */
1311
1312         /* get the optional video properties */
1313         ret = of_property_read_u32(np, "video-ports", &video);
1314         if (ret == 0) {
1315                 priv->vip_cntrl_0 = video >> 16;
1316                 priv->vip_cntrl_1 = video >> 8;
1317                 priv->vip_cntrl_2 = video;
1318         }
1319
1320         return 0;
1321
1322 fail:
1323         /* if encoder_init fails, the encoder slave is never registered,
1324          * so cleanup here:
1325          */
1326         if (priv->cec)
1327                 i2c_unregister_device(priv->cec);
1328         return -ENXIO;
1329 }
1330
1331 struct tda998x_priv2 {
1332         struct tda998x_priv base;
1333         struct drm_encoder encoder;
1334         struct drm_connector connector;
1335 };
1336
1337 #define conn_to_tda998x_priv2(x) \
1338         container_of(x, struct tda998x_priv2, connector);
1339
1340 #define enc_to_tda998x_priv2(x) \
1341         container_of(x, struct tda998x_priv2, encoder);
1342
1343 static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1344 {
1345         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1346
1347         tda998x_encoder_dpms(&priv->base, mode);
1348 }
1349
1350 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1351 {
1352         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1353 }
1354
1355 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1356 {
1357         tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1358 }
1359
1360 static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1361                                       struct drm_display_mode *mode,
1362                                       struct drm_display_mode *adjusted_mode)
1363 {
1364         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1365
1366         tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1367 }
1368
1369 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1370         .dpms = tda998x_encoder2_dpms,
1371         .save = tda998x_encoder_save,
1372         .restore = tda998x_encoder_restore,
1373         .mode_fixup = tda998x_encoder_mode_fixup,
1374         .prepare = tda998x_encoder_prepare,
1375         .commit = tda998x_encoder_commit,
1376         .mode_set = tda998x_encoder2_mode_set,
1377 };
1378
1379 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1380 {
1381         struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1382
1383         tda998x_destroy(&priv->base);
1384         drm_encoder_cleanup(encoder);
1385 }
1386
1387 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1388         .destroy = tda998x_encoder_destroy,
1389 };
1390
1391 static int tda998x_connector_get_modes(struct drm_connector *connector)
1392 {
1393         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1394
1395         return tda998x_encoder_get_modes(&priv->base, connector);
1396 }
1397
1398 static int tda998x_connector_mode_valid(struct drm_connector *connector,
1399                                         struct drm_display_mode *mode)
1400 {
1401         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1402
1403         return tda998x_encoder_mode_valid(&priv->base, mode);
1404 }
1405
1406 static struct drm_encoder *
1407 tda998x_connector_best_encoder(struct drm_connector *connector)
1408 {
1409         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1410
1411         return &priv->encoder;
1412 }
1413
1414 static
1415 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1416         .get_modes = tda998x_connector_get_modes,
1417         .mode_valid = tda998x_connector_mode_valid,
1418         .best_encoder = tda998x_connector_best_encoder,
1419 };
1420
1421 static enum drm_connector_status
1422 tda998x_connector_detect(struct drm_connector *connector, bool force)
1423 {
1424         struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1425
1426         return tda998x_encoder_detect(&priv->base);
1427 }
1428
1429 static void tda998x_connector_destroy(struct drm_connector *connector)
1430 {
1431         drm_connector_unregister(connector);
1432         drm_connector_cleanup(connector);
1433 }
1434
1435 static const struct drm_connector_funcs tda998x_connector_funcs = {
1436         .dpms = drm_helper_connector_dpms,
1437         .fill_modes = drm_helper_probe_single_connector_modes,
1438         .detect = tda998x_connector_detect,
1439         .destroy = tda998x_connector_destroy,
1440 };
1441
1442 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1443 {
1444         struct tda998x_encoder_params *params = dev->platform_data;
1445         struct i2c_client *client = to_i2c_client(dev);
1446         struct drm_device *drm = data;
1447         struct tda998x_priv2 *priv;
1448         u32 crtcs = 0;
1449         int ret;
1450
1451         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1452         if (!priv)
1453                 return -ENOMEM;
1454
1455         dev_set_drvdata(dev, priv);
1456
1457         if (dev->of_node)
1458                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1459
1460         /* If no CRTCs were found, fall back to our old behaviour */
1461         if (crtcs == 0) {
1462                 dev_warn(dev, "Falling back to first CRTC\n");
1463                 crtcs = 1 << 0;
1464         }
1465
1466         priv->base.encoder = &priv->encoder;
1467         priv->connector.interlace_allowed = 1;
1468         priv->encoder.possible_crtcs = crtcs;
1469
1470         ret = tda998x_create(client, &priv->base);
1471         if (ret)
1472                 return ret;
1473
1474         if (!dev->of_node && params)
1475                 tda998x_encoder_set_config(&priv->base, params);
1476
1477         tda998x_encoder_set_polling(&priv->base, &priv->connector);
1478
1479         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1480         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1481                                DRM_MODE_ENCODER_TMDS);
1482         if (ret)
1483                 goto err_encoder;
1484
1485         drm_connector_helper_add(&priv->connector,
1486                                  &tda998x_connector_helper_funcs);
1487         ret = drm_connector_init(drm, &priv->connector,
1488                                  &tda998x_connector_funcs,
1489                                  DRM_MODE_CONNECTOR_HDMIA);
1490         if (ret)
1491                 goto err_connector;
1492
1493         ret = drm_connector_register(&priv->connector);
1494         if (ret)
1495                 goto err_sysfs;
1496
1497         priv->connector.encoder = &priv->encoder;
1498         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1499
1500         return 0;
1501
1502 err_sysfs:
1503         drm_connector_cleanup(&priv->connector);
1504 err_connector:
1505         drm_encoder_cleanup(&priv->encoder);
1506 err_encoder:
1507         tda998x_destroy(&priv->base);
1508         return ret;
1509 }
1510
1511 static void tda998x_unbind(struct device *dev, struct device *master,
1512                            void *data)
1513 {
1514         struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1515
1516         drm_connector_cleanup(&priv->connector);
1517         drm_encoder_cleanup(&priv->encoder);
1518         tda998x_destroy(&priv->base);
1519 }
1520
1521 static const struct component_ops tda998x_ops = {
1522         .bind = tda998x_bind,
1523         .unbind = tda998x_unbind,
1524 };
1525
1526 static int
1527 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1528 {
1529         return component_add(&client->dev, &tda998x_ops);
1530 }
1531
1532 static int tda998x_remove(struct i2c_client *client)
1533 {
1534         component_del(&client->dev, &tda998x_ops);
1535         return 0;
1536 }
1537
1538 #ifdef CONFIG_OF
1539 static const struct of_device_id tda998x_dt_ids[] = {
1540         { .compatible = "nxp,tda998x", },
1541         { }
1542 };
1543 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1544 #endif
1545
1546 static struct i2c_device_id tda998x_ids[] = {
1547         { "tda998x", 0 },
1548         { }
1549 };
1550 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1551
1552 static struct i2c_driver tda998x_driver = {
1553         .probe = tda998x_probe,
1554         .remove = tda998x_remove,
1555         .driver = {
1556                 .name = "tda998x",
1557                 .of_match_table = of_match_ptr(tda998x_dt_ids),
1558         },
1559         .id_table = tda998x_ids,
1560 };
1561
1562 module_i2c_driver(tda998x_driver);
1563
1564 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1565 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1566 MODULE_LICENSE("GPL");