2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
23 #include <drm/exynos_drm.h>
24 #include "regs-fimc.h"
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_ipp.h"
27 #include "exynos_drm_fimc.h"
30 * FIMC stands for Fully Interactive Mobile Camera and
31 * supports image scaler/rotator and input/output DMA operations.
32 * input DMA reads image data from the memory.
33 * output DMA writes image data to memory.
34 * FIMC supports image rotation and image effect functions.
36 * M2M operation : supports crop/scale/rotation/csc so on.
37 * Memory ----> FIMC H/W ----> Memory.
38 * Writeback operation : supports cloned screen with FIMD.
39 * FIMD ----> FIMC H/W ----> Memory.
40 * Output operation : supports direct display using local path.
41 * Memory ----> FIMC H/W ----> FIMD.
46 * 1. check suspend/resume api if needed.
47 * 2. need to check use case platform_device_id.
48 * 3. check src/dst size with, height.
49 * 4. added check_prepare api for right register.
50 * 5. need to add supported list in prop_list.
51 * 6. check prescaler/scaler optimization.
54 #define FIMC_MAX_DEVS 4
55 #define FIMC_MAX_SRC 2
56 #define FIMC_MAX_DST 32
57 #define FIMC_SHFACTOR 10
58 #define FIMC_BUF_STOP 1
59 #define FIMC_BUF_START 2
60 #define FIMC_REG_SZ 32
61 #define FIMC_WIDTH_ITU_709 1280
62 #define FIMC_REFRESH_MAX 60
63 #define FIMC_REFRESH_MIN 12
64 #define FIMC_CROP_MAX 8192
65 #define FIMC_CROP_MIN 32
66 #define FIMC_SCALE_MAX 4224
67 #define FIMC_SCALE_MIN 32
69 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
70 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
71 struct fimc_context, ippdrv);
72 #define fimc_read(offset) readl(ctx->regs + (offset))
73 #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
91 static const char * const fimc_clock_names[] = {
92 [FIMC_CLK_LCLK] = "sclk_fimc",
93 [FIMC_CLK_GATE] = "fimc",
94 [FIMC_CLK_WB_A] = "pxl_async0",
95 [FIMC_CLK_WB_B] = "pxl_async1",
96 [FIMC_CLK_MUX] = "mux",
97 [FIMC_CLK_PARENT] = "parent",
100 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
103 * A structure of scaler.
105 * @range: narrow, wide.
106 * @bypass: unused scaler path.
107 * @up_h: horizontal scale up.
108 * @up_v: vertical scale up.
109 * @hratio: horizontal ratio.
110 * @vratio: vertical ratio.
122 * A structure of scaler capability.
124 * find user manual table 43-1.
125 * @in_hori: scaler input horizontal size.
126 * @bypass: scaler bypass mode.
127 * @dst_h_wo_rot: target horizontal size without output rotation.
128 * @dst_h_rot: target horizontal size with output rotation.
129 * @rl_w_wo_rot: real width without input rotation.
130 * @rl_h_rot: real height without output rotation.
132 struct fimc_capability {
145 * A structure of fimc context.
147 * @ippdrv: prepare initialization using ippdrv.
148 * @regs_res: register resources.
149 * @regs: memory mapped io registers.
150 * @lock: locking of operations.
151 * @clocks: fimc clocks.
152 * @clk_frequency: LCLK clock frequency.
153 * @sysreg: handle to SYSREG block regmap.
154 * @sc: scaler infomations.
155 * @pol: porarity of writeback.
158 * @suspended: qos operations.
160 struct fimc_context {
161 struct exynos_drm_ippdrv ippdrv;
162 struct resource *regs_res;
165 struct clk *clocks[FIMC_CLKS_MAX];
167 struct regmap *sysreg;
168 struct fimc_scaler sc;
169 struct exynos_drm_ipp_pol pol;
175 static void fimc_sw_reset(struct fimc_context *ctx)
179 /* stop dma operation */
180 cfg = fimc_read(EXYNOS_CISTATUS);
181 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
182 cfg = fimc_read(EXYNOS_MSCTRL);
183 cfg &= ~EXYNOS_MSCTRL_ENVID;
184 fimc_write(cfg, EXYNOS_MSCTRL);
187 cfg = fimc_read(EXYNOS_CISRCFMT);
188 cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
189 fimc_write(cfg, EXYNOS_CISRCFMT);
191 /* disable image capture */
192 cfg = fimc_read(EXYNOS_CIIMGCPT);
193 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
194 fimc_write(cfg, EXYNOS_CIIMGCPT);
197 cfg = fimc_read(EXYNOS_CIGCTRL);
198 cfg |= (EXYNOS_CIGCTRL_SWRST);
199 fimc_write(cfg, EXYNOS_CIGCTRL);
201 /* s/w reset complete */
202 cfg = fimc_read(EXYNOS_CIGCTRL);
203 cfg &= ~EXYNOS_CIGCTRL_SWRST;
204 fimc_write(cfg, EXYNOS_CIGCTRL);
207 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
210 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
212 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
213 SYSREG_FIMD0WB_DEST_MASK,
214 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
217 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
221 DRM_DEBUG_KMS("wb[%d]\n", wb);
223 cfg = fimc_read(EXYNOS_CIGCTRL);
224 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
225 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
226 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
227 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
228 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
229 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
233 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
234 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
237 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
238 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
242 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
243 EXYNOS_CIGCTRL_SELWRITEBACK_A |
244 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
245 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
249 fimc_write(cfg, EXYNOS_CIGCTRL);
252 static void fimc_set_polarity(struct fimc_context *ctx,
253 struct exynos_drm_ipp_pol *pol)
257 DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
258 pol->inv_pclk, pol->inv_vsync);
259 DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
260 pol->inv_href, pol->inv_hsync);
262 cfg = fimc_read(EXYNOS_CIGCTRL);
263 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
264 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
267 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
269 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
271 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
273 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
275 fimc_write(cfg, EXYNOS_CIGCTRL);
278 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
282 DRM_DEBUG_KMS("enable[%d]\n", enable);
284 cfg = fimc_read(EXYNOS_CIGCTRL);
286 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
288 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
290 fimc_write(cfg, EXYNOS_CIGCTRL);
293 static void fimc_handle_irq(struct fimc_context *ctx, bool enable,
294 bool overflow, bool level)
298 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
299 enable, overflow, level);
301 cfg = fimc_read(EXYNOS_CIGCTRL);
303 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL);
304 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE;
306 cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN;
308 cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL;
310 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE);
312 fimc_write(cfg, EXYNOS_CIGCTRL);
315 static void fimc_clear_irq(struct fimc_context *ctx)
319 cfg = fimc_read(EXYNOS_CIGCTRL);
320 cfg |= EXYNOS_CIGCTRL_IRQ_CLR;
321 fimc_write(cfg, EXYNOS_CIGCTRL);
324 static bool fimc_check_ovf(struct fimc_context *ctx)
326 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
327 u32 cfg, status, flag;
329 status = fimc_read(EXYNOS_CISTATUS);
330 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
331 EXYNOS_CISTATUS_OVFICR;
333 DRM_DEBUG_KMS("flag[0x%x]\n", flag);
336 cfg = fimc_read(EXYNOS_CIWDOFST);
337 cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
338 EXYNOS_CIWDOFST_CLROVFICR);
340 fimc_write(cfg, EXYNOS_CIWDOFST);
342 cfg = fimc_read(EXYNOS_CIWDOFST);
343 cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
344 EXYNOS_CIWDOFST_CLROVFICR);
346 fimc_write(cfg, EXYNOS_CIWDOFST);
348 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
356 static bool fimc_check_frame_end(struct fimc_context *ctx)
360 cfg = fimc_read(EXYNOS_CISTATUS);
362 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
364 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
367 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
368 fimc_write(cfg, EXYNOS_CISTATUS);
373 static int fimc_get_buf_id(struct fimc_context *ctx)
376 int frame_cnt, buf_id;
378 cfg = fimc_read(EXYNOS_CISTATUS2);
379 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
382 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
384 DRM_DEBUG_KMS("present[%d]before[%d]\n",
385 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
386 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
388 if (frame_cnt == 0) {
389 DRM_ERROR("failed to get frame count.\n");
393 buf_id = frame_cnt - 1;
394 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
399 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
403 DRM_DEBUG_KMS("enable[%d]\n", enable);
405 cfg = fimc_read(EXYNOS_CIOCTRL);
407 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
409 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
411 fimc_write(cfg, EXYNOS_CIOCTRL);
415 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
417 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
420 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
423 cfg = fimc_read(EXYNOS_CISCCTRL);
424 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
427 case DRM_FORMAT_RGB565:
428 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
429 fimc_write(cfg, EXYNOS_CISCCTRL);
431 case DRM_FORMAT_RGB888:
432 case DRM_FORMAT_XRGB8888:
433 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
434 fimc_write(cfg, EXYNOS_CISCCTRL);
442 cfg = fimc_read(EXYNOS_MSCTRL);
443 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
444 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
445 EXYNOS_MSCTRL_ORDER422_YCBYCR);
448 case DRM_FORMAT_YUYV:
449 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
451 case DRM_FORMAT_YVYU:
452 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
454 case DRM_FORMAT_UYVY:
455 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
457 case DRM_FORMAT_VYUY:
458 case DRM_FORMAT_YUV444:
459 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
461 case DRM_FORMAT_NV21:
462 case DRM_FORMAT_NV61:
463 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
464 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
466 case DRM_FORMAT_YUV422:
467 case DRM_FORMAT_YUV420:
468 case DRM_FORMAT_YVU420:
469 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
471 case DRM_FORMAT_NV12:
472 case DRM_FORMAT_NV12MT:
473 case DRM_FORMAT_NV16:
474 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
475 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
478 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
482 fimc_write(cfg, EXYNOS_MSCTRL);
487 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
489 struct fimc_context *ctx = get_fimc_context(dev);
490 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
493 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
495 cfg = fimc_read(EXYNOS_MSCTRL);
496 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
499 case DRM_FORMAT_RGB565:
500 case DRM_FORMAT_RGB888:
501 case DRM_FORMAT_XRGB8888:
502 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
504 case DRM_FORMAT_YUV444:
505 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
507 case DRM_FORMAT_YUYV:
508 case DRM_FORMAT_YVYU:
509 case DRM_FORMAT_UYVY:
510 case DRM_FORMAT_VYUY:
511 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
513 case DRM_FORMAT_NV16:
514 case DRM_FORMAT_NV61:
515 case DRM_FORMAT_YUV422:
516 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
518 case DRM_FORMAT_YUV420:
519 case DRM_FORMAT_YVU420:
520 case DRM_FORMAT_NV12:
521 case DRM_FORMAT_NV21:
522 case DRM_FORMAT_NV12MT:
523 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
526 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
530 fimc_write(cfg, EXYNOS_MSCTRL);
532 cfg = fimc_read(EXYNOS_CIDMAPARAM);
533 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
535 if (fmt == DRM_FORMAT_NV12MT)
536 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
538 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
540 fimc_write(cfg, EXYNOS_CIDMAPARAM);
542 return fimc_src_set_fmt_order(ctx, fmt);
545 static int fimc_src_set_transf(struct device *dev,
546 enum drm_exynos_degree degree,
547 enum drm_exynos_flip flip, bool *swap)
549 struct fimc_context *ctx = get_fimc_context(dev);
550 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
553 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
555 cfg1 = fimc_read(EXYNOS_MSCTRL);
556 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
557 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
559 cfg2 = fimc_read(EXYNOS_CITRGFMT);
560 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
563 case EXYNOS_DRM_DEGREE_0:
564 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
565 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
566 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
567 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
569 case EXYNOS_DRM_DEGREE_90:
570 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
571 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
572 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
573 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
574 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
576 case EXYNOS_DRM_DEGREE_180:
577 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
578 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
579 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
580 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
581 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
582 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
584 case EXYNOS_DRM_DEGREE_270:
585 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
586 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
587 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
588 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
589 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
590 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
591 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
594 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
598 fimc_write(cfg1, EXYNOS_MSCTRL);
599 fimc_write(cfg2, EXYNOS_CITRGFMT);
600 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
605 static int fimc_set_window(struct fimc_context *ctx,
606 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
608 u32 cfg, h1, h2, v1, v2;
612 h2 = sz->hsize - pos->w - pos->x;
614 v2 = sz->vsize - pos->h - pos->y;
616 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
617 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
618 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
621 * set window offset 1, 2 size
622 * check figure 43-21 in user manual
624 cfg = fimc_read(EXYNOS_CIWDOFST);
625 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
626 EXYNOS_CIWDOFST_WINVEROFST_MASK);
627 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
628 EXYNOS_CIWDOFST_WINVEROFST(v1));
629 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
630 fimc_write(cfg, EXYNOS_CIWDOFST);
632 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
633 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
634 fimc_write(cfg, EXYNOS_CIWDOFST2);
639 static int fimc_src_set_size(struct device *dev, int swap,
640 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
642 struct fimc_context *ctx = get_fimc_context(dev);
643 struct drm_exynos_pos img_pos = *pos;
644 struct drm_exynos_sz img_sz = *sz;
647 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
648 swap, sz->hsize, sz->vsize);
651 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
652 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
654 fimc_write(cfg, EXYNOS_ORGISIZE);
656 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
661 img_sz.hsize = sz->vsize;
662 img_sz.vsize = sz->hsize;
665 /* set input DMA image size */
666 cfg = fimc_read(EXYNOS_CIREAL_ISIZE);
667 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
668 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
669 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
670 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
671 fimc_write(cfg, EXYNOS_CIREAL_ISIZE);
674 * set input FIFO image size
675 * for now, we support only ITU601 8 bit mode
677 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
678 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
679 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
680 fimc_write(cfg, EXYNOS_CISRCFMT);
682 /* offset Y(RGB), Cb, Cr */
683 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
684 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
685 fimc_write(cfg, EXYNOS_CIIYOFF);
686 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
687 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
688 fimc_write(cfg, EXYNOS_CIICBOFF);
689 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
690 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
691 fimc_write(cfg, EXYNOS_CIICROFF);
693 return fimc_set_window(ctx, &img_pos, &img_sz);
696 static int fimc_src_set_addr(struct device *dev,
697 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
698 enum drm_exynos_ipp_buf_type buf_type)
700 struct fimc_context *ctx = get_fimc_context(dev);
701 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
702 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
703 struct drm_exynos_ipp_property *property;
704 struct drm_exynos_ipp_config *config;
707 DRM_ERROR("failed to get c_node.\n");
711 property = &c_node->property;
713 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
714 property->prop_id, buf_id, buf_type);
716 if (buf_id > FIMC_MAX_SRC) {
717 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
721 /* address register set */
723 case IPP_BUF_ENQUEUE:
724 config = &property->config[EXYNOS_DRM_OPS_SRC];
725 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
726 EXYNOS_CIIYSA(buf_id));
728 if (config->fmt == DRM_FORMAT_YVU420) {
729 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
730 EXYNOS_CIICBSA(buf_id));
731 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
732 EXYNOS_CIICRSA(buf_id));
734 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
735 EXYNOS_CIICBSA(buf_id));
736 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
737 EXYNOS_CIICRSA(buf_id));
740 case IPP_BUF_DEQUEUE:
741 fimc_write(0x0, EXYNOS_CIIYSA(buf_id));
742 fimc_write(0x0, EXYNOS_CIICBSA(buf_id));
743 fimc_write(0x0, EXYNOS_CIICRSA(buf_id));
753 static struct exynos_drm_ipp_ops fimc_src_ops = {
754 .set_fmt = fimc_src_set_fmt,
755 .set_transf = fimc_src_set_transf,
756 .set_size = fimc_src_set_size,
757 .set_addr = fimc_src_set_addr,
760 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
762 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
765 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
768 cfg = fimc_read(EXYNOS_CISCCTRL);
769 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
772 case DRM_FORMAT_RGB565:
773 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
774 fimc_write(cfg, EXYNOS_CISCCTRL);
776 case DRM_FORMAT_RGB888:
777 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
778 fimc_write(cfg, EXYNOS_CISCCTRL);
780 case DRM_FORMAT_XRGB8888:
781 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
782 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
783 fimc_write(cfg, EXYNOS_CISCCTRL);
791 cfg = fimc_read(EXYNOS_CIOCTRL);
792 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
793 EXYNOS_CIOCTRL_ORDER422_MASK |
794 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
797 case DRM_FORMAT_XRGB8888:
798 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
800 case DRM_FORMAT_YUYV:
801 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
803 case DRM_FORMAT_YVYU:
804 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
806 case DRM_FORMAT_UYVY:
807 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
809 case DRM_FORMAT_VYUY:
810 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
812 case DRM_FORMAT_NV21:
813 case DRM_FORMAT_NV61:
814 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
815 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
817 case DRM_FORMAT_YUV422:
818 case DRM_FORMAT_YUV420:
819 case DRM_FORMAT_YVU420:
820 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
822 case DRM_FORMAT_NV12:
823 case DRM_FORMAT_NV12MT:
824 case DRM_FORMAT_NV16:
825 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
826 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
829 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
833 fimc_write(cfg, EXYNOS_CIOCTRL);
838 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
840 struct fimc_context *ctx = get_fimc_context(dev);
841 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
844 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
846 cfg = fimc_read(EXYNOS_CIEXTEN);
848 if (fmt == DRM_FORMAT_AYUV) {
849 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
850 fimc_write(cfg, EXYNOS_CIEXTEN);
852 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
853 fimc_write(cfg, EXYNOS_CIEXTEN);
855 cfg = fimc_read(EXYNOS_CITRGFMT);
856 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
859 case DRM_FORMAT_RGB565:
860 case DRM_FORMAT_RGB888:
861 case DRM_FORMAT_XRGB8888:
862 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
864 case DRM_FORMAT_YUYV:
865 case DRM_FORMAT_YVYU:
866 case DRM_FORMAT_UYVY:
867 case DRM_FORMAT_VYUY:
868 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
870 case DRM_FORMAT_NV16:
871 case DRM_FORMAT_NV61:
872 case DRM_FORMAT_YUV422:
873 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
875 case DRM_FORMAT_YUV420:
876 case DRM_FORMAT_YVU420:
877 case DRM_FORMAT_NV12:
878 case DRM_FORMAT_NV12MT:
879 case DRM_FORMAT_NV21:
880 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
883 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
888 fimc_write(cfg, EXYNOS_CITRGFMT);
891 cfg = fimc_read(EXYNOS_CIDMAPARAM);
892 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
894 if (fmt == DRM_FORMAT_NV12MT)
895 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
897 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
899 fimc_write(cfg, EXYNOS_CIDMAPARAM);
901 return fimc_dst_set_fmt_order(ctx, fmt);
904 static int fimc_dst_set_transf(struct device *dev,
905 enum drm_exynos_degree degree,
906 enum drm_exynos_flip flip, bool *swap)
908 struct fimc_context *ctx = get_fimc_context(dev);
909 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
912 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
914 cfg = fimc_read(EXYNOS_CITRGFMT);
915 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
916 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
919 case EXYNOS_DRM_DEGREE_0:
920 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
921 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
922 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
923 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
925 case EXYNOS_DRM_DEGREE_90:
926 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
927 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
928 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
929 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
930 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
932 case EXYNOS_DRM_DEGREE_180:
933 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
934 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
935 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
936 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
937 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
938 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
940 case EXYNOS_DRM_DEGREE_270:
941 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
942 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
943 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
944 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
945 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
946 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
947 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
950 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
954 fimc_write(cfg, EXYNOS_CITRGFMT);
955 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
960 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
961 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
963 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
964 u32 cfg, cfg_ext, shfactor;
965 u32 pre_dst_width, pre_dst_height;
966 u32 hfactor, vfactor;
968 u32 src_w, src_h, dst_w, dst_h;
970 cfg_ext = fimc_read(EXYNOS_CITRGFMT);
971 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
979 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
987 /* fimc_ippdrv_check_property assures that dividers are not null */
988 hfactor = fls(src_w / dst_w / 2);
989 if (hfactor > FIMC_SHFACTOR / 2) {
990 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
994 vfactor = fls(src_h / dst_h / 2);
995 if (vfactor > FIMC_SHFACTOR / 2) {
996 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
1000 pre_dst_width = src_w >> hfactor;
1001 pre_dst_height = src_h >> vfactor;
1002 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
1003 pre_dst_width, pre_dst_height);
1004 DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
1006 sc->hratio = (src_w << 14) / (dst_w << hfactor);
1007 sc->vratio = (src_h << 14) / (dst_h << vfactor);
1008 sc->up_h = (dst_w >= src_w) ? true : false;
1009 sc->up_v = (dst_h >= src_h) ? true : false;
1010 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1011 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1013 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1014 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1016 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1017 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1018 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1019 fimc_write(cfg, EXYNOS_CISCPRERATIO);
1021 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1022 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1023 fimc_write(cfg, EXYNOS_CISCPREDST);
1028 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1032 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1033 sc->range, sc->bypass, sc->up_h, sc->up_v);
1034 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1035 sc->hratio, sc->vratio);
1037 cfg = fimc_read(EXYNOS_CISCCTRL);
1038 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1039 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1040 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1041 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1042 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1043 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1046 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1047 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1049 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1051 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1053 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1055 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1056 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1057 fimc_write(cfg, EXYNOS_CISCCTRL);
1059 cfg_ext = fimc_read(EXYNOS_CIEXTEN);
1060 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1061 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1062 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1063 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1064 fimc_write(cfg_ext, EXYNOS_CIEXTEN);
1067 static int fimc_dst_set_size(struct device *dev, int swap,
1068 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1070 struct fimc_context *ctx = get_fimc_context(dev);
1071 struct drm_exynos_pos img_pos = *pos;
1072 struct drm_exynos_sz img_sz = *sz;
1075 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1076 swap, sz->hsize, sz->vsize);
1079 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1080 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1082 fimc_write(cfg, EXYNOS_ORGOSIZE);
1084 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1087 cfg = fimc_read(EXYNOS_CIGCTRL);
1088 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1090 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1091 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1093 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1095 fimc_write(cfg, EXYNOS_CIGCTRL);
1100 img_sz.hsize = sz->vsize;
1101 img_sz.vsize = sz->hsize;
1104 /* target image size */
1105 cfg = fimc_read(EXYNOS_CITRGFMT);
1106 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1107 EXYNOS_CITRGFMT_TARGETV_MASK);
1108 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1109 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1110 fimc_write(cfg, EXYNOS_CITRGFMT);
1113 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1114 fimc_write(cfg, EXYNOS_CITAREA);
1116 /* offset Y(RGB), Cb, Cr */
1117 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1118 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1119 fimc_write(cfg, EXYNOS_CIOYOFF);
1120 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1121 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1122 fimc_write(cfg, EXYNOS_CIOCBOFF);
1123 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1124 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1125 fimc_write(cfg, EXYNOS_CIOCROFF);
1130 static int fimc_dst_get_buf_seq(struct fimc_context *ctx)
1132 u32 cfg, i, buf_num = 0;
1133 u32 mask = 0x00000001;
1135 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1137 for (i = 0; i < FIMC_REG_SZ; i++)
1138 if (cfg & (mask << i))
1141 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1146 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1147 enum drm_exynos_ipp_buf_type buf_type)
1149 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1152 u32 mask = 0x00000001 << buf_id;
1155 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1157 mutex_lock(&ctx->lock);
1159 /* mask register set */
1160 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1163 case IPP_BUF_ENQUEUE:
1166 case IPP_BUF_DEQUEUE:
1170 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1177 cfg |= (enable << buf_id);
1178 fimc_write(cfg, EXYNOS_CIFCNTSEQ);
1180 /* interrupt enable */
1181 if (buf_type == IPP_BUF_ENQUEUE &&
1182 fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START)
1183 fimc_handle_irq(ctx, true, false, true);
1185 /* interrupt disable */
1186 if (buf_type == IPP_BUF_DEQUEUE &&
1187 fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP)
1188 fimc_handle_irq(ctx, false, false, true);
1191 mutex_unlock(&ctx->lock);
1195 static int fimc_dst_set_addr(struct device *dev,
1196 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1197 enum drm_exynos_ipp_buf_type buf_type)
1199 struct fimc_context *ctx = get_fimc_context(dev);
1200 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1201 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1202 struct drm_exynos_ipp_property *property;
1203 struct drm_exynos_ipp_config *config;
1206 DRM_ERROR("failed to get c_node.\n");
1210 property = &c_node->property;
1212 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1213 property->prop_id, buf_id, buf_type);
1215 if (buf_id > FIMC_MAX_DST) {
1216 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1220 /* address register set */
1222 case IPP_BUF_ENQUEUE:
1223 config = &property->config[EXYNOS_DRM_OPS_DST];
1225 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1226 EXYNOS_CIOYSA(buf_id));
1228 if (config->fmt == DRM_FORMAT_YVU420) {
1229 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1230 EXYNOS_CIOCBSA(buf_id));
1231 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1232 EXYNOS_CIOCRSA(buf_id));
1234 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1235 EXYNOS_CIOCBSA(buf_id));
1236 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1237 EXYNOS_CIOCRSA(buf_id));
1240 case IPP_BUF_DEQUEUE:
1241 fimc_write(0x0, EXYNOS_CIOYSA(buf_id));
1242 fimc_write(0x0, EXYNOS_CIOCBSA(buf_id));
1243 fimc_write(0x0, EXYNOS_CIOCRSA(buf_id));
1250 return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1253 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1254 .set_fmt = fimc_dst_set_fmt,
1255 .set_transf = fimc_dst_set_transf,
1256 .set_size = fimc_dst_set_size,
1257 .set_addr = fimc_dst_set_addr,
1260 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1262 DRM_DEBUG_KMS("enable[%d]\n", enable);
1265 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1266 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1267 ctx->suspended = false;
1269 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1270 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1271 ctx->suspended = true;
1277 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1279 struct fimc_context *ctx = dev_id;
1280 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1281 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1282 struct drm_exynos_ipp_event_work *event_work =
1286 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1288 fimc_clear_irq(ctx);
1289 if (fimc_check_ovf(ctx))
1292 if (!fimc_check_frame_end(ctx))
1295 buf_id = fimc_get_buf_id(ctx);
1299 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1301 if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1302 DRM_ERROR("failed to dequeue.\n");
1306 event_work->ippdrv = ippdrv;
1307 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1308 queue_work(ippdrv->event_workq, (struct work_struct *)event_work);
1313 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1315 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1317 prop_list->version = 1;
1318 prop_list->writeback = 1;
1319 prop_list->refresh_min = FIMC_REFRESH_MIN;
1320 prop_list->refresh_max = FIMC_REFRESH_MAX;
1321 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1322 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1323 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1324 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1325 (1 << EXYNOS_DRM_DEGREE_90) |
1326 (1 << EXYNOS_DRM_DEGREE_180) |
1327 (1 << EXYNOS_DRM_DEGREE_270);
1329 prop_list->crop = 1;
1330 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1331 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1332 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1333 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1334 prop_list->scale = 1;
1335 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1336 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1337 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1338 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1343 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1346 case EXYNOS_DRM_FLIP_NONE:
1347 case EXYNOS_DRM_FLIP_VERTICAL:
1348 case EXYNOS_DRM_FLIP_HORIZONTAL:
1349 case EXYNOS_DRM_FLIP_BOTH:
1352 DRM_DEBUG_KMS("invalid flip\n");
1357 static int fimc_ippdrv_check_property(struct device *dev,
1358 struct drm_exynos_ipp_property *property)
1360 struct fimc_context *ctx = get_fimc_context(dev);
1361 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1362 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1363 struct drm_exynos_ipp_config *config;
1364 struct drm_exynos_pos *pos;
1365 struct drm_exynos_sz *sz;
1369 for_each_ipp_ops(i) {
1370 if ((i == EXYNOS_DRM_OPS_SRC) &&
1371 (property->cmd == IPP_CMD_WB))
1374 config = &property->config[i];
1378 /* check for flip */
1379 if (!fimc_check_drm_flip(config->flip)) {
1380 DRM_ERROR("invalid flip.\n");
1384 /* check for degree */
1385 switch (config->degree) {
1386 case EXYNOS_DRM_DEGREE_90:
1387 case EXYNOS_DRM_DEGREE_270:
1390 case EXYNOS_DRM_DEGREE_0:
1391 case EXYNOS_DRM_DEGREE_180:
1395 DRM_ERROR("invalid degree.\n");
1399 /* check for buffer bound */
1400 if ((pos->x + pos->w > sz->hsize) ||
1401 (pos->y + pos->h > sz->vsize)) {
1402 DRM_ERROR("out of buf bound.\n");
1406 /* check for crop */
1407 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1409 if ((pos->h < pp->crop_min.hsize) ||
1410 (sz->vsize > pp->crop_max.hsize) ||
1411 (pos->w < pp->crop_min.vsize) ||
1412 (sz->hsize > pp->crop_max.vsize)) {
1413 DRM_ERROR("out of crop size.\n");
1417 if ((pos->w < pp->crop_min.hsize) ||
1418 (sz->hsize > pp->crop_max.hsize) ||
1419 (pos->h < pp->crop_min.vsize) ||
1420 (sz->vsize > pp->crop_max.vsize)) {
1421 DRM_ERROR("out of crop size.\n");
1427 /* check for scale */
1428 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1430 if ((pos->h < pp->scale_min.hsize) ||
1431 (sz->vsize > pp->scale_max.hsize) ||
1432 (pos->w < pp->scale_min.vsize) ||
1433 (sz->hsize > pp->scale_max.vsize)) {
1434 DRM_ERROR("out of scale size.\n");
1438 if ((pos->w < pp->scale_min.hsize) ||
1439 (sz->hsize > pp->scale_max.hsize) ||
1440 (pos->h < pp->scale_min.vsize) ||
1441 (sz->vsize > pp->scale_max.vsize)) {
1442 DRM_ERROR("out of scale size.\n");
1452 for_each_ipp_ops(i) {
1453 if ((i == EXYNOS_DRM_OPS_SRC) &&
1454 (property->cmd == IPP_CMD_WB))
1457 config = &property->config[i];
1461 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1462 i ? "dst" : "src", config->flip, config->degree,
1463 pos->x, pos->y, pos->w, pos->h,
1464 sz->hsize, sz->vsize);
1470 static void fimc_clear_addr(struct fimc_context *ctx)
1474 for (i = 0; i < FIMC_MAX_SRC; i++) {
1475 fimc_write(0, EXYNOS_CIIYSA(i));
1476 fimc_write(0, EXYNOS_CIICBSA(i));
1477 fimc_write(0, EXYNOS_CIICRSA(i));
1480 for (i = 0; i < FIMC_MAX_DST; i++) {
1481 fimc_write(0, EXYNOS_CIOYSA(i));
1482 fimc_write(0, EXYNOS_CIOCBSA(i));
1483 fimc_write(0, EXYNOS_CIOCRSA(i));
1487 static int fimc_ippdrv_reset(struct device *dev)
1489 struct fimc_context *ctx = get_fimc_context(dev);
1491 /* reset h/w block */
1494 /* reset scaler capability */
1495 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1497 fimc_clear_addr(ctx);
1502 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1504 struct fimc_context *ctx = get_fimc_context(dev);
1505 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1506 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1507 struct drm_exynos_ipp_property *property;
1508 struct drm_exynos_ipp_config *config;
1509 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1510 struct drm_exynos_ipp_set_wb set_wb;
1514 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1517 DRM_ERROR("failed to get c_node.\n");
1521 property = &c_node->property;
1523 fimc_handle_irq(ctx, true, false, true);
1525 for_each_ipp_ops(i) {
1526 config = &property->config[i];
1527 img_pos[i] = config->pos;
1530 ret = fimc_set_prescaler(ctx, &ctx->sc,
1531 &img_pos[EXYNOS_DRM_OPS_SRC],
1532 &img_pos[EXYNOS_DRM_OPS_DST]);
1534 dev_err(dev, "failed to set precalser.\n");
1538 /* If set ture, we can save jpeg about screen */
1539 fimc_handle_jpeg(ctx, false);
1540 fimc_set_scaler(ctx, &ctx->sc);
1541 fimc_set_polarity(ctx, &ctx->pol);
1545 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1546 fimc_handle_lastend(ctx, false);
1549 cfg0 = fimc_read(EXYNOS_MSCTRL);
1550 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1551 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1552 fimc_write(cfg0, EXYNOS_MSCTRL);
1555 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1556 fimc_handle_lastend(ctx, true);
1559 ret = fimc_set_camblk_fimd0_wb(ctx);
1561 dev_err(dev, "camblk setup failed.\n");
1566 set_wb.refresh = property->refresh_rate;
1567 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1569 case IPP_CMD_OUTPUT:
1572 dev_err(dev, "invalid operations.\n");
1577 fimc_write(0x0, EXYNOS_CISTATUS);
1579 cfg0 = fimc_read(EXYNOS_CIIMGCPT);
1580 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1581 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1584 cfg1 = fimc_read(EXYNOS_CISCCTRL);
1585 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1586 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1587 EXYNOS_CISCCTRL_SCALERSTART);
1589 fimc_write(cfg1, EXYNOS_CISCCTRL);
1591 /* Enable image capture*/
1592 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1593 fimc_write(cfg0, EXYNOS_CIIMGCPT);
1595 /* Disable frame end irq */
1596 cfg0 = fimc_read(EXYNOS_CIGCTRL);
1597 cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1598 fimc_write(cfg0, EXYNOS_CIGCTRL);
1600 cfg0 = fimc_read(EXYNOS_CIOCTRL);
1601 cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK;
1602 fimc_write(cfg0, EXYNOS_CIOCTRL);
1604 if (cmd == IPP_CMD_M2M) {
1605 cfg0 = fimc_read(EXYNOS_MSCTRL);
1606 cfg0 |= EXYNOS_MSCTRL_ENVID;
1607 fimc_write(cfg0, EXYNOS_MSCTRL);
1609 cfg0 = fimc_read(EXYNOS_MSCTRL);
1610 cfg0 |= EXYNOS_MSCTRL_ENVID;
1611 fimc_write(cfg0, EXYNOS_MSCTRL);
1617 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1619 struct fimc_context *ctx = get_fimc_context(dev);
1620 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1623 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1628 cfg = fimc_read(EXYNOS_MSCTRL);
1629 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1630 cfg &= ~EXYNOS_MSCTRL_ENVID;
1631 fimc_write(cfg, EXYNOS_MSCTRL);
1634 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1636 case IPP_CMD_OUTPUT:
1638 dev_err(dev, "invalid operations.\n");
1642 fimc_handle_irq(ctx, false, false, true);
1644 /* reset sequence */
1645 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
1647 /* Scaler disable */
1648 cfg = fimc_read(EXYNOS_CISCCTRL);
1649 cfg &= ~EXYNOS_CISCCTRL_SCALERSTART;
1650 fimc_write(cfg, EXYNOS_CISCCTRL);
1652 /* Disable image capture */
1653 cfg = fimc_read(EXYNOS_CIIMGCPT);
1654 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1655 fimc_write(cfg, EXYNOS_CIIMGCPT);
1657 /* Enable frame end irq */
1658 cfg = fimc_read(EXYNOS_CIGCTRL);
1659 cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1660 fimc_write(cfg, EXYNOS_CIGCTRL);
1663 static void fimc_put_clocks(struct fimc_context *ctx)
1667 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1668 if (IS_ERR(ctx->clocks[i]))
1670 clk_put(ctx->clocks[i]);
1671 ctx->clocks[i] = ERR_PTR(-EINVAL);
1675 static int fimc_setup_clocks(struct fimc_context *ctx)
1677 struct device *fimc_dev = ctx->ippdrv.dev;
1681 for (i = 0; i < FIMC_CLKS_MAX; i++)
1682 ctx->clocks[i] = ERR_PTR(-EINVAL);
1684 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1685 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1686 dev = fimc_dev->parent;
1690 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1691 if (IS_ERR(ctx->clocks[i])) {
1692 if (i >= FIMC_CLK_MUX)
1694 ret = PTR_ERR(ctx->clocks[i]);
1695 dev_err(fimc_dev, "failed to get clock: %s\n",
1696 fimc_clock_names[i]);
1701 /* Optional FIMC LCLK parent clock setting */
1702 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1703 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1704 ctx->clocks[FIMC_CLK_PARENT]);
1706 dev_err(fimc_dev, "failed to set parent.\n");
1711 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1715 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1719 fimc_put_clocks(ctx);
1723 static int fimc_parse_dt(struct fimc_context *ctx)
1725 struct device_node *node = ctx->ippdrv.dev->of_node;
1727 /* Handle only devices that support the LCD Writeback data path */
1728 if (!of_property_read_bool(node, "samsung,lcd-wb"))
1731 if (of_property_read_u32(node, "clock-frequency",
1732 &ctx->clk_frequency))
1733 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1735 ctx->id = of_alias_get_id(node, "fimc");
1738 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1745 static int fimc_probe(struct platform_device *pdev)
1747 struct device *dev = &pdev->dev;
1748 struct fimc_context *ctx;
1749 struct resource *res;
1750 struct exynos_drm_ippdrv *ippdrv;
1753 if (!dev->of_node) {
1754 dev_err(dev, "device tree node not found.\n");
1758 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1762 ctx->ippdrv.dev = dev;
1764 ret = fimc_parse_dt(ctx);
1768 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1770 if (IS_ERR(ctx->sysreg)) {
1771 dev_err(dev, "syscon regmap lookup failed.\n");
1772 return PTR_ERR(ctx->sysreg);
1775 /* resource memory */
1776 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1777 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1778 if (IS_ERR(ctx->regs))
1779 return PTR_ERR(ctx->regs);
1782 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1784 dev_err(dev, "failed to request irq resource.\n");
1788 ctx->irq = res->start;
1789 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1790 IRQF_ONESHOT, "drm_fimc", ctx);
1792 dev_err(dev, "failed to request irq.\n");
1796 ret = fimc_setup_clocks(ctx);
1800 ippdrv = &ctx->ippdrv;
1801 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1802 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1803 ippdrv->check_property = fimc_ippdrv_check_property;
1804 ippdrv->reset = fimc_ippdrv_reset;
1805 ippdrv->start = fimc_ippdrv_start;
1806 ippdrv->stop = fimc_ippdrv_stop;
1807 ret = fimc_init_prop_list(ippdrv);
1809 dev_err(dev, "failed to init property list.\n");
1813 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1815 mutex_init(&ctx->lock);
1816 platform_set_drvdata(pdev, ctx);
1818 pm_runtime_set_active(dev);
1819 pm_runtime_enable(dev);
1821 ret = exynos_drm_ippdrv_register(ippdrv);
1823 dev_err(dev, "failed to register drm fimc device.\n");
1827 dev_info(dev, "drm fimc registered successfully.\n");
1832 pm_runtime_disable(dev);
1834 fimc_put_clocks(ctx);
1839 static int fimc_remove(struct platform_device *pdev)
1841 struct device *dev = &pdev->dev;
1842 struct fimc_context *ctx = get_fimc_context(dev);
1843 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1845 exynos_drm_ippdrv_unregister(ippdrv);
1846 mutex_destroy(&ctx->lock);
1848 fimc_put_clocks(ctx);
1849 pm_runtime_set_suspended(dev);
1850 pm_runtime_disable(dev);
1855 #ifdef CONFIG_PM_SLEEP
1856 static int fimc_suspend(struct device *dev)
1858 struct fimc_context *ctx = get_fimc_context(dev);
1860 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1862 if (pm_runtime_suspended(dev))
1865 return fimc_clk_ctrl(ctx, false);
1868 static int fimc_resume(struct device *dev)
1870 struct fimc_context *ctx = get_fimc_context(dev);
1872 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1874 if (!pm_runtime_suspended(dev))
1875 return fimc_clk_ctrl(ctx, true);
1881 #ifdef CONFIG_PM_RUNTIME
1882 static int fimc_runtime_suspend(struct device *dev)
1884 struct fimc_context *ctx = get_fimc_context(dev);
1886 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1888 return fimc_clk_ctrl(ctx, false);
1891 static int fimc_runtime_resume(struct device *dev)
1893 struct fimc_context *ctx = get_fimc_context(dev);
1895 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1897 return fimc_clk_ctrl(ctx, true);
1901 static const struct dev_pm_ops fimc_pm_ops = {
1902 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1903 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1906 static const struct of_device_id fimc_of_match[] = {
1907 { .compatible = "samsung,exynos4210-fimc" },
1908 { .compatible = "samsung,exynos4212-fimc" },
1912 struct platform_driver fimc_driver = {
1913 .probe = fimc_probe,
1914 .remove = fimc_remove,
1916 .of_match_table = fimc_of_match,
1917 .name = "exynos-drm-fimc",
1918 .owner = THIS_MODULE,