2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_displayid.h>
39 #define version_greater(edid, maj, min) \
40 (((edid)->version > (maj)) || \
41 ((edid)->version == (maj) && (edid)->revision > (min)))
43 #define EDID_EST_TIMINGS 16
44 #define EDID_STD_TIMINGS 8
45 #define EDID_DETAILED_TIMINGS 4
48 * EDID blocks out in the wild have a variety of bugs, try to collect
49 * them here (note that userspace may work around broken monitors first,
50 * but fixes should make their way here so that the kernel "just works"
51 * on as many displays as possible).
54 /* First detailed mode wrong, use largest 60Hz mode */
55 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
56 /* Reported 135MHz pixel clock is too high, needs adjustment */
57 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
58 /* Prefer the largest mode at 75 Hz */
59 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
60 /* Detail timing is in cm not mm */
61 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
62 /* Detailed timing descriptors have bogus size values, so just take the
63 * maximum size and use that.
65 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
66 /* Monitor forgot to set the first detailed is preferred bit. */
67 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
68 /* use +hsync +vsync for detailed mode */
69 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
70 /* Force reduced-blanking timings for detailed modes */
71 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
73 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
75 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
77 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
79 struct detailed_mode_closure {
80 struct drm_connector *connector;
92 static struct edid_quirk {
96 } edid_quirk_list[] = {
98 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
100 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
102 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
104 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
105 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
107 /* Belinea 10 15 55 */
108 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
109 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
111 /* Envision Peripherals, Inc. EN-7100e */
112 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
113 /* Envision EN2028 */
114 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
116 /* Funai Electronics PM36B */
117 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
118 EDID_QUIRK_DETAILED_IN_CM },
120 /* LG Philips LCD LP154W01-A5 */
121 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
122 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
124 /* Philips 107p5 CRT */
125 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
128 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130 /* Samsung SyncMaster 205BW. Note: irony */
131 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
132 /* Samsung SyncMaster 22[5-6]BW */
133 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
134 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
137 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
139 /* ViewSonic VA2026w */
140 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
142 /* Medion MD 30217 PG */
143 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
145 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
146 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
148 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
149 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
153 * Autogenerated from the DMT spec.
154 * This table is copied from xfree86/modes/xf86EdidModes.c.
156 static const struct drm_display_mode drm_dmt_modes[] = {
157 /* 0x01 - 640x350@85Hz */
158 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
159 736, 832, 0, 350, 382, 385, 445, 0,
160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
161 /* 0x02 - 640x400@85Hz */
162 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
163 736, 832, 0, 400, 401, 404, 445, 0,
164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
165 /* 0x03 - 720x400@85Hz */
166 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
167 828, 936, 0, 400, 401, 404, 446, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
169 /* 0x04 - 640x480@60Hz */
170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
171 752, 800, 0, 480, 490, 492, 525, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
173 /* 0x05 - 640x480@72Hz */
174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
175 704, 832, 0, 480, 489, 492, 520, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
177 /* 0x06 - 640x480@75Hz */
178 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
179 720, 840, 0, 480, 481, 484, 500, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
181 /* 0x07 - 640x480@85Hz */
182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
183 752, 832, 0, 480, 481, 484, 509, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
185 /* 0x08 - 800x600@56Hz */
186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
187 896, 1024, 0, 600, 601, 603, 625, 0,
188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
189 /* 0x09 - 800x600@60Hz */
190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
191 968, 1056, 0, 600, 601, 605, 628, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 0x0a - 800x600@72Hz */
194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
195 976, 1040, 0, 600, 637, 643, 666, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 0x0b - 800x600@75Hz */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
199 896, 1056, 0, 600, 601, 604, 625, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 0x0c - 800x600@85Hz */
202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
203 896, 1048, 0, 600, 601, 604, 631, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x0d - 800x600@120Hz RB */
206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
207 880, 960, 0, 600, 603, 607, 636, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
209 /* 0x0e - 848x480@60Hz */
210 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
211 976, 1088, 0, 480, 486, 494, 517, 0,
212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
213 /* 0x0f - 1024x768@43Hz, interlace */
214 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
215 1208, 1264, 0, 768, 768, 772, 817, 0,
216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
217 DRM_MODE_FLAG_INTERLACE) },
218 /* 0x10 - 1024x768@60Hz */
219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
220 1184, 1344, 0, 768, 771, 777, 806, 0,
221 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
222 /* 0x11 - 1024x768@70Hz */
223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
224 1184, 1328, 0, 768, 771, 777, 806, 0,
225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
226 /* 0x12 - 1024x768@75Hz */
227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
228 1136, 1312, 0, 768, 769, 772, 800, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
230 /* 0x13 - 1024x768@85Hz */
231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
232 1168, 1376, 0, 768, 769, 772, 808, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
234 /* 0x14 - 1024x768@120Hz RB */
235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
236 1104, 1184, 0, 768, 771, 775, 813, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 0x15 - 1152x864@75Hz */
239 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
240 1344, 1600, 0, 864, 865, 868, 900, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
242 /* 0x55 - 1280x720@60Hz */
243 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
244 1430, 1650, 0, 720, 725, 730, 750, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x16 - 1280x768@60Hz RB */
247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
248 1360, 1440, 0, 768, 771, 778, 790, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
250 /* 0x17 - 1280x768@60Hz */
251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
252 1472, 1664, 0, 768, 771, 778, 798, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x18 - 1280x768@75Hz */
255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
256 1488, 1696, 0, 768, 771, 778, 805, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x19 - 1280x768@85Hz */
259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
260 1496, 1712, 0, 768, 771, 778, 809, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
262 /* 0x1a - 1280x768@120Hz RB */
263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
264 1360, 1440, 0, 768, 771, 778, 813, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x1b - 1280x800@60Hz RB */
267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
268 1360, 1440, 0, 800, 803, 809, 823, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x1c - 1280x800@60Hz */
271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
272 1480, 1680, 0, 800, 803, 809, 831, 0,
273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x1d - 1280x800@75Hz */
275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
276 1488, 1696, 0, 800, 803, 809, 838, 0,
277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x1e - 1280x800@85Hz */
279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
280 1496, 1712, 0, 800, 803, 809, 843, 0,
281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x1f - 1280x800@120Hz RB */
283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
284 1360, 1440, 0, 800, 803, 809, 847, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 0x20 - 1280x960@60Hz */
287 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
288 1488, 1800, 0, 960, 961, 964, 1000, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 0x21 - 1280x960@85Hz */
291 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
292 1504, 1728, 0, 960, 961, 964, 1011, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x22 - 1280x960@120Hz RB */
295 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
296 1360, 1440, 0, 960, 963, 967, 1017, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x23 - 1280x1024@60Hz */
299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
300 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x24 - 1280x1024@75Hz */
303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
304 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x25 - 1280x1024@85Hz */
307 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
308 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x26 - 1280x1024@120Hz RB */
311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
312 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x27 - 1360x768@60Hz */
315 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
316 1536, 1792, 0, 768, 771, 777, 795, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x28 - 1360x768@120Hz RB */
319 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
320 1440, 1520, 0, 768, 771, 776, 813, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
322 /* 0x51 - 1366x768@60Hz */
323 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
324 1579, 1792, 0, 768, 771, 774, 798, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x56 - 1366x768@60Hz */
327 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
328 1436, 1500, 0, 768, 769, 772, 800, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x29 - 1400x1050@60Hz RB */
331 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
332 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x2a - 1400x1050@60Hz */
335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
336 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x2b - 1400x1050@75Hz */
339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
340 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x2c - 1400x1050@85Hz */
343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
344 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x2d - 1400x1050@120Hz RB */
347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
348 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x2e - 1440x900@60Hz RB */
351 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
352 1520, 1600, 0, 900, 903, 909, 926, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x2f - 1440x900@60Hz */
355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
356 1672, 1904, 0, 900, 903, 909, 934, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x30 - 1440x900@75Hz */
359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
360 1688, 1936, 0, 900, 903, 909, 942, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x31 - 1440x900@85Hz */
363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
364 1696, 1952, 0, 900, 903, 909, 948, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x32 - 1440x900@120Hz RB */
367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
368 1520, 1600, 0, 900, 903, 909, 953, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
370 /* 0x53 - 1600x900@60Hz */
371 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
372 1704, 1800, 0, 900, 901, 904, 1000, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x33 - 1600x1200@60Hz */
375 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
376 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x34 - 1600x1200@65Hz */
379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x35 - 1600x1200@70Hz */
383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x36 - 1600x1200@75Hz */
387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x37 - 1600x1200@85Hz */
391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x38 - 1600x1200@120Hz RB */
395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
396 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x39 - 1680x1050@60Hz RB */
399 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
400 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x3a - 1680x1050@60Hz */
403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
404 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x3b - 1680x1050@75Hz */
407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
408 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x3c - 1680x1050@85Hz */
411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
412 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x3d - 1680x1050@120Hz RB */
415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
416 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x3e - 1792x1344@60Hz */
419 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
420 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x3f - 1792x1344@75Hz */
423 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
424 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x40 - 1792x1344@120Hz RB */
427 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
428 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x41 - 1856x1392@60Hz */
431 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
432 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x42 - 1856x1392@75Hz */
435 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
436 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x43 - 1856x1392@120Hz RB */
439 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
440 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
442 /* 0x52 - 1920x1080@60Hz */
443 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
444 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x44 - 1920x1200@60Hz RB */
447 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
448 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 0x45 - 1920x1200@60Hz */
451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
452 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x46 - 1920x1200@75Hz */
455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
456 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x47 - 1920x1200@85Hz */
459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
460 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x48 - 1920x1200@120Hz RB */
463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
464 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x49 - 1920x1440@60Hz */
467 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
468 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x4a - 1920x1440@75Hz */
471 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
472 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x4b - 1920x1440@120Hz RB */
475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
476 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x54 - 2048x1152@60Hz */
479 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
480 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x4c - 2560x1600@60Hz RB */
483 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
484 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x4d - 2560x1600@60Hz */
487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
488 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x4e - 2560x1600@75Hz */
491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
492 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x4f - 2560x1600@85Hz */
495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
496 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x50 - 2560x1600@120Hz RB */
499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
500 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
502 /* 0x57 - 4096x2160@60Hz RB */
503 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
504 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x58 - 4096x2160@59.94Hz RB */
507 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
508 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
513 * These more or less come from the DMT spec. The 720x400 modes are
514 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
515 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
516 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
519 * The DMT modes have been fact-checked; the rest are mild guesses.
521 static const struct drm_display_mode edid_est_modes[] = {
522 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
523 968, 1056, 0, 600, 601, 605, 628, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
525 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
526 896, 1024, 0, 600, 601, 603, 625, 0,
527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
528 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
529 720, 840, 0, 480, 481, 484, 500, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
531 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
532 704, 832, 0, 480, 489, 491, 520, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
535 768, 864, 0, 480, 483, 486, 525, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
537 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
538 752, 800, 0, 480, 490, 492, 525, 0,
539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
540 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
541 846, 900, 0, 400, 421, 423, 449, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
543 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
544 846, 900, 0, 400, 412, 414, 449, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
546 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
547 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
549 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
550 1136, 1312, 0, 768, 769, 772, 800, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
552 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
553 1184, 1328, 0, 768, 771, 777, 806, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
555 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
556 1184, 1344, 0, 768, 771, 777, 806, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
558 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
559 1208, 1264, 0, 768, 768, 776, 817, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
561 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
562 928, 1152, 0, 624, 625, 628, 667, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
564 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
565 896, 1056, 0, 600, 601, 604, 625, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
567 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
568 976, 1040, 0, 600, 637, 643, 666, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
570 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
571 1344, 1600, 0, 864, 865, 868, 900, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
582 static const struct minimode est3_modes[] = {
590 { 1024, 768, 85, 0 },
591 { 1152, 864, 75, 0 },
593 { 1280, 768, 60, 1 },
594 { 1280, 768, 60, 0 },
595 { 1280, 768, 75, 0 },
596 { 1280, 768, 85, 0 },
597 { 1280, 960, 60, 0 },
598 { 1280, 960, 85, 0 },
599 { 1280, 1024, 60, 0 },
600 { 1280, 1024, 85, 0 },
602 { 1360, 768, 60, 0 },
603 { 1440, 900, 60, 1 },
604 { 1440, 900, 60, 0 },
605 { 1440, 900, 75, 0 },
606 { 1440, 900, 85, 0 },
607 { 1400, 1050, 60, 1 },
608 { 1400, 1050, 60, 0 },
609 { 1400, 1050, 75, 0 },
611 { 1400, 1050, 85, 0 },
612 { 1680, 1050, 60, 1 },
613 { 1680, 1050, 60, 0 },
614 { 1680, 1050, 75, 0 },
615 { 1680, 1050, 85, 0 },
616 { 1600, 1200, 60, 0 },
617 { 1600, 1200, 65, 0 },
618 { 1600, 1200, 70, 0 },
620 { 1600, 1200, 75, 0 },
621 { 1600, 1200, 85, 0 },
622 { 1792, 1344, 60, 0 },
623 { 1792, 1344, 75, 0 },
624 { 1856, 1392, 60, 0 },
625 { 1856, 1392, 75, 0 },
626 { 1920, 1200, 60, 1 },
627 { 1920, 1200, 60, 0 },
629 { 1920, 1200, 75, 0 },
630 { 1920, 1200, 85, 0 },
631 { 1920, 1440, 60, 0 },
632 { 1920, 1440, 75, 0 },
635 static const struct minimode extra_modes[] = {
636 { 1024, 576, 60, 0 },
637 { 1366, 768, 60, 0 },
638 { 1600, 900, 60, 0 },
639 { 1680, 945, 60, 0 },
640 { 1920, 1080, 60, 0 },
641 { 2048, 1152, 60, 0 },
642 { 2048, 1536, 60, 0 },
646 * Probably taken from CEA-861 spec.
647 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
649 * Index using the VIC.
651 static const struct drm_display_mode edid_cea_modes[] = {
652 /* 0 - dummy, VICs start at 1 */
654 /* 1 - 640x480@60Hz */
655 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
656 752, 800, 0, 480, 490, 492, 525, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
659 /* 2 - 720x480@60Hz */
660 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
661 798, 858, 0, 480, 489, 495, 525, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
664 /* 3 - 720x480@60Hz */
665 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
666 798, 858, 0, 480, 489, 495, 525, 0,
667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
669 /* 4 - 1280x720@60Hz */
670 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
671 1430, 1650, 0, 720, 725, 730, 750, 0,
672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
674 /* 5 - 1920x1080i@60Hz */
675 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
676 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
678 DRM_MODE_FLAG_INTERLACE),
679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
680 /* 6 - 720(1440)x480i@60Hz */
681 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
682 801, 858, 0, 480, 488, 494, 525, 0,
683 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
684 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
686 /* 7 - 720(1440)x480i@60Hz */
687 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
688 801, 858, 0, 480, 488, 494, 525, 0,
689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
690 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
692 /* 8 - 720(1440)x240@60Hz */
693 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
694 801, 858, 0, 240, 244, 247, 262, 0,
695 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
696 DRM_MODE_FLAG_DBLCLK),
697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
698 /* 9 - 720(1440)x240@60Hz */
699 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
700 801, 858, 0, 240, 244, 247, 262, 0,
701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
702 DRM_MODE_FLAG_DBLCLK),
703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
704 /* 10 - 2880x480i@60Hz */
705 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
706 3204, 3432, 0, 480, 488, 494, 525, 0,
707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
708 DRM_MODE_FLAG_INTERLACE),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
710 /* 11 - 2880x480i@60Hz */
711 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
712 3204, 3432, 0, 480, 488, 494, 525, 0,
713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
714 DRM_MODE_FLAG_INTERLACE),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
716 /* 12 - 2880x240@60Hz */
717 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
718 3204, 3432, 0, 240, 244, 247, 262, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
721 /* 13 - 2880x240@60Hz */
722 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
723 3204, 3432, 0, 240, 244, 247, 262, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
726 /* 14 - 1440x480@60Hz */
727 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
728 1596, 1716, 0, 480, 489, 495, 525, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
731 /* 15 - 1440x480@60Hz */
732 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
733 1596, 1716, 0, 480, 489, 495, 525, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
736 /* 16 - 1920x1080@60Hz */
737 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
738 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 17 - 720x576@50Hz */
742 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
743 796, 864, 0, 576, 581, 586, 625, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 18 - 720x576@50Hz */
747 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
748 796, 864, 0, 576, 581, 586, 625, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 19 - 1280x720@50Hz */
752 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
753 1760, 1980, 0, 720, 725, 730, 750, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 20 - 1920x1080i@50Hz */
757 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
758 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
760 DRM_MODE_FLAG_INTERLACE),
761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 21 - 720(1440)x576i@50Hz */
763 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
764 795, 864, 0, 576, 580, 586, 625, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
768 /* 22 - 720(1440)x576i@50Hz */
769 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
770 795, 864, 0, 576, 580, 586, 625, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 23 - 720(1440)x288@50Hz */
775 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
776 795, 864, 0, 288, 290, 293, 312, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_DBLCLK),
779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
780 /* 24 - 720(1440)x288@50Hz */
781 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
782 795, 864, 0, 288, 290, 293, 312, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_DBLCLK),
785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
786 /* 25 - 2880x576i@50Hz */
787 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
788 3180, 3456, 0, 576, 580, 586, 625, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_INTERLACE),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 26 - 2880x576i@50Hz */
793 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
794 3180, 3456, 0, 576, 580, 586, 625, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_INTERLACE),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 27 - 2880x288@50Hz */
799 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
800 3180, 3456, 0, 288, 290, 293, 312, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803 /* 28 - 2880x288@50Hz */
804 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
805 3180, 3456, 0, 288, 290, 293, 312, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 29 - 1440x576@50Hz */
809 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
810 1592, 1728, 0, 576, 581, 586, 625, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
813 /* 30 - 1440x576@50Hz */
814 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
815 1592, 1728, 0, 576, 581, 586, 625, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 31 - 1920x1080@50Hz */
819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
820 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 32 - 1920x1080@24Hz */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
825 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 33 - 1920x1080@25Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
832 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 34 - 1920x1080@30Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
835 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 35 - 2880x480@60Hz */
839 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
840 3192, 3432, 0, 480, 489, 495, 525, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
843 /* 36 - 2880x480@60Hz */
844 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
845 3192, 3432, 0, 480, 489, 495, 525, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
847 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848 /* 37 - 2880x576@50Hz */
849 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
850 3184, 3456, 0, 576, 581, 586, 625, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 38 - 2880x576@50Hz */
854 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
855 3184, 3456, 0, 576, 581, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 39 - 1920x1080i@50Hz */
859 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
860 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 40 - 1920x1080i@100Hz */
865 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
866 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
868 DRM_MODE_FLAG_INTERLACE),
869 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 41 - 1280x720@100Hz */
871 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
872 1760, 1980, 0, 720, 725, 730, 750, 0,
873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 42 - 720x576@100Hz */
876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
877 796, 864, 0, 576, 581, 586, 625, 0,
878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
880 /* 43 - 720x576@100Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 44 - 720(1440)x576i@100Hz */
886 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
887 795, 864, 0, 576, 580, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
889 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
891 /* 45 - 720(1440)x576i@100Hz */
892 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
893 795, 864, 0, 576, 580, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
896 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897 /* 46 - 1920x1080i@120Hz */
898 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
901 DRM_MODE_FLAG_INTERLACE),
902 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 47 - 1280x720@120Hz */
904 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
905 1430, 1650, 0, 720, 725, 730, 750, 0,
906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 48 - 720x480@120Hz */
909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
910 798, 858, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
913 /* 49 - 720x480@120Hz */
914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
915 798, 858, 0, 480, 489, 495, 525, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 50 - 720(1440)x480i@120Hz */
919 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
920 801, 858, 0, 480, 488, 494, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
924 /* 51 - 720(1440)x480i@120Hz */
925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
926 801, 858, 0, 480, 488, 494, 525, 0,
927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
929 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 52 - 720x576@200Hz */
931 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
932 796, 864, 0, 576, 581, 586, 625, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
935 /* 53 - 720x576@200Hz */
936 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
937 796, 864, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 54 - 720(1440)x576i@200Hz */
941 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 795, 864, 0, 576, 580, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
944 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
945 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
946 /* 55 - 720(1440)x576i@200Hz */
947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
948 795, 864, 0, 576, 580, 586, 625, 0,
949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
951 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 56 - 720x480@240Hz */
953 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
954 798, 858, 0, 480, 489, 495, 525, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
956 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
957 /* 57 - 720x480@240Hz */
958 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
959 798, 858, 0, 480, 489, 495, 525, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 58 - 720(1440)x480i@240 */
963 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
964 801, 858, 0, 480, 488, 494, 525, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
967 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
968 /* 59 - 720(1440)x480i@240 */
969 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
970 801, 858, 0, 480, 488, 494, 525, 0,
971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
973 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
974 /* 60 - 1280x720@24Hz */
975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
976 3080, 3300, 0, 720, 725, 730, 750, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 61 - 1280x720@25Hz */
980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
981 3740, 3960, 0, 720, 725, 730, 750, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
983 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 62 - 1280x720@30Hz */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
986 3080, 3300, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 63 - 1920x1080@120Hz */
990 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
991 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 64 - 1920x1080@100Hz */
995 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
996 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
998 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 65 - 1280x720@24Hz */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1001 3080, 3300, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1004 /* 66 - 1280x720@25Hz */
1005 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1006 3740, 3960, 0, 720, 725, 730, 750, 0,
1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1008 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1009 /* 67 - 1280x720@30Hz */
1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1011 3080, 3300, 0, 720, 725, 730, 750, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1014 /* 68 - 1280x720@50Hz */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1016 1760, 1980, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1019 /* 69 - 1280x720@60Hz */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1021 1430, 1650, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1024 /* 70 - 1280x720@100Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1026 1760, 1980, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 71 - 1280x720@120Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1031 1430, 1650, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 72 - 1920x1080@24Hz */
1035 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1036 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 73 - 1920x1080@25Hz */
1040 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1041 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 74 - 1920x1080@30Hz */
1045 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1046 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 75 - 1920x1080@50Hz */
1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1051 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 76 - 1920x1080@60Hz */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 77 - 1920x1080@100Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 78 - 1920x1080@120Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1066 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 79 - 1680x720@24Hz */
1070 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1071 3080, 3300, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 80 - 1680x720@25Hz */
1075 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1076 2948, 3168, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 81 - 1680x720@30Hz */
1080 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1081 2420, 2640, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 82 - 1680x720@50Hz */
1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1086 1980, 2200, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 83 - 1680x720@60Hz */
1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1091 1980, 2200, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 84 - 1680x720@100Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1096 1780, 2000, 0, 720, 725, 730, 825, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 85 - 1680x720@120Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1101 1780, 2000, 0, 720, 725, 730, 825, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 86 - 2560x1080@24Hz */
1105 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1106 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 87 - 2560x1080@25Hz */
1110 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1111 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 88 - 2560x1080@30Hz */
1115 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1116 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 89 - 2560x1080@50Hz */
1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1121 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 90 - 2560x1080@60Hz */
1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1126 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 91 - 2560x1080@100Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1131 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 92 - 2560x1080@120Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1136 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 93 - 3840x2160p@24Hz 16:9 */
1140 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1141 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,},
1144 /* 94 - 3840x2160p@25Hz 16:9 */
1145 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1146 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1149 /* 95 - 3840x2160p@30Hz 16:9 */
1150 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1151 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1154 /* 96 - 3840x2160p@50Hz 16:9 */
1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1156 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1159 /* 97 - 3840x2160p@60Hz 16:9 */
1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1161 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1164 /* 98 - 4096x2160p@24Hz 256:135 */
1165 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1166 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1169 /* 99 - 4096x2160p@25Hz 256:135 */
1170 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1171 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1174 /* 100 - 4096x2160p@30Hz 256:135 */
1175 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1176 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1179 /* 101 - 4096x2160p@50Hz 256:135 */
1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1181 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1184 /* 102 - 4096x2160p@60Hz 256:135 */
1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1186 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1189 /* 103 - 3840x2160p@24Hz 64:27 */
1190 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1191 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1194 /* 104 - 3840x2160p@25Hz 64:27 */
1195 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1196 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1199 /* 105 - 3840x2160p@30Hz 64:27 */
1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1201 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1204 /* 106 - 3840x2160p@50Hz 64:27 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1206 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1209 /* 107 - 3840x2160p@60Hz 64:27 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1211 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1217 * HDMI 1.4 4k modes. Index using the VIC.
1219 static const struct drm_display_mode edid_4k_modes[] = {
1220 /* 0 - dummy, VICs start at 1 */
1222 /* 1 - 3840x2160@30Hz */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1224 3840, 4016, 4104, 4400, 0,
1225 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 /* 2 - 3840x2160@25Hz */
1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1230 3840, 4896, 4984, 5280, 0,
1231 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 /* 3 - 3840x2160@24Hz */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1236 3840, 5116, 5204, 5500, 0,
1237 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 /* 4 - 4096x2160@24Hz (SMPTE) */
1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1242 4096, 5116, 5204, 5500, 0,
1243 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 /*** DDC fetch and block validation ***/
1250 static const u8 edid_header[] = {
1251 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1255 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1256 * @raw_edid: pointer to raw base EDID block
1258 * Sanity check the header of the base EDID block.
1260 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1262 int drm_edid_header_is_valid(const u8 *raw_edid)
1266 for (i = 0; i < sizeof(edid_header); i++)
1267 if (raw_edid[i] == edid_header[i])
1272 EXPORT_SYMBOL(drm_edid_header_is_valid);
1274 static int edid_fixup __read_mostly = 6;
1275 module_param_named(edid_fixup, edid_fixup, int, 0400);
1276 MODULE_PARM_DESC(edid_fixup,
1277 "Minimum number of valid EDID header bytes (0-8, default 6)");
1279 static void drm_get_displayid(struct drm_connector *connector,
1282 static int drm_edid_block_checksum(const u8 *raw_edid)
1286 for (i = 0; i < EDID_LENGTH; i++)
1287 csum += raw_edid[i];
1292 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1294 if (memchr_inv(in_edid, 0, length))
1301 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1302 * @raw_edid: pointer to raw EDID block
1303 * @block: type of block to validate (0 for base, extension otherwise)
1304 * @print_bad_edid: if true, dump bad EDID blocks to the console
1305 * @edid_corrupt: if true, the header or checksum is invalid
1307 * Validate a base or extension EDID block and optionally dump bad blocks to
1310 * Return: True if the block is valid, false otherwise.
1312 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1316 struct edid *edid = (struct edid *)raw_edid;
1318 if (WARN_ON(!raw_edid))
1321 if (edid_fixup > 8 || edid_fixup < 0)
1325 int score = drm_edid_header_is_valid(raw_edid);
1328 *edid_corrupt = false;
1329 } else if (score >= edid_fixup) {
1330 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1331 * The corrupt flag needs to be set here otherwise, the
1332 * fix-up code here will correct the problem, the
1333 * checksum is correct and the test fails
1336 *edid_corrupt = true;
1337 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1338 memcpy(raw_edid, edid_header, sizeof(edid_header));
1341 *edid_corrupt = true;
1346 csum = drm_edid_block_checksum(raw_edid);
1348 if (print_bad_edid) {
1349 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1353 *edid_corrupt = true;
1355 /* allow CEA to slide through, switches mangle this */
1356 if (raw_edid[0] != 0x02)
1360 /* per-block-type checks */
1361 switch (raw_edid[0]) {
1363 if (edid->version != 1) {
1364 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1368 if (edid->revision > 4)
1369 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1379 if (print_bad_edid) {
1380 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1381 printk(KERN_ERR "EDID block is all zeroes\n");
1383 printk(KERN_ERR "Raw EDID:\n");
1384 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1385 raw_edid, EDID_LENGTH, false);
1390 EXPORT_SYMBOL(drm_edid_block_valid);
1393 * drm_edid_is_valid - sanity check EDID data
1396 * Sanity-check an entire EDID record (including extensions)
1398 * Return: True if the EDID data is valid, false otherwise.
1400 bool drm_edid_is_valid(struct edid *edid)
1403 u8 *raw = (u8 *)edid;
1408 for (i = 0; i <= edid->extensions; i++)
1409 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1414 EXPORT_SYMBOL(drm_edid_is_valid);
1416 #define DDC_SEGMENT_ADDR 0x30
1418 * drm_do_probe_ddc_edid() - get EDID information via I2C
1419 * @data: I2C device adapter
1420 * @buf: EDID data buffer to be filled
1421 * @block: 128 byte EDID block to start fetching from
1422 * @len: EDID data buffer length to fetch
1424 * Try to fetch EDID information by calling I2C driver functions.
1426 * Return: 0 on success or -1 on failure.
1429 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1431 struct i2c_adapter *adapter = data;
1432 unsigned char start = block * EDID_LENGTH;
1433 unsigned char segment = block >> 1;
1434 unsigned char xfers = segment ? 3 : 2;
1435 int ret, retries = 5;
1438 * The core I2C driver will automatically retry the transfer if the
1439 * adapter reports EAGAIN. However, we find that bit-banging transfers
1440 * are susceptible to errors under a heavily loaded machine and
1441 * generate spurious NAKs and timeouts. Retrying the transfer
1442 * of the individual block a few times seems to overcome this.
1445 struct i2c_msg msgs[] = {
1447 .addr = DDC_SEGMENT_ADDR,
1465 * Avoid sending the segment addr to not upset non-compliant
1468 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1470 if (ret == -ENXIO) {
1471 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1475 } while (ret != xfers && --retries);
1477 return ret == xfers ? 0 : -1;
1481 * drm_do_get_edid - get EDID data using a custom EDID block read function
1482 * @connector: connector we're probing
1483 * @get_edid_block: EDID block read function
1484 * @data: private data passed to the block read function
1486 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1487 * exposes a different interface to read EDID blocks this function can be used
1488 * to get EDID data using a custom block read function.
1490 * As in the general case the DDC bus is accessible by the kernel at the I2C
1491 * level, drivers must make all reasonable efforts to expose it as an I2C
1492 * adapter and use drm_get_edid() instead of abusing this function.
1494 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1496 struct edid *drm_do_get_edid(struct drm_connector *connector,
1497 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1501 int i, j = 0, valid_extensions = 0;
1503 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1505 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1508 /* base block fetch */
1509 for (i = 0; i < 4; i++) {
1510 if (get_edid_block(data, block, 0, EDID_LENGTH))
1512 if (drm_edid_block_valid(block, 0, print_bad_edid,
1513 &connector->edid_corrupt))
1515 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1516 connector->null_edid_counter++;
1523 /* if there's no extensions, we're done */
1524 if (block[0x7e] == 0)
1525 return (struct edid *)block;
1527 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1532 for (j = 1; j <= block[0x7e]; j++) {
1533 for (i = 0; i < 4; i++) {
1534 if (get_edid_block(data,
1535 block + (valid_extensions + 1) * EDID_LENGTH,
1538 if (drm_edid_block_valid(block + (valid_extensions + 1)
1547 if (i == 4 && print_bad_edid) {
1548 dev_warn(connector->dev->dev,
1549 "%s: Ignoring invalid EDID block %d.\n",
1550 connector->name, j);
1552 connector->bad_edid_counter++;
1556 if (valid_extensions != block[0x7e]) {
1557 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1558 block[0x7e] = valid_extensions;
1559 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1565 return (struct edid *)block;
1568 if (print_bad_edid) {
1569 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1570 connector->name, j);
1572 connector->bad_edid_counter++;
1578 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1581 * drm_probe_ddc() - probe DDC presence
1582 * @adapter: I2C adapter to probe
1584 * Return: True on success, false on failure.
1587 drm_probe_ddc(struct i2c_adapter *adapter)
1591 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1593 EXPORT_SYMBOL(drm_probe_ddc);
1596 * drm_get_edid - get EDID data, if available
1597 * @connector: connector we're probing
1598 * @adapter: I2C adapter to use for DDC
1600 * Poke the given I2C channel to grab EDID data if possible. If found,
1601 * attach it to the connector.
1603 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1605 struct edid *drm_get_edid(struct drm_connector *connector,
1606 struct i2c_adapter *adapter)
1610 if (!drm_probe_ddc(adapter))
1613 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1615 drm_get_displayid(connector, edid);
1618 EXPORT_SYMBOL(drm_get_edid);
1621 * drm_edid_duplicate - duplicate an EDID and the extensions
1622 * @edid: EDID to duplicate
1624 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1626 struct edid *drm_edid_duplicate(const struct edid *edid)
1628 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1630 EXPORT_SYMBOL(drm_edid_duplicate);
1632 /*** EDID parsing ***/
1635 * edid_vendor - match a string against EDID's obfuscated vendor field
1636 * @edid: EDID to match
1637 * @vendor: vendor string
1639 * Returns true if @vendor is in @edid, false otherwise
1641 static bool edid_vendor(struct edid *edid, char *vendor)
1643 char edid_vendor[3];
1645 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1646 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1647 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1648 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1650 return !strncmp(edid_vendor, vendor, 3);
1654 * edid_get_quirks - return quirk flags for a given EDID
1655 * @edid: EDID to process
1657 * This tells subsequent routines what fixes they need to apply.
1659 static u32 edid_get_quirks(struct edid *edid)
1661 struct edid_quirk *quirk;
1664 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1665 quirk = &edid_quirk_list[i];
1667 if (edid_vendor(edid, quirk->vendor) &&
1668 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1669 return quirk->quirks;
1675 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1676 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1679 * edid_fixup_preferred - set preferred modes based on quirk list
1680 * @connector: has mode list to fix up
1681 * @quirks: quirks list
1683 * Walk the mode list for @connector, clearing the preferred status
1684 * on existing modes and setting it anew for the right mode ala @quirks.
1686 static void edid_fixup_preferred(struct drm_connector *connector,
1689 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1690 int target_refresh = 0;
1691 int cur_vrefresh, preferred_vrefresh;
1693 if (list_empty(&connector->probed_modes))
1696 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1697 target_refresh = 60;
1698 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1699 target_refresh = 75;
1701 preferred_mode = list_first_entry(&connector->probed_modes,
1702 struct drm_display_mode, head);
1704 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1705 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1707 if (cur_mode == preferred_mode)
1710 /* Largest mode is preferred */
1711 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1712 preferred_mode = cur_mode;
1714 cur_vrefresh = cur_mode->vrefresh ?
1715 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1716 preferred_vrefresh = preferred_mode->vrefresh ?
1717 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1718 /* At a given size, try to get closest to target refresh */
1719 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1720 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1721 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1722 preferred_mode = cur_mode;
1726 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1730 mode_is_rb(const struct drm_display_mode *mode)
1732 return (mode->htotal - mode->hdisplay == 160) &&
1733 (mode->hsync_end - mode->hdisplay == 80) &&
1734 (mode->hsync_end - mode->hsync_start == 32) &&
1735 (mode->vsync_start - mode->vdisplay == 3);
1739 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1740 * @dev: Device to duplicate against
1741 * @hsize: Mode width
1742 * @vsize: Mode height
1743 * @fresh: Mode refresh rate
1744 * @rb: Mode reduced-blanking-ness
1746 * Walk the DMT mode list looking for a match for the given parameters.
1748 * Return: A newly allocated copy of the mode, or NULL if not found.
1750 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1751 int hsize, int vsize, int fresh,
1756 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1757 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1758 if (hsize != ptr->hdisplay)
1760 if (vsize != ptr->vdisplay)
1762 if (fresh != drm_mode_vrefresh(ptr))
1764 if (rb != mode_is_rb(ptr))
1767 return drm_mode_duplicate(dev, ptr);
1772 EXPORT_SYMBOL(drm_mode_find_dmt);
1774 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1777 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1781 u8 *det_base = ext + d;
1784 for (i = 0; i < n; i++)
1785 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1789 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1791 unsigned int i, n = min((int)ext[0x02], 6);
1792 u8 *det_base = ext + 5;
1795 return; /* unknown version */
1797 for (i = 0; i < n; i++)
1798 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1802 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1805 struct edid *edid = (struct edid *)raw_edid;
1810 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1811 cb(&(edid->detailed_timings[i]), closure);
1813 for (i = 1; i <= raw_edid[0x7e]; i++) {
1814 u8 *ext = raw_edid + (i * EDID_LENGTH);
1817 cea_for_each_detailed_block(ext, cb, closure);
1820 vtb_for_each_detailed_block(ext, cb, closure);
1829 is_rb(struct detailed_timing *t, void *data)
1832 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1834 *(bool *)data = true;
1837 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1839 drm_monitor_supports_rb(struct edid *edid)
1841 if (edid->revision >= 4) {
1843 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1847 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1851 find_gtf2(struct detailed_timing *t, void *data)
1854 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1858 /* Secondary GTF curve kicks in above some break frequency */
1860 drm_gtf2_hbreak(struct edid *edid)
1863 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1864 return r ? (r[12] * 2) : 0;
1868 drm_gtf2_2c(struct edid *edid)
1871 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1872 return r ? r[13] : 0;
1876 drm_gtf2_m(struct edid *edid)
1879 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1880 return r ? (r[15] << 8) + r[14] : 0;
1884 drm_gtf2_k(struct edid *edid)
1887 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1888 return r ? r[16] : 0;
1892 drm_gtf2_2j(struct edid *edid)
1895 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1896 return r ? r[17] : 0;
1900 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1901 * @edid: EDID block to scan
1903 static int standard_timing_level(struct edid *edid)
1905 if (edid->revision >= 2) {
1906 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1908 if (drm_gtf2_hbreak(edid))
1916 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1917 * monitors fill with ascii space (0x20) instead.
1920 bad_std_timing(u8 a, u8 b)
1922 return (a == 0x00 && b == 0x00) ||
1923 (a == 0x01 && b == 0x01) ||
1924 (a == 0x20 && b == 0x20);
1928 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1929 * @connector: connector of for the EDID block
1930 * @edid: EDID block to scan
1931 * @t: standard timing params
1933 * Take the standard timing params (in this case width, aspect, and refresh)
1934 * and convert them into a real mode using CVT/GTF/DMT.
1936 static struct drm_display_mode *
1937 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1938 struct std_timing *t)
1940 struct drm_device *dev = connector->dev;
1941 struct drm_display_mode *m, *mode = NULL;
1944 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1945 >> EDID_TIMING_ASPECT_SHIFT;
1946 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1947 >> EDID_TIMING_VFREQ_SHIFT;
1948 int timing_level = standard_timing_level(edid);
1950 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1953 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1954 hsize = t->hsize * 8 + 248;
1955 /* vrefresh_rate = vfreq + 60 */
1956 vrefresh_rate = vfreq + 60;
1957 /* the vdisplay is calculated based on the aspect ratio */
1958 if (aspect_ratio == 0) {
1959 if (edid->revision < 3)
1962 vsize = (hsize * 10) / 16;
1963 } else if (aspect_ratio == 1)
1964 vsize = (hsize * 3) / 4;
1965 else if (aspect_ratio == 2)
1966 vsize = (hsize * 4) / 5;
1968 vsize = (hsize * 9) / 16;
1970 /* HDTV hack, part 1 */
1971 if (vrefresh_rate == 60 &&
1972 ((hsize == 1360 && vsize == 765) ||
1973 (hsize == 1368 && vsize == 769))) {
1979 * If this connector already has a mode for this size and refresh
1980 * rate (because it came from detailed or CVT info), use that
1981 * instead. This way we don't have to guess at interlace or
1984 list_for_each_entry(m, &connector->probed_modes, head)
1985 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1986 drm_mode_vrefresh(m) == vrefresh_rate)
1989 /* HDTV hack, part 2 */
1990 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1991 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1993 mode->hdisplay = 1366;
1994 mode->hsync_start = mode->hsync_start - 1;
1995 mode->hsync_end = mode->hsync_end - 1;
1999 /* check whether it can be found in default mode table */
2000 if (drm_monitor_supports_rb(edid)) {
2001 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2006 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2010 /* okay, generate it */
2011 switch (timing_level) {
2015 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2019 * This is potentially wrong if there's ever a monitor with
2020 * more than one ranges section, each claiming a different
2021 * secondary GTF curve. Please don't do that.
2023 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2026 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2027 drm_mode_destroy(dev, mode);
2028 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2029 vrefresh_rate, 0, 0,
2037 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2045 * EDID is delightfully ambiguous about how interlaced modes are to be
2046 * encoded. Our internal representation is of frame height, but some
2047 * HDTV detailed timings are encoded as field height.
2049 * The format list here is from CEA, in frame size. Technically we
2050 * should be checking refresh rate too. Whatever.
2053 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2054 struct detailed_pixel_timing *pt)
2057 static const struct {
2059 } cea_interlaced[] = {
2069 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2072 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2073 if ((mode->hdisplay == cea_interlaced[i].w) &&
2074 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2075 mode->vdisplay *= 2;
2076 mode->vsync_start *= 2;
2077 mode->vsync_end *= 2;
2083 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2087 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2088 * @dev: DRM device (needed to create new mode)
2090 * @timing: EDID detailed timing info
2091 * @quirks: quirks to apply
2093 * An EDID detailed timing block contains enough info for us to create and
2094 * return a new struct drm_display_mode.
2096 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2098 struct detailed_timing *timing,
2101 struct drm_display_mode *mode;
2102 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2103 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2104 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2105 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2106 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2107 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2108 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2109 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2110 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2112 /* ignore tiny modes */
2113 if (hactive < 64 || vactive < 64)
2116 if (pt->misc & DRM_EDID_PT_STEREO) {
2117 DRM_DEBUG_KMS("stereo mode not supported\n");
2120 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2121 DRM_DEBUG_KMS("composite sync not supported\n");
2124 /* it is incorrect if hsync/vsync width is zero */
2125 if (!hsync_pulse_width || !vsync_pulse_width) {
2126 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2127 "Wrong Hsync/Vsync pulse width\n");
2131 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2132 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2139 mode = drm_mode_create(dev);
2143 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2144 timing->pixel_clock = cpu_to_le16(1088);
2146 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2148 mode->hdisplay = hactive;
2149 mode->hsync_start = mode->hdisplay + hsync_offset;
2150 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2151 mode->htotal = mode->hdisplay + hblank;
2153 mode->vdisplay = vactive;
2154 mode->vsync_start = mode->vdisplay + vsync_offset;
2155 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2156 mode->vtotal = mode->vdisplay + vblank;
2158 /* Some EDIDs have bogus h/vtotal values */
2159 if (mode->hsync_end > mode->htotal)
2160 mode->htotal = mode->hsync_end + 1;
2161 if (mode->vsync_end > mode->vtotal)
2162 mode->vtotal = mode->vsync_end + 1;
2164 drm_mode_do_interlace_quirk(mode, pt);
2166 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2167 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2170 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2171 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2172 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2173 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2176 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2177 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2179 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2180 mode->width_mm *= 10;
2181 mode->height_mm *= 10;
2184 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2185 mode->width_mm = edid->width_cm * 10;
2186 mode->height_mm = edid->height_cm * 10;
2189 mode->type = DRM_MODE_TYPE_DRIVER;
2190 mode->vrefresh = drm_mode_vrefresh(mode);
2191 drm_mode_set_name(mode);
2197 mode_in_hsync_range(const struct drm_display_mode *mode,
2198 struct edid *edid, u8 *t)
2200 int hsync, hmin, hmax;
2203 if (edid->revision >= 4)
2204 hmin += ((t[4] & 0x04) ? 255 : 0);
2206 if (edid->revision >= 4)
2207 hmax += ((t[4] & 0x08) ? 255 : 0);
2208 hsync = drm_mode_hsync(mode);
2210 return (hsync <= hmax && hsync >= hmin);
2214 mode_in_vsync_range(const struct drm_display_mode *mode,
2215 struct edid *edid, u8 *t)
2217 int vsync, vmin, vmax;
2220 if (edid->revision >= 4)
2221 vmin += ((t[4] & 0x01) ? 255 : 0);
2223 if (edid->revision >= 4)
2224 vmax += ((t[4] & 0x02) ? 255 : 0);
2225 vsync = drm_mode_vrefresh(mode);
2227 return (vsync <= vmax && vsync >= vmin);
2231 range_pixel_clock(struct edid *edid, u8 *t)
2234 if (t[9] == 0 || t[9] == 255)
2237 /* 1.4 with CVT support gives us real precision, yay */
2238 if (edid->revision >= 4 && t[10] == 0x04)
2239 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2241 /* 1.3 is pathetic, so fuzz up a bit */
2242 return t[9] * 10000 + 5001;
2246 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2247 struct detailed_timing *timing)
2250 u8 *t = (u8 *)timing;
2252 if (!mode_in_hsync_range(mode, edid, t))
2255 if (!mode_in_vsync_range(mode, edid, t))
2258 if ((max_clock = range_pixel_clock(edid, t)))
2259 if (mode->clock > max_clock)
2262 /* 1.4 max horizontal check */
2263 if (edid->revision >= 4 && t[10] == 0x04)
2264 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2267 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2273 static bool valid_inferred_mode(const struct drm_connector *connector,
2274 const struct drm_display_mode *mode)
2276 const struct drm_display_mode *m;
2279 list_for_each_entry(m, &connector->probed_modes, head) {
2280 if (mode->hdisplay == m->hdisplay &&
2281 mode->vdisplay == m->vdisplay &&
2282 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2283 return false; /* duplicated */
2284 if (mode->hdisplay <= m->hdisplay &&
2285 mode->vdisplay <= m->vdisplay)
2292 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2293 struct detailed_timing *timing)
2296 struct drm_display_mode *newmode;
2297 struct drm_device *dev = connector->dev;
2299 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2300 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2301 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2302 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2304 drm_mode_probed_add(connector, newmode);
2313 /* fix up 1366x768 mode from 1368x768;
2314 * GFT/CVT can't express 1366 width which isn't dividable by 8
2316 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2318 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2319 mode->hdisplay = 1366;
2320 mode->hsync_start--;
2322 drm_mode_set_name(mode);
2327 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2328 struct detailed_timing *timing)
2331 struct drm_display_mode *newmode;
2332 struct drm_device *dev = connector->dev;
2334 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2335 const struct minimode *m = &extra_modes[i];
2336 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2340 fixup_mode_1366x768(newmode);
2341 if (!mode_in_range(newmode, edid, timing) ||
2342 !valid_inferred_mode(connector, newmode)) {
2343 drm_mode_destroy(dev, newmode);
2347 drm_mode_probed_add(connector, newmode);
2355 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2356 struct detailed_timing *timing)
2359 struct drm_display_mode *newmode;
2360 struct drm_device *dev = connector->dev;
2361 bool rb = drm_monitor_supports_rb(edid);
2363 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2364 const struct minimode *m = &extra_modes[i];
2365 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2369 fixup_mode_1366x768(newmode);
2370 if (!mode_in_range(newmode, edid, timing) ||
2371 !valid_inferred_mode(connector, newmode)) {
2372 drm_mode_destroy(dev, newmode);
2376 drm_mode_probed_add(connector, newmode);
2384 do_inferred_modes(struct detailed_timing *timing, void *c)
2386 struct detailed_mode_closure *closure = c;
2387 struct detailed_non_pixel *data = &timing->data.other_data;
2388 struct detailed_data_monitor_range *range = &data->data.range;
2390 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2393 closure->modes += drm_dmt_modes_for_range(closure->connector,
2397 if (!version_greater(closure->edid, 1, 1))
2398 return; /* GTF not defined yet */
2400 switch (range->flags) {
2401 case 0x02: /* secondary gtf, XXX could do more */
2402 case 0x00: /* default gtf */
2403 closure->modes += drm_gtf_modes_for_range(closure->connector,
2407 case 0x04: /* cvt, only in 1.4+ */
2408 if (!version_greater(closure->edid, 1, 3))
2411 closure->modes += drm_cvt_modes_for_range(closure->connector,
2415 case 0x01: /* just the ranges, no formula */
2422 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2424 struct detailed_mode_closure closure = {
2425 .connector = connector,
2429 if (version_greater(edid, 1, 0))
2430 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2433 return closure.modes;
2437 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2439 int i, j, m, modes = 0;
2440 struct drm_display_mode *mode;
2441 u8 *est = ((u8 *)timing) + 5;
2443 for (i = 0; i < 6; i++) {
2444 for (j = 7; j >= 0; j--) {
2445 m = (i * 8) + (7 - j);
2446 if (m >= ARRAY_SIZE(est3_modes))
2448 if (est[i] & (1 << j)) {
2449 mode = drm_mode_find_dmt(connector->dev,
2455 drm_mode_probed_add(connector, mode);
2466 do_established_modes(struct detailed_timing *timing, void *c)
2468 struct detailed_mode_closure *closure = c;
2469 struct detailed_non_pixel *data = &timing->data.other_data;
2471 if (data->type == EDID_DETAIL_EST_TIMINGS)
2472 closure->modes += drm_est3_modes(closure->connector, timing);
2476 * add_established_modes - get est. modes from EDID and add them
2477 * @connector: connector to add mode(s) to
2478 * @edid: EDID block to scan
2480 * Each EDID block contains a bitmap of the supported "established modes" list
2481 * (defined above). Tease them out and add them to the global modes list.
2484 add_established_modes(struct drm_connector *connector, struct edid *edid)
2486 struct drm_device *dev = connector->dev;
2487 unsigned long est_bits = edid->established_timings.t1 |
2488 (edid->established_timings.t2 << 8) |
2489 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2491 struct detailed_mode_closure closure = {
2492 .connector = connector,
2496 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2497 if (est_bits & (1<<i)) {
2498 struct drm_display_mode *newmode;
2499 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2501 drm_mode_probed_add(connector, newmode);
2507 if (version_greater(edid, 1, 0))
2508 drm_for_each_detailed_block((u8 *)edid,
2509 do_established_modes, &closure);
2511 return modes + closure.modes;
2515 do_standard_modes(struct detailed_timing *timing, void *c)
2517 struct detailed_mode_closure *closure = c;
2518 struct detailed_non_pixel *data = &timing->data.other_data;
2519 struct drm_connector *connector = closure->connector;
2520 struct edid *edid = closure->edid;
2522 if (data->type == EDID_DETAIL_STD_MODES) {
2524 for (i = 0; i < 6; i++) {
2525 struct std_timing *std;
2526 struct drm_display_mode *newmode;
2528 std = &data->data.timings[i];
2529 newmode = drm_mode_std(connector, edid, std);
2531 drm_mode_probed_add(connector, newmode);
2539 * add_standard_modes - get std. modes from EDID and add them
2540 * @connector: connector to add mode(s) to
2541 * @edid: EDID block to scan
2543 * Standard modes can be calculated using the appropriate standard (DMT,
2544 * GTF or CVT. Grab them from @edid and add them to the list.
2547 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2550 struct detailed_mode_closure closure = {
2551 .connector = connector,
2555 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2556 struct drm_display_mode *newmode;
2558 newmode = drm_mode_std(connector, edid,
2559 &edid->standard_timings[i]);
2561 drm_mode_probed_add(connector, newmode);
2566 if (version_greater(edid, 1, 0))
2567 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2570 /* XXX should also look for standard codes in VTB blocks */
2572 return modes + closure.modes;
2575 static int drm_cvt_modes(struct drm_connector *connector,
2576 struct detailed_timing *timing)
2578 int i, j, modes = 0;
2579 struct drm_display_mode *newmode;
2580 struct drm_device *dev = connector->dev;
2581 struct cvt_timing *cvt;
2582 const int rates[] = { 60, 85, 75, 60, 50 };
2583 const u8 empty[3] = { 0, 0, 0 };
2585 for (i = 0; i < 4; i++) {
2586 int uninitialized_var(width), height;
2587 cvt = &(timing->data.other_data.data.cvt[i]);
2589 if (!memcmp(cvt->code, empty, 3))
2592 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2593 switch (cvt->code[1] & 0x0c) {
2595 width = height * 4 / 3;
2598 width = height * 16 / 9;
2601 width = height * 16 / 10;
2604 width = height * 15 / 9;
2608 for (j = 1; j < 5; j++) {
2609 if (cvt->code[2] & (1 << j)) {
2610 newmode = drm_cvt_mode(dev, width, height,
2614 drm_mode_probed_add(connector, newmode);
2625 do_cvt_mode(struct detailed_timing *timing, void *c)
2627 struct detailed_mode_closure *closure = c;
2628 struct detailed_non_pixel *data = &timing->data.other_data;
2630 if (data->type == EDID_DETAIL_CVT_3BYTE)
2631 closure->modes += drm_cvt_modes(closure->connector, timing);
2635 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2637 struct detailed_mode_closure closure = {
2638 .connector = connector,
2642 if (version_greater(edid, 1, 2))
2643 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2645 /* XXX should also look for CVT codes in VTB blocks */
2647 return closure.modes;
2650 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2653 do_detailed_mode(struct detailed_timing *timing, void *c)
2655 struct detailed_mode_closure *closure = c;
2656 struct drm_display_mode *newmode;
2658 if (timing->pixel_clock) {
2659 newmode = drm_mode_detailed(closure->connector->dev,
2660 closure->edid, timing,
2665 if (closure->preferred)
2666 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2669 * Detailed modes are limited to 10kHz pixel clock resolution,
2670 * so fix up anything that looks like CEA/HDMI mode, but the clock
2671 * is just slightly off.
2673 fixup_detailed_cea_mode_clock(newmode);
2675 drm_mode_probed_add(closure->connector, newmode);
2677 closure->preferred = 0;
2682 * add_detailed_modes - Add modes from detailed timings
2683 * @connector: attached connector
2684 * @edid: EDID block to scan
2685 * @quirks: quirks to apply
2688 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2691 struct detailed_mode_closure closure = {
2692 .connector = connector,
2698 if (closure.preferred && !version_greater(edid, 1, 3))
2700 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2702 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2704 return closure.modes;
2707 #define AUDIO_BLOCK 0x01
2708 #define VIDEO_BLOCK 0x02
2709 #define VENDOR_BLOCK 0x03
2710 #define SPEAKER_BLOCK 0x04
2711 #define VIDEO_CAPABILITY_BLOCK 0x07
2712 #define VIDEO_DATA_BLOCK_420 0x0E
2713 #define VIDEO_CAP_BLOCK_420 0x0F
2714 #define EDID_BASIC_AUDIO (1 << 6)
2715 #define EDID_CEA_YCRCB444 (1 << 5)
2716 #define EDID_CEA_YCRCB422 (1 << 4)
2717 #define EDID_CEA_VCDB_QS (1 << 6)
2720 * Search EDID for CEA extension block.
2722 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2724 u8 *edid_ext = NULL;
2727 /* No EDID or EDID extensions */
2728 if (edid == NULL || edid->extensions == 0)
2731 /* Find CEA extension */
2732 for (i = 0; i < edid->extensions; i++) {
2733 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2734 if (edid_ext[0] == ext_id)
2738 if (i == edid->extensions)
2744 static u8 *drm_find_cea_extension(struct edid *edid)
2746 return drm_find_edid_extension(edid, CEA_EXT);
2749 static u8 *drm_find_displayid_extension(struct edid *edid)
2751 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2755 * Calculate the alternate clock for the CEA mode
2756 * (60Hz vs. 59.94Hz etc.)
2759 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2761 unsigned int clock = cea_mode->clock;
2763 if (cea_mode->vrefresh % 6 != 0)
2767 * edid_cea_modes contains the 59.94Hz
2768 * variant for 240 and 480 line modes,
2769 * and the 60Hz variant otherwise.
2771 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2772 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2774 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2779 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2780 unsigned int clock_tolerance)
2784 if (!to_match->clock)
2787 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2788 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2789 unsigned int clock1, clock2;
2791 /* Check both 60Hz and 59.94Hz */
2792 clock1 = cea_mode->clock;
2793 clock2 = cea_mode_alternate_clock(cea_mode);
2795 if (abs(to_match->clock - clock1) > clock_tolerance &&
2796 abs(to_match->clock - clock2) > clock_tolerance)
2799 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2807 * drm_match_cea_mode - look for a CEA mode matching given mode
2808 * @to_match: display mode
2810 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2813 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2817 if (!to_match->clock)
2820 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2821 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2822 unsigned int clock1, clock2;
2824 /* Check both 60Hz and 59.94Hz */
2825 clock1 = cea_mode->clock;
2826 clock2 = cea_mode_alternate_clock(cea_mode);
2828 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2829 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2830 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2835 EXPORT_SYMBOL(drm_match_cea_mode);
2837 static bool drm_valid_cea_vic(u8 vic)
2839 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2843 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2844 * the input VIC from the CEA mode list
2845 * @video_code: ID given to each of the CEA modes
2847 * Returns picture aspect ratio
2849 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2851 return edid_cea_modes[video_code].picture_aspect_ratio;
2853 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2856 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2859 * It's almost like cea_mode_alternate_clock(), we just need to add an
2860 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2864 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2866 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2867 return hdmi_mode->clock;
2869 return cea_mode_alternate_clock(hdmi_mode);
2872 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2873 unsigned int clock_tolerance)
2877 if (!to_match->clock)
2880 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2881 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2882 unsigned int clock1, clock2;
2884 /* Make sure to also match alternate clocks */
2885 clock1 = hdmi_mode->clock;
2886 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2888 if (abs(to_match->clock - clock1) > clock_tolerance &&
2889 abs(to_match->clock - clock2) > clock_tolerance)
2892 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2900 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2901 * @to_match: display mode
2903 * An HDMI mode is one defined in the HDMI vendor specific block.
2905 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2907 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2911 if (!to_match->clock)
2914 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2915 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2916 unsigned int clock1, clock2;
2918 /* Make sure to also match alternate clocks */
2919 clock1 = hdmi_mode->clock;
2920 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2922 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2923 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2924 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2930 static bool drm_valid_hdmi_vic(u8 vic)
2932 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2936 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2938 struct drm_device *dev = connector->dev;
2939 struct drm_display_mode *mode, *tmp;
2943 /* Don't add CEA modes if the CEA extension block is missing */
2944 if (!drm_find_cea_extension(edid))
2948 * Go through all probed modes and create a new mode
2949 * with the alternate clock for certain CEA modes.
2951 list_for_each_entry(mode, &connector->probed_modes, head) {
2952 const struct drm_display_mode *cea_mode = NULL;
2953 struct drm_display_mode *newmode;
2954 u8 vic = drm_match_cea_mode(mode);
2955 unsigned int clock1, clock2;
2957 if (drm_valid_cea_vic(vic)) {
2958 cea_mode = &edid_cea_modes[vic];
2959 clock2 = cea_mode_alternate_clock(cea_mode);
2961 vic = drm_match_hdmi_mode(mode);
2962 if (drm_valid_hdmi_vic(vic)) {
2963 cea_mode = &edid_4k_modes[vic];
2964 clock2 = hdmi_mode_alternate_clock(cea_mode);
2971 clock1 = cea_mode->clock;
2973 if (clock1 == clock2)
2976 if (mode->clock != clock1 && mode->clock != clock2)
2979 newmode = drm_mode_duplicate(dev, cea_mode);
2983 /* Carry over the stereo flags */
2984 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2987 * The current mode could be either variant. Make
2988 * sure to pick the "other" clock for the new mode.
2990 if (mode->clock != clock1)
2991 newmode->clock = clock1;
2993 newmode->clock = clock2;
2995 list_add_tail(&newmode->head, &list);
2998 list_for_each_entry_safe(mode, tmp, &list, head) {
2999 list_del(&mode->head);
3000 drm_mode_probed_add(connector, mode);
3007 static struct drm_display_mode *
3008 drm_display_mode_from_vic_index(struct drm_connector *connector,
3009 const u8 *video_db, u8 video_len,
3012 struct drm_device *dev = connector->dev;
3013 struct drm_display_mode *newmode;
3016 if (video_db == NULL || video_index >= video_len)
3019 /* CEA modes are numbered 1..127 */
3020 vic = (video_db[video_index] & 127);
3021 if (!drm_valid_cea_vic(vic))
3024 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3028 newmode->vrefresh = 0;
3034 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3038 for (i = 0; i < len; i++) {
3039 struct drm_display_mode *mode;
3040 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3042 drm_mode_probed_add(connector, mode);
3050 struct stereo_mandatory_mode {
3051 int width, height, vrefresh;
3055 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3056 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3057 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3059 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3061 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3062 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3063 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3064 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3065 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3069 stereo_match_mandatory(const struct drm_display_mode *mode,
3070 const struct stereo_mandatory_mode *stereo_mode)
3072 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3074 return mode->hdisplay == stereo_mode->width &&
3075 mode->vdisplay == stereo_mode->height &&
3076 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3077 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3080 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3082 struct drm_device *dev = connector->dev;
3083 const struct drm_display_mode *mode;
3084 struct list_head stereo_modes;
3087 INIT_LIST_HEAD(&stereo_modes);
3089 list_for_each_entry(mode, &connector->probed_modes, head) {
3090 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3091 const struct stereo_mandatory_mode *mandatory;
3092 struct drm_display_mode *new_mode;
3094 if (!stereo_match_mandatory(mode,
3095 &stereo_mandatory_modes[i]))
3098 mandatory = &stereo_mandatory_modes[i];
3099 new_mode = drm_mode_duplicate(dev, mode);
3103 new_mode->flags |= mandatory->flags;
3104 list_add_tail(&new_mode->head, &stereo_modes);
3109 list_splice_tail(&stereo_modes, &connector->probed_modes);
3114 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3116 struct drm_device *dev = connector->dev;
3117 struct drm_display_mode *newmode;
3119 if (!drm_valid_hdmi_vic(vic)) {
3120 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3124 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3128 drm_mode_probed_add(connector, newmode);
3133 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3134 const u8 *video_db, u8 video_len, u8 video_index)
3136 struct drm_display_mode *newmode;
3139 if (structure & (1 << 0)) {
3140 newmode = drm_display_mode_from_vic_index(connector, video_db,
3144 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3145 drm_mode_probed_add(connector, newmode);
3149 if (structure & (1 << 6)) {
3150 newmode = drm_display_mode_from_vic_index(connector, video_db,
3154 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3155 drm_mode_probed_add(connector, newmode);
3159 if (structure & (1 << 8)) {
3160 newmode = drm_display_mode_from_vic_index(connector, video_db,
3164 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3165 drm_mode_probed_add(connector, newmode);
3173 static int add_420_mode(struct drm_connector *connector, u8 vic)
3175 struct drm_device *dev = connector->dev;
3176 struct drm_display_mode *newmode;
3178 if (!drm_valid_cea_vic(vic))
3181 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3185 newmode->flags |= DRM_MODE_FLAG_420_ONLY;
3186 drm_mode_probed_add(connector, newmode);
3191 static int add_420_vdb_modes(struct drm_connector *connector, const u8 *svds,
3196 for (i = 0; i < svds_len; i++)
3197 modes += add_420_mode(connector, svds[i]);
3202 static int add_420_vcb_modes(struct drm_connector *connector, const u8 *svds,
3203 u8 svds_len, const u8 *video_db, u8 video_len)
3205 struct drm_display_mode *newmode = NULL;
3206 int modes = 0, i, j;
3208 for (i = 0; i < svds_len; i++) {
3211 for (j = 0; j < 8; j++) {
3212 if (mask & (1 << j)) {
3213 newmode = drm_display_mode_from_vic_index(
3214 connector, video_db, video_len,
3217 newmode->flags |= DRM_MODE_FLAG_420;
3218 drm_mode_probed_add(connector, newmode);
3228 static int add_420_vcb_modes_all(struct drm_connector *connector,
3229 const u8 *video_db, u8 video_len)
3231 struct drm_display_mode *newmode = NULL;
3234 for (i = 0; i < video_len; i++) {
3235 newmode = drm_display_mode_from_vic_index(connector, video_db,
3238 newmode->flags |= DRM_MODE_FLAG_420;
3239 drm_mode_probed_add(connector, newmode);
3247 static int do_hdmi_420_modes(struct drm_connector *connector, const u8 *vdb,
3248 u8 vdb_len, const u8 *vcb, u8 vcb_len, const u8 *video_db,
3253 if (vdb && (vdb_len > 1)) /* Add 4:2:0 modes present in EDID */
3254 modes += add_420_vdb_modes(connector, &vdb[2], vdb_len - 1);
3256 if (vcb && (vcb_len > 1)) /* Parse bit mask of supported modes */
3257 modes += add_420_vcb_modes(connector, &vcb[2], vcb_len - 1,
3258 video_db, video_len);
3259 else if (vcb) /* All modes support 4:2:0 mode */
3260 modes += add_420_vcb_modes_all(connector, video_db, video_len);
3262 DRM_DEBUG("added %d 4:2:0 modes\n", modes);
3267 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3268 * @connector: connector corresponding to the HDMI sink
3269 * @db: start of the CEA vendor specific block
3270 * @len: length of the CEA block payload, ie. one can access up to db[len]
3272 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3273 * also adds the stereo 3d modes when applicable.
3276 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3277 const u8 *video_db, u8 video_len)
3279 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3280 u8 vic_len, hdmi_3d_len = 0;
3287 /* no HDMI_Video_Present */
3288 if (!(db[8] & (1 << 5)))
3291 /* Latency_Fields_Present */
3292 if (db[8] & (1 << 7))
3295 /* I_Latency_Fields_Present */
3296 if (db[8] & (1 << 6))
3299 /* the declared length is not long enough for the 2 first bytes
3300 * of additional video format capabilities */
3301 if (len < (8 + offset + 2))
3306 if (db[8 + offset] & (1 << 7)) {
3307 modes += add_hdmi_mandatory_stereo_modes(connector);
3309 /* 3D_Multi_present */
3310 multi_present = (db[8 + offset] & 0x60) >> 5;
3314 vic_len = db[8 + offset] >> 5;
3315 hdmi_3d_len = db[8 + offset] & 0x1f;
3317 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3320 vic = db[9 + offset + i];
3321 modes += add_hdmi_mode(connector, vic);
3323 offset += 1 + vic_len;
3325 if (multi_present == 1)
3327 else if (multi_present == 2)
3332 if (len < (8 + offset + hdmi_3d_len - 1))
3335 if (hdmi_3d_len < multi_len)
3338 if (multi_present == 1 || multi_present == 2) {
3339 /* 3D_Structure_ALL */
3340 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3342 /* check if 3D_MASK is present */
3343 if (multi_present == 2)
3344 mask = (db[10 + offset] << 8) | db[11 + offset];
3348 for (i = 0; i < 16; i++) {
3349 if (mask & (1 << i))
3350 modes += add_3d_struct_modes(connector,
3357 offset += multi_len;
3359 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3361 struct drm_display_mode *newmode = NULL;
3362 unsigned int newflag = 0;
3363 bool detail_present;
3365 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3367 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3370 /* 2D_VIC_order_X */
3371 vic_index = db[8 + offset + i] >> 4;
3373 /* 3D_Structure_X */
3374 switch (db[8 + offset + i] & 0x0f) {
3376 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3379 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3383 if ((db[9 + offset + i] >> 4) == 1)
3384 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3389 newmode = drm_display_mode_from_vic_index(connector,
3395 newmode->flags |= newflag;
3396 drm_mode_probed_add(connector, newmode);
3410 cea_db_payload_len(const u8 *db)
3412 return db[0] & 0x1f;
3416 cea_db_tag(const u8 *db)
3422 cea_db_extended_tag(const u8 *db)
3428 cea_revision(const u8 *cea)
3434 cea_db_offsets(const u8 *cea, int *start, int *end)
3436 /* Data block offset in CEA extension block */
3441 if (*end < 4 || *end > 127)
3446 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3450 if (cea_db_tag(db) != VENDOR_BLOCK)
3453 if (cea_db_payload_len(db) < 5)
3456 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3458 return hdmi_id == HDMI_IEEE_OUI;
3461 static bool cea_db_is_hdmi_hf_vsdb(const u8 *db)
3465 if (cea_db_tag(db) != VENDOR_BLOCK)
3468 if (cea_db_payload_len(db) < 7)
3471 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3473 return hdmi_id == HDMI_IEEE_OUI_HF;
3476 static bool cea_db_is_hdmi_vdb420(const u8 *db)
3478 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3481 if (cea_db_extended_tag(db) != VIDEO_DATA_BLOCK_420)
3487 static bool cea_db_is_hdmi_vcb420(const u8 *db)
3489 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3492 if (cea_db_extended_tag(db) != VIDEO_CAP_BLOCK_420)
3498 #define for_each_cea_db(cea, i, start, end) \
3499 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3502 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3504 const u8 *cea = drm_find_cea_extension(edid);
3505 const u8 *db, *hdmi = NULL, *video = NULL, *vdb420 = NULL,
3507 u8 dbl, hdmi_len, video_len = 0, vdb420_len = 0, vcb420_len = 0;
3510 if (cea && cea_revision(cea) >= 3) {
3513 if (cea_db_offsets(cea, &start, &end))
3516 for_each_cea_db(cea, i, start, end) {
3518 dbl = cea_db_payload_len(db);
3520 if (cea_db_tag(db) == VIDEO_BLOCK) {
3523 modes += do_cea_modes(connector, video, dbl);
3525 else if (cea_db_is_hdmi_vsdb(db)) {
3528 } else if (cea_db_is_hdmi_vdb420(db)) {
3531 } else if (cea_db_is_hdmi_vcb420(db)) {
3539 * We parse the HDMI VSDB after having added the cea modes as we will
3540 * be patching their flags when the sink supports stereo 3D.
3543 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3546 if (vdb420 || vcb420)
3547 modes += do_hdmi_420_modes(connector, vdb420, vdb420_len,
3548 vcb420, vcb420_len, video, video_len);
3553 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3555 const struct drm_display_mode *cea_mode;
3556 int clock1, clock2, clock;
3561 * allow 5kHz clock difference either way to account for
3562 * the 10kHz clock resolution limit of detailed timings.
3564 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3565 if (drm_valid_cea_vic(vic)) {
3567 cea_mode = &edid_cea_modes[vic];
3568 clock1 = cea_mode->clock;
3569 clock2 = cea_mode_alternate_clock(cea_mode);
3571 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3572 if (drm_valid_hdmi_vic(vic)) {
3574 cea_mode = &edid_4k_modes[vic];
3575 clock1 = cea_mode->clock;
3576 clock2 = hdmi_mode_alternate_clock(cea_mode);
3582 /* pick whichever is closest */
3583 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3588 if (mode->clock == clock)
3591 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3592 type, vic, mode->clock, clock);
3593 mode->clock = clock;
3597 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3599 u8 len = cea_db_payload_len(db);
3602 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3603 connector->dvi_dual = db[6] & 1;
3606 connector->max_tmds_clock = db[7] * 5;
3608 connector->latency_present[0] = db[8] >> 7;
3609 connector->latency_present[1] = (db[8] >> 6) & 1;
3612 connector->video_latency[0] = db[9];
3614 connector->audio_latency[0] = db[10];
3616 connector->video_latency[1] = db[11];
3618 connector->audio_latency[1] = db[12];
3620 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3621 "max TMDS clock %d, "
3622 "latency present %d %d, "
3623 "video latency %d %d, "
3624 "audio latency %d %d\n",
3625 connector->dvi_dual,
3626 connector->max_tmds_clock,
3627 (int) connector->latency_present[0],
3628 (int) connector->latency_present[1],
3629 connector->video_latency[0],
3630 connector->video_latency[1],
3631 connector->audio_latency[0],
3632 connector->audio_latency[1]);
3636 parse_hdmi_hf_vsdb(struct drm_connector *connector, const u8 *db)
3638 u8 len = cea_db_payload_len(db);
3644 return; /* invalid version */
3646 connector->max_tmds_char = db[5] * 5;
3647 connector->scdc_present = db[6] & (1 << 7);
3648 connector->rr_capable = db[6] & (1 << 6);
3649 connector->flags_3d = db[6] & 0x7;
3650 connector->lte_340mcsc_scramble = db[6] & (1 << 3);
3652 DRM_DEBUG_KMS("HDMI v2: max TMDS clock %d, "
3657 connector->max_tmds_char,
3658 connector->scdc_present ? "available" : "not available",
3659 connector->rr_capable ? "capable" : "not capable",
3660 connector->flags_3d,
3661 connector->lte_340mcsc_scramble ?
3662 "supported" : "not supported");
3666 monitor_name(struct detailed_timing *t, void *data)
3668 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3669 *(u8 **)data = t->data.other_data.data.str.str;
3673 * drm_edid_to_eld - build ELD from EDID
3674 * @connector: connector corresponding to the HDMI/DP sink
3675 * @edid: EDID to parse
3677 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3678 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3681 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3683 uint8_t *eld = connector->eld;
3687 int total_sad_count = 0;
3691 memset(eld, 0, sizeof(connector->eld));
3693 cea = drm_find_cea_extension(edid);
3695 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3700 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3701 /* max: 13 bytes EDID, 16 bytes ELD */
3702 for (mnl = 0; name && mnl < 13; mnl++) {
3703 if (name[mnl] == 0x0a)
3705 eld[20 + mnl] = name[mnl];
3707 eld[4] = (cea[1] << 5) | mnl;
3708 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3710 eld[0] = 2 << 3; /* ELD version: 2 */
3712 eld[16] = edid->mfg_id[0];
3713 eld[17] = edid->mfg_id[1];
3714 eld[18] = edid->prod_code[0];
3715 eld[19] = edid->prod_code[1];
3717 if (cea_revision(cea) >= 3) {
3720 if (cea_db_offsets(cea, &start, &end)) {
3725 for_each_cea_db(cea, i, start, end) {
3727 dbl = cea_db_payload_len(db);
3729 switch (cea_db_tag(db)) {
3733 /* Audio Data Block, contains SADs */
3734 sad_count = min(dbl / 3, 15 - total_sad_count);
3736 memcpy(eld + 20 + mnl + total_sad_count * 3,
3737 &db[1], sad_count * 3);
3738 total_sad_count += sad_count;
3741 /* Speaker Allocation Data Block */
3746 /* HDMI Vendor-Specific Data Block */
3747 if (cea_db_is_hdmi_vsdb(db))
3748 parse_hdmi_vsdb(connector, db);
3749 /* HDMI Forum Vendor-Specific Data Block */
3750 else if (cea_db_is_hdmi_hf_vsdb(db))
3751 parse_hdmi_hf_vsdb(connector, db);
3758 eld[5] |= total_sad_count << 4;
3760 eld[DRM_ELD_BASELINE_ELD_LEN] =
3761 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3763 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3764 drm_eld_size(eld), total_sad_count);
3766 EXPORT_SYMBOL(drm_edid_to_eld);
3769 * drm_edid_to_sad - extracts SADs from EDID
3770 * @edid: EDID to parse
3771 * @sads: pointer that will be set to the extracted SADs
3773 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3775 * Note: The returned pointer needs to be freed using kfree().
3777 * Return: The number of found SADs or negative number on error.
3779 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3782 int i, start, end, dbl;
3785 cea = drm_find_cea_extension(edid);
3787 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3791 if (cea_revision(cea) < 3) {
3792 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3796 if (cea_db_offsets(cea, &start, &end)) {
3797 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3801 for_each_cea_db(cea, i, start, end) {
3804 if (cea_db_tag(db) == AUDIO_BLOCK) {
3806 dbl = cea_db_payload_len(db);
3808 count = dbl / 3; /* SAD is 3B */
3809 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3812 for (j = 0; j < count; j++) {
3813 u8 *sad = &db[1 + j * 3];
3815 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3816 (*sads)[j].channels = sad[0] & 0x7;
3817 (*sads)[j].freq = sad[1] & 0x7F;
3818 (*sads)[j].byte2 = sad[2];
3826 EXPORT_SYMBOL(drm_edid_to_sad);
3829 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3830 * @edid: EDID to parse
3831 * @sadb: pointer to the speaker block
3833 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3835 * Note: The returned pointer needs to be freed using kfree().
3837 * Return: The number of found Speaker Allocation Blocks or negative number on
3840 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3843 int i, start, end, dbl;
3846 cea = drm_find_cea_extension(edid);
3848 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3852 if (cea_revision(cea) < 3) {
3853 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3857 if (cea_db_offsets(cea, &start, &end)) {
3858 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3862 for_each_cea_db(cea, i, start, end) {
3863 const u8 *db = &cea[i];
3865 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3866 dbl = cea_db_payload_len(db);
3868 /* Speaker Allocation Data Block */
3870 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3881 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3884 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3885 * @connector: connector associated with the HDMI/DP sink
3886 * @mode: the display mode
3888 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3889 * the sink doesn't support audio or video.
3891 int drm_av_sync_delay(struct drm_connector *connector,
3892 const struct drm_display_mode *mode)
3894 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3897 if (!connector->latency_present[0])
3899 if (!connector->latency_present[1])
3902 a = connector->audio_latency[i];
3903 v = connector->video_latency[i];
3906 * HDMI/DP sink doesn't support audio or video?
3908 if (a == 255 || v == 255)
3912 * Convert raw EDID values to millisecond.
3913 * Treat unknown latency as 0ms.
3916 a = min(2 * (a - 1), 500);
3918 v = min(2 * (v - 1), 500);
3920 return max(v - a, 0);
3922 EXPORT_SYMBOL(drm_av_sync_delay);
3925 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3926 * @encoder: the encoder just changed display mode
3928 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3929 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3931 * Return: The connector associated with the first HDMI/DP sink that has ELD
3934 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3936 struct drm_connector *connector;
3937 struct drm_device *dev = encoder->dev;
3939 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3940 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3942 drm_for_each_connector(connector, dev)
3943 if (connector->encoder == encoder && connector->eld[0])
3948 EXPORT_SYMBOL(drm_select_eld);
3951 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3952 * @edid: monitor EDID information
3954 * Parse the CEA extension according to CEA-861-B.
3956 * Return: True if the monitor is HDMI, false if not or unknown.
3958 bool drm_detect_hdmi_monitor(struct edid *edid)
3962 int start_offset, end_offset;
3964 edid_ext = drm_find_cea_extension(edid);
3968 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3972 * Because HDMI identifier is in Vendor Specific Block,
3973 * search it from all data blocks of CEA extension.
3975 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3976 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3982 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3985 * drm_detect_monitor_audio - check monitor audio capability
3986 * @edid: EDID block to scan
3988 * Monitor should have CEA extension block.
3989 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3990 * audio' only. If there is any audio extension block and supported
3991 * audio format, assume at least 'basic audio' support, even if 'basic
3992 * audio' is not defined in EDID.
3994 * Return: True if the monitor supports audio, false otherwise.
3996 bool drm_detect_monitor_audio(struct edid *edid)
4000 bool has_audio = false;
4001 int start_offset, end_offset;
4003 edid_ext = drm_find_cea_extension(edid);
4007 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4010 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4014 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4017 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4018 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4020 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4021 DRM_DEBUG_KMS("CEA audio format %d\n",
4022 (edid_ext[i + j] >> 3) & 0xf);
4029 EXPORT_SYMBOL(drm_detect_monitor_audio);
4032 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4033 * @edid: EDID block to scan
4035 * Check whether the monitor reports the RGB quantization range selection
4036 * as supported. The AVI infoframe can then be used to inform the monitor
4037 * which quantization range (full or limited) is used.
4039 * Return: True if the RGB quantization range is selectable, false otherwise.
4041 bool drm_rgb_quant_range_selectable(struct edid *edid)
4046 edid_ext = drm_find_cea_extension(edid);
4050 if (cea_db_offsets(edid_ext, &start, &end))
4053 for_each_cea_db(edid_ext, i, start, end) {
4054 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
4055 cea_db_payload_len(&edid_ext[i]) == 2) {
4056 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4057 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4063 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4066 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
4067 * hdmi deep color modes and update drm_display_info if so.
4068 * @edid: monitor EDID information
4069 * @info: Updated with maximum supported deep color bpc and color format
4070 * if deep color supported.
4071 * @connector: DRM connector, used only for debug output
4073 * Parse the CEA extension according to CEA-861-B.
4074 * Return true if HDMI deep color supported, false if not or unknown.
4076 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
4077 struct drm_display_info *info,
4078 struct drm_connector *connector)
4080 u8 *edid_ext, *hdmi;
4082 int start_offset, end_offset;
4083 unsigned int dc_bpc = 0;
4085 edid_ext = drm_find_cea_extension(edid);
4089 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4093 * Because HDMI identifier is in Vendor Specific Block,
4094 * search it from all data blocks of CEA extension.
4096 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4097 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
4098 /* HDMI supports at least 8 bpc */
4101 hdmi = &edid_ext[i];
4102 if (cea_db_payload_len(hdmi) < 6)
4105 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4107 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4108 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4112 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4114 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4115 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4119 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4121 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4122 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4127 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4128 connector->name, dc_bpc);
4132 * Deep color support mandates RGB444 support for all video
4133 * modes and forbids YCRCB422 support for all video modes per
4136 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4138 /* YCRCB444 is optional according to spec. */
4139 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4140 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4141 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4146 * Spec says that if any deep color mode is supported at all,
4147 * then deep color 36 bit must be supported.
4149 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4150 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4157 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4167 * drm_add_display_info - pull display info out if present
4169 * @info: display info (attached to connector)
4170 * @connector: connector whose edid is used to build display info
4172 * Grab any available display info and stuff it into the drm_display_info
4173 * structure that's part of the connector. Useful for tracking bpp and
4176 static void drm_add_display_info(struct edid *edid,
4177 struct drm_display_info *info,
4178 struct drm_connector *connector)
4182 info->width_mm = edid->width_cm * 10;
4183 info->height_mm = edid->height_cm * 10;
4185 /* driver figures it out in this case */
4187 info->color_formats = 0;
4189 if (edid->revision < 3)
4192 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4195 /* Get data from CEA blocks if present */
4196 edid_ext = drm_find_cea_extension(edid);
4198 info->cea_rev = edid_ext[1];
4200 /* The existence of a CEA block should imply RGB support */
4201 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4202 if (edid_ext[3] & EDID_CEA_YCRCB444)
4203 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4204 if (edid_ext[3] & EDID_CEA_YCRCB422)
4205 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4208 /* HDMI deep color modes supported? Assign to info, if so */
4209 drm_assign_hdmi_deep_color_info(edid, info, connector);
4211 /* Only defined for 1.4 with digital displays */
4212 if (edid->revision < 4)
4215 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4216 case DRM_EDID_DIGITAL_DEPTH_6:
4219 case DRM_EDID_DIGITAL_DEPTH_8:
4222 case DRM_EDID_DIGITAL_DEPTH_10:
4225 case DRM_EDID_DIGITAL_DEPTH_12:
4228 case DRM_EDID_DIGITAL_DEPTH_14:
4231 case DRM_EDID_DIGITAL_DEPTH_16:
4234 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4240 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4241 connector->name, info->bpc);
4243 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4244 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4245 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4246 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4247 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4251 * drm_add_edid_modes - add modes from EDID data, if available
4252 * @connector: connector we're probing
4255 * Add the specified modes to the connector's mode list.
4257 * Return: The number of modes added or 0 if we couldn't find any.
4259 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4267 if (!drm_edid_is_valid(edid)) {
4268 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4273 quirks = edid_get_quirks(edid);
4276 * EDID spec says modes should be preferred in this order:
4277 * - preferred detailed mode
4278 * - other detailed modes from base block
4279 * - detailed modes from extension blocks
4280 * - CVT 3-byte code modes
4281 * - standard timing codes
4282 * - established timing codes
4283 * - modes inferred from GTF or CVT range information
4285 * We get this pretty much right.
4287 * XXX order for additional mode types in extension blocks?
4289 num_modes += add_detailed_modes(connector, edid, quirks);
4290 num_modes += add_cvt_modes(connector, edid);
4291 num_modes += add_standard_modes(connector, edid);
4292 num_modes += add_established_modes(connector, edid);
4293 num_modes += add_cea_modes(connector, edid);
4294 num_modes += add_alternate_cea_modes(connector, edid);
4295 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4296 num_modes += add_inferred_modes(connector, edid);
4298 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4299 edid_fixup_preferred(connector, quirks);
4301 drm_add_display_info(edid, &connector->display_info, connector);
4303 if (quirks & EDID_QUIRK_FORCE_6BPC)
4304 connector->display_info.bpc = 6;
4306 if (quirks & EDID_QUIRK_FORCE_8BPC)
4307 connector->display_info.bpc = 8;
4309 if (quirks & EDID_QUIRK_FORCE_12BPC)
4310 connector->display_info.bpc = 12;
4314 EXPORT_SYMBOL(drm_add_edid_modes);
4317 * drm_add_modes_noedid - add modes for the connectors without EDID
4318 * @connector: connector we're probing
4319 * @hdisplay: the horizontal display limit
4320 * @vdisplay: the vertical display limit
4322 * Add the specified modes to the connector's mode list. Only when the
4323 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4325 * Return: The number of modes added or 0 if we couldn't find any.
4327 int drm_add_modes_noedid(struct drm_connector *connector,
4328 int hdisplay, int vdisplay)
4330 int i, count, num_modes = 0;
4331 struct drm_display_mode *mode;
4332 struct drm_device *dev = connector->dev;
4334 count = ARRAY_SIZE(drm_dmt_modes);
4340 for (i = 0; i < count; i++) {
4341 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4342 if (hdisplay && vdisplay) {
4344 * Only when two are valid, they will be used to check
4345 * whether the mode should be added to the mode list of
4348 if (ptr->hdisplay > hdisplay ||
4349 ptr->vdisplay > vdisplay)
4352 if (drm_mode_vrefresh(ptr) > 61)
4354 mode = drm_mode_duplicate(dev, ptr);
4356 drm_mode_probed_add(connector, mode);
4362 EXPORT_SYMBOL(drm_add_modes_noedid);
4365 * drm_set_preferred_mode - Sets the preferred mode of a connector
4366 * @connector: connector whose mode list should be processed
4367 * @hpref: horizontal resolution of preferred mode
4368 * @vpref: vertical resolution of preferred mode
4370 * Marks a mode as preferred if it matches the resolution specified by @hpref
4373 void drm_set_preferred_mode(struct drm_connector *connector,
4374 int hpref, int vpref)
4376 struct drm_display_mode *mode;
4378 list_for_each_entry(mode, &connector->probed_modes, head) {
4379 if (mode->hdisplay == hpref &&
4380 mode->vdisplay == vpref)
4381 mode->type |= DRM_MODE_TYPE_PREFERRED;
4384 EXPORT_SYMBOL(drm_set_preferred_mode);
4387 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4388 * data from a DRM display mode
4389 * @frame: HDMI AVI infoframe
4390 * @mode: DRM display mode
4391 * @is_hdmi2: Sink is HDMI 2.0 compliant
4393 * Return: 0 on success or a negative error code on failure.
4396 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4397 const struct drm_display_mode *mode,
4402 if (!frame || !mode)
4405 err = hdmi_avi_infoframe_init(frame);
4409 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4410 frame->pixel_repeat = 1;
4412 frame->video_code = drm_match_cea_mode(mode);
4415 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4416 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4417 * have to make sure we dont break HDMI 1.4 sinks.
4419 if (!is_hdmi2 && frame->video_code > 64)
4420 frame->video_code = 0;
4422 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4425 * Populate picture aspect ratio from either
4426 * user input (if specified) or from the CEA mode list.
4428 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4429 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4430 frame->picture_aspect = mode->picture_aspect_ratio;
4431 else if (frame->video_code > 0)
4432 frame->picture_aspect = drm_get_cea_aspect_ratio(
4435 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4436 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4440 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4442 static enum hdmi_3d_structure
4443 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4445 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4448 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4449 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4450 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4451 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4452 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4453 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4454 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4455 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4456 case DRM_MODE_FLAG_3D_L_DEPTH:
4457 return HDMI_3D_STRUCTURE_L_DEPTH;
4458 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4459 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4460 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4461 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4462 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4463 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4465 return HDMI_3D_STRUCTURE_INVALID;
4470 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4471 * data from a DRM display mode
4472 * @frame: HDMI vendor infoframe
4473 * @mode: DRM display mode
4475 * Note that there's is a need to send HDMI vendor infoframes only when using a
4476 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4477 * function will return -EINVAL, error that can be safely ignored.
4479 * Return: 0 on success or a negative error code on failure.
4482 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4483 const struct drm_display_mode *mode)
4489 if (!frame || !mode)
4492 vic = drm_match_hdmi_mode(mode);
4493 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4495 if (!vic && !s3d_flags)
4498 if (vic && s3d_flags)
4501 err = hdmi_vendor_infoframe_init(frame);
4508 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4512 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4514 static int drm_parse_display_id(struct drm_connector *connector,
4515 u8 *displayid, int length,
4516 bool is_edid_extension)
4518 /* if this is an EDID extension the first byte will be 0x70 */
4520 struct displayid_hdr *base;
4521 struct displayid_block *block;
4525 if (is_edid_extension)
4528 base = (struct displayid_hdr *)&displayid[idx];
4530 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4531 base->rev, base->bytes, base->prod_id, base->ext_count);
4533 if (base->bytes + 5 > length - idx)
4536 for (i = idx; i <= base->bytes + 5; i++) {
4537 csum += displayid[i];
4540 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4544 block = (struct displayid_block *)&displayid[idx + 4];
4545 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
4546 block->tag, block->rev, block->num_bytes);
4548 switch (block->tag) {
4549 case DATA_BLOCK_TILED_DISPLAY: {
4550 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4553 u8 tile_v_loc, tile_h_loc;
4554 u8 num_v_tile, num_h_tile;
4555 struct drm_tile_group *tg;
4557 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4558 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4560 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4561 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4562 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4563 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4565 connector->has_tile = true;
4566 if (tile->tile_cap & 0x80)
4567 connector->tile_is_single_monitor = true;
4569 connector->num_h_tile = num_h_tile + 1;
4570 connector->num_v_tile = num_v_tile + 1;
4571 connector->tile_h_loc = tile_h_loc;
4572 connector->tile_v_loc = tile_v_loc;
4573 connector->tile_h_size = w + 1;
4574 connector->tile_v_size = h + 1;
4576 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4577 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4578 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4579 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4580 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4582 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4584 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4589 if (connector->tile_group != tg) {
4590 /* if we haven't got a pointer,
4591 take the reference, drop ref to old tile group */
4592 if (connector->tile_group) {
4593 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4595 connector->tile_group = tg;
4597 /* if same tile group, then release the ref we just took. */
4598 drm_mode_put_tile_group(connector->dev, tg);
4602 printk("unknown displayid tag %d\n", block->tag);
4608 static void drm_get_displayid(struct drm_connector *connector,
4611 void *displayid = NULL;
4613 connector->has_tile = false;
4614 displayid = drm_find_displayid_extension(edid);
4616 /* drop reference to any tile group we had */
4620 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4623 if (!connector->has_tile)
4627 if (connector->tile_group) {
4628 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4629 connector->tile_group = NULL;
projects / firefly-linux-kernel-4.4.55.git / blob