2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * Designware High-Definition Multimedia Interface (HDMI) driver
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
13 #include <linux/module.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/hdmi.h>
19 #include <linux/of_device.h>
21 #include <drm/drm_of.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_edid.h>
25 #include <drm/drm_encoder_slave.h>
26 #include <drm/bridge/dw_hdmi.h>
30 #define HDMI_EDID_LEN 512
34 #define YCBCR422_16BITS 2
35 #define YCBCR422_8BITS 3
52 static const u16 csc_coeff_default[3][4] = {
53 { 0x2000, 0x0000, 0x0000, 0x0000 },
54 { 0x0000, 0x2000, 0x0000, 0x0000 },
55 { 0x0000, 0x0000, 0x2000, 0x0000 }
58 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
59 { 0x2000, 0x6926, 0x74fd, 0x010e },
60 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
61 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
64 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
65 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
66 { 0x2000, 0x3264, 0x0000, 0x7e6d },
67 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
70 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
71 { 0x2591, 0x1322, 0x074b, 0x0000 },
72 { 0x6535, 0x2000, 0x7acc, 0x0200 },
73 { 0x6acd, 0x7534, 0x2000, 0x0200 }
76 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
77 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
78 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
79 { 0x6756, 0x78ab, 0x2000, 0x0200 }
87 bool mdataenablepolarity;
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
94 struct hdmi_data_info {
95 unsigned int enc_in_format;
96 unsigned int enc_out_format;
97 unsigned int enc_color_depth;
98 unsigned int colorimetry;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
105 struct drm_connector connector;
106 struct drm_encoder *encoder;
107 struct drm_bridge *bridge;
109 enum dw_hdmi_devtype dev_type;
111 struct clk *isfr_clk;
112 struct clk *iahb_clk;
114 struct hdmi_data_info hdmi_data;
115 const struct dw_hdmi_plat_data *plat_data;
119 u8 edid[HDMI_EDID_LEN];
123 struct drm_display_mode previous_mode;
125 struct regmap *regmap;
126 struct i2c_adapter *ddc;
129 unsigned int sample_rate;
132 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
133 u8 (*read)(struct dw_hdmi *hdmi, int offset);
136 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
138 writel(val, hdmi->regs + (offset << 2));
141 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
143 return readl(hdmi->regs + (offset << 2));
146 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
148 writeb(val, hdmi->regs + offset);
151 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
153 return readb(hdmi->regs + offset);
156 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
158 hdmi->write(hdmi, val, offset);
161 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
163 return hdmi->read(hdmi, offset);
166 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
168 u8 val = hdmi_readb(hdmi, reg) & ~mask;
171 hdmi_writeb(hdmi, val, reg);
174 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
177 hdmi_modb(hdmi, data << shift, mask, reg);
180 static void hdmi_set_clock_regenerator_n(struct dw_hdmi *hdmi,
183 hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
184 hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
185 hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
187 /* nshift factor = 0 */
188 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
191 static void hdmi_regenerate_cts(struct dw_hdmi *hdmi, unsigned int cts)
193 /* Must be set/cleared first */
194 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
196 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
197 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
198 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
199 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
202 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
205 unsigned int n = (128 * freq) / 1000;
209 if (pixel_clk == 25170000)
210 n = (ratio == 150) ? 9152 : 4576;
211 else if (pixel_clk == 27020000)
212 n = (ratio == 150) ? 8192 : 4096;
213 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
220 if (pixel_clk == 25170000)
222 else if (pixel_clk == 74170000)
224 else if (pixel_clk == 148350000)
225 n = (ratio == 150) ? 17836 : 8918;
231 if (pixel_clk == 25170000)
232 n = (ratio == 150) ? 9152 : 6864;
233 else if (pixel_clk == 27020000)
234 n = (ratio == 150) ? 8192 : 6144;
235 else if (pixel_clk == 74170000)
237 else if (pixel_clk == 148350000)
238 n = (ratio == 150) ? 11648 : 5824;
244 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
248 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
252 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
256 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
266 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
269 unsigned int cts = 0;
271 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
276 if (pixel_clk == 297000000) {
289 cts = pixel_clk / 1000;
295 * All other TMDS clocks are not supported by
296 * DWC_hdmi_tx. The TMDS clocks divided or
297 * multiplied by 1,001 coefficients are not
335 return (cts * ratio) / 100;
338 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
339 unsigned long pixel_clk)
341 unsigned int clk_n, clk_cts;
343 clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
345 clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
349 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
350 __func__, pixel_clk);
354 dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
355 __func__, hdmi->sample_rate, hdmi->ratio,
356 pixel_clk, clk_n, clk_cts);
358 hdmi_set_clock_regenerator_n(hdmi, clk_n);
359 hdmi_regenerate_cts(hdmi, clk_cts);
362 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
364 hdmi_set_clk_regenerator(hdmi, 74250000);
367 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
369 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
373 * this submodule is responsible for the video data synchronization.
374 * for example, for RGB 4:4:4 input, the data map is defined as
375 * pin{47~40} <==> R[7:0]
376 * pin{31~24} <==> G[7:0]
377 * pin{15~8} <==> B[7:0]
379 static void hdmi_video_sample(struct dw_hdmi *hdmi)
381 int color_format = 0;
384 if (hdmi->hdmi_data.enc_in_format == RGB) {
385 if (hdmi->hdmi_data.enc_color_depth == 8)
387 else if (hdmi->hdmi_data.enc_color_depth == 10)
389 else if (hdmi->hdmi_data.enc_color_depth == 12)
391 else if (hdmi->hdmi_data.enc_color_depth == 16)
395 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
396 if (hdmi->hdmi_data.enc_color_depth == 8)
398 else if (hdmi->hdmi_data.enc_color_depth == 10)
400 else if (hdmi->hdmi_data.enc_color_depth == 12)
402 else if (hdmi->hdmi_data.enc_color_depth == 16)
406 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
407 if (hdmi->hdmi_data.enc_color_depth == 8)
409 else if (hdmi->hdmi_data.enc_color_depth == 10)
411 else if (hdmi->hdmi_data.enc_color_depth == 12)
417 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
418 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
419 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
420 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
422 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
423 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
424 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
425 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
426 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
427 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
428 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
429 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
430 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
431 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
432 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
435 static int is_color_space_conversion(struct dw_hdmi *hdmi)
437 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
440 static int is_color_space_decimation(struct dw_hdmi *hdmi)
442 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
444 if (hdmi->hdmi_data.enc_in_format == RGB ||
445 hdmi->hdmi_data.enc_in_format == YCBCR444)
450 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
452 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
454 if (hdmi->hdmi_data.enc_out_format == RGB ||
455 hdmi->hdmi_data.enc_out_format == YCBCR444)
460 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
462 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
466 if (is_color_space_conversion(hdmi)) {
467 if (hdmi->hdmi_data.enc_out_format == RGB) {
468 if (hdmi->hdmi_data.colorimetry ==
469 HDMI_COLORIMETRY_ITU_601)
470 csc_coeff = &csc_coeff_rgb_out_eitu601;
472 csc_coeff = &csc_coeff_rgb_out_eitu709;
473 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
474 if (hdmi->hdmi_data.colorimetry ==
475 HDMI_COLORIMETRY_ITU_601)
476 csc_coeff = &csc_coeff_rgb_in_eitu601;
478 csc_coeff = &csc_coeff_rgb_in_eitu709;
483 /* The CSC registers are sequential, alternating MSB then LSB */
484 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
485 u16 coeff_a = (*csc_coeff)[0][i];
486 u16 coeff_b = (*csc_coeff)[1][i];
487 u16 coeff_c = (*csc_coeff)[2][i];
489 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
490 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
491 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
492 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
493 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
494 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
497 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
501 static void hdmi_video_csc(struct dw_hdmi *hdmi)
504 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
507 /* YCC422 interpolation to 444 mode */
508 if (is_color_space_interpolation(hdmi))
509 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
510 else if (is_color_space_decimation(hdmi))
511 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
513 if (hdmi->hdmi_data.enc_color_depth == 8)
514 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
515 else if (hdmi->hdmi_data.enc_color_depth == 10)
516 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
517 else if (hdmi->hdmi_data.enc_color_depth == 12)
518 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
519 else if (hdmi->hdmi_data.enc_color_depth == 16)
520 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
524 /* Configure the CSC registers */
525 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
526 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
529 dw_hdmi_update_csc_coeffs(hdmi);
533 * HDMI video packetizer is used to packetize the data.
534 * for example, if input is YCC422 mode or repeater is used,
535 * data should be repacked this module can be bypassed.
537 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
539 unsigned int color_depth = 0;
540 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
541 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
542 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
545 if (hdmi_data->enc_out_format == RGB ||
546 hdmi_data->enc_out_format == YCBCR444) {
547 if (!hdmi_data->enc_color_depth) {
548 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
549 } else if (hdmi_data->enc_color_depth == 8) {
551 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
552 } else if (hdmi_data->enc_color_depth == 10) {
554 } else if (hdmi_data->enc_color_depth == 12) {
556 } else if (hdmi_data->enc_color_depth == 16) {
561 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
562 if (!hdmi_data->enc_color_depth ||
563 hdmi_data->enc_color_depth == 8)
564 remap_size = HDMI_VP_REMAP_YCC422_16bit;
565 else if (hdmi_data->enc_color_depth == 10)
566 remap_size = HDMI_VP_REMAP_YCC422_20bit;
567 else if (hdmi_data->enc_color_depth == 12)
568 remap_size = HDMI_VP_REMAP_YCC422_24bit;
571 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
576 /* set the packetizer registers */
577 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
578 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
579 ((hdmi_data->pix_repet_factor <<
580 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
581 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
582 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
584 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
585 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
587 /* Data from pixel repeater block */
588 if (hdmi_data->pix_repet_factor > 1) {
589 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
590 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
591 } else { /* data from packetizer block */
592 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
593 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
596 hdmi_modb(hdmi, vp_conf,
597 HDMI_VP_CONF_PR_EN_MASK |
598 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
600 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
601 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
603 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
605 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
606 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
607 HDMI_VP_CONF_PP_EN_ENABLE |
608 HDMI_VP_CONF_YCC422_EN_DISABLE;
609 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
610 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
611 HDMI_VP_CONF_PP_EN_DISABLE |
612 HDMI_VP_CONF_YCC422_EN_ENABLE;
613 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
614 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
615 HDMI_VP_CONF_PP_EN_DISABLE |
616 HDMI_VP_CONF_YCC422_EN_DISABLE;
621 hdmi_modb(hdmi, vp_conf,
622 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
623 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
625 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
626 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
627 HDMI_VP_STUFF_PP_STUFFING_MASK |
628 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
630 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
634 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
637 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
638 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
641 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
644 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
645 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
648 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
651 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
652 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
655 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
658 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
661 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
664 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
667 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
671 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
676 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
681 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
684 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
685 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
686 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
687 HDMI_PHY_I2CM_DATAO_1_ADDR);
688 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
689 HDMI_PHY_I2CM_DATAO_0_ADDR);
690 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
691 HDMI_PHY_I2CM_OPERATION_ADDR);
692 hdmi_phy_wait_i2c_done(hdmi, 1000);
695 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
698 __hdmi_phy_i2c_write(hdmi, data, addr);
702 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
704 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
705 HDMI_PHY_CONF0_PDZ_OFFSET,
706 HDMI_PHY_CONF0_PDZ_MASK);
709 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
711 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
712 HDMI_PHY_CONF0_ENTMDS_OFFSET,
713 HDMI_PHY_CONF0_ENTMDS_MASK);
716 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
718 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
719 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
720 HDMI_PHY_CONF0_SPARECTRL_MASK);
723 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
725 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
726 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
727 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
730 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
732 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
733 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
734 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
737 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
739 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
740 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
741 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
744 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
746 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
747 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
748 HDMI_PHY_CONF0_SELDIPIF_MASK);
751 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
752 unsigned char res, int cscon)
756 const struct dw_hdmi_mpll_config *mpll_config =
757 hdmi->plat_data->mpll_cfg;
758 const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
759 const struct dw_hdmi_sym_term *sym_term = hdmi->plat_data->sym_term;
765 case 0: /* color resolution 0 is 8 bit colour depth */
767 res_idx = DW_HDMI_RES_8;
770 res_idx = DW_HDMI_RES_10;
773 res_idx = DW_HDMI_RES_12;
779 /* Enable csc path */
781 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
783 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
785 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
787 /* gen2 tx power off */
788 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
791 dw_hdmi_phy_gen2_pddq(hdmi, 1);
794 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
795 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
797 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
799 hdmi_phy_test_clear(hdmi, 1);
800 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
801 HDMI_PHY_I2CM_SLAVE_ADDR);
802 hdmi_phy_test_clear(hdmi, 0);
804 /* PLL/MPLL Cfg - always match on final entry */
805 for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
806 if (hdmi->hdmi_data.video_mode.mpixelclock <=
807 mpll_config[i].mpixelclock)
810 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
811 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
813 for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
814 if (hdmi->hdmi_data.video_mode.mpixelclock <=
815 curr_ctrl[i].mpixelclock)
818 if (curr_ctrl[i].mpixelclock == (~0UL)) {
819 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
820 hdmi->hdmi_data.video_mode.mpixelclock);
825 hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
827 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
828 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
830 for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
831 if (hdmi->hdmi_data.video_mode.mpixelclock <=
832 sym_term[i].mpixelclock)
835 /* RESISTANCE TERM 133Ohm Cfg */
836 hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
837 /* PREEMP Cgf 0.00 */
838 hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
841 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
842 /* REMOVE CLK TERM */
843 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
845 dw_hdmi_phy_enable_power(hdmi, 1);
847 /* toggle TMDS enable */
848 dw_hdmi_phy_enable_tmds(hdmi, 0);
849 dw_hdmi_phy_enable_tmds(hdmi, 1);
851 /* gen2 tx power on */
852 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
853 dw_hdmi_phy_gen2_pddq(hdmi, 0);
855 if (hdmi->dev_type == RK3288_HDMI)
856 dw_hdmi_phy_enable_spare(hdmi, 1);
858 /*Wait for PHY PLL lock */
861 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
866 dev_err(hdmi->dev, "PHY PLL not locked\n");
877 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
882 /*check csc whether needed activated in HDMI mode */
883 cscon = (is_color_space_conversion(hdmi) &&
884 !hdmi->hdmi_data.video_mode.mdvi);
886 /* HDMI Phy spec says to do the phy initialization sequence twice */
887 for (i = 0; i < 2; i++) {
888 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
889 dw_hdmi_phy_sel_interface_control(hdmi, 0);
890 dw_hdmi_phy_enable_tmds(hdmi, 0);
891 dw_hdmi_phy_enable_power(hdmi, 0);
894 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
899 hdmi->phy_enabled = true;
903 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
907 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
908 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
910 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
912 /* disable rx detect */
913 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
914 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
916 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
918 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
919 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
922 static void hdmi_config_AVI(struct dw_hdmi *hdmi)
924 u8 val, pix_fmt, under_scan;
925 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
928 aspect_16_9 = false; /* FIXME */
930 /* AVI Data Byte 1 */
931 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
932 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
933 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
934 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
936 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
938 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
941 * Active format identification data is present in the AVI InfoFrame.
942 * Under scan info, no bar data
944 val = pix_fmt | under_scan |
945 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
946 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
948 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
950 /* AVI Data Byte 2 -Set the Aspect Ratio */
952 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
953 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
955 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
956 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
959 /* Set up colorimetry */
960 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
961 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
962 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
964 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
965 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
967 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
968 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
969 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
970 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
971 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
972 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
973 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
974 } else { /* Carries no data */
975 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
976 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
979 val = colorimetry | coded_ratio | act_ratio;
980 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
982 /* AVI Data Byte 3 */
983 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
984 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
985 HDMI_FC_AVICONF2_SCALING_NONE;
986 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
988 /* AVI Data Byte 4 */
989 hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
991 /* AVI Data Byte 5- set up input and output pixel repetition */
992 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
993 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
994 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
995 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
996 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
997 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
998 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1000 /* IT Content and quantization range = don't care */
1001 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1002 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1003 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1005 /* AVI Data Bytes 6-13 */
1006 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1007 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1008 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1009 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1010 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1011 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1012 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1013 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1016 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1017 const struct drm_display_mode *mode)
1020 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1021 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1023 vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1024 vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1025 vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1026 vmode->mpixelclock = mode->clock * 1000;
1028 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1030 /* Set up HDMI_FC_INVIDCONF */
1031 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1032 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1033 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1035 inv_val |= (vmode->mvsyncpolarity ?
1036 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1037 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1039 inv_val |= (vmode->mhsyncpolarity ?
1040 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1041 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1043 inv_val |= (vmode->mdataenablepolarity ?
1044 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1045 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1047 if (hdmi->vic == 39)
1048 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1050 inv_val |= (vmode->minterlaced ?
1051 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1052 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1054 inv_val |= (vmode->minterlaced ?
1055 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1056 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1058 inv_val |= (vmode->mdvi ?
1059 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1060 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1062 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1064 /* Set up horizontal active pixel width */
1065 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1066 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1068 /* Set up vertical active lines */
1069 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1070 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1072 /* Set up horizontal blanking pixel region width */
1073 hblank = mode->htotal - mode->hdisplay;
1074 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1075 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1077 /* Set up vertical blanking pixel region width */
1078 vblank = mode->vtotal - mode->vdisplay;
1079 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1081 /* Set up HSYNC active edge delay width (in pixel clks) */
1082 h_de_hs = mode->hsync_start - mode->hdisplay;
1083 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1084 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1086 /* Set up VSYNC active edge delay (in lines) */
1087 v_de_vs = mode->vsync_start - mode->vdisplay;
1088 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1090 /* Set up HSYNC active pulse width (in pixel clks) */
1091 hsync_len = mode->hsync_end - mode->hsync_start;
1092 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1093 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1095 /* Set up VSYNC active edge delay (in lines) */
1096 vsync_len = mode->vsync_end - mode->vsync_start;
1097 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1100 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1102 if (!hdmi->phy_enabled)
1105 dw_hdmi_phy_enable_tmds(hdmi, 0);
1106 dw_hdmi_phy_enable_power(hdmi, 0);
1108 hdmi->phy_enabled = false;
1111 /* HDMI Initialization Step B.4 */
1112 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1116 /* control period minimum duration */
1117 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1118 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1119 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1121 /* Set to fill TMDS data channels */
1122 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1123 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1124 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1126 /* Enable pixel clock and tmds data path */
1128 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1129 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1131 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1132 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1134 /* Enable csc path */
1135 if (is_color_space_conversion(hdmi)) {
1136 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1137 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1141 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1143 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1146 /* Workaround to clear the overflow condition */
1147 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1152 /* TMDS software reset */
1153 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1155 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1156 if (hdmi->dev_type == IMX6DL_HDMI) {
1157 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1161 for (count = 0; count < 4; count++)
1162 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1165 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1167 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1168 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1171 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1173 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1174 HDMI_IH_MUTE_FC_STAT2);
1177 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1181 hdmi_disable_overflow_interrupts(hdmi);
1183 hdmi->vic = drm_match_cea_mode(mode);
1186 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1187 hdmi->hdmi_data.video_mode.mdvi = true;
1189 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1190 hdmi->hdmi_data.video_mode.mdvi = false;
1193 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1194 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1195 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1196 (hdmi->vic == 17) || (hdmi->vic == 18))
1197 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1199 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1201 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1202 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1203 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1204 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1205 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1206 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1207 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1208 (hdmi->vic == 37) || (hdmi->vic == 38))
1209 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1211 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1213 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1215 /* TODO: Get input format from IPU (via FB driver interface) */
1216 hdmi->hdmi_data.enc_in_format = RGB;
1218 hdmi->hdmi_data.enc_out_format = RGB;
1220 hdmi->hdmi_data.enc_color_depth = 8;
1221 hdmi->hdmi_data.pix_repet_factor = 0;
1222 hdmi->hdmi_data.hdcp_enable = 0;
1223 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1225 /* HDMI Initialization Step B.1 */
1226 hdmi_av_composer(hdmi, mode);
1228 /* HDMI Initializateion Step B.2 */
1229 ret = dw_hdmi_phy_init(hdmi);
1233 /* HDMI Initialization Step B.3 */
1234 dw_hdmi_enable_video_path(hdmi);
1236 /* not for DVI mode */
1237 if (hdmi->hdmi_data.video_mode.mdvi) {
1238 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1240 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1242 /* HDMI Initialization Step E - Configure audio */
1243 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1244 hdmi_enable_audio_clk(hdmi);
1246 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1247 hdmi_config_AVI(hdmi);
1250 hdmi_video_packetize(hdmi);
1251 hdmi_video_csc(hdmi);
1252 hdmi_video_sample(hdmi);
1253 hdmi_tx_hdcp_config(hdmi);
1255 dw_hdmi_clear_overflow(hdmi);
1256 if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1257 hdmi_enable_overflow_interrupts(hdmi);
1262 /* Wait until we are registered to enable interrupts */
1263 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1265 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1266 HDMI_PHY_I2CM_INT_ADDR);
1268 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1269 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1270 HDMI_PHY_I2CM_CTLINT_ADDR);
1272 /* enable cable hot plug irq */
1273 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1275 /* Clear Hotplug interrupts */
1276 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1281 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1286 * Boot up defaults are:
1287 * HDMI_IH_MUTE = 0x03 (disabled)
1288 * HDMI_IH_MUTE_* = 0x00 (enabled)
1290 * Disable top level interrupt bits in HDMI block
1292 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1293 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1294 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1296 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1298 /* by default mask all interrupts */
1299 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1300 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1301 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1302 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1303 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1304 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1305 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1306 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1307 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1308 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1309 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1310 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1311 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1312 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1313 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1315 /* Disable interrupts in the IH_MUTE_* registers */
1316 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1317 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1318 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1319 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1320 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1321 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1322 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1323 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1324 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1325 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1327 /* Enable top level interrupt bits in HDMI block */
1328 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1329 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1330 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1333 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1335 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1338 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1340 dw_hdmi_phy_disable(hdmi);
1343 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1344 struct drm_display_mode *orig_mode,
1345 struct drm_display_mode *mode)
1347 struct dw_hdmi *hdmi = bridge->driver_private;
1349 dw_hdmi_setup(hdmi, mode);
1351 /* Store the display mode for plugin/DKMS poweron events */
1352 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1355 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1356 const struct drm_display_mode *mode,
1357 struct drm_display_mode *adjusted_mode)
1362 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1364 struct dw_hdmi *hdmi = bridge->driver_private;
1366 dw_hdmi_poweroff(hdmi);
1369 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1371 struct dw_hdmi *hdmi = bridge->driver_private;
1373 dw_hdmi_poweron(hdmi);
1376 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1381 static enum drm_connector_status
1382 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1384 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1387 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1388 connector_status_connected : connector_status_disconnected;
1391 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1393 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1401 edid = drm_get_edid(connector, hdmi->ddc);
1403 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1404 edid->width_cm, edid->height_cm);
1406 drm_mode_connector_update_edid_property(connector, edid);
1407 ret = drm_add_edid_modes(connector, edid);
1410 dev_dbg(hdmi->dev, "failed to get edid\n");
1416 static enum drm_mode_status
1417 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1418 struct drm_display_mode *mode)
1420 struct dw_hdmi *hdmi = container_of(connector,
1421 struct dw_hdmi, connector);
1422 enum drm_mode_status mode_status = MODE_OK;
1424 if (hdmi->plat_data->mode_valid)
1425 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1430 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1433 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1436 return hdmi->encoder;
1439 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1441 drm_connector_unregister(connector);
1442 drm_connector_cleanup(connector);
1445 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1446 .dpms = drm_helper_connector_dpms,
1447 .fill_modes = drm_helper_probe_single_connector_modes,
1448 .detect = dw_hdmi_connector_detect,
1449 .destroy = dw_hdmi_connector_destroy,
1452 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1453 .get_modes = dw_hdmi_connector_get_modes,
1454 .mode_valid = dw_hdmi_connector_mode_valid,
1455 .best_encoder = dw_hdmi_connector_best_encoder,
1458 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1459 .enable = dw_hdmi_bridge_enable,
1460 .disable = dw_hdmi_bridge_disable,
1461 .pre_enable = dw_hdmi_bridge_nop,
1462 .post_disable = dw_hdmi_bridge_nop,
1463 .mode_set = dw_hdmi_bridge_mode_set,
1464 .mode_fixup = dw_hdmi_bridge_mode_fixup,
1467 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1469 struct dw_hdmi *hdmi = dev_id;
1472 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1474 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1476 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1479 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1481 struct dw_hdmi *hdmi = dev_id;
1485 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1487 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1489 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1490 if (phy_int_pol & HDMI_PHY_HPD) {
1491 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1493 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1495 dw_hdmi_poweron(hdmi);
1497 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1499 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1502 dw_hdmi_poweroff(hdmi);
1504 drm_helper_hpd_irq_event(hdmi->connector.dev);
1507 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1508 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1513 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1515 struct drm_encoder *encoder = hdmi->encoder;
1516 struct drm_bridge *bridge;
1519 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1521 DRM_ERROR("Failed to allocate drm bridge\n");
1525 hdmi->bridge = bridge;
1526 bridge->driver_private = hdmi;
1527 bridge->funcs = &dw_hdmi_bridge_funcs;
1528 ret = drm_bridge_attach(drm, bridge);
1530 DRM_ERROR("Failed to initialize bridge with drm\n");
1534 encoder->bridge = bridge;
1535 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1537 drm_connector_helper_add(&hdmi->connector,
1538 &dw_hdmi_connector_helper_funcs);
1539 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1540 DRM_MODE_CONNECTOR_HDMIA);
1542 hdmi->connector.encoder = encoder;
1544 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1549 int dw_hdmi_bind(struct device *dev, struct device *master,
1550 void *data, struct drm_encoder *encoder,
1551 struct resource *iores, int irq,
1552 const struct dw_hdmi_plat_data *plat_data)
1554 struct drm_device *drm = data;
1555 struct device_node *np = dev->of_node;
1556 struct device_node *ddc_node;
1557 struct dw_hdmi *hdmi;
1561 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1565 hdmi->plat_data = plat_data;
1567 hdmi->dev_type = plat_data->dev_type;
1568 hdmi->sample_rate = 48000;
1570 hdmi->encoder = encoder;
1572 of_property_read_u32(np, "reg-io-width", &val);
1576 hdmi->write = dw_hdmi_writel;
1577 hdmi->read = dw_hdmi_readl;
1580 hdmi->write = dw_hdmi_writeb;
1581 hdmi->read = dw_hdmi_readb;
1584 dev_err(dev, "reg-io-width must be 1 or 4\n");
1588 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1590 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1591 of_node_put(ddc_node);
1593 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1594 return -EPROBE_DEFER;
1598 dev_dbg(hdmi->dev, "no ddc property found\n");
1601 hdmi->regs = devm_ioremap_resource(dev, iores);
1602 if (IS_ERR(hdmi->regs))
1603 return PTR_ERR(hdmi->regs);
1605 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1606 if (IS_ERR(hdmi->isfr_clk)) {
1607 ret = PTR_ERR(hdmi->isfr_clk);
1608 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1612 ret = clk_prepare_enable(hdmi->isfr_clk);
1614 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1618 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1619 if (IS_ERR(hdmi->iahb_clk)) {
1620 ret = PTR_ERR(hdmi->iahb_clk);
1621 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1625 ret = clk_prepare_enable(hdmi->iahb_clk);
1627 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1631 /* Product and revision IDs */
1633 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1634 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1635 hdmi_readb(hdmi, HDMI_REVISION_ID),
1636 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1637 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1639 initialize_hdmi_ih_mutes(hdmi);
1641 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1642 dw_hdmi_irq, IRQF_SHARED,
1643 dev_name(dev), hdmi);
1648 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1649 * N and cts values before enabling phy
1651 hdmi_init_clk_regenerator(hdmi);
1654 * Configure registers related to HDMI interrupt
1655 * generation before registering IRQ.
1657 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1659 /* Clear Hotplug interrupts */
1660 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1662 ret = dw_hdmi_fb_registered(hdmi);
1666 ret = dw_hdmi_register(drm, hdmi);
1670 /* Unmute interrupts */
1671 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1673 dev_set_drvdata(dev, hdmi);
1678 clk_disable_unprepare(hdmi->iahb_clk);
1680 clk_disable_unprepare(hdmi->isfr_clk);
1684 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1686 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1688 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1690 /* Disable all interrupts */
1691 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1693 hdmi->connector.funcs->destroy(&hdmi->connector);
1694 hdmi->encoder->funcs->destroy(hdmi->encoder);
1696 clk_disable_unprepare(hdmi->iahb_clk);
1697 clk_disable_unprepare(hdmi->isfr_clk);
1698 i2c_put_adapter(hdmi->ddc);
1700 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1702 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1703 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1704 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1705 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1706 MODULE_LICENSE("GPL");
1707 MODULE_ALIAS("platform:dw-hdmi");