2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
13 /* Identification Registers */
14 #define HDMI_DESIGN_ID 0x0000
15 #define HDMI_REVISION_ID 0x0001
16 #define HDMI_PRODUCT_ID0 0x0002
17 #define HDMI_PRODUCT_ID1 0x0003
18 #define HDMI_CONFIG0_ID 0x0004
19 #define HDMI_CONFIG1_ID 0x0005
20 #define HDMI_CONFIG2_ID 0x0006
21 #define HDMI_CONFIG3_ID 0x0007
23 /* Interrupt Registers */
24 #define HDMI_IH_FC_STAT0 0x0100
25 #define HDMI_IH_FC_STAT1 0x0101
26 #define HDMI_IH_FC_STAT2 0x0102
27 #define HDMI_IH_AS_STAT0 0x0103
28 #define HDMI_IH_PHY_STAT0 0x0104
29 #define HDMI_IH_I2CM_STAT0 0x0105
30 #define HDMI_IH_CEC_STAT0 0x0106
31 #define HDMI_IH_VP_STAT0 0x0107
32 #define HDMI_IH_I2CMPHY_STAT0 0x0108
33 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
35 #define HDMI_IH_MUTE_FC_STAT0 0x0180
36 #define HDMI_IH_MUTE_FC_STAT1 0x0181
37 #define HDMI_IH_MUTE_FC_STAT2 0x0182
38 #define HDMI_IH_MUTE_AS_STAT0 0x0183
39 #define HDMI_IH_MUTE_PHY_STAT0 0x0184
40 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
41 #define HDMI_IH_MUTE_CEC_STAT0 0x0186
42 #define HDMI_IH_MUTE_VP_STAT0 0x0187
43 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
44 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
45 #define HDMI_IH_MUTE 0x01FF
47 /* Video Sample Registers */
48 #define HDMI_TX_INVID0 0x0200
49 #define HDMI_TX_INSTUFFING 0x0201
50 #define HDMI_TX_GYDATA0 0x0202
51 #define HDMI_TX_GYDATA1 0x0203
52 #define HDMI_TX_RCRDATA0 0x0204
53 #define HDMI_TX_RCRDATA1 0x0205
54 #define HDMI_TX_BCBDATA0 0x0206
55 #define HDMI_TX_BCBDATA1 0x0207
57 /* Video Packetizer Registers */
58 #define HDMI_VP_STATUS 0x0800
59 #define HDMI_VP_PR_CD 0x0801
60 #define HDMI_VP_STUFF 0x0802
61 #define HDMI_VP_REMAP 0x0803
62 #define HDMI_VP_CONF 0x0804
63 #define HDMI_VP_STAT 0x0805
64 #define HDMI_VP_INT 0x0806
65 #define HDMI_VP_MASK 0x0807
66 #define HDMI_VP_POL 0x0808
68 /* Frame Composer Registers */
69 #define HDMI_FC_INVIDCONF 0x1000
70 #define HDMI_FC_INHACTV0 0x1001
71 #define HDMI_FC_INHACTV1 0x1002
72 #define HDMI_FC_INHBLANK0 0x1003
73 #define HDMI_FC_INHBLANK1 0x1004
74 #define HDMI_FC_INVACTV0 0x1005
75 #define HDMI_FC_INVACTV1 0x1006
76 #define HDMI_FC_INVBLANK 0x1007
77 #define HDMI_FC_HSYNCINDELAY0 0x1008
78 #define HDMI_FC_HSYNCINDELAY1 0x1009
79 #define HDMI_FC_HSYNCINWIDTH0 0x100A
80 #define HDMI_FC_HSYNCINWIDTH1 0x100B
81 #define HDMI_FC_VSYNCINDELAY 0x100C
82 #define HDMI_FC_VSYNCINWIDTH 0x100D
83 #define HDMI_FC_INFREQ0 0x100E
84 #define HDMI_FC_INFREQ1 0x100F
85 #define HDMI_FC_INFREQ2 0x1010
86 #define HDMI_FC_CTRLDUR 0x1011
87 #define HDMI_FC_EXCTRLDUR 0x1012
88 #define HDMI_FC_EXCTRLSPAC 0x1013
89 #define HDMI_FC_CH0PREAM 0x1014
90 #define HDMI_FC_CH1PREAM 0x1015
91 #define HDMI_FC_CH2PREAM 0x1016
92 #define HDMI_FC_AVICONF3 0x1017
93 #define HDMI_FC_GCP 0x1018
94 #define HDMI_FC_AVICONF0 0x1019
95 #define HDMI_FC_AVICONF1 0x101A
96 #define HDMI_FC_AVICONF2 0x101B
97 #define HDMI_FC_AVIVID 0x101C
98 #define HDMI_FC_AVIETB0 0x101D
99 #define HDMI_FC_AVIETB1 0x101E
100 #define HDMI_FC_AVISBB0 0x101F
101 #define HDMI_FC_AVISBB1 0x1020
102 #define HDMI_FC_AVIELB0 0x1021
103 #define HDMI_FC_AVIELB1 0x1022
104 #define HDMI_FC_AVISRB0 0x1023
105 #define HDMI_FC_AVISRB1 0x1024
106 #define HDMI_FC_AUDICONF0 0x1025
107 #define HDMI_FC_AUDICONF1 0x1026
108 #define HDMI_FC_AUDICONF2 0x1027
109 #define HDMI_FC_AUDICONF3 0x1028
110 #define HDMI_FC_VSDIEEEID0 0x1029
111 #define HDMI_FC_VSDSIZE 0x102A
112 #define HDMI_FC_VSDIEEEID1 0x1030
113 #define HDMI_FC_VSDIEEEID2 0x1031
114 #define HDMI_FC_VSDPAYLOAD0 0x1032
115 #define HDMI_FC_VSDPAYLOAD1 0x1033
116 #define HDMI_FC_VSDPAYLOAD2 0x1034
117 #define HDMI_FC_VSDPAYLOAD3 0x1035
118 #define HDMI_FC_VSDPAYLOAD4 0x1036
119 #define HDMI_FC_VSDPAYLOAD5 0x1037
120 #define HDMI_FC_VSDPAYLOAD6 0x1038
121 #define HDMI_FC_VSDPAYLOAD7 0x1039
122 #define HDMI_FC_VSDPAYLOAD8 0x103A
123 #define HDMI_FC_VSDPAYLOAD9 0x103B
124 #define HDMI_FC_VSDPAYLOAD10 0x103C
125 #define HDMI_FC_VSDPAYLOAD11 0x103D
126 #define HDMI_FC_VSDPAYLOAD12 0x103E
127 #define HDMI_FC_VSDPAYLOAD13 0x103F
128 #define HDMI_FC_VSDPAYLOAD14 0x1040
129 #define HDMI_FC_VSDPAYLOAD15 0x1041
130 #define HDMI_FC_VSDPAYLOAD16 0x1042
131 #define HDMI_FC_VSDPAYLOAD17 0x1043
132 #define HDMI_FC_VSDPAYLOAD18 0x1044
133 #define HDMI_FC_VSDPAYLOAD19 0x1045
134 #define HDMI_FC_VSDPAYLOAD20 0x1046
135 #define HDMI_FC_VSDPAYLOAD21 0x1047
136 #define HDMI_FC_VSDPAYLOAD22 0x1048
137 #define HDMI_FC_VSDPAYLOAD23 0x1049
138 #define HDMI_FC_SPDVENDORNAME0 0x104A
139 #define HDMI_FC_SPDVENDORNAME1 0x104B
140 #define HDMI_FC_SPDVENDORNAME2 0x104C
141 #define HDMI_FC_SPDVENDORNAME3 0x104D
142 #define HDMI_FC_SPDVENDORNAME4 0x104E
143 #define HDMI_FC_SPDVENDORNAME5 0x104F
144 #define HDMI_FC_SPDVENDORNAME6 0x1050
145 #define HDMI_FC_SPDVENDORNAME7 0x1051
146 #define HDMI_FC_SDPPRODUCTNAME0 0x1052
147 #define HDMI_FC_SDPPRODUCTNAME1 0x1053
148 #define HDMI_FC_SDPPRODUCTNAME2 0x1054
149 #define HDMI_FC_SDPPRODUCTNAME3 0x1055
150 #define HDMI_FC_SDPPRODUCTNAME4 0x1056
151 #define HDMI_FC_SDPPRODUCTNAME5 0x1057
152 #define HDMI_FC_SDPPRODUCTNAME6 0x1058
153 #define HDMI_FC_SDPPRODUCTNAME7 0x1059
154 #define HDMI_FC_SDPPRODUCTNAME8 0x105A
155 #define HDMI_FC_SDPPRODUCTNAME9 0x105B
156 #define HDMI_FC_SDPPRODUCTNAME10 0x105C
157 #define HDMI_FC_SDPPRODUCTNAME11 0x105D
158 #define HDMI_FC_SDPPRODUCTNAME12 0x105E
159 #define HDMI_FC_SDPPRODUCTNAME13 0x105F
160 #define HDMI_FC_SDPPRODUCTNAME14 0x1060
161 #define HDMI_FC_SPDPRODUCTNAME15 0x1061
162 #define HDMI_FC_SPDDEVICEINF 0x1062
163 #define HDMI_FC_AUDSCONF 0x1063
164 #define HDMI_FC_AUDSSTAT 0x1064
165 #define HDMI_FC_DATACH0FILL 0x1070
166 #define HDMI_FC_DATACH1FILL 0x1071
167 #define HDMI_FC_DATACH2FILL 0x1072
168 #define HDMI_FC_CTRLQHIGH 0x1073
169 #define HDMI_FC_CTRLQLOW 0x1074
170 #define HDMI_FC_ACP0 0x1075
171 #define HDMI_FC_ACP28 0x1076
172 #define HDMI_FC_ACP27 0x1077
173 #define HDMI_FC_ACP26 0x1078
174 #define HDMI_FC_ACP25 0x1079
175 #define HDMI_FC_ACP24 0x107A
176 #define HDMI_FC_ACP23 0x107B
177 #define HDMI_FC_ACP22 0x107C
178 #define HDMI_FC_ACP21 0x107D
179 #define HDMI_FC_ACP20 0x107E
180 #define HDMI_FC_ACP19 0x107F
181 #define HDMI_FC_ACP18 0x1080
182 #define HDMI_FC_ACP17 0x1081
183 #define HDMI_FC_ACP16 0x1082
184 #define HDMI_FC_ACP15 0x1083
185 #define HDMI_FC_ACP14 0x1084
186 #define HDMI_FC_ACP13 0x1085
187 #define HDMI_FC_ACP12 0x1086
188 #define HDMI_FC_ACP11 0x1087
189 #define HDMI_FC_ACP10 0x1088
190 #define HDMI_FC_ACP9 0x1089
191 #define HDMI_FC_ACP8 0x108A
192 #define HDMI_FC_ACP7 0x108B
193 #define HDMI_FC_ACP6 0x108C
194 #define HDMI_FC_ACP5 0x108D
195 #define HDMI_FC_ACP4 0x108E
196 #define HDMI_FC_ACP3 0x108F
197 #define HDMI_FC_ACP2 0x1090
198 #define HDMI_FC_ACP1 0x1091
199 #define HDMI_FC_ISCR1_0 0x1092
200 #define HDMI_FC_ISCR1_16 0x1093
201 #define HDMI_FC_ISCR1_15 0x1094
202 #define HDMI_FC_ISCR1_14 0x1095
203 #define HDMI_FC_ISCR1_13 0x1096
204 #define HDMI_FC_ISCR1_12 0x1097
205 #define HDMI_FC_ISCR1_11 0x1098
206 #define HDMI_FC_ISCR1_10 0x1099
207 #define HDMI_FC_ISCR1_9 0x109A
208 #define HDMI_FC_ISCR1_8 0x109B
209 #define HDMI_FC_ISCR1_7 0x109C
210 #define HDMI_FC_ISCR1_6 0x109D
211 #define HDMI_FC_ISCR1_5 0x109E
212 #define HDMI_FC_ISCR1_4 0x109F
213 #define HDMI_FC_ISCR1_3 0x10A0
214 #define HDMI_FC_ISCR1_2 0x10A1
215 #define HDMI_FC_ISCR1_1 0x10A2
216 #define HDMI_FC_ISCR2_15 0x10A3
217 #define HDMI_FC_ISCR2_14 0x10A4
218 #define HDMI_FC_ISCR2_13 0x10A5
219 #define HDMI_FC_ISCR2_12 0x10A6
220 #define HDMI_FC_ISCR2_11 0x10A7
221 #define HDMI_FC_ISCR2_10 0x10A8
222 #define HDMI_FC_ISCR2_9 0x10A9
223 #define HDMI_FC_ISCR2_8 0x10AA
224 #define HDMI_FC_ISCR2_7 0x10AB
225 #define HDMI_FC_ISCR2_6 0x10AC
226 #define HDMI_FC_ISCR2_5 0x10AD
227 #define HDMI_FC_ISCR2_4 0x10AE
228 #define HDMI_FC_ISCR2_3 0x10AF
229 #define HDMI_FC_ISCR2_2 0x10B0
230 #define HDMI_FC_ISCR2_1 0x10B1
231 #define HDMI_FC_ISCR2_0 0x10B2
232 #define HDMI_FC_DATAUTO0 0x10B3
233 #define HDMI_FC_DATAUTO1 0x10B4
234 #define HDMI_FC_DATAUTO2 0x10B5
235 #define HDMI_FC_DATMAN 0x10B6
236 #define HDMI_FC_DATAUTO3 0x10B7
237 #define HDMI_FC_RDRB0 0x10B8
238 #define HDMI_FC_RDRB1 0x10B9
239 #define HDMI_FC_RDRB2 0x10BA
240 #define HDMI_FC_RDRB3 0x10BB
241 #define HDMI_FC_RDRB4 0x10BC
242 #define HDMI_FC_RDRB5 0x10BD
243 #define HDMI_FC_RDRB6 0x10BE
244 #define HDMI_FC_RDRB7 0x10BF
245 #define HDMI_FC_STAT0 0x10D0
246 #define HDMI_FC_INT0 0x10D1
247 #define HDMI_FC_MASK0 0x10D2
248 #define HDMI_FC_POL0 0x10D3
249 #define HDMI_FC_STAT1 0x10D4
250 #define HDMI_FC_INT1 0x10D5
251 #define HDMI_FC_MASK1 0x10D6
252 #define HDMI_FC_POL1 0x10D7
253 #define HDMI_FC_STAT2 0x10D8
254 #define HDMI_FC_INT2 0x10D9
255 #define HDMI_FC_MASK2 0x10DA
256 #define HDMI_FC_POL2 0x10DB
257 #define HDMI_FC_PRCONF 0x10E0
258 #define HDMI_FC_SCRAMBLER_CTRL 0x10E1
260 #define HDMI_FC_GMD_STAT 0x1100
261 #define HDMI_FC_GMD_EN 0x1101
262 #define HDMI_FC_GMD_UP 0x1102
263 #define HDMI_FC_GMD_CONF 0x1103
264 #define HDMI_FC_GMD_HB 0x1104
265 #define HDMI_FC_GMD_PB0 0x1105
266 #define HDMI_FC_GMD_PB1 0x1106
267 #define HDMI_FC_GMD_PB2 0x1107
268 #define HDMI_FC_GMD_PB3 0x1108
269 #define HDMI_FC_GMD_PB4 0x1109
270 #define HDMI_FC_GMD_PB5 0x110A
271 #define HDMI_FC_GMD_PB6 0x110B
272 #define HDMI_FC_GMD_PB7 0x110C
273 #define HDMI_FC_GMD_PB8 0x110D
274 #define HDMI_FC_GMD_PB9 0x110E
275 #define HDMI_FC_GMD_PB10 0x110F
276 #define HDMI_FC_GMD_PB11 0x1110
277 #define HDMI_FC_GMD_PB12 0x1111
278 #define HDMI_FC_GMD_PB13 0x1112
279 #define HDMI_FC_GMD_PB14 0x1113
280 #define HDMI_FC_GMD_PB15 0x1114
281 #define HDMI_FC_GMD_PB16 0x1115
282 #define HDMI_FC_GMD_PB17 0x1116
283 #define HDMI_FC_GMD_PB18 0x1117
284 #define HDMI_FC_GMD_PB19 0x1118
285 #define HDMI_FC_GMD_PB20 0x1119
286 #define HDMI_FC_GMD_PB21 0x111A
287 #define HDMI_FC_GMD_PB22 0x111B
288 #define HDMI_FC_GMD_PB23 0x111C
289 #define HDMI_FC_GMD_PB24 0x111D
290 #define HDMI_FC_GMD_PB25 0x111E
291 #define HDMI_FC_GMD_PB26 0x111F
292 #define HDMI_FC_GMD_PB27 0x1120
294 #define HDMI_FC_DBGFORCE 0x1200
295 #define HDMI_FC_DBGAUD0CH0 0x1201
296 #define HDMI_FC_DBGAUD1CH0 0x1202
297 #define HDMI_FC_DBGAUD2CH0 0x1203
298 #define HDMI_FC_DBGAUD0CH1 0x1204
299 #define HDMI_FC_DBGAUD1CH1 0x1205
300 #define HDMI_FC_DBGAUD2CH1 0x1206
301 #define HDMI_FC_DBGAUD0CH2 0x1207
302 #define HDMI_FC_DBGAUD1CH2 0x1208
303 #define HDMI_FC_DBGAUD2CH2 0x1209
304 #define HDMI_FC_DBGAUD0CH3 0x120A
305 #define HDMI_FC_DBGAUD1CH3 0x120B
306 #define HDMI_FC_DBGAUD2CH3 0x120C
307 #define HDMI_FC_DBGAUD0CH4 0x120D
308 #define HDMI_FC_DBGAUD1CH4 0x120E
309 #define HDMI_FC_DBGAUD2CH4 0x120F
310 #define HDMI_FC_DBGAUD0CH5 0x1210
311 #define HDMI_FC_DBGAUD1CH5 0x1211
312 #define HDMI_FC_DBGAUD2CH5 0x1212
313 #define HDMI_FC_DBGAUD0CH6 0x1213
314 #define HDMI_FC_DBGAUD1CH6 0x1214
315 #define HDMI_FC_DBGAUD2CH6 0x1215
316 #define HDMI_FC_DBGAUD0CH7 0x1216
317 #define HDMI_FC_DBGAUD1CH7 0x1217
318 #define HDMI_FC_DBGAUD2CH7 0x1218
319 #define HDMI_FC_DBGTMDS0 0x1219
320 #define HDMI_FC_DBGTMDS1 0x121A
321 #define HDMI_FC_DBGTMDS2 0x121B
323 /* HDMI Source PHY Registers */
324 #define HDMI_PHY_CONF0 0x3000
325 #define HDMI_PHY_TST0 0x3001
326 #define HDMI_PHY_TST1 0x3002
327 #define HDMI_PHY_TST2 0x3003
328 #define HDMI_PHY_STAT0 0x3004
329 #define HDMI_PHY_INT0 0x3005
330 #define HDMI_PHY_MASK0 0x3006
331 #define HDMI_PHY_POL0 0x3007
333 /* HDMI Master PHY Registers */
334 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
335 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
336 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
337 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
338 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
339 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
340 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
341 #define HDMI_PHY_I2CM_INT_ADDR 0x3027
342 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
343 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
344 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
345 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
346 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
347 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
348 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
349 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
350 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
351 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
352 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
354 /* Audio Sampler Registers */
355 #define HDMI_AUD_CONF0 0x3100
356 #define HDMI_AUD_CONF1 0x3101
357 #define HDMI_AUD_INT 0x3102
358 #define HDMI_AUD_CONF2 0x3103
359 #define HDMI_AUD_N1 0x3200
360 #define HDMI_AUD_N2 0x3201
361 #define HDMI_AUD_N3 0x3202
362 #define HDMI_AUD_CTS1 0x3203
363 #define HDMI_AUD_CTS2 0x3204
364 #define HDMI_AUD_CTS3 0x3205
365 #define HDMI_AUD_INPUTCLKFS 0x3206
366 #define HDMI_AUD_SPDIFINT 0x3302
367 #define HDMI_AUD_CONF0_HBR 0x3400
368 #define HDMI_AUD_HBR_STATUS 0x3401
369 #define HDMI_AUD_HBR_INT 0x3402
370 #define HDMI_AUD_HBR_POL 0x3403
371 #define HDMI_AUD_HBR_MASK 0x3404
374 * Generic Parallel Audio Interface Registers
375 * Not used as GPAUD interface is not enabled in hw
377 #define HDMI_GP_CONF0 0x3500
378 #define HDMI_GP_CONF1 0x3501
379 #define HDMI_GP_CONF2 0x3502
380 #define HDMI_GP_STAT 0x3503
381 #define HDMI_GP_INT 0x3504
382 #define HDMI_GP_MASK 0x3505
383 #define HDMI_GP_POL 0x3506
385 /* Audio DMA Registers */
386 #define HDMI_AHB_DMA_CONF0 0x3600
387 #define HDMI_AHB_DMA_START 0x3601
388 #define HDMI_AHB_DMA_STOP 0x3602
389 #define HDMI_AHB_DMA_THRSLD 0x3603
390 #define HDMI_AHB_DMA_STRADDR0 0x3604
391 #define HDMI_AHB_DMA_STRADDR1 0x3605
392 #define HDMI_AHB_DMA_STRADDR2 0x3606
393 #define HDMI_AHB_DMA_STRADDR3 0x3607
394 #define HDMI_AHB_DMA_STPADDR0 0x3608
395 #define HDMI_AHB_DMA_STPADDR1 0x3609
396 #define HDMI_AHB_DMA_STPADDR2 0x360a
397 #define HDMI_AHB_DMA_STPADDR3 0x360b
398 #define HDMI_AHB_DMA_BSTADDR0 0x360c
399 #define HDMI_AHB_DMA_BSTADDR1 0x360d
400 #define HDMI_AHB_DMA_BSTADDR2 0x360e
401 #define HDMI_AHB_DMA_BSTADDR3 0x360f
402 #define HDMI_AHB_DMA_MBLENGTH0 0x3610
403 #define HDMI_AHB_DMA_MBLENGTH1 0x3611
404 #define HDMI_AHB_DMA_STAT 0x3612
405 #define HDMI_AHB_DMA_INT 0x3613
406 #define HDMI_AHB_DMA_MASK 0x3614
407 #define HDMI_AHB_DMA_POL 0x3615
408 #define HDMI_AHB_DMA_CONF1 0x3616
409 #define HDMI_AHB_DMA_BUFFSTAT 0x3617
410 #define HDMI_AHB_DMA_BUFFINT 0x3618
411 #define HDMI_AHB_DMA_BUFFMASK 0x3619
412 #define HDMI_AHB_DMA_BUFFPOL 0x361a
414 /* Main Controller Registers */
415 #define HDMI_MC_SFRDIV 0x4000
416 #define HDMI_MC_CLKDIS 0x4001
417 #define HDMI_MC_SWRSTZ 0x4002
418 #define HDMI_MC_OPCTRL 0x4003
419 #define HDMI_MC_FLOWCTRL 0x4004
420 #define HDMI_MC_PHYRSTZ 0x4005
421 #define HDMI_MC_LOCKONCLOCK 0x4006
422 #define HDMI_MC_HEACPHY_RST 0x4007
424 /* Color Space Converter Registers */
425 #define HDMI_CSC_CFG 0x4100
426 #define HDMI_CSC_SCALE 0x4101
427 #define HDMI_CSC_COEF_A1_MSB 0x4102
428 #define HDMI_CSC_COEF_A1_LSB 0x4103
429 #define HDMI_CSC_COEF_A2_MSB 0x4104
430 #define HDMI_CSC_COEF_A2_LSB 0x4105
431 #define HDMI_CSC_COEF_A3_MSB 0x4106
432 #define HDMI_CSC_COEF_A3_LSB 0x4107
433 #define HDMI_CSC_COEF_A4_MSB 0x4108
434 #define HDMI_CSC_COEF_A4_LSB 0x4109
435 #define HDMI_CSC_COEF_B1_MSB 0x410A
436 #define HDMI_CSC_COEF_B1_LSB 0x410B
437 #define HDMI_CSC_COEF_B2_MSB 0x410C
438 #define HDMI_CSC_COEF_B2_LSB 0x410D
439 #define HDMI_CSC_COEF_B3_MSB 0x410E
440 #define HDMI_CSC_COEF_B3_LSB 0x410F
441 #define HDMI_CSC_COEF_B4_MSB 0x4110
442 #define HDMI_CSC_COEF_B4_LSB 0x4111
443 #define HDMI_CSC_COEF_C1_MSB 0x4112
444 #define HDMI_CSC_COEF_C1_LSB 0x4113
445 #define HDMI_CSC_COEF_C2_MSB 0x4114
446 #define HDMI_CSC_COEF_C2_LSB 0x4115
447 #define HDMI_CSC_COEF_C3_MSB 0x4116
448 #define HDMI_CSC_COEF_C3_LSB 0x4117
449 #define HDMI_CSC_COEF_C4_MSB 0x4118
450 #define HDMI_CSC_COEF_C4_LSB 0x4119
452 /* HDCP Encryption Engine Registers */
453 #define HDMI_A_HDCPCFG0 0x5000
454 #define HDMI_A_HDCPCFG1 0x5001
455 #define HDMI_A_HDCPOBS0 0x5002
456 #define HDMI_A_HDCPOBS1 0x5003
457 #define HDMI_A_HDCPOBS2 0x5004
458 #define HDMI_A_HDCPOBS3 0x5005
459 #define HDMI_A_APIINTCLR 0x5006
460 #define HDMI_A_APIINTSTAT 0x5007
461 #define HDMI_A_APIINTMSK 0x5008
462 #define HDMI_A_VIDPOLCFG 0x5009
463 #define HDMI_A_OESSWCFG 0x500A
464 #define HDMI_A_TIMER1SETUP0 0x500B
465 #define HDMI_A_TIMER1SETUP1 0x500C
466 #define HDMI_A_TIMER2SETUP0 0x500D
467 #define HDMI_A_TIMER2SETUP1 0x500E
468 #define HDMI_A_100MSCFG 0x500F
469 #define HDMI_A_2SCFG0 0x5010
470 #define HDMI_A_2SCFG1 0x5011
471 #define HDMI_A_5SCFG0 0x5012
472 #define HDMI_A_5SCFG1 0x5013
473 #define HDMI_A_SRMVERLSB 0x5014
474 #define HDMI_A_SRMVERMSB 0x5015
475 #define HDMI_A_SRMCTRL 0x5016
476 #define HDMI_A_SFRSETUP 0x5017
477 #define HDMI_A_I2CHSETUP 0x5018
478 #define HDMI_A_INTSETUP 0x5019
479 #define HDMI_A_PRESETUP 0x501A
480 #define HDMI_A_SRM_BASE 0x5020
482 /* CEC Engine Registers */
483 #define HDMI_CEC_CTRL 0x7D00
484 #define HDMI_CEC_STAT 0x7D01
485 #define HDMI_CEC_MASK 0x7D02
486 #define HDMI_CEC_POLARITY 0x7D03
487 #define HDMI_CEC_INT 0x7D04
488 #define HDMI_CEC_ADDR_L 0x7D05
489 #define HDMI_CEC_ADDR_H 0x7D06
490 #define HDMI_CEC_TX_CNT 0x7D07
491 #define HDMI_CEC_RX_CNT 0x7D08
492 #define HDMI_CEC_TX_DATA0 0x7D10
493 #define HDMI_CEC_TX_DATA1 0x7D11
494 #define HDMI_CEC_TX_DATA2 0x7D12
495 #define HDMI_CEC_TX_DATA3 0x7D13
496 #define HDMI_CEC_TX_DATA4 0x7D14
497 #define HDMI_CEC_TX_DATA5 0x7D15
498 #define HDMI_CEC_TX_DATA6 0x7D16
499 #define HDMI_CEC_TX_DATA7 0x7D17
500 #define HDMI_CEC_TX_DATA8 0x7D18
501 #define HDMI_CEC_TX_DATA9 0x7D19
502 #define HDMI_CEC_TX_DATA10 0x7D1a
503 #define HDMI_CEC_TX_DATA11 0x7D1b
504 #define HDMI_CEC_TX_DATA12 0x7D1c
505 #define HDMI_CEC_TX_DATA13 0x7D1d
506 #define HDMI_CEC_TX_DATA14 0x7D1e
507 #define HDMI_CEC_TX_DATA15 0x7D1f
508 #define HDMI_CEC_RX_DATA0 0x7D20
509 #define HDMI_CEC_RX_DATA1 0x7D21
510 #define HDMI_CEC_RX_DATA2 0x7D22
511 #define HDMI_CEC_RX_DATA3 0x7D23
512 #define HDMI_CEC_RX_DATA4 0x7D24
513 #define HDMI_CEC_RX_DATA5 0x7D25
514 #define HDMI_CEC_RX_DATA6 0x7D26
515 #define HDMI_CEC_RX_DATA7 0x7D27
516 #define HDMI_CEC_RX_DATA8 0x7D28
517 #define HDMI_CEC_RX_DATA9 0x7D29
518 #define HDMI_CEC_RX_DATA10 0x7D2a
519 #define HDMI_CEC_RX_DATA11 0x7D2b
520 #define HDMI_CEC_RX_DATA12 0x7D2c
521 #define HDMI_CEC_RX_DATA13 0x7D2d
522 #define HDMI_CEC_RX_DATA14 0x7D2e
523 #define HDMI_CEC_RX_DATA15 0x7D2f
524 #define HDMI_CEC_LOCK 0x7D30
525 #define HDMI_CEC_WKUPCTRL 0x7D31
527 /* I2C Master Registers (E-DDC) */
528 #define HDMI_I2CM_SLAVE 0x7E00
529 #define HDMI_I2CM_ADDRESS 0x7E01
530 #define HDMI_I2CM_DATAO 0x7E02
531 #define HDMI_I2CM_DATAI 0x7E03
532 #define HDMI_I2CM_OPERATION 0x7E04
533 #define HDMI_I2CM_INT 0x7E05
534 #define HDMI_I2CM_CTLINT 0x7E06
535 #define HDMI_I2CM_DIV 0x7E07
536 #define HDMI_I2CM_SEGADDR 0x7E08
537 #define HDMI_I2CM_SOFTRSTZ 0x7E09
538 #define HDMI_I2CM_SEGPTR 0x7E0A
539 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
540 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
541 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
542 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
543 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
544 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
545 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
546 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
550 /* CONFIG0_ID field values */
551 HDMI_CONFIG0_I2S = 0x10,
553 /* CONFIG1_ID field values */
554 HDMI_CONFIG1_AHB = 0x01,
556 /* IH_FC_INT2 field values */
557 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
558 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
559 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
561 /* IH_FC_STAT2 field values */
562 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
563 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
564 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
566 /* IH_PHY_STAT0 field values */
567 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
568 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
569 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
570 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
571 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
572 HDMI_IH_PHY_STAT0_HPD = 0x1,
574 /* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */
575 HDMI_IH_I2CM_STAT0_DONE = 0x2,
576 HDMI_IH_I2CM_STAT0_ERROR = 0x1,
578 /* IH_MUTE_I2CMPHY_STAT0 field values */
579 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
580 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
582 /* IH_AHBDMAAUD_STAT0 field values */
583 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
584 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
585 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
586 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
587 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
588 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
590 /* IH_MUTE_FC_STAT2 field values */
591 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
592 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
593 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
595 /* IH_MUTE_AHBDMAAUD_STAT0 field values */
596 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
597 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
598 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
599 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
600 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
601 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
603 /* IH_MUTE field values */
604 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
605 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
607 /* TX_INVID0 field values */
608 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
609 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
610 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
611 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
612 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
614 /* TX_INSTUFFING field values */
615 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
616 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
617 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
618 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
619 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
620 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
621 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
622 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
623 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
625 /* VP_PR_CD field values */
626 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
627 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
628 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
629 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
631 /* VP_STUFF field values */
632 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
633 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
634 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
635 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
636 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
637 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
638 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
639 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
640 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
641 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
642 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
643 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
644 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
645 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
646 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
648 /* VP_CONF field values */
649 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
650 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
651 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
652 HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
653 HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
654 HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
655 HDMI_VP_CONF_PR_EN_MASK = 0x10,
656 HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
657 HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
658 HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
659 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
660 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
661 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
662 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
663 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
664 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
665 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
666 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
667 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
669 /* VP_REMAP field values */
670 HDMI_VP_REMAP_MASK = 0x3,
671 HDMI_VP_REMAP_YCC422_24bit = 0x2,
672 HDMI_VP_REMAP_YCC422_20bit = 0x1,
673 HDMI_VP_REMAP_YCC422_16bit = 0x0,
675 /* FC_INVIDCONF field values */
676 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
677 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
678 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
679 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
680 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
681 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
682 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
683 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
684 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
685 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
686 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
687 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
688 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
689 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
690 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
691 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
692 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
693 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
694 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
695 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
696 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
698 /* FC_AUDICONF0 field values */
699 HDMI_FC_AUDICONF0_CC_OFFSET = 4,
700 HDMI_FC_AUDICONF0_CC_MASK = 0x70,
701 HDMI_FC_AUDICONF0_CT_OFFSET = 0,
702 HDMI_FC_AUDICONF0_CT_MASK = 0xF,
704 /* FC_AUDICONF1 field values */
705 HDMI_FC_AUDICONF1_SS_OFFSET = 3,
706 HDMI_FC_AUDICONF1_SS_MASK = 0x18,
707 HDMI_FC_AUDICONF1_SF_OFFSET = 0,
708 HDMI_FC_AUDICONF1_SF_MASK = 0x7,
710 /* FC_AUDICONF3 field values */
711 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
712 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
713 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
714 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
715 HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
716 HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
718 /* FC_AUDSCHNLS0 field values */
719 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
720 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
721 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
722 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
724 /* FC_AUDSCHNLS3-6 field values */
725 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
726 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
727 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
728 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
729 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
730 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
731 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
732 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
734 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
735 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
736 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
737 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
738 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
739 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
740 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
741 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
743 /* HDMI_FC_AUDSCHNLS7 field values */
744 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
745 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
747 /* HDMI_FC_AUDSCHNLS8 field values */
748 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
749 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
750 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
751 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
753 /* FC_AUDSCONF field values */
754 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
755 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
756 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
757 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
758 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
759 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
761 /* FC_STAT2 field values */
762 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
763 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
764 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
766 /* FC_INT2 field values */
767 HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
768 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
769 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
771 /* FC_MASK2 field values */
772 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
773 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
774 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
776 /* FC_PRCONF field values */
777 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
778 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
779 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
780 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
782 /* FC_AVICONF0-FC_AVICONF3 field values */
783 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
784 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
785 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
786 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
787 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
788 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
789 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
790 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
791 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
792 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
793 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
794 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
795 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
796 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
797 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
798 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
800 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
801 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
802 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
803 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
804 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
805 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
806 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
807 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
808 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
809 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
810 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
811 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
812 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
813 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
815 HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
816 HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
817 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
818 HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
819 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
820 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
821 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
822 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
823 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
824 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
825 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
826 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
827 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
828 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
829 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
830 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
831 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
832 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
834 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
835 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
836 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
837 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
838 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
839 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
840 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
841 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
843 /* FC_DBGFORCE field values */
844 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
845 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
847 /* FC_DATAUTO0 field values */
848 HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
849 HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
851 /* PHY_CONF0 field values */
852 HDMI_PHY_CONF0_PDZ_MASK = 0x80,
853 HDMI_PHY_CONF0_PDZ_OFFSET = 7,
854 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
855 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
856 HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
857 HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
858 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
859 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
860 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
861 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
862 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
863 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
864 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
865 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
866 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
867 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
869 /* PHY_TST0 field values */
870 HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
871 HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
872 HDMI_PHY_TST0_TSTEN_MASK = 0x10,
873 HDMI_PHY_TST0_TSTEN_OFFSET = 4,
874 HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
875 HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
877 /* PHY_STAT0 field values */
878 HDMI_PHY_RX_SENSE3 = 0x80,
879 HDMI_PHY_RX_SENSE2 = 0x40,
880 HDMI_PHY_RX_SENSE1 = 0x20,
881 HDMI_PHY_RX_SENSE0 = 0x10,
883 HDMI_PHY_TX_PHY_LOCK = 0x01,
885 /* PHY_I2CM_SLAVE_ADDR field values */
886 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
887 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
889 /* PHY_I2CM_OPERATION_ADDR field values */
890 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
891 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
893 /* HDMI_PHY_I2CM_INT_ADDR */
894 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
895 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
897 /* HDMI_PHY_I2CM_CTLINT_ADDR */
898 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
899 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
900 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
901 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
903 /* AUD_CONF0 field values */
904 HDMI_AUD_CONF0_SW_RESET = 0x80,
905 HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21,
906 HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23,
907 HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27,
908 HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F,
909 HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F,
911 /* AUD_CONF1 field values */
912 HDMI_AUD_CONF1_MODE_I2S = 0x00,
913 HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02,
914 HDMI_AUD_CONF1_MODE_LEFT_J = 0x04,
915 HDMI_AUD_CONF1_WIDTH_16 = 0x10,
916 HDMI_AUD_CONF1_WIDTH_24 = 0x18,
918 /* AUD_CONF2 filed values */
919 HDMI_AUD_CONF2_HBR = 0x1,
920 HDMI_AUD_CONF2_NLPCM = 0x2,
921 HDMI_AUD_CONF2_INSERT_PCUV = 0x04,
923 /* AUD_CTS3 field values */
924 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
925 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
926 HDMI_AUD_CTS3_N_SHIFT_1 = 0,
927 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
928 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
929 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
930 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
931 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
932 /* note that the CTS3 MANUAL bit has been removed
933 from our part. Can't set it, will read as 0. */
934 HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
935 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
937 /* HDMI_AUD_INPUTCLKFS field values */
938 HDMI_AUD_INPUTCLKFS_128FS = 0,
939 HDMI_AUD_INPUTCLKFS_256FS = 1,
940 HDMI_AUD_INPUTCLKFS_512FS = 2,
941 HDMI_AUD_INPUTCLKFS_64FS = 4,
943 /* AHB_DMA_CONF0 field values */
944 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
945 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
946 HDMI_AHB_DMA_CONF0_HBR = 0x10,
947 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
948 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
949 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
950 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
951 HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
952 HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
953 HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
954 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
956 /* HDMI_AHB_DMA_START field values */
957 HDMI_AHB_DMA_START_START_OFFSET = 0,
958 HDMI_AHB_DMA_START_START_MASK = 0x01,
960 /* HDMI_AHB_DMA_STOP field values */
961 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
962 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
964 /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
965 HDMI_AHB_DMA_DONE = 0x80,
966 HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
967 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
968 HDMI_AHB_DMA_ERROR = 0x10,
969 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
970 HDMI_AHB_DMA_FIFO_FULL = 0x02,
971 HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
973 /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
974 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
975 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
977 /* MC_CLKDIS field values */
978 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
979 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
980 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
981 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
982 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
983 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
984 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
986 /* MC_SWRSTZ field values */
987 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
989 /* MC_FLOWCTRL field values */
990 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
991 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
992 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
994 /* MC_PHYRSTZ field values */
995 HDMI_MC_PHYRSTZ_ASSERT = 0x0,
996 HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
998 /* MC_HEACPHY_RST field values */
999 HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
1000 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
1002 /* CSC_CFG field values */
1003 HDMI_CSC_CFG_INTMODE_MASK = 0x30,
1004 HDMI_CSC_CFG_INTMODE_OFFSET = 4,
1005 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
1006 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
1007 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
1008 HDMI_CSC_CFG_DECMODE_MASK = 0x3,
1009 HDMI_CSC_CFG_DECMODE_OFFSET = 0,
1010 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
1011 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
1012 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
1013 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
1015 /* CSC_SCALE field values */
1016 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
1017 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
1018 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
1019 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
1020 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
1021 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
1023 /* A_HDCPCFG0 field values */
1024 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
1025 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
1026 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
1027 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
1028 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
1029 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
1030 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
1031 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
1032 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
1033 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
1034 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
1035 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
1036 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
1037 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
1038 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
1039 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
1040 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
1041 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
1042 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
1043 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
1044 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
1045 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
1046 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1047 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1049 /* A_HDCPCFG1 field values */
1050 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1051 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1052 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1053 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1054 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1055 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1056 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1057 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1058 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1059 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1060 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1062 /* A_VIDPOLCFG field values */
1063 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1064 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1065 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1066 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1067 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1068 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1069 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1070 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1071 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1072 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1073 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1075 /* I2CM_OPERATION field values */
1076 HDMI_I2CM_OPERATION_WRITE = 0x10,
1077 HDMI_I2CM_OPERATION_READ_EXT = 0x2,
1078 HDMI_I2CM_OPERATION_READ = 0x1,
1080 /* I2CM_INT field values */
1081 HDMI_I2CM_INT_DONE_POL = 0x8,
1082 HDMI_I2CM_INT_DONE_MASK = 0x4,
1084 /* I2CM_CTLINT field values */
1085 HDMI_I2CM_CTLINT_NAC_POL = 0x80,
1086 HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
1087 HDMI_I2CM_CTLINT_ARB_POL = 0x8,
1088 HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
1090 /* I2CM_DIV field values */
1091 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
1092 HDMI_I2CM_DIV_FAST_MODE = 0x8,
1093 HDMI_I2CM_DIV_STD_MODE = 0,
1096 #endif /* __DW_HDMI_H__ */