drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include "dw-hdmi.h"
  39 #include "dw-hdmi-audio.h"
  40
  41 #define HDMI_EDID_LEN           512
  42 #define DDC_SEGMENT_ADDR       0x30
  43
  44 #define RGB                     0
  45 #define YCBCR444                1
  46 #define YCBCR422_16BITS         2
  47 #define YCBCR422_8BITS          3
  48 #define XVYCC444                4
  49 #define YCBCR420                5
  50
  51 enum hdmi_datamap {
  52         RGB444_8B = 0x01,
  53         RGB444_10B = 0x03,
  54         RGB444_12B = 0x05,
  55         RGB444_16B = 0x07,
  56         YCbCr444_8B = 0x09,
  57         YCbCr444_10B = 0x0B,
  58         YCbCr444_12B = 0x0D,
  59         YCbCr444_16B = 0x0F,
  60         YCbCr422_8B = 0x16,
  61         YCbCr422_10B = 0x14,
  62         YCbCr422_12B = 0x12,
  63 };
  64
  65 /*
  66  * Unless otherwise noted, entries in this table are 100% optimization.
  67  * Values can be obtained from hdmi_compute_n() but that function is
  68  * slow so we pre-compute values we expect to see.
  69  *
  70  * All 32k and 48k values are expected to be the same (due to the way
  71  * the math works) for any rate that's an exact kHz.
  72  */
  73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  74         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  75         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  76         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  77         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  78         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  79         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  80         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  81         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  82         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  83         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  84         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  85         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  86         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  87         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  88         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  89         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  90         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  91         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  92         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  93         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  94         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  95         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  96         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  97         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  98         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  99         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 100         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 101         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
 102         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 103         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 104         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 105         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 106         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 107         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 108         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 109         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 110         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 111
 112         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 113         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 114         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 115
 116         /* End of table */
 117         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 118 };
 119
 120 static const u16 csc_coeff_default[3][4] = {
 121         { 0x2000, 0x0000, 0x0000, 0x0000 },
 122         { 0x0000, 0x2000, 0x0000, 0x0000 },
 123         { 0x0000, 0x0000, 0x2000, 0x0000 }
 124 };
 125
 126 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 127         { 0x2000, 0x6926, 0x74fd, 0x010e },
 128         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 129         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 130 };
 131
 132 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 133         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 134         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 135         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 136 };
 137
 138 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 139         { 0x2591, 0x1322, 0x074b, 0x0000 },
 140         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 141         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 142 };
 143
 144 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 145         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 146         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 147         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 148 };
 149
 150 struct hdmi_vmode {
 151         bool mdataenablepolarity;
 152
 153         unsigned int mpixelclock;
 154         unsigned int mpixelrepetitioninput;
 155         unsigned int mpixelrepetitionoutput;
 156 };
 157
 158 struct hdmi_data_info {
 159         unsigned int enc_in_format;
 160         unsigned int enc_out_format;
 161         unsigned int enc_color_depth;
 162         unsigned int colorimetry;
 163         unsigned int pix_repet_factor;
 164         unsigned int hdcp_enable;
 165         struct hdmi_vmode video_mode;
 166 };
 167
 168 struct dw_hdmi_i2c {
 169         struct i2c_adapter      adap;
 170
 171         struct mutex            lock;
 172         struct completion       cmp;
 173         u8                      stat;
 174
 175         u8                      slave_reg;
 176         bool                    is_regaddr;
 177         bool                    is_segment;
 178
 179         unsigned int            scl_high_ns;
 180         unsigned int            scl_low_ns;
 181 };
 182
 183 struct dw_hdmi {
 184         struct drm_connector connector;
 185         struct drm_encoder *encoder;
 186         struct drm_bridge *bridge;
 187
 188         struct platform_device *audio;
 189         enum dw_hdmi_devtype dev_type;
 190         struct device *dev;
 191         struct clk *isfr_clk;
 192         struct clk *iahb_clk;
 193         struct dw_hdmi_i2c *i2c;
 194
 195         struct hdmi_data_info hdmi_data;
 196         const struct dw_hdmi_plat_data *plat_data;
 197
 198         int vic;
 199
 200         u8 edid[HDMI_EDID_LEN];
 201         bool cable_plugin;
 202
 203         bool phy_enabled;
 204         struct drm_display_mode previous_mode;
 205
 206         struct i2c_adapter *ddc;
 207         void __iomem *regs;
 208         bool sink_is_hdmi;
 209         bool sink_has_audio;
 210         bool hpd_state;
 211
 212         struct delayed_work work;
 213         struct workqueue_struct *workqueue;
 214
 215         struct mutex mutex;             /* for state below and previous_mode */
 216         enum drm_connector_force force; /* mutex-protected force state */
 217         bool disabled;                  /* DRM has disabled our bridge */
 218         bool bridge_is_on;              /* indicates the bridge is on */
 219         bool rxsense;                   /* rxsense state */
 220         u8 phy_mask;                    /* desired phy int mask settings */
 221
 222         spinlock_t audio_lock;
 223         struct mutex audio_mutex;
 224         unsigned int sample_rate;
 225         unsigned int audio_cts;
 226         unsigned int audio_n;
 227         bool audio_enable;
 228
 229 #ifdef CONFIG_SWITCH
 230         struct switch_dev switchdev;
 231 #endif
 232         int irq;
 233
 234         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 235         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 236 };
 237
 238 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 239         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 240          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 241
 242 #define HDMI_PHY_RX_SENSE \
 243         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 244          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 245
 246 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 247 {
 248         writel(val, hdmi->regs + (offset << 2));
 249 }
 250
 251 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 252 {
 253         return readl(hdmi->regs + (offset << 2));
 254 }
 255
 256 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 257 {
 258         writeb(val, hdmi->regs + offset);
 259 }
 260
 261 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 262 {
 263         return readb(hdmi->regs + offset);
 264 }
 265
 266 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 267 {
 268         hdmi->write(hdmi, val, offset);
 269 }
 270
 271 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 272 {
 273         return hdmi->read(hdmi, offset);
 274 }
 275
 276 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 277 {
 278         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 279
 280         val |= data & mask;
 281         hdmi_writeb(hdmi, val, reg);
 282 }
 283
 284 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 285                              u8 shift, u8 mask)
 286 {
 287         hdmi_modb(hdmi, data << shift, mask, reg);
 288 }
 289
 290 static void repo_hpd_event(struct work_struct *p_work)
 291 {
 292         struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
 293
 294         drm_helper_hpd_irq_event(hdmi->bridge->dev);
 295 #ifdef CONFIG_SWITCH
 296         if (hdmi->hpd_state)
 297                 switch_set_state(&hdmi->switchdev, 1);
 298         else
 299                 switch_set_state(&hdmi->switchdev, 0);
 300 #endif
 301 }
 302
 303 static bool check_hdmi_irq(struct dw_hdmi *hdmi, int intr_stat,
 304                            int phy_int_pol)
 305 {
 306         int msecs;
 307
 308         /* To determine whether interrupt type is HPD */
 309         if (!(intr_stat & HDMI_IH_PHY_STAT0_HPD))
 310                 return false;
 311
 312         if (phy_int_pol & HDMI_PHY_HPD) {
 313                 dev_dbg(hdmi->dev, "dw hdmi plug in\n");
 314                 msecs = 150;
 315                 hdmi->hpd_state = true;
 316         } else {
 317                 dev_dbg(hdmi->dev, "dw hdmi plug out\n");
 318                 msecs = 20;
 319                 hdmi->hpd_state = false;
 320         }
 321         mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs));
 322
 323         return true;
 324 }
 325
 326 static void init_hpd_work(struct dw_hdmi *hdmi)
 327 {
 328         hdmi->workqueue = create_workqueue("hpd_queue");
 329         INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event);
 330 }
 331
 332 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
 333 {
 334         unsigned long clk_rate_khz;
 335         unsigned long low_ns, high_ns;
 336         unsigned long div_low, div_high;
 337
 338         /* Standard-mode */
 339         if (hdmi->i2c->scl_high_ns < 4000)
 340                 high_ns = 4708;
 341         else
 342                 high_ns = hdmi->i2c->scl_high_ns;
 343
 344         if (hdmi->i2c->scl_low_ns < 4700)
 345                 low_ns = 4916;
 346         else
 347                 low_ns = hdmi->i2c->scl_low_ns;
 348
 349         /* Adjust to avoid overflow */
 350         clk_rate_khz = DIV_ROUND_UP(clk_get_rate(hdmi->isfr_clk), 1000);
 351
 352         div_low = (clk_rate_khz * low_ns) / 1000000;
 353         if ((clk_rate_khz * low_ns) % 1000000)
 354                 div_low++;
 355
 356         div_high = (clk_rate_khz * high_ns) / 1000000;
 357         if ((clk_rate_khz * high_ns) % 1000000)
 358                 div_high++;
 359
 360         /* Maximum divider supported by hw is 0xffff */
 361         if (div_low > 0xffff)
 362                 div_low = 0xffff;
 363
 364         if (div_high > 0xffff)
 365                 div_high = 0xffff;
 366
 367         hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
 368         hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
 369                     HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
 370         hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
 371         hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
 372                     HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
 373 }
 374
 375 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 376 {
 377         /* Software reset */
 378         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 379
 380         /* Set Standard Mode speed */
 381         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 382                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 383
 384         /* Set done, not acknowledged and arbitration interrupt polarities */
 385         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 386         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 387                     HDMI_I2CM_CTLINT);
 388
 389         /* Clear DONE and ERROR interrupts */
 390         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 391                     HDMI_IH_I2CM_STAT0);
 392
 393         /* Mute DONE and ERROR interrupts */
 394         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 395                     HDMI_IH_MUTE_I2CM_STAT0);
 396
 397         /* set SDA high level holding time */
 398         hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
 399
 400         dw_hdmi_i2c_set_divs(hdmi);
 401 }
 402
 403 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 404                             unsigned char *buf, unsigned int length)
 405 {
 406         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 407         int stat;
 408
 409         if (!i2c->is_regaddr) {
 410                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 411                 i2c->slave_reg = 0x00;
 412                 i2c->is_regaddr = true;
 413         }
 414
 415         while (length--) {
 416                 reinit_completion(&i2c->cmp);
 417
 418                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 419                 if (i2c->is_segment)
 420                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 421                                     HDMI_I2CM_OPERATION);
 422                 else
 423                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 424                                     HDMI_I2CM_OPERATION);
 425
 426                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 427                 if (!stat)
 428                         return -EAGAIN;
 429
 430                 /* Check for error condition on the bus */
 431                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 432                         return -EIO;
 433
 434                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 435         }
 436         i2c->is_segment = false;
 437
 438         return 0;
 439 }
 440
 441 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 442                              unsigned char *buf, unsigned int length)
 443 {
 444         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 445         int stat;
 446
 447         if (!i2c->is_regaddr) {
 448                 /* Use the first write byte as register address */
 449                 i2c->slave_reg = buf[0];
 450                 length--;
 451                 buf++;
 452                 i2c->is_regaddr = true;
 453         }
 454
 455         while (length--) {
 456                 reinit_completion(&i2c->cmp);
 457
 458                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 459                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 460                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 461                             HDMI_I2CM_OPERATION);
 462
 463         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 464                 if (!stat)
 465                         return -EAGAIN;
 466
 467                 /* Check for error condition on the bus */
 468                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 469                         return -EIO;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 476                             struct i2c_msg *msgs, int num)
 477 {
 478         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 479         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 480         u8 addr = msgs[0].addr;
 481         int i, ret = 0;
 482
 483         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 484
 485         for (i = 0; i < num; i++) {
 486                 if (msgs[i].len == 0) {
 487                         dev_dbg(hdmi->dev,
 488                                 "unsupported transfer %d/%d, no data\n",
 489                                 i + 1, num);
 490                         return -EOPNOTSUPP;
 491                 }
 492         }
 493
 494         mutex_lock(&i2c->lock);
 495
 496         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 497
 498         /* Set slave device address taken from the first I2C message */
 499         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 500
 501         /* Set slave device register address on transfer */
 502         i2c->is_regaddr = false;
 503
 504         /* Set segment pointer for I2C extended read mode operation */
 505         i2c->is_segment = false;
 506
 507         for (i = 0; i < num; i++) {
 508                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 509                         i + 1, num, msgs[i].len, msgs[i].flags);
 510                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 511                         i2c->is_segment = true;
 512                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 513                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 514                 } else {
 515                         if (msgs[i].flags & I2C_M_RD)
 516                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 517                                                        msgs[i].len);
 518                         else
 519                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 520                                                         msgs[i].len);
 521                 }
 522                 if (ret < 0)
 523                         break;
 524         }
 525
 526         if (!ret)
 527                 ret = num;
 528
 529         /* Mute DONE and ERROR interrupts */
 530         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 531                     HDMI_IH_MUTE_I2CM_STAT0);
 532
 533         mutex_unlock(&i2c->lock);
 534
 535         return ret;
 536 }
 537
 538 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 539 {
 540         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 541 }
 542
 543 static const struct i2c_algorithm dw_hdmi_algorithm = {
 544         .master_xfer    = dw_hdmi_i2c_xfer,
 545         .functionality  = dw_hdmi_i2c_func,
 546 };
 547
 548 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 549 {
 550         struct i2c_adapter *adap;
 551         struct dw_hdmi_i2c *i2c;
 552         int ret;
 553
 554         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 555         if (!i2c)
 556                 return ERR_PTR(-ENOMEM);
 557
 558         mutex_init(&i2c->lock);
 559         init_completion(&i2c->cmp);
 560
 561         adap = &i2c->adap;
 562         adap->class = I2C_CLASS_DDC;
 563         adap->owner = THIS_MODULE;
 564         adap->dev.parent = hdmi->dev;
 565         adap->dev.of_node = hdmi->dev->of_node;
 566         adap->algo = &dw_hdmi_algorithm;
 567         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 568         i2c_set_adapdata(adap, hdmi);
 569
 570         ret = i2c_add_adapter(adap);
 571         if (ret) {
 572                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 573                 devm_kfree(hdmi->dev, i2c);
 574                 return ERR_PTR(ret);
 575         }
 576
 577         hdmi->i2c = i2c;
 578
 579         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 580
 581         return adap;
 582 }
 583
 584 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 585                            unsigned int n)
 586 {
 587         /* Must be set/cleared first */
 588         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 589
 590         /* nshift factor = 0 */
 591         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 592
 593         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 594                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 595         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 596         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 597
 598         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 599         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 600         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 601 }
 602
 603 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 604                                    unsigned long pixel_clk,
 605                                    unsigned long freq)
 606 {
 607         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 608         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 609         int i;
 610
 611         if (plat_data->tmds_n_table) {
 612                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 613                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 614                                 tmds_n = &plat_data->tmds_n_table[i];
 615                                 break;
 616                         }
 617                 }
 618         }
 619
 620         if (tmds_n == NULL) {
 621                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 622                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 623                                 tmds_n = &common_tmds_n_table[i];
 624                                 break;
 625                         }
 626                 }
 627         }
 628
 629         if (tmds_n == NULL)
 630                 return -ENOENT;
 631
 632         switch (freq) {
 633         case 32000:
 634                 return tmds_n->n_32k;
 635         case 44100:
 636         case 88200:
 637         case 176400:
 638                 return (freq / 44100) * tmds_n->n_44k1;
 639         case 48000:
 640         case 96000:
 641         case 192000:
 642                 return (freq / 48000) * tmds_n->n_48k;
 643         default:
 644                 return -ENOENT;
 645         }
 646 }
 647
 648 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 649                                 unsigned int pixel_clk)
 650 {
 651         u64 final, diff;
 652         u64 cts;
 653
 654         final = (u64)pixel_clk * n;
 655
 656         cts = final;
 657         do_div(cts, 128 * freq);
 658
 659         diff = final - (u64)cts * (128 * freq);
 660
 661         return diff;
 662 }
 663
 664 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 665                                    unsigned long pixel_clk,
 666                                    unsigned long freq)
 667 {
 668         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 669         unsigned int max_n = (128 * freq) / 300;
 670         unsigned int ideal_n = (128 * freq) / 1000;
 671         unsigned int best_n_distance = ideal_n;
 672         unsigned int best_n = 0;
 673         u64 best_diff = U64_MAX;
 674         int n;
 675
 676         /* If the ideal N could satisfy the audio math, then just take it */
 677         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 678                 return ideal_n;
 679
 680         for (n = min_n; n <= max_n; n++) {
 681                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 682
 683                 if (diff < best_diff || (diff == best_diff &&
 684                     abs(n - ideal_n) < best_n_distance)) {
 685                         best_n = n;
 686                         best_diff = diff;
 687                         best_n_distance = abs(best_n - ideal_n);
 688                 }
 689
 690                 /*
 691                  * The best N already satisfy the audio math, and also be
 692                  * the closest value to ideal N, so just cut the loop.
 693                  */
 694                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 695                         break;
 696         }
 697
 698         return best_n;
 699 }
 700
 701 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 702                                 unsigned long sample_rate)
 703 {
 704         int n;
 705
 706         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 707         if (n > 0)
 708                 return n;
 709
 710         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 711                  pixel_clk);
 712
 713         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 714 }
 715
 716 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 717         unsigned long pixel_clk, unsigned int sample_rate)
 718 {
 719         unsigned long ftdms = pixel_clk;
 720         unsigned int n, cts;
 721         u64 tmp;
 722
 723         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 724
 725         /*
 726          * Compute the CTS value from the N value.  Note that CTS and N
 727          * can be up to 20 bits in total, so we need 64-bit math.  Also
 728          * note that our TDMS clock is not fully accurate; it is accurate
 729          * to kHz.  This can introduce an unnecessary remainder in the
 730          * calculation below, so we don't try to warn about that.
 731          */
 732         tmp = (u64)ftdms * n;
 733         do_div(tmp, 128 * sample_rate);
 734         cts = tmp;
 735
 736         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 737                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 738                 n, cts);
 739
 740         spin_lock_irq(&hdmi->audio_lock);
 741         hdmi->audio_n = n;
 742         hdmi->audio_cts = cts;
 743         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 744         spin_unlock_irq(&hdmi->audio_lock);
 745 }
 746
 747 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 748 {
 749         mutex_lock(&hdmi->audio_mutex);
 750         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 751         mutex_unlock(&hdmi->audio_mutex);
 752 }
 753
 754 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 755 {
 756         mutex_lock(&hdmi->audio_mutex);
 757         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 758                                  hdmi->sample_rate);
 759         mutex_unlock(&hdmi->audio_mutex);
 760 }
 761
 762 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 763 {
 764         mutex_lock(&hdmi->audio_mutex);
 765         hdmi->sample_rate = rate;
 766         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 767                                  hdmi->sample_rate);
 768         mutex_unlock(&hdmi->audio_mutex);
 769 }
 770 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 771
 772 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 773 {
 774         unsigned long flags;
 775
 776         spin_lock_irqsave(&hdmi->audio_lock, flags);
 777         hdmi->audio_enable = true;
 778         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 779         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 780 }
 781 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 782
 783 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 784 {
 785         unsigned long flags;
 786
 787         spin_lock_irqsave(&hdmi->audio_lock, flags);
 788         hdmi->audio_enable = false;
 789         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 790         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 791 }
 792 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 793
 794 /*
 795  * this submodule is responsible for the video data synchronization.
 796  * for example, for RGB 4:4:4 input, the data map is defined as
 797  *                      pin{47~40} <==> R[7:0]
 798  *                      pin{31~24} <==> G[7:0]
 799  *                      pin{15~8}  <==> B[7:0]
 800  */
 801 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 802 {
 803         int color_format = 0;
 804         u8 val;
 805
 806         if (hdmi->hdmi_data.enc_in_format == RGB) {
 807                 if (hdmi->hdmi_data.enc_color_depth == 8)
 808                         color_format = 0x01;
 809                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 810                         color_format = 0x03;
 811                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 812                         color_format = 0x05;
 813                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 814                         color_format = 0x07;
 815                 else
 816                         return;
 817         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
 818                    hdmi->hdmi_data.enc_in_format == YCBCR420) {
 819                 if (hdmi->hdmi_data.enc_color_depth == 8)
 820                         color_format = 0x09;
 821                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 822                         color_format = 0x0B;
 823                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 824                         color_format = 0x0D;
 825                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 826                         color_format = 0x0F;
 827                 else
 828                         return;
 829         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 830                 if (hdmi->hdmi_data.enc_color_depth == 8)
 831                         color_format = 0x16;
 832                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 833                         color_format = 0x14;
 834                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 835                         color_format = 0x12;
 836                 else
 837                         return;
 838         }
 839
 840         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 841                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 842                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 843         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 844
 845         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 846         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 847                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 848                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 849         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 850         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 851         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 852         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 853         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 854         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 855         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 856 }
 857
 858 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 859 {
 860         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 861 }
 862
 863 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 864 {
 865         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 866                 return 0;
 867         if (hdmi->hdmi_data.enc_in_format == RGB ||
 868             hdmi->hdmi_data.enc_in_format == YCBCR444)
 869                 return 1;
 870         return 0;
 871 }
 872
 873 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 874 {
 875         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 876                 return 0;
 877         if (hdmi->hdmi_data.enc_out_format == RGB ||
 878             hdmi->hdmi_data.enc_out_format == YCBCR444)
 879                 return 1;
 880         return 0;
 881 }
 882
 883 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 884 {
 885         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 886         unsigned i;
 887         u32 csc_scale = 1;
 888
 889         if (is_color_space_conversion(hdmi)) {
 890                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 891                         if (hdmi->hdmi_data.colorimetry ==
 892                                         HDMI_COLORIMETRY_ITU_601)
 893                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 894                         else
 895                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 896                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 897                         if (hdmi->hdmi_data.colorimetry ==
 898                                         HDMI_COLORIMETRY_ITU_601)
 899                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 900                         else
 901                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 902                         csc_scale = 0;
 903                 }
 904         }
 905
 906         /* The CSC registers are sequential, alternating MSB then LSB */
 907         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 908                 u16 coeff_a = (*csc_coeff)[0][i];
 909                 u16 coeff_b = (*csc_coeff)[1][i];
 910                 u16 coeff_c = (*csc_coeff)[2][i];
 911
 912                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 913                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 914                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 915                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 916                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 917                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 918         }
 919
 920         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 921                   HDMI_CSC_SCALE);
 922 }
 923
 924 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 925 {
 926         int color_depth = 0;
 927         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 928         int decimation = 0;
 929
 930         /* YCC422 interpolation to 444 mode */
 931         if (is_color_space_interpolation(hdmi))
 932                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 933         else if (is_color_space_decimation(hdmi))
 934                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 935
 936         if (hdmi->hdmi_data.enc_color_depth == 8)
 937                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 938         else if (hdmi->hdmi_data.enc_color_depth == 10)
 939                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 940         else if (hdmi->hdmi_data.enc_color_depth == 12)
 941                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 942         else if (hdmi->hdmi_data.enc_color_depth == 16)
 943                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 944         else
 945                 return;
 946
 947         /* Configure the CSC registers */
 948         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 949         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 950                   HDMI_CSC_SCALE);
 951
 952         dw_hdmi_update_csc_coeffs(hdmi);
 953 }
 954
 955 /*
 956  * HDMI video packetizer is used to packetize the data.
 957  * for example, if input is YCC422 mode or repeater is used,
 958  * data should be repacked this module can be bypassed.
 959  */
 960 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 961 {
 962         unsigned int color_depth = 0;
 963         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 964         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 965         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 966         u8 val, vp_conf;
 967
 968         if (hdmi_data->enc_out_format == RGB ||
 969             hdmi_data->enc_out_format == YCBCR444 ||
 970             hdmi_data->enc_out_format == YCBCR420) {
 971                 if (!hdmi_data->enc_color_depth) {
 972                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 973                 } else if (hdmi_data->enc_color_depth == 8) {
 974                         color_depth = 0;
 975                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 976                 } else if (hdmi_data->enc_color_depth == 10) {
 977                         color_depth = 5;
 978                 } else if (hdmi_data->enc_color_depth == 12) {
 979                         color_depth = 6;
 980                 } else if (hdmi_data->enc_color_depth == 16) {
 981                         color_depth = 7;
 982                 } else {
 983                         return;
 984                 }
 985         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 986                 if (!hdmi_data->enc_color_depth ||
 987                     hdmi_data->enc_color_depth == 8)
 988                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 989                 else if (hdmi_data->enc_color_depth == 10)
 990                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 991                 else if (hdmi_data->enc_color_depth == 12)
 992                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 993                 else
 994                         return;
 995                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 996         } else {
 997                 return;
 998         }
 999
1000         /* set the packetizer registers */
1001         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1002                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1003                 ((hdmi_data->pix_repet_factor <<
1004                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1005                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1006         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1007
1008         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1009                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1010
1011         /* Data from pixel repeater block */
1012         if (hdmi_data->pix_repet_factor > 0) {
1013                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1014                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1015         } else { /* data from packetizer block */
1016                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1017                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1018         }
1019
1020         hdmi_modb(hdmi, vp_conf,
1021                   HDMI_VP_CONF_PR_EN_MASK |
1022                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1023
1024         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1025                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1026
1027         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1028
1029         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1030                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1031                           HDMI_VP_CONF_PP_EN_ENABLE |
1032                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1033         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1034                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1035                           HDMI_VP_CONF_PP_EN_DISABLE |
1036                           HDMI_VP_CONF_YCC422_EN_ENABLE;
1037         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1038                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1039                           HDMI_VP_CONF_PP_EN_DISABLE |
1040                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1041         } else {
1042                 return;
1043         }
1044
1045         hdmi_modb(hdmi, vp_conf,
1046                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1047                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1048
1049         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1050                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1051                   HDMI_VP_STUFF_PP_STUFFING_MASK |
1052                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1053
1054         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1055                   HDMI_VP_CONF);
1056 }
1057
1058 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1059                                        unsigned char bit)
1060 {
1061         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1062                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1063 }
1064
1065 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
1066                                         unsigned char bit)
1067 {
1068         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
1069                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
1070 }
1071
1072 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
1073                                        unsigned char bit)
1074 {
1075         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
1076                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
1077 }
1078
1079 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
1080                                      unsigned char bit)
1081 {
1082         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
1083 }
1084
1085 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
1086                                       unsigned char bit)
1087 {
1088         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
1089 }
1090
1091 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1092 {
1093         u32 val;
1094
1095         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1096                 if (msec-- == 0)
1097                         return false;
1098                 udelay(1000);
1099         }
1100         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1101
1102         return true;
1103 }
1104
1105 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1106                                  unsigned char addr)
1107 {
1108         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1109         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1110         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1111                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1112         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1113                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1114         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1115                     HDMI_PHY_I2CM_OPERATION_ADDR);
1116         hdmi_phy_wait_i2c_done(hdmi, 1000);
1117 }
1118
1119 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1120                               unsigned char addr)
1121 {
1122         __hdmi_phy_i2c_write(hdmi, data, addr);
1123         return 0;
1124 }
1125
1126 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1127 {
1128         int val;
1129
1130         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1131         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1132         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1133         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1134         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1135                     HDMI_PHY_I2CM_OPERATION_ADDR);
1136         hdmi_phy_wait_i2c_done(hdmi, 1000);
1137         val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1138         val = (val & 0xff) << 8;
1139         val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1140         return val;
1141 }
1142
1143 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1144 {
1145         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1146                          HDMI_PHY_CONF0_PDZ_OFFSET,
1147                          HDMI_PHY_CONF0_PDZ_MASK);
1148 }
1149
1150 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1151 {
1152         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1153                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1154                          HDMI_PHY_CONF0_ENTMDS_MASK);
1155 }
1156
1157 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1158 {
1159         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1160                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1161                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1162 }
1163
1164 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1165 {
1166         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1167                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1168                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1169 }
1170
1171 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1172 {
1173         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1174                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1175                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1176 }
1177
1178 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1179 {
1180         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1181                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1182                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1183 }
1184
1185 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1186 {
1187         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1188                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1189                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1190 }
1191
1192 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1193                               unsigned char res, int cscon)
1194 {
1195         unsigned res_idx;
1196         u8 val, msec, tmds_cfg;
1197         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1198         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1199         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1200         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1201
1202         if (prep)
1203                 return -EINVAL;
1204
1205         switch (res) {
1206         case 0: /* color resolution 0 is 8 bit colour depth */
1207         case 8:
1208                 res_idx = DW_HDMI_RES_8;
1209                 break;
1210         case 10:
1211                 res_idx = DW_HDMI_RES_10;
1212                 break;
1213         case 12:
1214                 res_idx = DW_HDMI_RES_12;
1215                 break;
1216         default:
1217                 return -EINVAL;
1218         }
1219
1220         /* PLL/MPLL Cfg - always match on final entry */
1221         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1222                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1223                     mpll_config->mpixelclock)
1224                         break;
1225
1226         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1227                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1228                     curr_ctrl->mpixelclock)
1229                         break;
1230
1231         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1232                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1233                     phy_config->mpixelclock)
1234                         break;
1235
1236         if (mpll_config->mpixelclock == ~0UL ||
1237             curr_ctrl->mpixelclock == ~0UL ||
1238             phy_config->mpixelclock == ~0UL) {
1239                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1240                         hdmi->hdmi_data.video_mode.mpixelclock);
1241                 return -EINVAL;
1242         }
1243
1244         /* Enable csc path */
1245         if (cscon)
1246                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1247         else
1248                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1249
1250         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1251
1252         /* gen2 tx power off */
1253         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1254
1255         /* gen2 pddq */
1256         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1257
1258         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1259         if (hdmi->connector.scdc_present) {
1260                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1261                 if (mpll_config->mpixelclock > 340000000)
1262                         tmds_cfg |= 2;
1263                 else
1264                         tmds_cfg &= 0x1;
1265                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1266         }
1267
1268         /* PHY reset */
1269         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1270         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1271
1272         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1273
1274         hdmi_phy_test_clear(hdmi, 1);
1275         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1276                     HDMI_PHY_I2CM_SLAVE_ADDR);
1277         hdmi_phy_test_clear(hdmi, 0);
1278         /*
1279          * RK3399 mpll clock source is vpll, also is vop clock source.
1280          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1281          * to enable mpll pre-divider.
1282          */
1283         if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1284             hdmi->dev_type == RK3399_HDMI)
1285                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1286                                    0x06);
1287         else
1288                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1289         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1290
1291         /* CURRCTRL */
1292         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1293
1294         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1295         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1296
1297         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1298         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1299         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1300
1301         /* REMOVE CLK TERM */
1302         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1303
1304         dw_hdmi_phy_enable_powerdown(hdmi, false);
1305
1306         /* toggle TMDS disable */
1307         dw_hdmi_phy_enable_tmds(hdmi, 0);
1308
1309         /* Wait for resuming transmission of TMDS clock and data */
1310         if (mpll_config->mpixelclock > 340000000)
1311                 msleep(100);
1312
1313         /* toggle TMDS enable */
1314         dw_hdmi_phy_enable_tmds(hdmi, 1);
1315
1316         /* gen2 tx power on */
1317         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1318         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1319
1320         if (is_rockchip(hdmi->dev_type))
1321                 dw_hdmi_phy_enable_spare(hdmi, 1);
1322
1323         /* Wait for PHY PLL lock */
1324         msec = 5;
1325         do {
1326                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1327                 if (!val)
1328                         break;
1329
1330                 if (msec == 0) {
1331                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1332                         return -ETIMEDOUT;
1333                 }
1334
1335                 udelay(1000);
1336                 msec--;
1337         } while (1);
1338
1339         return 0;
1340 }
1341
1342 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1343 {
1344         int i, ret;
1345         bool cscon;
1346
1347         /*check csc whether needed activated in HDMI mode */
1348         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1349
1350         /* HDMI Phy spec says to do the phy initialization sequence twice */
1351         for (i = 0; i < 2; i++) {
1352                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1353                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1354                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1355                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1356
1357                 /* Enable CSC */
1358                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1359                 if (ret)
1360                         return ret;
1361         }
1362
1363         hdmi->phy_enabled = true;
1364         return 0;
1365 }
1366
1367 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1368 {
1369         u8 de;
1370
1371         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1372                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1373         else
1374                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1375
1376         /* disable rx detect */
1377         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1378                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1379
1380         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1381
1382         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1383                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1384 }
1385
1386 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1387 {
1388         struct hdmi_avi_infoframe frame;
1389         u8 val;
1390         bool is_hdmi2 = false;
1391
1392         if ((mode->flags & DRM_MODE_FLAG_420_MASK) ||
1393             hdmi->connector.scdc_present)
1394                 is_hdmi2 = true;
1395         /* Initialise info frame from DRM mode */
1396         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1397
1398         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1399                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1400         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1401                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1402         else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1403                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1404         else
1405                 frame.colorspace = HDMI_COLORSPACE_RGB;
1406
1407         /* Set up colorimetry */
1408         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1409                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1410                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1411                         frame.extended_colorimetry =
1412                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1413                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1414                         frame.extended_colorimetry =
1415                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1416         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1417                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1418                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1419         } else { /* Carries no data */
1420                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1421                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1422         }
1423
1424         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1425
1426         /*
1427          * The Designware IP uses a different byte format from standard
1428          * AVI info frames, though generally the bits are in the correct
1429          * bytes.
1430          */
1431
1432         /*
1433          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1434          * 5,6,7, active aspect present in bit 6 rather than 4.
1435          */
1436         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1437         if (frame.active_aspect & 15)
1438                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1439         if (frame.top_bar || frame.bottom_bar)
1440                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1441         if (frame.left_bar || frame.right_bar)
1442                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1443         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1444
1445         /* AVI data byte 2 differences: none */
1446         val = ((frame.colorimetry & 0x3) << 6) |
1447               ((frame.picture_aspect & 0x3) << 4) |
1448               (frame.active_aspect & 0xf);
1449         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1450
1451         /* AVI data byte 3 differences: none */
1452         val = ((frame.extended_colorimetry & 0x7) << 4) |
1453               ((frame.quantization_range & 0x3) << 2) |
1454               (frame.nups & 0x3);
1455         if (frame.itc)
1456                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1457         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1458
1459         /* AVI data byte 4 differences: none */
1460         val = frame.video_code & 0x7f;
1461         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1462
1463         /* AVI Data Byte 5- set up input and output pixel repetition */
1464         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1465                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1466                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1467                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1468                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1469                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1470         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1471
1472         /*
1473          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1474          * ycc range in bits 2,3 rather than 6,7
1475          */
1476         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1477               (frame.content_type & 0x3);
1478         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1479
1480         /* AVI Data Bytes 6-13 */
1481         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1482         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1483         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1484         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1485         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1486         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1487         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1488         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1489 }
1490
1491 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1492                                                  struct drm_display_mode *mode)
1493 {
1494         struct hdmi_vendor_infoframe frame;
1495         u8 buffer[10];
1496         ssize_t err;
1497
1498         /* Disable HDMI vendor specific infoframe send */
1499         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1500                         HDMI_FC_DATAUTO0_VSD_MASK);
1501
1502         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1503         if (err < 0)
1504                 /*
1505                  * Going into that statement does not means vendor infoframe
1506                  * fails. It just informed us that vendor infoframe is not
1507                  * needed for the selected mode. Only 4k or stereoscopic 3D
1508                  * mode requires vendor infoframe. So just simply return.
1509                  */
1510                 return;
1511
1512         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1513         if (err < 0) {
1514                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1515                         err);
1516                 return;
1517         }
1518
1519         /* Set the length of HDMI vendor specific InfoFrame payload */
1520         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1521
1522         /* Set 24bit IEEE Registration Identifier */
1523         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1524         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1525         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1526
1527         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1528         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1529         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1530
1531         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1532                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1533
1534         /* Packet frame interpolation */
1535         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1536
1537         /* Auto packets per frame and line spacing */
1538         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1539
1540         /* Configures the Frame Composer On RDRB mode */
1541         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1542                         HDMI_FC_DATAUTO0_VSD_MASK);
1543 }
1544
1545 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1546                              const struct drm_display_mode *mode)
1547 {
1548         u8 inv_val, bytes;
1549         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1550         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1551         unsigned int hdisplay, vdisplay;
1552
1553         vmode->mpixelclock = mode->crtc_clock * 1000;
1554         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1555                 vmode->mpixelclock /= 2;
1556         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1557                 DRM_MODE_FLAG_3D_FRAME_PACKING)
1558                 vmode->mpixelclock *= 2;
1559         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1560
1561         /* Set up HDMI_FC_INVIDCONF
1562          * fc_invidconf.HDCP_keepout must be set (1'b1)
1563          * when activate the scrambler feature.
1564          */
1565         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1566                    vmode->mpixelclock > 340000000 ||
1567                    hdmi->connector.lte_340mcsc_scramble ?
1568                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1569                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1570
1571         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1572                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1573                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1574
1575         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1576                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1577                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1578
1579         inv_val |= (vmode->mdataenablepolarity ?
1580                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1581                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1582
1583         if (hdmi->vic == 39)
1584                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1585         else
1586                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1587                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1588                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1589
1590         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1591                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1592                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1593
1594         inv_val |= hdmi->sink_is_hdmi ?
1595                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1596                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1597
1598         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1599
1600         hdisplay = mode->hdisplay;
1601         hblank = mode->htotal - mode->hdisplay;
1602         h_de_hs = mode->hsync_start - mode->hdisplay;
1603         hsync_len = mode->hsync_end - mode->hsync_start;
1604
1605         /*
1606          * When we're setting a YCbCr420 mode, we need
1607          * to adjust the horizontal timing to suit.
1608          */
1609         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1610                 hdisplay /= 2;
1611                 hblank /= 2;
1612                 h_de_hs /= 2;
1613                 hsync_len /= 2;
1614         }
1615
1616         vdisplay = mode->vdisplay;
1617         vblank = mode->vtotal - mode->vdisplay;
1618         v_de_vs = mode->vsync_start - mode->vdisplay;
1619         vsync_len = mode->vsync_end - mode->vsync_start;
1620
1621         /*
1622          * When we're setting an interlaced mode, we need
1623          * to adjust the vertical timing to suit.
1624          */
1625         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1626                 vdisplay /= 2;
1627                 vblank /= 2;
1628                 v_de_vs /= 2;
1629                 vsync_len /= 2;
1630         } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1631                 DRM_MODE_FLAG_3D_FRAME_PACKING) {
1632                 vdisplay += mode->vtotal;
1633         }
1634
1635         /* Scrambling Control */
1636         if (hdmi->connector.scdc_present) {
1637                 if (vmode->mpixelclock > 340000000 ||
1638                     hdmi->connector.lte_340mcsc_scramble) {
1639                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1640                                        &bytes);
1641                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1642                                         bytes);
1643                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1644                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1645                                     HDMI_MC_SWRSTZ);
1646                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1647                 } else {
1648                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1649                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1650                                     HDMI_MC_SWRSTZ);
1651                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1652                 }
1653         }
1654
1655         /* Set up horizontal active pixel width */
1656         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1657         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1658
1659         /* Set up vertical active lines */
1660         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1661         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1662
1663         /* Set up horizontal blanking pixel region width */
1664         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1665         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1666
1667         /* Set up vertical blanking pixel region width */
1668         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1669
1670         /* Set up HSYNC active edge delay width (in pixel clks) */
1671         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1672         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1673
1674         /* Set up VSYNC active edge delay (in lines) */
1675         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1676
1677         /* Set up HSYNC active pulse width (in pixel clks) */
1678         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1679         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1680
1681         /* Set up VSYNC active edge delay (in lines) */
1682         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1683 }
1684
1685 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1686 {
1687         if (!hdmi->phy_enabled)
1688                 return;
1689
1690         dw_hdmi_phy_enable_tmds(hdmi, 0);
1691         dw_hdmi_phy_enable_powerdown(hdmi, true);
1692
1693         hdmi->phy_enabled = false;
1694 }
1695
1696 /* HDMI Initialization Step B.4 */
1697 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1698 {
1699         u8 clkdis;
1700
1701         /* control period minimum duration */
1702         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1703         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1704         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1705
1706         /* Set to fill TMDS data channels */
1707         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1708         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1709         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1710
1711         /* Enable pixel clock and tmds data path */
1712         clkdis = 0x7F;
1713         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1714         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1715
1716         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1717         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1718
1719         /* Enable csc path */
1720         if (is_color_space_conversion(hdmi)) {
1721                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1722                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1723         }
1724
1725         /* Enable pixel repetition path */
1726         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1727                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1728                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1729         }
1730 }
1731
1732 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1733 {
1734         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1735 }
1736
1737 /* Workaround to clear the overflow condition */
1738 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1739 {
1740         int count;
1741         u8 val;
1742
1743         /* TMDS software reset */
1744         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1745
1746         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1747         if (hdmi->dev_type == IMX6DL_HDMI) {
1748                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1749                 return;
1750         }
1751
1752         for (count = 0; count < 4; count++)
1753                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1754 }
1755
1756 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1757 {
1758         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1759         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1760 }
1761
1762 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1763 {
1764         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1765                     HDMI_IH_MUTE_FC_STAT2);
1766 }
1767
1768 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1769 {
1770         int ret;
1771
1772         hdmi_disable_overflow_interrupts(hdmi);
1773
1774         hdmi->vic = drm_match_cea_mode(mode);
1775
1776         if (!hdmi->vic) {
1777                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1778         } else {
1779                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1780         }
1781
1782         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1783             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1784             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1785             (hdmi->vic == 17) || (hdmi->vic == 18))
1786                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1787         else
1788                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1789
1790         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1791                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1792                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1793         } else {
1794                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1795                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1796         }
1797         /* TODO: Get input format from IPU (via FB driver interface) */
1798         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1799                 hdmi->hdmi_data.enc_in_format = YCBCR420;
1800                 hdmi->hdmi_data.enc_out_format = YCBCR420;
1801         } else {
1802                 hdmi->hdmi_data.enc_in_format = RGB;
1803                 hdmi->hdmi_data.enc_out_format = RGB;
1804         }
1805         hdmi->hdmi_data.enc_color_depth = 8;
1806         /*
1807          * According to the dw-hdmi specification 6.4.2
1808          * vp_pr_cd[3:0]:
1809          * 0000b: No pixel repetition (pixel sent only once)
1810          * 0001b: Pixel sent two times (pixel repeated once)
1811          */
1812         hdmi->hdmi_data.pix_repet_factor =
1813                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1814         hdmi->hdmi_data.hdcp_enable = 0;
1815         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1816
1817         /* HDMI Initialization Step B.1 */
1818         hdmi_av_composer(hdmi, mode);
1819
1820         /* HDMI Initializateion Step B.2 */
1821         ret = dw_hdmi_phy_init(hdmi);
1822         if (ret)
1823                 return ret;
1824
1825         /* HDMI Initialization Step B.3 */
1826         dw_hdmi_enable_video_path(hdmi);
1827
1828         if (hdmi->sink_has_audio) {
1829                 dev_dbg(hdmi->dev, "sink has audio support\n");
1830
1831                 /* HDMI Initialization Step E - Configure audio */
1832                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1833                 hdmi_enable_audio_clk(hdmi);
1834         }
1835
1836         /* not for DVI mode */
1837         if (hdmi->sink_is_hdmi) {
1838                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1839
1840                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1841                 hdmi_config_AVI(hdmi, mode);
1842                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1843         } else {
1844                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1845         }
1846
1847         hdmi_video_packetize(hdmi);
1848         hdmi_video_csc(hdmi);
1849         hdmi_video_sample(hdmi);
1850         hdmi_tx_hdcp_config(hdmi);
1851
1852         dw_hdmi_clear_overflow(hdmi);
1853         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1854                 hdmi_enable_overflow_interrupts(hdmi);
1855
1856         return 0;
1857 }
1858
1859 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1860 {
1861         u8 ih_mute;
1862
1863         /*
1864          * Boot up defaults are:
1865          * HDMI_IH_MUTE   = 0x03 (disabled)
1866          * HDMI_IH_MUTE_* = 0x00 (enabled)
1867          *
1868          * Disable top level interrupt bits in HDMI block
1869          */
1870         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1871                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1872                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1873
1874         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1875
1876         /* by default mask all interrupts */
1877         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1878         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1879         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1880         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1881         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1882         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1883         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1884         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1885         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1886         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1887         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1888         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1889         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1890         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1891         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1892
1893         /* Disable interrupts in the IH_MUTE_* registers */
1894         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1895         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1896         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1897         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1898         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1899         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1900         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1901         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1902         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1903         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1904
1905         /* Enable top level interrupt bits in HDMI block */
1906         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1907                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1908         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1909 }
1910
1911 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1912 {
1913         hdmi->bridge_is_on = true;
1914         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1915 }
1916
1917 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1918 {
1919         dw_hdmi_phy_disable(hdmi);
1920         hdmi->bridge_is_on = false;
1921 }
1922
1923 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1924 {
1925         int force = hdmi->force;
1926
1927         if (hdmi->disabled) {
1928                 force = DRM_FORCE_OFF;
1929         } else if (force == DRM_FORCE_UNSPECIFIED) {
1930                 if (hdmi->rxsense)
1931                         force = DRM_FORCE_ON;
1932                 else
1933                         force = DRM_FORCE_OFF;
1934         }
1935
1936         if (force == DRM_FORCE_OFF) {
1937                 if (hdmi->bridge_is_on)
1938                         dw_hdmi_poweroff(hdmi);
1939         } else {
1940                 if (!hdmi->bridge_is_on)
1941                         dw_hdmi_poweron(hdmi);
1942         }
1943 }
1944
1945 /*
1946  * Adjust the detection of RXSENSE according to whether we have a forced
1947  * connection mode enabled, or whether we have been disabled.  There is
1948  * no point processing RXSENSE interrupts if we have a forced connection
1949  * state, or DRM has us disabled.
1950  *
1951  * We also disable rxsense interrupts when we think we're disconnected
1952  * to avoid floating TDMS signals giving false rxsense interrupts.
1953  *
1954  * Note: we still need to listen for HPD interrupts even when DRM has us
1955  * disabled so that we can detect a connect event.
1956  */
1957 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1958 {
1959         u8 old_mask = hdmi->phy_mask;
1960
1961         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1962                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1963         else
1964                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1965
1966         if (old_mask != hdmi->phy_mask)
1967                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1968 }
1969
1970 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1971                                     struct drm_display_mode *orig_mode,
1972                                     struct drm_display_mode *mode)
1973 {
1974         struct dw_hdmi *hdmi = bridge->driver_private;
1975
1976         mutex_lock(&hdmi->mutex);
1977
1978         /* Store the display mode for plugin/DKMS poweron events */
1979         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1980
1981         mutex_unlock(&hdmi->mutex);
1982 }
1983
1984 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1985 {
1986         struct dw_hdmi *hdmi = bridge->driver_private;
1987
1988         mutex_lock(&hdmi->mutex);
1989         hdmi->disabled = true;
1990         dw_hdmi_update_power(hdmi);
1991         dw_hdmi_update_phy_mask(hdmi);
1992         mutex_unlock(&hdmi->mutex);
1993 }
1994
1995 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1996 {
1997         struct dw_hdmi *hdmi = bridge->driver_private;
1998
1999         mutex_lock(&hdmi->mutex);
2000         hdmi->disabled = false;
2001         dw_hdmi_update_power(hdmi);
2002         dw_hdmi_update_phy_mask(hdmi);
2003         mutex_unlock(&hdmi->mutex);
2004 }
2005
2006 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
2007 {
2008         /* do nothing */
2009 }
2010
2011 static enum drm_connector_status
2012 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2013 {
2014         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2015                                              connector);
2016
2017         mutex_lock(&hdmi->mutex);
2018         hdmi->force = DRM_FORCE_UNSPECIFIED;
2019         dw_hdmi_update_power(hdmi);
2020         dw_hdmi_update_phy_mask(hdmi);
2021         mutex_unlock(&hdmi->mutex);
2022
2023         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
2024                 connector_status_connected : connector_status_disconnected;
2025 }
2026
2027 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2028 {
2029         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2030                                              connector);
2031         struct edid *edid;
2032         int ret = 0;
2033
2034         if (!hdmi->ddc)
2035                 return 0;
2036
2037         edid = drm_get_edid(connector, hdmi->ddc);
2038         if (edid) {
2039                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2040                         edid->width_cm, edid->height_cm);
2041
2042                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2043                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2044                 drm_mode_connector_update_edid_property(connector, edid);
2045                 ret = drm_add_edid_modes(connector, edid);
2046                 /* Store the ELD */
2047                 drm_edid_to_eld(connector, edid);
2048                 kfree(edid);
2049         } else {
2050                 dev_dbg(hdmi->dev, "failed to get edid\n");
2051         }
2052
2053         return ret;
2054 }
2055
2056 static enum drm_mode_status
2057 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
2058                              struct drm_display_mode *mode)
2059 {
2060         struct dw_hdmi *hdmi = container_of(connector,
2061                                            struct dw_hdmi, connector);
2062         enum drm_mode_status mode_status = MODE_OK;
2063
2064         if (hdmi->plat_data->mode_valid)
2065                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2066
2067         return mode_status;
2068 }
2069
2070 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
2071                                                            *connector)
2072 {
2073         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2074                                              connector);
2075
2076         return hdmi->encoder;
2077 }
2078
2079 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
2080 {
2081         drm_connector_unregister(connector);
2082         drm_connector_cleanup(connector);
2083 }
2084
2085 static void dw_hdmi_connector_force(struct drm_connector *connector)
2086 {
2087         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2088                                              connector);
2089
2090         mutex_lock(&hdmi->mutex);
2091         hdmi->force = connector->force;
2092         dw_hdmi_update_power(hdmi);
2093         dw_hdmi_update_phy_mask(hdmi);
2094         mutex_unlock(&hdmi->mutex);
2095 }
2096
2097 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2098         .dpms = drm_helper_connector_dpms,
2099         .fill_modes = drm_helper_probe_single_connector_modes,
2100         .detect = dw_hdmi_connector_detect,
2101         .destroy = dw_hdmi_connector_destroy,
2102         .force = dw_hdmi_connector_force,
2103 };
2104
2105 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
2106         .dpms = drm_atomic_helper_connector_dpms,
2107         .fill_modes = drm_helper_probe_single_connector_modes,
2108         .detect = dw_hdmi_connector_detect,
2109         .destroy = dw_hdmi_connector_destroy,
2110         .force = dw_hdmi_connector_force,
2111         .reset = drm_atomic_helper_connector_reset,
2112         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2113         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2114 };
2115
2116 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2117         .get_modes = dw_hdmi_connector_get_modes,
2118         .mode_valid = dw_hdmi_connector_mode_valid,
2119         .best_encoder = dw_hdmi_connector_best_encoder,
2120 };
2121
2122 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2123         .enable = dw_hdmi_bridge_enable,
2124         .disable = dw_hdmi_bridge_disable,
2125         .pre_enable = dw_hdmi_bridge_nop,
2126         .post_disable = dw_hdmi_bridge_nop,
2127         .mode_set = dw_hdmi_bridge_mode_set,
2128 };
2129
2130 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2131 {
2132         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2133         unsigned int stat;
2134
2135         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2136         if (!stat)
2137                 return IRQ_NONE;
2138
2139         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2140
2141         i2c->stat = stat;
2142
2143         complete(&i2c->cmp);
2144
2145         return IRQ_HANDLED;
2146 }
2147
2148 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2149 {
2150         struct dw_hdmi *hdmi = dev_id;
2151         u8 intr_stat;
2152         irqreturn_t ret = IRQ_NONE;
2153
2154         if (hdmi->i2c)
2155                 ret = dw_hdmi_i2c_irq(hdmi);
2156
2157         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2158         if (intr_stat) {
2159                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2160                 return IRQ_WAKE_THREAD;
2161         }
2162
2163         return ret;
2164 }
2165
2166 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2167 {
2168         struct dw_hdmi *hdmi = dev_id;
2169         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2170
2171         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2172         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2173         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2174
2175         phy_pol_mask = 0;
2176         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2177                 phy_pol_mask |= HDMI_PHY_HPD;
2178         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2179                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2180         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2181                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2182         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2183                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2184         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2185                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2186
2187         if (phy_pol_mask)
2188                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2189
2190         /*
2191          * RX sense tells us whether the TDMS transmitters are detecting
2192          * load - in other words, there's something listening on the
2193          * other end of the link.  Use this to decide whether we should
2194          * power on the phy as HPD may be toggled by the sink to merely
2195          * ask the source to re-read the EDID.
2196          */
2197         if (intr_stat &
2198             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2199                 mutex_lock(&hdmi->mutex);
2200                 if (!hdmi->bridge_is_on && !hdmi->force) {
2201                         /*
2202                          * If the RX sense status indicates we're disconnected,
2203                          * clear the software rxsense status.
2204                          */
2205                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2206                                 hdmi->rxsense = false;
2207
2208                         /*
2209                          * Only set the software rxsense status when both
2210                          * rxsense and hpd indicates we're connected.
2211                          * This avoids what seems to be bad behaviour in
2212                          * at least iMX6S versions of the phy.
2213                          */
2214                         if (phy_stat & HDMI_PHY_HPD)
2215                                 hdmi->rxsense = true;
2216
2217                         dw_hdmi_update_power(hdmi);
2218                         dw_hdmi_update_phy_mask(hdmi);
2219                 }
2220                 mutex_unlock(&hdmi->mutex);
2221         }
2222
2223         check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
2224
2225         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2226         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2227                     HDMI_IH_MUTE_PHY_STAT0);
2228
2229         return IRQ_HANDLED;
2230 }
2231
2232 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2233 {
2234         struct drm_encoder *encoder = hdmi->encoder;
2235         struct drm_bridge *bridge;
2236         int ret;
2237
2238         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2239         if (!bridge) {
2240                 DRM_ERROR("Failed to allocate drm bridge\n");
2241                 return -ENOMEM;
2242         }
2243
2244         hdmi->bridge = bridge;
2245         bridge->driver_private = hdmi;
2246         bridge->funcs = &dw_hdmi_bridge_funcs;
2247         ret = drm_bridge_attach(drm, bridge);
2248         if (ret) {
2249                 DRM_ERROR("Failed to initialize bridge with drm\n");
2250                 return -EINVAL;
2251         }
2252
2253         encoder->bridge = bridge;
2254         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2255         hdmi->connector.port = hdmi->dev->of_node;
2256
2257         drm_connector_helper_add(&hdmi->connector,
2258                                  &dw_hdmi_connector_helper_funcs);
2259
2260         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2261                 drm_connector_init(drm, &hdmi->connector,
2262                                    &dw_hdmi_atomic_connector_funcs,
2263                                    DRM_MODE_CONNECTOR_HDMIA);
2264         else
2265                 drm_connector_init(drm, &hdmi->connector,
2266                                    &dw_hdmi_connector_funcs,
2267                                    DRM_MODE_CONNECTOR_HDMIA);
2268
2269         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2270
2271         return 0;
2272 }
2273
2274 #include <linux/fs.h>
2275 #include <linux/debugfs.h>
2276 #include <linux/seq_file.h>
2277
2278 struct dw_hdmi_reg_table {
2279         int reg_base;
2280         int reg_end;
2281 };
2282
2283 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
2284         {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
2285         {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
2286         {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
2287         {HDMI_VP_STATUS, HDMI_VP_POL},
2288         {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
2289         {HDMI_PHY_CONF0, HDMI_PHY_POL0},
2290         {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
2291         {HDMI_AUD_CONF0, 0x3624},
2292         {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
2293         {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
2294         {HDMI_A_HDCPCFG0, 0x52bb},
2295         {0x7800, 0x7818},
2296         {0x7900, 0x790e},
2297         {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
2298         {HDMI_I2CM_SLAVE, 0x7e31},
2299 };
2300
2301 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
2302 {
2303         struct dw_hdmi *hdmi = s->private;
2304         u32 i = 0, j = 0, val = 0;
2305
2306         seq_puts(s, "\n>>>hdmi_ctl reg ");
2307         for (i = 0; i < 16; i++)
2308                 seq_printf(s, " %2x", i);
2309         seq_puts(s, "\n---------------------------------------------------");
2310
2311         for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
2312                 for (j = hdmi_reg_table[i].reg_base;
2313                      j <= hdmi_reg_table[i].reg_end; j++) {
2314                         val = hdmi_readb(hdmi, j);
2315                         if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
2316                                 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
2317                         seq_printf(s, " %02x", val);
2318                 }
2319         }
2320         seq_puts(s, "\n---------------------------------------------------\n");
2321
2322         return 0;
2323 }
2324
2325 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
2326 {
2327         return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
2328 }
2329
2330 static ssize_t
2331 dw_hdmi_ctrl_write(struct file *file, const char __user *buf,
2332                    size_t count, loff_t *ppos)
2333 {
2334         struct dw_hdmi *hdmi =
2335                 ((struct seq_file *)file->private_data)->private;
2336         u32 reg, val;
2337         char kbuf[25];
2338
2339         if (copy_from_user(kbuf, buf, count))
2340                 return -EFAULT;
2341         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2342                 return -EFAULT;
2343         if ((reg < 0) || (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR)) {
2344                 dev_err(hdmi->dev, "it is no a hdmi register\n");
2345                 return count;
2346         }
2347         dev_info(hdmi->dev, "/**********hdmi register config******/");
2348         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2349         hdmi_writeb(hdmi, val, reg);
2350         return count;
2351 }
2352
2353 static const struct file_operations dw_hdmi_ctrl_fops = {
2354         .owner = THIS_MODULE,
2355         .open = dw_hdmi_ctrl_open,
2356         .read = seq_read,
2357         .write = dw_hdmi_ctrl_write,
2358         .llseek = seq_lseek,
2359         .release = single_release,
2360 };
2361
2362 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
2363 {
2364         struct dw_hdmi *hdmi = s->private;
2365         u32 i;
2366
2367         seq_puts(s, "\n>>>hdmi_phy reg ");
2368         for (i = 0; i < 0x28; i++)
2369                 seq_printf(s, "regs %02x val %04x\n",
2370                            i, hdmi_phy_i2c_read(hdmi, i));
2371         return 0;
2372 }
2373
2374 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
2375 {
2376         return single_open(file, dw_hdmi_phy_show, inode->i_private);
2377 }
2378
2379 static ssize_t
2380 dw_hdmi_phy_write(struct file *file, const char __user *buf,
2381                   size_t count, loff_t *ppos)
2382 {
2383         struct dw_hdmi *hdmi =
2384                 ((struct seq_file *)file->private_data)->private;
2385         u32 reg, val;
2386         char kbuf[25];
2387
2388         if (copy_from_user(kbuf, buf, count))
2389                 return -EFAULT;
2390         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2391                 return -EFAULT;
2392         if ((reg < 0) || (reg > 0x28)) {
2393                 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
2394                 return count;
2395         }
2396         dev_info(hdmi->dev, "/*******hdmi phy register config******/");
2397         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2398         hdmi_phy_i2c_write(hdmi, val, reg);
2399         return count;
2400 }
2401
2402 static const struct file_operations dw_hdmi_phy_fops = {
2403         .owner = THIS_MODULE,
2404         .open = dw_hdmi_phy_open,
2405         .read = seq_read,
2406         .write = dw_hdmi_phy_write,
2407         .llseek = seq_lseek,
2408         .release = single_release,
2409 };
2410
2411 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
2412 {
2413         struct dentry *debugfs_dir;
2414
2415         debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
2416         if (IS_ERR(debugfs_dir)) {
2417                 dev_err(dev, "failed to create debugfs dir!\n");
2418                 return;
2419         }
2420         debugfs_create_file("ctrl", 0400, debugfs_dir,
2421                             hdmi, &dw_hdmi_ctrl_fops);
2422         debugfs_create_file("phy", 0400, debugfs_dir,
2423                             hdmi, &dw_hdmi_phy_fops);
2424 }
2425
2426 int dw_hdmi_bind(struct device *dev, struct device *master,
2427                  void *data, struct drm_encoder *encoder,
2428                  struct resource *iores, int irq,
2429                  const struct dw_hdmi_plat_data *plat_data)
2430 {
2431         struct drm_device *drm = data;
2432         struct device_node *np = dev->of_node;
2433         struct platform_device_info pdevinfo;
2434         struct device_node *ddc_node;
2435         struct dw_hdmi *hdmi;
2436         int ret;
2437         u32 val = 1;
2438         u8 config0;
2439         u8 config1;
2440
2441         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2442         if (!hdmi)
2443                 return -ENOMEM;
2444
2445         hdmi->connector.interlace_allowed = 1;
2446         hdmi->connector.stereo_allowed = 1;
2447
2448         hdmi->plat_data = plat_data;
2449         hdmi->dev = dev;
2450         hdmi->dev_type = plat_data->dev_type;
2451         hdmi->sample_rate = 48000;
2452         hdmi->encoder = encoder;
2453         hdmi->disabled = true;
2454         hdmi->rxsense = true;
2455         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2456         hdmi->irq = irq;
2457
2458         mutex_init(&hdmi->mutex);
2459         mutex_init(&hdmi->audio_mutex);
2460         spin_lock_init(&hdmi->audio_lock);
2461
2462         of_property_read_u32(np, "reg-io-width", &val);
2463
2464         switch (val) {
2465         case 4:
2466                 hdmi->write = dw_hdmi_writel;
2467                 hdmi->read = dw_hdmi_readl;
2468                 break;
2469         case 1:
2470                 hdmi->write = dw_hdmi_writeb;
2471                 hdmi->read = dw_hdmi_readb;
2472                 break;
2473         default:
2474                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2475                 return -EINVAL;
2476         }
2477
2478         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2479         if (ddc_node) {
2480                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2481                 of_node_put(ddc_node);
2482                 if (!hdmi->ddc) {
2483                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2484                         return -EPROBE_DEFER;
2485                 }
2486
2487         } else {
2488                 dev_dbg(hdmi->dev, "no ddc property found\n");
2489         }
2490
2491         /* If DDC bus is not specified, try to register HDMI I2C bus */
2492         if (!hdmi->ddc) {
2493                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2494                 if (IS_ERR(hdmi->ddc))
2495                         hdmi->ddc = NULL;
2496                 /*
2497                  * Read high and low time from device tree. If not available use
2498                  * the default timing scl clock rate is about 99.6KHz.
2499                  */
2500                 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2501                                          &hdmi->i2c->scl_high_ns))
2502                         hdmi->i2c->scl_high_ns = 4708;
2503                 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2504                                          &hdmi->i2c->scl_low_ns))
2505                         hdmi->i2c->scl_low_ns = 4916;
2506         }
2507
2508         hdmi->regs = devm_ioremap_resource(dev, iores);
2509         if (IS_ERR(hdmi->regs))
2510                 return PTR_ERR(hdmi->regs);
2511
2512         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2513         if (IS_ERR(hdmi->isfr_clk)) {
2514                 ret = PTR_ERR(hdmi->isfr_clk);
2515                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2516                 return ret;
2517         }
2518
2519         ret = clk_prepare_enable(hdmi->isfr_clk);
2520         if (ret) {
2521                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2522                 return ret;
2523         }
2524
2525         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2526         if (IS_ERR(hdmi->iahb_clk)) {
2527                 ret = PTR_ERR(hdmi->iahb_clk);
2528                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2529                 goto err_isfr;
2530         }
2531
2532         ret = clk_prepare_enable(hdmi->iahb_clk);
2533         if (ret) {
2534                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2535                 goto err_isfr;
2536         }
2537
2538         /* Product and revision IDs */
2539         dev_info(dev,
2540                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2541                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2542                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2543                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2544                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2545
2546         init_hpd_work(hdmi);
2547         initialize_hdmi_ih_mutes(hdmi);
2548
2549         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2550                                         dw_hdmi_irq, IRQF_SHARED,
2551                                         dev_name(dev), hdmi);
2552         if (ret)
2553                 goto err_iahb;
2554
2555         /*
2556          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2557          * N and cts values before enabling phy
2558          */
2559         hdmi_init_clk_regenerator(hdmi);
2560
2561         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2562                     HDMI_PHY_I2CM_INT_ADDR);
2563
2564         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2565                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2566                     HDMI_PHY_I2CM_CTLINT_ADDR);
2567
2568         /* Re-init HPD polarity */
2569         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2570
2571         /* Unmask HPD, clear transitory interrupts, then unmute */
2572         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2573
2574         ret = dw_hdmi_register(drm, hdmi);
2575         if (ret)
2576                 goto err_iahb;
2577
2578 #ifdef CONFIG_SWITCH
2579         hdmi->switchdev.name = "hdmi";
2580         switch_dev_register(&hdmi->switchdev);
2581 #endif
2582
2583         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2584                     HDMI_IH_MUTE_PHY_STAT0);
2585
2586         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2587         if (hdmi->i2c)
2588                 dw_hdmi_i2c_init(hdmi);
2589
2590         memset(&pdevinfo, 0, sizeof(pdevinfo));
2591         pdevinfo.parent = dev;
2592         pdevinfo.id = PLATFORM_DEVID_AUTO;
2593
2594         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2595         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2596
2597         if (config1 & HDMI_CONFIG1_AHB) {
2598                 struct dw_hdmi_audio_data audio;
2599
2600                 audio.phys = iores->start;
2601                 audio.base = hdmi->regs;
2602                 audio.irq = irq;
2603                 audio.hdmi = hdmi;
2604                 audio.eld = hdmi->connector.eld;
2605
2606                 pdevinfo.name = "dw-hdmi-ahb-audio";
2607                 pdevinfo.data = &audio;
2608                 pdevinfo.size_data = sizeof(audio);
2609                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2610                 hdmi->audio = platform_device_register_full(&pdevinfo);
2611         } else if (config0 & HDMI_CONFIG0_I2S) {
2612                 struct dw_hdmi_i2s_audio_data audio;
2613
2614                 audio.hdmi      = hdmi;
2615                 audio.write     = hdmi_writeb;
2616                 audio.read      = hdmi_readb;
2617                 audio.mod       = hdmi_modb;
2618
2619                 pdevinfo.name = "dw-hdmi-i2s-audio";
2620                 pdevinfo.data = &audio;
2621                 pdevinfo.size_data = sizeof(audio);
2622                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2623                 hdmi->audio = platform_device_register_full(&pdevinfo);
2624         }
2625
2626         dev_set_drvdata(dev, hdmi);
2627
2628         dw_hdmi_register_debugfs(dev, hdmi);
2629
2630         return 0;
2631
2632 err_iahb:
2633         if (hdmi->i2c)
2634                 i2c_del_adapter(&hdmi->i2c->adap);
2635
2636         clk_disable_unprepare(hdmi->iahb_clk);
2637 err_isfr:
2638         clk_disable_unprepare(hdmi->isfr_clk);
2639
2640         return ret;
2641 }
2642 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2643
2644 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2645 {
2646         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2647
2648         if (hdmi->audio && !IS_ERR(hdmi->audio))
2649                 platform_device_unregister(hdmi->audio);
2650
2651         /* Disable all interrupts */
2652         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2653
2654 #ifdef CONFIG_SWITCH
2655         switch_dev_unregister(&hdmi->switchdev);
2656 #endif
2657         hdmi->connector.funcs->destroy(&hdmi->connector);
2658         hdmi->encoder->funcs->destroy(hdmi->encoder);
2659
2660         clk_disable_unprepare(hdmi->iahb_clk);
2661         clk_disable_unprepare(hdmi->isfr_clk);
2662
2663         if (hdmi->i2c)
2664                 i2c_del_adapter(&hdmi->i2c->adap);
2665         else
2666                 i2c_put_adapter(hdmi->ddc);
2667 }
2668 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2669
2670 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2671 {
2672         if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2673                 initialize_hdmi_ih_mutes(hdmi);
2674                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2675                             HDMI_PHY_I2CM_INT_ADDR);
2676
2677                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2678                             HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2679                             HDMI_PHY_I2CM_CTLINT_ADDR);
2680
2681                 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2682                             HDMI_PHY_POL0);
2683                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2684                 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2685                             HDMI_IH_PHY_STAT0_RX_SENSE),
2686                             HDMI_IH_MUTE_PHY_STAT0);
2687         }
2688 }
2689
2690 void dw_hdmi_suspend(struct device *dev)
2691 {
2692         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2693
2694         mutex_lock(&hdmi->mutex);
2695         if (hdmi->irq)
2696                 disable_irq(hdmi->irq);
2697         mutex_unlock(&hdmi->mutex);
2698 }
2699 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2700
2701 void dw_hdmi_resume(struct device *dev)
2702 {
2703         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2704
2705         mutex_lock(&hdmi->mutex);
2706         dw_hdmi_reg_initial(hdmi);
2707         if (hdmi->i2c)
2708                 dw_hdmi_i2c_init(hdmi);
2709         if (hdmi->irq)
2710                 enable_irq(hdmi->irq);
2711         mutex_unlock(&hdmi->mutex);
2712 }
2713 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2714
2715 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2716 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2717 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2718 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2719 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2720 MODULE_LICENSE("GPL");
2721 MODULE_ALIAS("platform:dw-hdmi");