drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include "dw-hdmi.h"
  39 #include "dw-hdmi-audio.h"
  40
  41 #define HDMI_EDID_LEN           512
  42 #define DDC_SEGMENT_ADDR       0x30
  43
  44 #define RGB                     0
  45 #define YCBCR444                1
  46 #define YCBCR422_16BITS         2
  47 #define YCBCR422_8BITS          3
  48 #define XVYCC444                4
  49 #define YCBCR420                5
  50
  51 enum hdmi_datamap {
  52         RGB444_8B = 0x01,
  53         RGB444_10B = 0x03,
  54         RGB444_12B = 0x05,
  55         RGB444_16B = 0x07,
  56         YCbCr444_8B = 0x09,
  57         YCbCr444_10B = 0x0B,
  58         YCbCr444_12B = 0x0D,
  59         YCbCr444_16B = 0x0F,
  60         YCbCr422_8B = 0x16,
  61         YCbCr422_10B = 0x14,
  62         YCbCr422_12B = 0x12,
  63 };
  64
  65 /*
  66  * Unless otherwise noted, entries in this table are 100% optimization.
  67  * Values can be obtained from hdmi_compute_n() but that function is
  68  * slow so we pre-compute values we expect to see.
  69  *
  70  * All 32k and 48k values are expected to be the same (due to the way
  71  * the math works) for any rate that's an exact kHz.
  72  */
  73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  74         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  75         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  76         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  77         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  78         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  79         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  80         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  81         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  82         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  83         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  84         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  85         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  86         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  87         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  88         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  89         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  90         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  91         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  92         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  93         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  94         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  95         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  96         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  97         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  98         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  99         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 100         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
 101         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
 102         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 103         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 104         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 105         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 106         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 107         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 108         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 109         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 110         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 111
 112         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 113         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 114         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 115
 116         /* End of table */
 117         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 118 };
 119
 120
 121 static const u16 csc_coeff_default[3][4] = {
 122         { 0x2000, 0x0000, 0x0000, 0x0000 },
 123         { 0x0000, 0x2000, 0x0000, 0x0000 },
 124         { 0x0000, 0x0000, 0x2000, 0x0000 }
 125 };
 126
 127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 128         { 0x2000, 0x6926, 0x74fd, 0x010e },
 129         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 130         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 131 };
 132
 133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 134         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 135         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 136         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 137 };
 138
 139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 140         { 0x2591, 0x1322, 0x074b, 0x0000 },
 141         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 142         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 143 };
 144
 145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 146         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 147         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 148         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 149 };
 150
 151 struct hdmi_vmode {
 152         bool mdataenablepolarity;
 153
 154         unsigned int mpixelclock;
 155         unsigned int mpixelrepetitioninput;
 156         unsigned int mpixelrepetitionoutput;
 157 };
 158
 159 struct hdmi_data_info {
 160         unsigned int enc_in_format;
 161         unsigned int enc_out_format;
 162         unsigned int enc_color_depth;
 163         unsigned int colorimetry;
 164         unsigned int pix_repet_factor;
 165         unsigned int hdcp_enable;
 166         struct hdmi_vmode video_mode;
 167 };
 168
 169 struct dw_hdmi_i2c {
 170         struct i2c_adapter      adap;
 171
 172         struct mutex            lock;
 173         struct completion       cmp;
 174         u8                      stat;
 175
 176         u8                      slave_reg;
 177         bool                    is_regaddr;
 178         bool                    is_segment;
 179
 180         unsigned int            scl_high_ns;
 181         unsigned int            scl_low_ns;
 182 };
 183
 184 struct dw_hdmi {
 185         struct drm_connector connector;
 186         struct drm_encoder *encoder;
 187         struct drm_bridge *bridge;
 188
 189         struct platform_device *audio;
 190         enum dw_hdmi_devtype dev_type;
 191         struct device *dev;
 192         struct clk *isfr_clk;
 193         struct clk *iahb_clk;
 194         struct dw_hdmi_i2c *i2c;
 195
 196         struct hdmi_data_info hdmi_data;
 197         const struct dw_hdmi_plat_data *plat_data;
 198
 199         int vic;
 200
 201         u8 edid[HDMI_EDID_LEN];
 202         bool cable_plugin;
 203
 204         bool phy_enabled;
 205         struct drm_display_mode previous_mode;
 206
 207         struct i2c_adapter *ddc;
 208         void __iomem *regs;
 209         bool sink_is_hdmi;
 210         bool sink_has_audio;
 211
 212         struct mutex mutex;             /* for state below and previous_mode */
 213         enum drm_connector_force force; /* mutex-protected force state */
 214         bool disabled;                  /* DRM has disabled our bridge */
 215         bool bridge_is_on;              /* indicates the bridge is on */
 216         bool rxsense;                   /* rxsense state */
 217         u8 phy_mask;                    /* desired phy int mask settings */
 218
 219         spinlock_t audio_lock;
 220         struct mutex audio_mutex;
 221         unsigned int sample_rate;
 222         unsigned int audio_cts;
 223         unsigned int audio_n;
 224         bool audio_enable;
 225
 226 #ifdef CONFIG_SWITCH
 227         struct switch_dev switchdev;
 228 #endif
 229         int irq;
 230
 231         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 232         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 233 };
 234
 235 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 236         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 237          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 238
 239 #define HDMI_PHY_RX_SENSE \
 240         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 241          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 242
 243 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 244 {
 245         writel(val, hdmi->regs + (offset << 2));
 246 }
 247
 248 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 249 {
 250         return readl(hdmi->regs + (offset << 2));
 251 }
 252
 253 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 254 {
 255         writeb(val, hdmi->regs + offset);
 256 }
 257
 258 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 259 {
 260         return readb(hdmi->regs + offset);
 261 }
 262
 263 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 264 {
 265         hdmi->write(hdmi, val, offset);
 266 }
 267
 268 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 269 {
 270         return hdmi->read(hdmi, offset);
 271 }
 272
 273 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 274 {
 275         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 276
 277         val |= data & mask;
 278         hdmi_writeb(hdmi, val, reg);
 279 }
 280
 281 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 282                              u8 shift, u8 mask)
 283 {
 284         hdmi_modb(hdmi, data << shift, mask, reg);
 285 }
 286
 287 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
 288 {
 289         unsigned long clk_rate_khz;
 290         unsigned long low_ns, high_ns;
 291         unsigned long div_low, div_high;
 292
 293         /* Standard-mode */
 294         if (hdmi->i2c->scl_high_ns < 4000)
 295                 high_ns = 4708;
 296         else
 297                 high_ns = hdmi->i2c->scl_high_ns;
 298
 299         if (hdmi->i2c->scl_low_ns < 4700)
 300                 low_ns = 4916;
 301         else
 302                 low_ns = hdmi->i2c->scl_low_ns;
 303
 304         /* Adjust to avoid overflow */
 305         clk_rate_khz = DIV_ROUND_UP(clk_get_rate(hdmi->isfr_clk), 1000);
 306
 307         div_low = (clk_rate_khz * low_ns) / 1000000;
 308         if ((clk_rate_khz * low_ns) % 1000000)
 309                 div_low++;
 310
 311         div_high = (clk_rate_khz * high_ns) / 1000000;
 312         if ((clk_rate_khz * high_ns) % 1000000)
 313                 div_high++;
 314
 315         /* Maximum divider supported by hw is 0xffff */
 316         if (div_low > 0xffff)
 317                 div_low = 0xffff;
 318
 319         if (div_high > 0xffff)
 320                 div_high = 0xffff;
 321
 322         hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
 323         hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
 324                     HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
 325         hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
 326         hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
 327                     HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
 328 }
 329
 330 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 331 {
 332         /* Software reset */
 333         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 334
 335         /* Set Standard Mode speed */
 336         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 337                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 338
 339         /* Set done, not acknowledged and arbitration interrupt polarities */
 340         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 341         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 342                     HDMI_I2CM_CTLINT);
 343
 344         /* Clear DONE and ERROR interrupts */
 345         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 346                     HDMI_IH_I2CM_STAT0);
 347
 348         /* Mute DONE and ERROR interrupts */
 349         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 350                     HDMI_IH_MUTE_I2CM_STAT0);
 351
 352         dw_hdmi_i2c_set_divs(hdmi);
 353 }
 354
 355 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 356                             unsigned char *buf, unsigned int length)
 357 {
 358         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 359         int stat;
 360
 361         if (!i2c->is_regaddr) {
 362                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 363                 i2c->slave_reg = 0x00;
 364                 i2c->is_regaddr = true;
 365         }
 366
 367         while (length--) {
 368                 reinit_completion(&i2c->cmp);
 369
 370                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 371                 if (i2c->is_segment)
 372                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 373                                     HDMI_I2CM_OPERATION);
 374                 else
 375                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 376                                     HDMI_I2CM_OPERATION);
 377
 378                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 379                 if (!stat)
 380                         return -EAGAIN;
 381
 382                 /* Check for error condition on the bus */
 383                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 384                         return -EIO;
 385
 386                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 387         }
 388         i2c->is_segment = false;
 389
 390         return 0;
 391 }
 392
 393 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 394                              unsigned char *buf, unsigned int length)
 395 {
 396         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 397         int stat;
 398
 399         if (!i2c->is_regaddr) {
 400                 /* Use the first write byte as register address */
 401                 i2c->slave_reg = buf[0];
 402                 length--;
 403                 buf++;
 404                 i2c->is_regaddr = true;
 405         }
 406
 407         while (length--) {
 408                 reinit_completion(&i2c->cmp);
 409
 410                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 411                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 412                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 413                             HDMI_I2CM_OPERATION);
 414
 415         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 416                 if (!stat)
 417                         return -EAGAIN;
 418
 419                 /* Check for error condition on the bus */
 420                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 421                         return -EIO;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 428                             struct i2c_msg *msgs, int num)
 429 {
 430         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 431         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 432         u8 addr = msgs[0].addr;
 433         int i, ret = 0;
 434
 435         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 436
 437         for (i = 0; i < num; i++) {
 438                 if (msgs[i].len == 0) {
 439                         dev_dbg(hdmi->dev,
 440                                 "unsupported transfer %d/%d, no data\n",
 441                                 i + 1, num);
 442                         return -EOPNOTSUPP;
 443                 }
 444         }
 445
 446         mutex_lock(&i2c->lock);
 447
 448         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 449
 450         /* Set slave device address taken from the first I2C message */
 451         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 452
 453         /* Set slave device register address on transfer */
 454         i2c->is_regaddr = false;
 455
 456         /* Set segment pointer for I2C extended read mode operation */
 457         i2c->is_segment = false;
 458
 459         for (i = 0; i < num; i++) {
 460                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 461                         i + 1, num, msgs[i].len, msgs[i].flags);
 462                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 463                         i2c->is_segment = true;
 464                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 465                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 466                 } else {
 467                         if (msgs[i].flags & I2C_M_RD)
 468                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 469                                                        msgs[i].len);
 470                         else
 471                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 472                                                         msgs[i].len);
 473                 }
 474                 if (ret < 0)
 475                         break;
 476         }
 477
 478         if (!ret)
 479                 ret = num;
 480
 481         /* Mute DONE and ERROR interrupts */
 482         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 483                     HDMI_IH_MUTE_I2CM_STAT0);
 484
 485         mutex_unlock(&i2c->lock);
 486
 487         return ret;
 488 }
 489
 490 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 491 {
 492         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 493 }
 494
 495 static const struct i2c_algorithm dw_hdmi_algorithm = {
 496         .master_xfer    = dw_hdmi_i2c_xfer,
 497         .functionality  = dw_hdmi_i2c_func,
 498 };
 499
 500 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 501 {
 502         struct i2c_adapter *adap;
 503         struct dw_hdmi_i2c *i2c;
 504         int ret;
 505
 506         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 507         if (!i2c)
 508                 return ERR_PTR(-ENOMEM);
 509
 510         mutex_init(&i2c->lock);
 511         init_completion(&i2c->cmp);
 512
 513         adap = &i2c->adap;
 514         adap->class = I2C_CLASS_DDC;
 515         adap->owner = THIS_MODULE;
 516         adap->dev.parent = hdmi->dev;
 517         adap->dev.of_node = hdmi->dev->of_node;
 518         adap->algo = &dw_hdmi_algorithm;
 519         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 520         i2c_set_adapdata(adap, hdmi);
 521
 522         ret = i2c_add_adapter(adap);
 523         if (ret) {
 524                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 525                 devm_kfree(hdmi->dev, i2c);
 526                 return ERR_PTR(ret);
 527         }
 528
 529         hdmi->i2c = i2c;
 530
 531         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 532
 533         return adap;
 534 }
 535
 536 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 537                            unsigned int n)
 538 {
 539         /* Must be set/cleared first */
 540         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 541
 542         /* nshift factor = 0 */
 543         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 544
 545         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 546                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 547         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 548         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 549
 550         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 551         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 552         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 553 }
 554
 555 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 556                                    unsigned long pixel_clk,
 557                                    unsigned long freq)
 558 {
 559         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 560         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 561         int i;
 562
 563         if (plat_data->tmds_n_table) {
 564                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 565                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 566                                 tmds_n = &plat_data->tmds_n_table[i];
 567                                 break;
 568                         }
 569                 }
 570         }
 571
 572         if (tmds_n == NULL) {
 573                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 574                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 575                                 tmds_n = &common_tmds_n_table[i];
 576                                 break;
 577                         }
 578                 }
 579         }
 580
 581         if (tmds_n == NULL)
 582                 return -ENOENT;
 583
 584         switch (freq) {
 585         case 32000:
 586                 return tmds_n->n_32k;
 587         case 44100:
 588         case 88200:
 589         case 176400:
 590                 return (freq / 44100) * tmds_n->n_44k1;
 591         case 48000:
 592         case 96000:
 593         case 192000:
 594                 return (freq / 48000) * tmds_n->n_48k;
 595         default:
 596                 return -ENOENT;
 597         }
 598 }
 599
 600 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 601                                 unsigned int pixel_clk)
 602 {
 603         u64 final, diff;
 604         u64 cts;
 605
 606         final = (u64)pixel_clk * n;
 607
 608         cts = final;
 609         do_div(cts, 128 * freq);
 610
 611         diff = final - (u64)cts * (128 * freq);
 612
 613         return diff;
 614 }
 615
 616 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 617                                    unsigned long pixel_clk,
 618                                    unsigned long freq)
 619 {
 620         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 621         unsigned int max_n = (128 * freq) / 300;
 622         unsigned int ideal_n = (128 * freq) / 1000;
 623         unsigned int best_n_distance = ideal_n;
 624         unsigned int best_n = 0;
 625         u64 best_diff = U64_MAX;
 626         int n;
 627
 628         /* If the ideal N could satisfy the audio math, then just take it */
 629         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 630                 return ideal_n;
 631
 632         for (n = min_n; n <= max_n; n++) {
 633                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 634
 635                 if (diff < best_diff || (diff == best_diff &&
 636                     abs(n - ideal_n) < best_n_distance)) {
 637                         best_n = n;
 638                         best_diff = diff;
 639                         best_n_distance = abs(best_n - ideal_n);
 640                 }
 641
 642                 /*
 643                  * The best N already satisfy the audio math, and also be
 644                  * the closest value to ideal N, so just cut the loop.
 645                  */
 646                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 647                         break;
 648         }
 649
 650         return best_n;
 651 }
 652
 653 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 654                                 unsigned long sample_rate)
 655 {
 656         int n;
 657
 658         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 659         if (n > 0)
 660                 return n;
 661
 662         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 663                  pixel_clk);
 664
 665         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 666 }
 667
 668 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 669         unsigned long pixel_clk, unsigned int sample_rate)
 670 {
 671         unsigned long ftdms = pixel_clk;
 672         unsigned int n, cts;
 673         u64 tmp;
 674
 675         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 676
 677         /*
 678          * Compute the CTS value from the N value.  Note that CTS and N
 679          * can be up to 20 bits in total, so we need 64-bit math.  Also
 680          * note that our TDMS clock is not fully accurate; it is accurate
 681          * to kHz.  This can introduce an unnecessary remainder in the
 682          * calculation below, so we don't try to warn about that.
 683          */
 684         tmp = (u64)ftdms * n;
 685         do_div(tmp, 128 * sample_rate);
 686         cts = tmp;
 687
 688         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 689                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 690                 n, cts);
 691
 692         spin_lock_irq(&hdmi->audio_lock);
 693         hdmi->audio_n = n;
 694         hdmi->audio_cts = cts;
 695         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 696         spin_unlock_irq(&hdmi->audio_lock);
 697 }
 698
 699 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 700 {
 701         mutex_lock(&hdmi->audio_mutex);
 702         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 703         mutex_unlock(&hdmi->audio_mutex);
 704 }
 705
 706 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 707 {
 708         mutex_lock(&hdmi->audio_mutex);
 709         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 710                                  hdmi->sample_rate);
 711         mutex_unlock(&hdmi->audio_mutex);
 712 }
 713
 714 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 715 {
 716         mutex_lock(&hdmi->audio_mutex);
 717         hdmi->sample_rate = rate;
 718         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 719                                  hdmi->sample_rate);
 720         mutex_unlock(&hdmi->audio_mutex);
 721 }
 722 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 723
 724 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 725 {
 726         unsigned long flags;
 727
 728         spin_lock_irqsave(&hdmi->audio_lock, flags);
 729         hdmi->audio_enable = true;
 730         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 731         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 732 }
 733 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 734
 735 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 736 {
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&hdmi->audio_lock, flags);
 740         hdmi->audio_enable = false;
 741         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 742         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 743 }
 744 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 745
 746 /*
 747  * this submodule is responsible for the video data synchronization.
 748  * for example, for RGB 4:4:4 input, the data map is defined as
 749  *                      pin{47~40} <==> R[7:0]
 750  *                      pin{31~24} <==> G[7:0]
 751  *                      pin{15~8}  <==> B[7:0]
 752  */
 753 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 754 {
 755         int color_format = 0;
 756         u8 val;
 757
 758         if (hdmi->hdmi_data.enc_in_format == RGB) {
 759                 if (hdmi->hdmi_data.enc_color_depth == 8)
 760                         color_format = 0x01;
 761                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 762                         color_format = 0x03;
 763                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 764                         color_format = 0x05;
 765                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 766                         color_format = 0x07;
 767                 else
 768                         return;
 769         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
 770                    hdmi->hdmi_data.enc_in_format == YCBCR420) {
 771                 if (hdmi->hdmi_data.enc_color_depth == 8)
 772                         color_format = 0x09;
 773                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 774                         color_format = 0x0B;
 775                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 776                         color_format = 0x0D;
 777                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 778                         color_format = 0x0F;
 779                 else
 780                         return;
 781         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 782                 if (hdmi->hdmi_data.enc_color_depth == 8)
 783                         color_format = 0x16;
 784                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 785                         color_format = 0x14;
 786                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 787                         color_format = 0x12;
 788                 else
 789                         return;
 790         }
 791
 792         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 793                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 794                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 795         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 796
 797         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 798         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 799                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 800                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 801         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 802         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 803         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 804         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 805         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 806         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 807         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 808 }
 809
 810 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 811 {
 812         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 813 }
 814
 815 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 816 {
 817         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 818                 return 0;
 819         if (hdmi->hdmi_data.enc_in_format == RGB ||
 820             hdmi->hdmi_data.enc_in_format == YCBCR444)
 821                 return 1;
 822         return 0;
 823 }
 824
 825 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 826 {
 827         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 828                 return 0;
 829         if (hdmi->hdmi_data.enc_out_format == RGB ||
 830             hdmi->hdmi_data.enc_out_format == YCBCR444)
 831                 return 1;
 832         return 0;
 833 }
 834
 835 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 836 {
 837         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 838         unsigned i;
 839         u32 csc_scale = 1;
 840
 841         if (is_color_space_conversion(hdmi)) {
 842                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 843                         if (hdmi->hdmi_data.colorimetry ==
 844                                         HDMI_COLORIMETRY_ITU_601)
 845                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 846                         else
 847                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 848                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 849                         if (hdmi->hdmi_data.colorimetry ==
 850                                         HDMI_COLORIMETRY_ITU_601)
 851                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 852                         else
 853                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 854                         csc_scale = 0;
 855                 }
 856         }
 857
 858         /* The CSC registers are sequential, alternating MSB then LSB */
 859         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 860                 u16 coeff_a = (*csc_coeff)[0][i];
 861                 u16 coeff_b = (*csc_coeff)[1][i];
 862                 u16 coeff_c = (*csc_coeff)[2][i];
 863
 864                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 865                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 866                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 867                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 868                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 869                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 870         }
 871
 872         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 873                   HDMI_CSC_SCALE);
 874 }
 875
 876 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 877 {
 878         int color_depth = 0;
 879         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 880         int decimation = 0;
 881
 882         /* YCC422 interpolation to 444 mode */
 883         if (is_color_space_interpolation(hdmi))
 884                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 885         else if (is_color_space_decimation(hdmi))
 886                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 887
 888         if (hdmi->hdmi_data.enc_color_depth == 8)
 889                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 890         else if (hdmi->hdmi_data.enc_color_depth == 10)
 891                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 892         else if (hdmi->hdmi_data.enc_color_depth == 12)
 893                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 894         else if (hdmi->hdmi_data.enc_color_depth == 16)
 895                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 896         else
 897                 return;
 898
 899         /* Configure the CSC registers */
 900         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 901         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 902                   HDMI_CSC_SCALE);
 903
 904         dw_hdmi_update_csc_coeffs(hdmi);
 905 }
 906
 907 /*
 908  * HDMI video packetizer is used to packetize the data.
 909  * for example, if input is YCC422 mode or repeater is used,
 910  * data should be repacked this module can be bypassed.
 911  */
 912 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 913 {
 914         unsigned int color_depth = 0;
 915         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 916         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 917         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 918         u8 val, vp_conf;
 919
 920         if (hdmi_data->enc_out_format == RGB ||
 921             hdmi_data->enc_out_format == YCBCR444 ||
 922             hdmi_data->enc_out_format == YCBCR420) {
 923                 if (!hdmi_data->enc_color_depth) {
 924                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 925                 } else if (hdmi_data->enc_color_depth == 8) {
 926                         color_depth = 4;
 927                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 928                 } else if (hdmi_data->enc_color_depth == 10) {
 929                         color_depth = 5;
 930                 } else if (hdmi_data->enc_color_depth == 12) {
 931                         color_depth = 6;
 932                 } else if (hdmi_data->enc_color_depth == 16) {
 933                         color_depth = 7;
 934                 } else {
 935                         return;
 936                 }
 937         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 938                 if (!hdmi_data->enc_color_depth ||
 939                     hdmi_data->enc_color_depth == 8)
 940                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 941                 else if (hdmi_data->enc_color_depth == 10)
 942                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 943                 else if (hdmi_data->enc_color_depth == 12)
 944                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 945                 else
 946                         return;
 947                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 948         } else {
 949                 return;
 950         }
 951
 952         /* set the packetizer registers */
 953         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 954                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 955                 ((hdmi_data->pix_repet_factor <<
 956                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 957                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 958         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 959
 960         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 961                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 962
 963         /* Data from pixel repeater block */
 964         if (hdmi_data->pix_repet_factor > 0) {
 965                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 966                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 967         } else { /* data from packetizer block */
 968                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 969                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 970         }
 971
 972         hdmi_modb(hdmi, vp_conf,
 973                   HDMI_VP_CONF_PR_EN_MASK |
 974                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 975
 976         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 977                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 978
 979         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 980
 981         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 982                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 983                           HDMI_VP_CONF_PP_EN_ENABLE |
 984                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 985         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 986                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 987                           HDMI_VP_CONF_PP_EN_DISABLE |
 988                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 989         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 990                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 991                           HDMI_VP_CONF_PP_EN_DISABLE |
 992                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 993         } else {
 994                 return;
 995         }
 996
 997         hdmi_modb(hdmi, vp_conf,
 998                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 999                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1000
1001         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1002                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1003                   HDMI_VP_STUFF_PP_STUFFING_MASK |
1004                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1005
1006         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1007                   HDMI_VP_CONF);
1008 }
1009
1010 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1011                                        unsigned char bit)
1012 {
1013         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1014                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1015 }
1016
1017 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
1018                                         unsigned char bit)
1019 {
1020         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
1021                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
1022 }
1023
1024 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
1025                                        unsigned char bit)
1026 {
1027         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
1028                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
1029 }
1030
1031 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
1032                                      unsigned char bit)
1033 {
1034         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
1035 }
1036
1037 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
1038                                       unsigned char bit)
1039 {
1040         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
1041 }
1042
1043 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1044 {
1045         u32 val;
1046
1047         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1048                 if (msec-- == 0)
1049                         return false;
1050                 udelay(1000);
1051         }
1052         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1053
1054         return true;
1055 }
1056
1057 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1058                                  unsigned char addr)
1059 {
1060         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1061         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1062         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1063                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1064         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1065                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1066         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1067                     HDMI_PHY_I2CM_OPERATION_ADDR);
1068         hdmi_phy_wait_i2c_done(hdmi, 1000);
1069 }
1070
1071 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1072                               unsigned char addr)
1073 {
1074         __hdmi_phy_i2c_write(hdmi, data, addr);
1075         return 0;
1076 }
1077
1078 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1079 {
1080         int val;
1081
1082         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1083         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1084         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1085         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1086         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1087                     HDMI_PHY_I2CM_OPERATION_ADDR);
1088         hdmi_phy_wait_i2c_done(hdmi, 1000);
1089         val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1090         val = (val & 0xff) << 8;
1091         val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1092         return val;
1093 }
1094
1095 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1096 {
1097         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1098                          HDMI_PHY_CONF0_PDZ_OFFSET,
1099                          HDMI_PHY_CONF0_PDZ_MASK);
1100 }
1101
1102 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1103 {
1104         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1105                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1106                          HDMI_PHY_CONF0_ENTMDS_MASK);
1107 }
1108
1109 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1110 {
1111         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1112                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1113                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1114 }
1115
1116 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1117 {
1118         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1119                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1120                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1121 }
1122
1123 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1124 {
1125         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1126                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1127                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1128 }
1129
1130 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1131 {
1132         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1133                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1134                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1135 }
1136
1137 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1138 {
1139         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1140                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1141                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1142 }
1143
1144 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1145                               unsigned char res, int cscon)
1146 {
1147         unsigned res_idx;
1148         u8 val, msec, tmds_cfg;
1149         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1150         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1151         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1152         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1153
1154         if (prep)
1155                 return -EINVAL;
1156
1157         switch (res) {
1158         case 0: /* color resolution 0 is 8 bit colour depth */
1159         case 8:
1160                 res_idx = DW_HDMI_RES_8;
1161                 break;
1162         case 10:
1163                 res_idx = DW_HDMI_RES_10;
1164                 break;
1165         case 12:
1166                 res_idx = DW_HDMI_RES_12;
1167                 break;
1168         default:
1169                 return -EINVAL;
1170         }
1171
1172         /* PLL/MPLL Cfg - always match on final entry */
1173         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1174                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1175                     mpll_config->mpixelclock)
1176                         break;
1177
1178         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1179                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1180                     curr_ctrl->mpixelclock)
1181                         break;
1182
1183         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1184                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1185                     phy_config->mpixelclock)
1186                         break;
1187
1188         if (mpll_config->mpixelclock == ~0UL ||
1189             curr_ctrl->mpixelclock == ~0UL ||
1190             phy_config->mpixelclock == ~0UL) {
1191                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1192                         hdmi->hdmi_data.video_mode.mpixelclock);
1193                 return -EINVAL;
1194         }
1195
1196         /* Enable csc path */
1197         if (cscon)
1198                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1199         else
1200                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1201
1202         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1203
1204         /* gen2 tx power off */
1205         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1206
1207         /* gen2 pddq */
1208         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1209
1210         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1211         if (hdmi->connector.scdc_present) {
1212                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1213                 if (mpll_config->mpixelclock > 340000000)
1214                         tmds_cfg |= 2;
1215                 else
1216                         tmds_cfg &= 0x1;
1217                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1218         }
1219
1220         /* PHY reset */
1221         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1222         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1223
1224         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1225
1226         hdmi_phy_test_clear(hdmi, 1);
1227         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1228                     HDMI_PHY_I2CM_SLAVE_ADDR);
1229         hdmi_phy_test_clear(hdmi, 0);
1230         /*
1231          * RK3399 mpll clock source is vpll, also is vop clock source.
1232          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1233          * to enable mpll pre-divider.
1234          */
1235         if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1236             hdmi->dev_type == RK3399_HDMI)
1237                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1238                                    0x06);
1239         else
1240                 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1241         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1242
1243         /* CURRCTRL */
1244         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1245
1246         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1247         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1248
1249         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1250         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1251         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1252
1253         /* REMOVE CLK TERM */
1254         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1255
1256         dw_hdmi_phy_enable_powerdown(hdmi, false);
1257
1258         /* toggle TMDS disable */
1259         dw_hdmi_phy_enable_tmds(hdmi, 0);
1260
1261         /* Wait for resuming transmission of TMDS clock and data */
1262         if (mpll_config->mpixelclock > 340000000)
1263                 msleep(100);
1264
1265         /* toggle TMDS enable */
1266         dw_hdmi_phy_enable_tmds(hdmi, 1);
1267
1268         /* gen2 tx power on */
1269         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1270         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1271
1272         if (is_rockchip(hdmi->dev_type))
1273                 dw_hdmi_phy_enable_spare(hdmi, 1);
1274
1275         /* Wait for PHY PLL lock */
1276         msec = 5;
1277         do {
1278                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1279                 if (!val)
1280                         break;
1281
1282                 if (msec == 0) {
1283                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1284                         return -ETIMEDOUT;
1285                 }
1286
1287                 udelay(1000);
1288                 msec--;
1289         } while (1);
1290
1291         return 0;
1292 }
1293
1294 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1295 {
1296         int i, ret;
1297         bool cscon;
1298
1299         /*check csc whether needed activated in HDMI mode */
1300         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1301
1302         /* HDMI Phy spec says to do the phy initialization sequence twice */
1303         for (i = 0; i < 2; i++) {
1304                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1305                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1306                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1307                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1308
1309                 /* Enable CSC */
1310                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1311                 if (ret)
1312                         return ret;
1313         }
1314
1315         hdmi->phy_enabled = true;
1316         return 0;
1317 }
1318
1319 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1320 {
1321         u8 de;
1322
1323         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1324                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1325         else
1326                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1327
1328         /* disable rx detect */
1329         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1330                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1331
1332         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1333
1334         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1335                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1336 }
1337
1338 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1339 {
1340         struct hdmi_avi_infoframe frame;
1341         u8 val;
1342         bool is_hdmi2 = false;
1343
1344         if ((mode->flags & DRM_MODE_FLAG_420_MASK) ||
1345             hdmi->connector.scdc_present)
1346                 is_hdmi2 = true;
1347         /* Initialise info frame from DRM mode */
1348         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1349
1350         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1351                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1352         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1353                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1354         else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1355                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1356         else
1357                 frame.colorspace = HDMI_COLORSPACE_RGB;
1358
1359         /* Set up colorimetry */
1360         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1361                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1362                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1363                         frame.extended_colorimetry =
1364                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1365                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1366                         frame.extended_colorimetry =
1367                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1368         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1369                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1370                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1371         } else { /* Carries no data */
1372                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1373                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1374         }
1375
1376         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1377
1378         /*
1379          * The Designware IP uses a different byte format from standard
1380          * AVI info frames, though generally the bits are in the correct
1381          * bytes.
1382          */
1383
1384         /*
1385          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1386          * 5,6,7, active aspect present in bit 6 rather than 4.
1387          */
1388         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1389         if (frame.active_aspect & 15)
1390                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1391         if (frame.top_bar || frame.bottom_bar)
1392                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1393         if (frame.left_bar || frame.right_bar)
1394                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1395         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1396
1397         /* AVI data byte 2 differences: none */
1398         val = ((frame.colorimetry & 0x3) << 6) |
1399               ((frame.picture_aspect & 0x3) << 4) |
1400               (frame.active_aspect & 0xf);
1401         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1402
1403         /* AVI data byte 3 differences: none */
1404         val = ((frame.extended_colorimetry & 0x7) << 4) |
1405               ((frame.quantization_range & 0x3) << 2) |
1406               (frame.nups & 0x3);
1407         if (frame.itc)
1408                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1409         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1410
1411         /* AVI data byte 4 differences: none */
1412         val = frame.video_code & 0x7f;
1413         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1414
1415         /* AVI Data Byte 5- set up input and output pixel repetition */
1416         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1417                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1418                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1419                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1420                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1421                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1422         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1423
1424         /*
1425          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1426          * ycc range in bits 2,3 rather than 6,7
1427          */
1428         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1429               (frame.content_type & 0x3);
1430         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1431
1432         /* AVI Data Bytes 6-13 */
1433         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1434         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1435         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1436         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1437         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1438         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1439         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1440         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1441 }
1442
1443 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1444                                                  struct drm_display_mode *mode)
1445 {
1446         struct hdmi_vendor_infoframe frame;
1447         u8 buffer[10];
1448         ssize_t err;
1449
1450         /* Disable HDMI vendor specific infoframe send */
1451         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1452                         HDMI_FC_DATAUTO0_VSD_MASK);
1453
1454         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1455         if (err < 0)
1456                 /*
1457                  * Going into that statement does not means vendor infoframe
1458                  * fails. It just informed us that vendor infoframe is not
1459                  * needed for the selected mode. Only 4k or stereoscopic 3D
1460                  * mode requires vendor infoframe. So just simply return.
1461                  */
1462                 return;
1463
1464         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1465         if (err < 0) {
1466                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1467                         err);
1468                 return;
1469         }
1470
1471         /* Set the length of HDMI vendor specific InfoFrame payload */
1472         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1473
1474         /* Set 24bit IEEE Registration Identifier */
1475         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1476         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1477         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1478
1479         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1480         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1481         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1482
1483         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1484                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1485
1486         /* Packet frame interpolation */
1487         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1488
1489         /* Auto packets per frame and line spacing */
1490         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1491
1492         /* Configures the Frame Composer On RDRB mode */
1493         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1494                         HDMI_FC_DATAUTO0_VSD_MASK);
1495 }
1496
1497 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1498                              const struct drm_display_mode *mode)
1499 {
1500         u8 inv_val, bytes;
1501         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1502         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1503         unsigned int hdisplay, vdisplay;
1504
1505         vmode->mpixelclock = mode->crtc_clock * 1000;
1506         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1507                 vmode->mpixelclock /= 2;
1508         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1509                 DRM_MODE_FLAG_3D_FRAME_PACKING)
1510                 vmode->mpixelclock *= 2;
1511         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1512
1513         /* Set up HDMI_FC_INVIDCONF
1514          * fc_invidconf.HDCP_keepout must be set (1'b1)
1515          * when activate the scrambler feature.
1516          */
1517         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1518                    vmode->mpixelclock > 340000000 ||
1519                    hdmi->connector.lte_340mcsc_scramble ?
1520                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1521                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1522
1523         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1524                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1525                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1526
1527         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1528                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1529                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1530
1531         inv_val |= (vmode->mdataenablepolarity ?
1532                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1533                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1534
1535         if (hdmi->vic == 39)
1536                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1537         else
1538                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1539                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1540                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1541
1542         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1543                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1544                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1545
1546         inv_val |= hdmi->sink_is_hdmi ?
1547                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1548                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1549
1550         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1551
1552         hdisplay = mode->hdisplay;
1553         hblank = mode->htotal - mode->hdisplay;
1554         h_de_hs = mode->hsync_start - mode->hdisplay;
1555         hsync_len = mode->hsync_end - mode->hsync_start;
1556
1557         /*
1558          * When we're setting a YCbCr420 mode, we need
1559          * to adjust the horizontal timing to suit.
1560          */
1561         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1562                 hdisplay /= 2;
1563                 hblank /= 2;
1564                 h_de_hs /= 2;
1565                 hsync_len /= 2;
1566         }
1567
1568         vdisplay = mode->vdisplay;
1569         vblank = mode->vtotal - mode->vdisplay;
1570         v_de_vs = mode->vsync_start - mode->vdisplay;
1571         vsync_len = mode->vsync_end - mode->vsync_start;
1572
1573         /*
1574          * When we're setting an interlaced mode, we need
1575          * to adjust the vertical timing to suit.
1576          */
1577         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1578                 vdisplay /= 2;
1579                 vblank /= 2;
1580                 v_de_vs /= 2;
1581                 vsync_len /= 2;
1582         } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1583                 DRM_MODE_FLAG_3D_FRAME_PACKING) {
1584                 vdisplay += mode->vtotal;
1585         }
1586
1587         /* Scrambling Control */
1588         if (hdmi->connector.scdc_present) {
1589                 if (vmode->mpixelclock > 340000000 ||
1590                     hdmi->connector.lte_340mcsc_scramble) {
1591                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1592                                        &bytes);
1593                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1594                                         bytes);
1595                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1596                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1597                                     HDMI_MC_SWRSTZ);
1598                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1599                 } else {
1600                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1601                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1602                                     HDMI_MC_SWRSTZ);
1603                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1604                 }
1605         }
1606
1607         /* Set up horizontal active pixel width */
1608         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1609         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1610
1611         /* Set up vertical active lines */
1612         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1613         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1614
1615         /* Set up horizontal blanking pixel region width */
1616         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1617         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1618
1619         /* Set up vertical blanking pixel region width */
1620         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1621
1622         /* Set up HSYNC active edge delay width (in pixel clks) */
1623         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1624         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1625
1626         /* Set up VSYNC active edge delay (in lines) */
1627         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1628
1629         /* Set up HSYNC active pulse width (in pixel clks) */
1630         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1631         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1632
1633         /* Set up VSYNC active edge delay (in lines) */
1634         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1635 }
1636
1637 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1638 {
1639         if (!hdmi->phy_enabled)
1640                 return;
1641
1642         dw_hdmi_phy_enable_tmds(hdmi, 0);
1643         dw_hdmi_phy_enable_powerdown(hdmi, true);
1644
1645         hdmi->phy_enabled = false;
1646 }
1647
1648 /* HDMI Initialization Step B.4 */
1649 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1650 {
1651         u8 clkdis;
1652
1653         /* control period minimum duration */
1654         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1655         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1656         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1657
1658         /* Set to fill TMDS data channels */
1659         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1660         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1661         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1662
1663         /* Enable pixel clock and tmds data path */
1664         clkdis = 0x7F;
1665         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1666         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1667
1668         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1669         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1670
1671         /* Enable csc path */
1672         if (is_color_space_conversion(hdmi)) {
1673                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1674                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1675         }
1676
1677         /* Enable pixel repetition path */
1678         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1679                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1680                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1681         }
1682 }
1683
1684 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1685 {
1686         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1687 }
1688
1689 /* Workaround to clear the overflow condition */
1690 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1691 {
1692         int count;
1693         u8 val;
1694
1695         /* TMDS software reset */
1696         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1697
1698         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1699         if (hdmi->dev_type == IMX6DL_HDMI) {
1700                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1701                 return;
1702         }
1703
1704         for (count = 0; count < 4; count++)
1705                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1706 }
1707
1708 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1709 {
1710         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1711         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1712 }
1713
1714 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1715 {
1716         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1717                     HDMI_IH_MUTE_FC_STAT2);
1718 }
1719
1720 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1721 {
1722         int ret;
1723
1724         hdmi_disable_overflow_interrupts(hdmi);
1725
1726         hdmi->vic = drm_match_cea_mode(mode);
1727
1728         if (!hdmi->vic) {
1729                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1730         } else {
1731                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1732         }
1733
1734         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1735             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1736             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1737             (hdmi->vic == 17) || (hdmi->vic == 18))
1738                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1739         else
1740                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1741
1742         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1743                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1744                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1745         } else {
1746                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1747                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1748         }
1749         /* TODO: Get input format from IPU (via FB driver interface) */
1750         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1751                 hdmi->hdmi_data.enc_in_format = YCBCR420;
1752                 hdmi->hdmi_data.enc_out_format = YCBCR420;
1753         } else {
1754                 hdmi->hdmi_data.enc_in_format = RGB;
1755                 hdmi->hdmi_data.enc_out_format = RGB;
1756         }
1757         hdmi->hdmi_data.enc_color_depth = 8;
1758         /*
1759          * According to the dw-hdmi specification 6.4.2
1760          * vp_pr_cd[3:0]:
1761          * 0000b: No pixel repetition (pixel sent only once)
1762          * 0001b: Pixel sent two times (pixel repeated once)
1763          */
1764         hdmi->hdmi_data.pix_repet_factor =
1765                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1766         hdmi->hdmi_data.hdcp_enable = 0;
1767         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1768
1769         /* HDMI Initialization Step B.1 */
1770         hdmi_av_composer(hdmi, mode);
1771
1772         /* HDMI Initializateion Step B.2 */
1773         ret = dw_hdmi_phy_init(hdmi);
1774         if (ret)
1775                 return ret;
1776
1777         /* HDMI Initialization Step B.3 */
1778         dw_hdmi_enable_video_path(hdmi);
1779
1780         if (hdmi->sink_has_audio) {
1781                 dev_dbg(hdmi->dev, "sink has audio support\n");
1782
1783                 /* HDMI Initialization Step E - Configure audio */
1784                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1785                 hdmi_enable_audio_clk(hdmi);
1786         }
1787
1788         /* not for DVI mode */
1789         if (hdmi->sink_is_hdmi) {
1790                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1791
1792                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1793                 hdmi_config_AVI(hdmi, mode);
1794                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1795         } else {
1796                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1797         }
1798
1799         hdmi_video_packetize(hdmi);
1800         hdmi_video_csc(hdmi);
1801         hdmi_video_sample(hdmi);
1802         hdmi_tx_hdcp_config(hdmi);
1803
1804         dw_hdmi_clear_overflow(hdmi);
1805         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1806                 hdmi_enable_overflow_interrupts(hdmi);
1807
1808         return 0;
1809 }
1810
1811 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1812 {
1813         u8 ih_mute;
1814
1815         /*
1816          * Boot up defaults are:
1817          * HDMI_IH_MUTE   = 0x03 (disabled)
1818          * HDMI_IH_MUTE_* = 0x00 (enabled)
1819          *
1820          * Disable top level interrupt bits in HDMI block
1821          */
1822         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1823                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1824                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1825
1826         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1827
1828         /* by default mask all interrupts */
1829         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1830         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1831         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1832         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1833         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1834         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1835         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1836         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1837         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1838         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1839         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1840         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1841         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1842         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1843         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1844
1845         /* Disable interrupts in the IH_MUTE_* registers */
1846         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1847         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1848         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1849         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1850         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1851         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1852         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1853         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1854         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1855         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1856
1857         /* Enable top level interrupt bits in HDMI block */
1858         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1859                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1860         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1861 }
1862
1863 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1864 {
1865         hdmi->bridge_is_on = true;
1866         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1867 }
1868
1869 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1870 {
1871         dw_hdmi_phy_disable(hdmi);
1872         hdmi->bridge_is_on = false;
1873 }
1874
1875 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1876 {
1877         int force = hdmi->force;
1878
1879         if (hdmi->disabled) {
1880                 force = DRM_FORCE_OFF;
1881         } else if (force == DRM_FORCE_UNSPECIFIED) {
1882                 if (hdmi->rxsense)
1883                         force = DRM_FORCE_ON;
1884                 else
1885                         force = DRM_FORCE_OFF;
1886         }
1887
1888         if (force == DRM_FORCE_OFF) {
1889                 if (hdmi->bridge_is_on)
1890                         dw_hdmi_poweroff(hdmi);
1891         } else {
1892                 if (!hdmi->bridge_is_on)
1893                         dw_hdmi_poweron(hdmi);
1894         }
1895 }
1896
1897 /*
1898  * Adjust the detection of RXSENSE according to whether we have a forced
1899  * connection mode enabled, or whether we have been disabled.  There is
1900  * no point processing RXSENSE interrupts if we have a forced connection
1901  * state, or DRM has us disabled.
1902  *
1903  * We also disable rxsense interrupts when we think we're disconnected
1904  * to avoid floating TDMS signals giving false rxsense interrupts.
1905  *
1906  * Note: we still need to listen for HPD interrupts even when DRM has us
1907  * disabled so that we can detect a connect event.
1908  */
1909 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1910 {
1911         u8 old_mask = hdmi->phy_mask;
1912
1913         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1914                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1915         else
1916                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1917
1918         if (old_mask != hdmi->phy_mask)
1919                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1920 }
1921
1922 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1923                                     struct drm_display_mode *orig_mode,
1924                                     struct drm_display_mode *mode)
1925 {
1926         struct dw_hdmi *hdmi = bridge->driver_private;
1927
1928         mutex_lock(&hdmi->mutex);
1929
1930         /* Store the display mode for plugin/DKMS poweron events */
1931         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1932
1933         mutex_unlock(&hdmi->mutex);
1934 }
1935
1936 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1937 {
1938         struct dw_hdmi *hdmi = bridge->driver_private;
1939
1940         mutex_lock(&hdmi->mutex);
1941         hdmi->disabled = true;
1942         dw_hdmi_update_power(hdmi);
1943         dw_hdmi_update_phy_mask(hdmi);
1944         mutex_unlock(&hdmi->mutex);
1945 }
1946
1947 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1948 {
1949         struct dw_hdmi *hdmi = bridge->driver_private;
1950
1951         mutex_lock(&hdmi->mutex);
1952         hdmi->disabled = false;
1953         dw_hdmi_update_power(hdmi);
1954         dw_hdmi_update_phy_mask(hdmi);
1955         mutex_unlock(&hdmi->mutex);
1956 }
1957
1958 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1959 {
1960         /* do nothing */
1961 }
1962
1963 static enum drm_connector_status
1964 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1965 {
1966         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1967                                              connector);
1968
1969         mutex_lock(&hdmi->mutex);
1970         hdmi->force = DRM_FORCE_UNSPECIFIED;
1971         dw_hdmi_update_power(hdmi);
1972         dw_hdmi_update_phy_mask(hdmi);
1973         mutex_unlock(&hdmi->mutex);
1974
1975         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1976                 connector_status_connected : connector_status_disconnected;
1977 }
1978
1979 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1980 {
1981         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1982                                              connector);
1983         struct edid *edid;
1984         int ret = 0;
1985
1986         if (!hdmi->ddc)
1987                 return 0;
1988
1989         edid = drm_get_edid(connector, hdmi->ddc);
1990         if (edid) {
1991                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1992                         edid->width_cm, edid->height_cm);
1993
1994                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1995                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1996                 drm_mode_connector_update_edid_property(connector, edid);
1997                 ret = drm_add_edid_modes(connector, edid);
1998                 /* Store the ELD */
1999                 drm_edid_to_eld(connector, edid);
2000                 kfree(edid);
2001         } else {
2002                 dev_dbg(hdmi->dev, "failed to get edid\n");
2003         }
2004
2005         return ret;
2006 }
2007
2008 static enum drm_mode_status
2009 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
2010                              struct drm_display_mode *mode)
2011 {
2012         struct dw_hdmi *hdmi = container_of(connector,
2013                                            struct dw_hdmi, connector);
2014         enum drm_mode_status mode_status = MODE_OK;
2015
2016         if (hdmi->plat_data->mode_valid)
2017                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2018
2019         return mode_status;
2020 }
2021
2022 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
2023                                                            *connector)
2024 {
2025         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2026                                              connector);
2027
2028         return hdmi->encoder;
2029 }
2030
2031 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
2032 {
2033         drm_connector_unregister(connector);
2034         drm_connector_cleanup(connector);
2035 }
2036
2037 static void dw_hdmi_connector_force(struct drm_connector *connector)
2038 {
2039         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2040                                              connector);
2041
2042         mutex_lock(&hdmi->mutex);
2043         hdmi->force = connector->force;
2044         dw_hdmi_update_power(hdmi);
2045         dw_hdmi_update_phy_mask(hdmi);
2046         mutex_unlock(&hdmi->mutex);
2047 }
2048
2049 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2050         .dpms = drm_helper_connector_dpms,
2051         .fill_modes = drm_helper_probe_single_connector_modes,
2052         .detect = dw_hdmi_connector_detect,
2053         .destroy = dw_hdmi_connector_destroy,
2054         .force = dw_hdmi_connector_force,
2055 };
2056
2057 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
2058         .dpms = drm_atomic_helper_connector_dpms,
2059         .fill_modes = drm_helper_probe_single_connector_modes,
2060         .detect = dw_hdmi_connector_detect,
2061         .destroy = dw_hdmi_connector_destroy,
2062         .force = dw_hdmi_connector_force,
2063         .reset = drm_atomic_helper_connector_reset,
2064         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2065         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2066 };
2067
2068 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2069         .get_modes = dw_hdmi_connector_get_modes,
2070         .mode_valid = dw_hdmi_connector_mode_valid,
2071         .best_encoder = dw_hdmi_connector_best_encoder,
2072 };
2073
2074 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2075         .enable = dw_hdmi_bridge_enable,
2076         .disable = dw_hdmi_bridge_disable,
2077         .pre_enable = dw_hdmi_bridge_nop,
2078         .post_disable = dw_hdmi_bridge_nop,
2079         .mode_set = dw_hdmi_bridge_mode_set,
2080 };
2081
2082 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2083 {
2084         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2085         unsigned int stat;
2086
2087         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2088         if (!stat)
2089                 return IRQ_NONE;
2090
2091         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2092
2093         i2c->stat = stat;
2094
2095         complete(&i2c->cmp);
2096
2097         return IRQ_HANDLED;
2098 }
2099
2100 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2101 {
2102         struct dw_hdmi *hdmi = dev_id;
2103         u8 intr_stat;
2104         irqreturn_t ret = IRQ_NONE;
2105
2106         if (hdmi->i2c)
2107                 ret = dw_hdmi_i2c_irq(hdmi);
2108
2109         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2110         if (intr_stat) {
2111                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2112                 return IRQ_WAKE_THREAD;
2113         }
2114
2115         return ret;
2116 }
2117
2118 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2119 {
2120         struct dw_hdmi *hdmi = dev_id;
2121         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2122
2123         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2124         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2125         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2126
2127         phy_pol_mask = 0;
2128         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2129                 phy_pol_mask |= HDMI_PHY_HPD;
2130         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2131                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2132         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2133                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2134         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2135                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2136         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2137                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2138
2139         if (phy_pol_mask)
2140                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2141
2142         /*
2143          * RX sense tells us whether the TDMS transmitters are detecting
2144          * load - in other words, there's something listening on the
2145          * other end of the link.  Use this to decide whether we should
2146          * power on the phy as HPD may be toggled by the sink to merely
2147          * ask the source to re-read the EDID.
2148          */
2149         if (intr_stat &
2150             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2151                 mutex_lock(&hdmi->mutex);
2152                 if (!hdmi->bridge_is_on && !hdmi->force) {
2153                         /*
2154                          * If the RX sense status indicates we're disconnected,
2155                          * clear the software rxsense status.
2156                          */
2157                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2158                                 hdmi->rxsense = false;
2159
2160                         /*
2161                          * Only set the software rxsense status when both
2162                          * rxsense and hpd indicates we're connected.
2163                          * This avoids what seems to be bad behaviour in
2164                          * at least iMX6S versions of the phy.
2165                          */
2166                         if (phy_stat & HDMI_PHY_HPD)
2167                                 hdmi->rxsense = true;
2168
2169                         dw_hdmi_update_power(hdmi);
2170                         dw_hdmi_update_phy_mask(hdmi);
2171                 }
2172                 mutex_unlock(&hdmi->mutex);
2173         }
2174
2175         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2176                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2177                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2178                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2179 #ifdef CONFIG_SWITCH
2180                 if (phy_int_pol & HDMI_PHY_HPD)
2181                         switch_set_state(&hdmi->switchdev, 1);
2182                 else
2183                         switch_set_state(&hdmi->switchdev, 0);
2184 #endif
2185         }
2186
2187         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2188         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2189                     HDMI_IH_MUTE_PHY_STAT0);
2190
2191         return IRQ_HANDLED;
2192 }
2193
2194 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2195 {
2196         struct drm_encoder *encoder = hdmi->encoder;
2197         struct drm_bridge *bridge;
2198         int ret;
2199
2200         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2201         if (!bridge) {
2202                 DRM_ERROR("Failed to allocate drm bridge\n");
2203                 return -ENOMEM;
2204         }
2205
2206         hdmi->bridge = bridge;
2207         bridge->driver_private = hdmi;
2208         bridge->funcs = &dw_hdmi_bridge_funcs;
2209         ret = drm_bridge_attach(drm, bridge);
2210         if (ret) {
2211                 DRM_ERROR("Failed to initialize bridge with drm\n");
2212                 return -EINVAL;
2213         }
2214
2215         encoder->bridge = bridge;
2216         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2217         hdmi->connector.port = hdmi->dev->of_node;
2218
2219         drm_connector_helper_add(&hdmi->connector,
2220                                  &dw_hdmi_connector_helper_funcs);
2221
2222         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2223                 drm_connector_init(drm, &hdmi->connector,
2224                                    &dw_hdmi_atomic_connector_funcs,
2225                                    DRM_MODE_CONNECTOR_HDMIA);
2226         else
2227                 drm_connector_init(drm, &hdmi->connector,
2228                                    &dw_hdmi_connector_funcs,
2229                                    DRM_MODE_CONNECTOR_HDMIA);
2230
2231         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2232
2233         return 0;
2234 }
2235
2236 #include <linux/fs.h>
2237 #include <linux/debugfs.h>
2238 #include <linux/seq_file.h>
2239
2240 struct dw_hdmi_reg_table {
2241         int reg_base;
2242         int reg_end;
2243 };
2244
2245 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
2246         {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
2247         {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
2248         {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
2249         {HDMI_VP_STATUS, HDMI_VP_POL},
2250         {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
2251         {HDMI_PHY_CONF0, HDMI_PHY_POL0},
2252         {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
2253         {HDMI_AUD_CONF0, 0x3624},
2254         {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
2255         {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
2256         {HDMI_A_HDCPCFG0, 0x52bb},
2257         {0x7800, 0x7818},
2258         {0x7900, 0x790e},
2259         {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
2260         {HDMI_I2CM_SLAVE, 0x7e31},
2261 };
2262
2263 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
2264 {
2265         struct dw_hdmi *hdmi = s->private;
2266         u32 i = 0, j = 0, val = 0;
2267
2268         seq_puts(s, "\n>>>hdmi_ctl reg ");
2269         for (i = 0; i < 16; i++)
2270                 seq_printf(s, " %2x", i);
2271         seq_puts(s, "\n---------------------------------------------------");
2272
2273         for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
2274                 for (j = hdmi_reg_table[i].reg_base;
2275                      j <= hdmi_reg_table[i].reg_end; j++) {
2276                         val = hdmi_readb(hdmi, j);
2277                         if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
2278                                 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
2279                         seq_printf(s, " %02x", val);
2280                 }
2281         }
2282         seq_puts(s, "\n---------------------------------------------------\n");
2283
2284         return 0;
2285 }
2286
2287 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
2288 {
2289         return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
2290 }
2291
2292 static ssize_t
2293 dw_hdmi_ctrl_write(struct file *file, const char __user *buf,
2294                    size_t count, loff_t *ppos)
2295 {
2296         struct dw_hdmi *hdmi =
2297                 ((struct seq_file *)file->private_data)->private;
2298         u32 reg, val;
2299         char kbuf[25];
2300
2301         if (copy_from_user(kbuf, buf, count))
2302                 return -EFAULT;
2303         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2304                 return -EFAULT;
2305         if ((reg < 0) || (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR)) {
2306                 dev_err(hdmi->dev, "it is no a hdmi register\n");
2307                 return count;
2308         }
2309         dev_info(hdmi->dev, "/**********hdmi register config******/");
2310         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2311         hdmi_writeb(hdmi, val, reg);
2312         return count;
2313 }
2314
2315 static const struct file_operations dw_hdmi_ctrl_fops = {
2316         .owner = THIS_MODULE,
2317         .open = dw_hdmi_ctrl_open,
2318         .read = seq_read,
2319         .write = dw_hdmi_ctrl_write,
2320         .llseek = seq_lseek,
2321         .release = single_release,
2322 };
2323
2324 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
2325 {
2326         struct dw_hdmi *hdmi = s->private;
2327         u32 i;
2328
2329         seq_puts(s, "\n>>>hdmi_phy reg ");
2330         for (i = 0; i < 0x28; i++)
2331                 seq_printf(s, "regs %02x val %04x\n",
2332                            i, hdmi_phy_i2c_read(hdmi, i));
2333         return 0;
2334 }
2335
2336 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
2337 {
2338         return single_open(file, dw_hdmi_phy_show, inode->i_private);
2339 }
2340
2341 static ssize_t
2342 dw_hdmi_phy_write(struct file *file, const char __user *buf,
2343                   size_t count, loff_t *ppos)
2344 {
2345         struct dw_hdmi *hdmi =
2346                 ((struct seq_file *)file->private_data)->private;
2347         u32 reg, val;
2348         char kbuf[25];
2349
2350         if (copy_from_user(kbuf, buf, count))
2351                 return -EFAULT;
2352         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2353                 return -EFAULT;
2354         if ((reg < 0) || (reg > 0x28)) {
2355                 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
2356                 return count;
2357         }
2358         dev_info(hdmi->dev, "/*******hdmi phy register config******/");
2359         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2360         hdmi_phy_i2c_write(hdmi, val, reg);
2361         return count;
2362 }
2363
2364 static const struct file_operations dw_hdmi_phy_fops = {
2365         .owner = THIS_MODULE,
2366         .open = dw_hdmi_phy_open,
2367         .read = seq_read,
2368         .write = dw_hdmi_phy_write,
2369         .llseek = seq_lseek,
2370         .release = single_release,
2371 };
2372
2373 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
2374 {
2375         struct dentry *debugfs_dir;
2376
2377         debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
2378         if (IS_ERR(debugfs_dir)) {
2379                 dev_err(dev, "failed to create debugfs dir!\n");
2380                 return;
2381         }
2382         debugfs_create_file("ctrl", 0400, debugfs_dir,
2383                             hdmi, &dw_hdmi_ctrl_fops);
2384         debugfs_create_file("phy", 0400, debugfs_dir,
2385                             hdmi, &dw_hdmi_phy_fops);
2386 }
2387
2388 int dw_hdmi_bind(struct device *dev, struct device *master,
2389                  void *data, struct drm_encoder *encoder,
2390                  struct resource *iores, int irq,
2391                  const struct dw_hdmi_plat_data *plat_data)
2392 {
2393         struct drm_device *drm = data;
2394         struct device_node *np = dev->of_node;
2395         struct platform_device_info pdevinfo;
2396         struct device_node *ddc_node;
2397         struct dw_hdmi *hdmi;
2398         int ret;
2399         u32 val = 1;
2400         u8 config0;
2401         u8 config1;
2402
2403         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2404         if (!hdmi)
2405                 return -ENOMEM;
2406
2407         hdmi->connector.interlace_allowed = 1;
2408         hdmi->connector.stereo_allowed = 1;
2409
2410         hdmi->plat_data = plat_data;
2411         hdmi->dev = dev;
2412         hdmi->dev_type = plat_data->dev_type;
2413         hdmi->sample_rate = 48000;
2414         hdmi->encoder = encoder;
2415         hdmi->disabled = true;
2416         hdmi->rxsense = true;
2417         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2418         hdmi->irq = irq;
2419
2420         mutex_init(&hdmi->mutex);
2421         mutex_init(&hdmi->audio_mutex);
2422         spin_lock_init(&hdmi->audio_lock);
2423
2424         of_property_read_u32(np, "reg-io-width", &val);
2425
2426         switch (val) {
2427         case 4:
2428                 hdmi->write = dw_hdmi_writel;
2429                 hdmi->read = dw_hdmi_readl;
2430                 break;
2431         case 1:
2432                 hdmi->write = dw_hdmi_writeb;
2433                 hdmi->read = dw_hdmi_readb;
2434                 break;
2435         default:
2436                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2437                 return -EINVAL;
2438         }
2439
2440         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2441         if (ddc_node) {
2442                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2443                 of_node_put(ddc_node);
2444                 if (!hdmi->ddc) {
2445                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2446                         return -EPROBE_DEFER;
2447                 }
2448
2449         } else {
2450                 dev_dbg(hdmi->dev, "no ddc property found\n");
2451         }
2452
2453         /* If DDC bus is not specified, try to register HDMI I2C bus */
2454         if (!hdmi->ddc) {
2455                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2456                 if (IS_ERR(hdmi->ddc))
2457                         hdmi->ddc = NULL;
2458                 /*
2459                  * Read high and low time from device tree. If not available use
2460                  * the default timing scl clock rate is about 99.6KHz.
2461                  */
2462                 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2463                                          &hdmi->i2c->scl_high_ns))
2464                         hdmi->i2c->scl_high_ns = 4708;
2465                 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2466                                          &hdmi->i2c->scl_low_ns))
2467                         hdmi->i2c->scl_low_ns = 4916;
2468         }
2469
2470         hdmi->regs = devm_ioremap_resource(dev, iores);
2471         if (IS_ERR(hdmi->regs))
2472                 return PTR_ERR(hdmi->regs);
2473
2474         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2475         if (IS_ERR(hdmi->isfr_clk)) {
2476                 ret = PTR_ERR(hdmi->isfr_clk);
2477                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2478                 return ret;
2479         }
2480
2481         ret = clk_prepare_enable(hdmi->isfr_clk);
2482         if (ret) {
2483                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2484                 return ret;
2485         }
2486
2487         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2488         if (IS_ERR(hdmi->iahb_clk)) {
2489                 ret = PTR_ERR(hdmi->iahb_clk);
2490                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2491                 goto err_isfr;
2492         }
2493
2494         ret = clk_prepare_enable(hdmi->iahb_clk);
2495         if (ret) {
2496                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2497                 goto err_isfr;
2498         }
2499
2500         /* Product and revision IDs */
2501         dev_info(dev,
2502                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2503                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2504                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2505                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2506                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2507
2508         initialize_hdmi_ih_mutes(hdmi);
2509
2510         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2511                                         dw_hdmi_irq, IRQF_SHARED,
2512                                         dev_name(dev), hdmi);
2513         if (ret)
2514                 goto err_iahb;
2515
2516         /*
2517          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2518          * N and cts values before enabling phy
2519          */
2520         hdmi_init_clk_regenerator(hdmi);
2521
2522         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2523                     HDMI_PHY_I2CM_INT_ADDR);
2524
2525         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2526                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2527                     HDMI_PHY_I2CM_CTLINT_ADDR);
2528
2529         /* Re-init HPD polarity */
2530         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2531
2532         /* Unmask HPD, clear transitory interrupts, then unmute */
2533         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2534
2535         ret = dw_hdmi_register(drm, hdmi);
2536         if (ret)
2537                 goto err_iahb;
2538
2539 #ifdef CONFIG_SWITCH
2540         hdmi->switchdev.name = "hdmi";
2541         switch_dev_register(&hdmi->switchdev);
2542 #endif
2543
2544         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2545                     HDMI_IH_MUTE_PHY_STAT0);
2546
2547         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2548         if (hdmi->i2c)
2549                 dw_hdmi_i2c_init(hdmi);
2550
2551         memset(&pdevinfo, 0, sizeof(pdevinfo));
2552         pdevinfo.parent = dev;
2553         pdevinfo.id = PLATFORM_DEVID_AUTO;
2554
2555         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2556         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2557
2558         if (config1 & HDMI_CONFIG1_AHB) {
2559                 struct dw_hdmi_audio_data audio;
2560
2561                 audio.phys = iores->start;
2562                 audio.base = hdmi->regs;
2563                 audio.irq = irq;
2564                 audio.hdmi = hdmi;
2565                 audio.eld = hdmi->connector.eld;
2566
2567                 pdevinfo.name = "dw-hdmi-ahb-audio";
2568                 pdevinfo.data = &audio;
2569                 pdevinfo.size_data = sizeof(audio);
2570                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2571                 hdmi->audio = platform_device_register_full(&pdevinfo);
2572         } else if (config0 & HDMI_CONFIG0_I2S) {
2573                 struct dw_hdmi_i2s_audio_data audio;
2574
2575                 audio.hdmi      = hdmi;
2576                 audio.write     = hdmi_writeb;
2577                 audio.read      = hdmi_readb;
2578
2579                 pdevinfo.name = "dw-hdmi-i2s-audio";
2580                 pdevinfo.data = &audio;
2581                 pdevinfo.size_data = sizeof(audio);
2582                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2583                 hdmi->audio = platform_device_register_full(&pdevinfo);
2584         }
2585
2586         dev_set_drvdata(dev, hdmi);
2587
2588         dw_hdmi_register_debugfs(dev, hdmi);
2589
2590         return 0;
2591
2592 err_iahb:
2593         if (hdmi->i2c)
2594                 i2c_del_adapter(&hdmi->i2c->adap);
2595
2596         clk_disable_unprepare(hdmi->iahb_clk);
2597 err_isfr:
2598         clk_disable_unprepare(hdmi->isfr_clk);
2599
2600         return ret;
2601 }
2602 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2603
2604 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2605 {
2606         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2607
2608         if (hdmi->audio && !IS_ERR(hdmi->audio))
2609                 platform_device_unregister(hdmi->audio);
2610
2611         /* Disable all interrupts */
2612         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2613
2614 #ifdef CONFIG_SWITCH
2615         switch_dev_unregister(&hdmi->switchdev);
2616 #endif
2617         hdmi->connector.funcs->destroy(&hdmi->connector);
2618         hdmi->encoder->funcs->destroy(hdmi->encoder);
2619
2620         clk_disable_unprepare(hdmi->iahb_clk);
2621         clk_disable_unprepare(hdmi->isfr_clk);
2622
2623         if (hdmi->i2c)
2624                 i2c_del_adapter(&hdmi->i2c->adap);
2625         else
2626                 i2c_put_adapter(hdmi->ddc);
2627 }
2628 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2629
2630 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2631 {
2632         if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2633                 initialize_hdmi_ih_mutes(hdmi);
2634                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2635                             HDMI_PHY_I2CM_INT_ADDR);
2636
2637                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2638                             HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2639                             HDMI_PHY_I2CM_CTLINT_ADDR);
2640
2641                 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2642                             HDMI_PHY_POL0);
2643                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2644                 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2645                             HDMI_IH_PHY_STAT0_RX_SENSE),
2646                             HDMI_IH_MUTE_PHY_STAT0);
2647         }
2648 }
2649
2650 void dw_hdmi_suspend(struct device *dev)
2651 {
2652         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2653
2654         mutex_lock(&hdmi->mutex);
2655         if (hdmi->irq)
2656                 disable_irq(hdmi->irq);
2657         mutex_unlock(&hdmi->mutex);
2658 }
2659 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2660
2661 void dw_hdmi_resume(struct device *dev)
2662 {
2663         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2664
2665         mutex_lock(&hdmi->mutex);
2666         dw_hdmi_reg_initial(hdmi);
2667         if (hdmi->i2c)
2668                 dw_hdmi_i2c_init(hdmi);
2669         if (hdmi->irq)
2670                 enable_irq(hdmi->irq);
2671         mutex_unlock(&hdmi->mutex);
2672 }
2673 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2674
2675 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2676 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2677 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2678 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2679 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2680 MODULE_LICENSE("GPL");
2681 MODULE_ALIAS("platform:dw-hdmi");