drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/bridge/dw_hdmi.h>
  33
  34 #include "dw-hdmi.h"
  35 #include "dw-hdmi-audio.h"
  36
  37 #define HDMI_EDID_LEN           512
  38
  39 #define RGB                     0
  40 #define YCBCR444                1
  41 #define YCBCR422_16BITS         2
  42 #define YCBCR422_8BITS          3
  43 #define XVYCC444                4
  44
  45 enum hdmi_datamap {
  46         RGB444_8B = 0x01,
  47         RGB444_10B = 0x03,
  48         RGB444_12B = 0x05,
  49         RGB444_16B = 0x07,
  50         YCbCr444_8B = 0x09,
  51         YCbCr444_10B = 0x0B,
  52         YCbCr444_12B = 0x0D,
  53         YCbCr444_16B = 0x0F,
  54         YCbCr422_8B = 0x16,
  55         YCbCr422_10B = 0x14,
  56         YCbCr422_12B = 0x12,
  57 };
  58
  59 /*
  60  * Unless otherwise noted, entries in this table are 100% optimization.
  61  * Values can be obtained from hdmi_compute_n() but that function is
  62  * slow so we pre-compute values we expect to see.
  63  *
  64  * All 32k and 48k values are expected to be the same (due to the way
  65  * the math works) for any rate that's an exact kHz.
  66  */
  67 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  68         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  69         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  70         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  71         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  72         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  73         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  74         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  75         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  76         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  77         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  78         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  79         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  80         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  81         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  82         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  83         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  84         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  85         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  86         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  87         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  88         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  89         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  90         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  91         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  92         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  93         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  94         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  95         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  96         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  97         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  98         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
  99         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 100         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 101         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 102         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 103         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 104         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 105
 106         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 107         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 108         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 109
 110         /* End of table */
 111         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 112 };
 113
 114
 115 static const u16 csc_coeff_default[3][4] = {
 116         { 0x2000, 0x0000, 0x0000, 0x0000 },
 117         { 0x0000, 0x2000, 0x0000, 0x0000 },
 118         { 0x0000, 0x0000, 0x2000, 0x0000 }
 119 };
 120
 121 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 122         { 0x2000, 0x6926, 0x74fd, 0x010e },
 123         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 124         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 125 };
 126
 127 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 128         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 129         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 130         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 131 };
 132
 133 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 134         { 0x2591, 0x1322, 0x074b, 0x0000 },
 135         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 136         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 137 };
 138
 139 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 140         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 141         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 142         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 143 };
 144
 145 struct hdmi_vmode {
 146         bool mdataenablepolarity;
 147
 148         unsigned int mpixelclock;
 149         unsigned int mpixelrepetitioninput;
 150         unsigned int mpixelrepetitionoutput;
 151 };
 152
 153 struct hdmi_data_info {
 154         unsigned int enc_in_format;
 155         unsigned int enc_out_format;
 156         unsigned int enc_color_depth;
 157         unsigned int colorimetry;
 158         unsigned int pix_repet_factor;
 159         unsigned int hdcp_enable;
 160         struct hdmi_vmode video_mode;
 161 };
 162
 163 struct dw_hdmi_i2c {
 164         struct i2c_adapter      adap;
 165
 166         struct mutex            lock;
 167         struct completion       cmp;
 168         u8                      stat;
 169
 170         u8                      slave_reg;
 171         bool                    is_regaddr;
 172 };
 173
 174 struct dw_hdmi {
 175         struct drm_connector connector;
 176         struct drm_encoder *encoder;
 177         struct drm_bridge *bridge;
 178
 179         struct platform_device *audio;
 180         enum dw_hdmi_devtype dev_type;
 181         struct device *dev;
 182         struct clk *isfr_clk;
 183         struct clk *iahb_clk;
 184         struct dw_hdmi_i2c *i2c;
 185
 186         struct hdmi_data_info hdmi_data;
 187         const struct dw_hdmi_plat_data *plat_data;
 188
 189         int vic;
 190
 191         u8 edid[HDMI_EDID_LEN];
 192         bool cable_plugin;
 193
 194         bool phy_enabled;
 195         struct drm_display_mode previous_mode;
 196
 197         struct i2c_adapter *ddc;
 198         void __iomem *regs;
 199         bool sink_is_hdmi;
 200         bool sink_has_audio;
 201
 202         struct mutex mutex;             /* for state below and previous_mode */
 203         enum drm_connector_force force; /* mutex-protected force state */
 204         bool disabled;                  /* DRM has disabled our bridge */
 205         bool bridge_is_on;              /* indicates the bridge is on */
 206         bool rxsense;                   /* rxsense state */
 207         u8 phy_mask;                    /* desired phy int mask settings */
 208
 209         spinlock_t audio_lock;
 210         struct mutex audio_mutex;
 211         unsigned int sample_rate;
 212         unsigned int audio_cts;
 213         unsigned int audio_n;
 214         bool audio_enable;
 215
 216         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 217         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 218 };
 219
 220 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 221         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 222          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 223
 224 #define HDMI_PHY_RX_SENSE \
 225         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 226          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 227
 228 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 229 {
 230         writel(val, hdmi->regs + (offset << 2));
 231 }
 232
 233 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 234 {
 235         return readl(hdmi->regs + (offset << 2));
 236 }
 237
 238 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 239 {
 240         writeb(val, hdmi->regs + offset);
 241 }
 242
 243 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 244 {
 245         return readb(hdmi->regs + offset);
 246 }
 247
 248 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 249 {
 250         hdmi->write(hdmi, val, offset);
 251 }
 252
 253 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 254 {
 255         return hdmi->read(hdmi, offset);
 256 }
 257
 258 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 259 {
 260         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 261
 262         val |= data & mask;
 263         hdmi_writeb(hdmi, val, reg);
 264 }
 265
 266 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 267                              u8 shift, u8 mask)
 268 {
 269         hdmi_modb(hdmi, data << shift, mask, reg);
 270 }
 271
 272 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 273 {
 274         /* Set Fast Mode speed */
 275         hdmi_writeb(hdmi, 0x0b, HDMI_I2CM_DIV);
 276
 277         /* Software reset */
 278         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 279
 280         /* Set done, not acknowledged and arbitration interrupt polarities */
 281         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 282         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 283                     HDMI_I2CM_CTLINT);
 284
 285         /* Clear DONE and ERROR interrupts */
 286         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 287                     HDMI_IH_I2CM_STAT0);
 288
 289         /* Mute DONE and ERROR interrupts */
 290         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 291                     HDMI_IH_MUTE_I2CM_STAT0);
 292 }
 293
 294 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 295                             unsigned char *buf, unsigned int length)
 296 {
 297         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 298         int stat;
 299
 300         if (!i2c->is_regaddr) {
 301                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 302                 i2c->slave_reg = 0x00;
 303                 i2c->is_regaddr = true;
 304         }
 305
 306         while (length--) {
 307                 reinit_completion(&i2c->cmp);
 308
 309                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 310                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 311                             HDMI_I2CM_OPERATION);
 312
 313                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 314                 if (!stat)
 315                         return -EAGAIN;
 316
 317                 /* Check for error condition on the bus */
 318                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 319                         return -EIO;
 320
 321                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 328                              unsigned char *buf, unsigned int length)
 329 {
 330         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 331         int stat;
 332
 333         if (!i2c->is_regaddr) {
 334                 /* Use the first write byte as register address */
 335                 i2c->slave_reg = buf[0];
 336                 length--;
 337                 buf++;
 338                 i2c->is_regaddr = true;
 339         }
 340
 341         while (length--) {
 342                 reinit_completion(&i2c->cmp);
 343
 344                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 345                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 346                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 347                             HDMI_I2CM_OPERATION);
 348
 349         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 350                 if (!stat)
 351                         return -EAGAIN;
 352
 353                 /* Check for error condition on the bus */
 354                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 355                         return -EIO;
 356         }
 357
 358         return 0;
 359 }
 360
 361 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 362                             struct i2c_msg *msgs, int num)
 363 {
 364         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 365         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 366         u8 addr = msgs[0].addr;
 367         int i, ret = 0;
 368
 369         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 370
 371         for (i = 0; i < num; i++) {
 372                 if (msgs[i].addr != addr) {
 373                         dev_warn(hdmi->dev,
 374                                  "unsupported transfer, changed slave address\n");
 375                         return -EOPNOTSUPP;
 376                 }
 377
 378                 if (msgs[i].len == 0) {
 379                         dev_dbg(hdmi->dev,
 380                                 "unsupported transfer %d/%d, no data\n",
 381                                 i + 1, num);
 382                         return -EOPNOTSUPP;
 383                 }
 384         }
 385
 386         mutex_lock(&i2c->lock);
 387
 388         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 389
 390         /* Set slave device address taken from the first I2C message */
 391         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 392
 393         /* Set slave device register address on transfer */
 394         i2c->is_regaddr = false;
 395
 396         for (i = 0; i < num; i++) {
 397                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 398                         i + 1, num, msgs[i].len, msgs[i].flags);
 399
 400                 if (msgs[i].flags & I2C_M_RD)
 401                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 402                 else
 403                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 404
 405                 if (ret < 0)
 406                         break;
 407         }
 408
 409         if (!ret)
 410                 ret = num;
 411
 412         /* Mute DONE and ERROR interrupts */
 413         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 414                     HDMI_IH_MUTE_I2CM_STAT0);
 415
 416         mutex_unlock(&i2c->lock);
 417
 418         return ret;
 419 }
 420
 421 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 422 {
 423         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 424 }
 425
 426 static const struct i2c_algorithm dw_hdmi_algorithm = {
 427         .master_xfer    = dw_hdmi_i2c_xfer,
 428         .functionality  = dw_hdmi_i2c_func,
 429 };
 430
 431 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 432 {
 433         struct i2c_adapter *adap;
 434         struct dw_hdmi_i2c *i2c;
 435         int ret;
 436
 437         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 438         if (!i2c)
 439                 return ERR_PTR(-ENOMEM);
 440
 441         mutex_init(&i2c->lock);
 442         init_completion(&i2c->cmp);
 443
 444         adap = &i2c->adap;
 445         adap->class = I2C_CLASS_DDC;
 446         adap->owner = THIS_MODULE;
 447         adap->dev.parent = hdmi->dev;
 448         adap->algo = &dw_hdmi_algorithm;
 449         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 450         i2c_set_adapdata(adap, hdmi);
 451
 452         ret = i2c_add_adapter(adap);
 453         if (ret) {
 454                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 455                 devm_kfree(hdmi->dev, i2c);
 456                 return ERR_PTR(ret);
 457         }
 458
 459         hdmi->i2c = i2c;
 460
 461         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 462
 463         return adap;
 464 }
 465
 466 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 467                            unsigned int n)
 468 {
 469         /* Must be set/cleared first */
 470         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 471
 472         /* nshift factor = 0 */
 473         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 474
 475         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 476                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 477         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 478         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 479
 480         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 481         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 482         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 483 }
 484
 485 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 486                                    unsigned long pixel_clk,
 487                                    unsigned long freq)
 488 {
 489         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 490         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 491         int i;
 492
 493         if (plat_data->tmds_n_table) {
 494                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 495                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 496                                 tmds_n = &plat_data->tmds_n_table[i];
 497                                 break;
 498                         }
 499                 }
 500         }
 501
 502         if (tmds_n == NULL) {
 503                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 504                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 505                                 tmds_n = &common_tmds_n_table[i];
 506                                 break;
 507                         }
 508                 }
 509         }
 510
 511         if (tmds_n == NULL)
 512                 return -ENOENT;
 513
 514         switch (freq) {
 515         case 32000:
 516                 return tmds_n->n_32k;
 517         case 44100:
 518         case 88200:
 519         case 176400:
 520                 return (freq / 44100) * tmds_n->n_44k1;
 521         case 48000:
 522         case 96000:
 523         case 192000:
 524                 return (freq / 48000) * tmds_n->n_48k;
 525         default:
 526                 return -ENOENT;
 527         }
 528 }
 529
 530 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 531                                 unsigned int pixel_clk)
 532 {
 533         u64 final, diff;
 534         u64 cts;
 535
 536         final = (u64)pixel_clk * n;
 537
 538         cts = final;
 539         do_div(cts, 128 * freq);
 540
 541         diff = final - (u64)cts * (128 * freq);
 542
 543         return diff;
 544 }
 545
 546 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 547                                    unsigned long pixel_clk,
 548                                    unsigned long freq)
 549 {
 550         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 551         unsigned int max_n = (128 * freq) / 300;
 552         unsigned int ideal_n = (128 * freq) / 1000;
 553         unsigned int best_n_distance = ideal_n;
 554         unsigned int best_n = 0;
 555         u64 best_diff = U64_MAX;
 556         int n;
 557
 558         /* If the ideal N could satisfy the audio math, then just take it */
 559         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 560                 return ideal_n;
 561
 562         for (n = min_n; n <= max_n; n++) {
 563                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 564
 565                 if (diff < best_diff || (diff == best_diff &&
 566                     abs(n - ideal_n) < best_n_distance)) {
 567                         best_n = n;
 568                         best_diff = diff;
 569                         best_n_distance = abs(best_n - ideal_n);
 570                 }
 571
 572                 /*
 573                  * The best N already satisfy the audio math, and also be
 574                  * the closest value to ideal N, so just cut the loop.
 575                  */
 576                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 577                         break;
 578         }
 579
 580         return best_n;
 581 }
 582
 583 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 584                                 unsigned long sample_rate)
 585 {
 586         int n;
 587
 588         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 589         if (n > 0)
 590                 return n;
 591
 592         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 593                  pixel_clk);
 594
 595         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 596 }
 597
 598 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 599         unsigned long pixel_clk, unsigned int sample_rate)
 600 {
 601         unsigned long ftdms = pixel_clk;
 602         unsigned int n, cts;
 603         u64 tmp;
 604
 605         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 606
 607         /*
 608          * Compute the CTS value from the N value.  Note that CTS and N
 609          * can be up to 20 bits in total, so we need 64-bit math.  Also
 610          * note that our TDMS clock is not fully accurate; it is accurate
 611          * to kHz.  This can introduce an unnecessary remainder in the
 612          * calculation below, so we don't try to warn about that.
 613          */
 614         tmp = (u64)ftdms * n;
 615         do_div(tmp, 128 * sample_rate);
 616         cts = tmp;
 617
 618         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 619                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 620                 n, cts);
 621
 622         spin_lock_irq(&hdmi->audio_lock);
 623         hdmi->audio_n = n;
 624         hdmi->audio_cts = cts;
 625         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 626         spin_unlock_irq(&hdmi->audio_lock);
 627 }
 628
 629 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 630 {
 631         mutex_lock(&hdmi->audio_mutex);
 632         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 633         mutex_unlock(&hdmi->audio_mutex);
 634 }
 635
 636 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 637 {
 638         mutex_lock(&hdmi->audio_mutex);
 639         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 640                                  hdmi->sample_rate);
 641         mutex_unlock(&hdmi->audio_mutex);
 642 }
 643
 644 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 645 {
 646         mutex_lock(&hdmi->audio_mutex);
 647         hdmi->sample_rate = rate;
 648         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 649                                  hdmi->sample_rate);
 650         mutex_unlock(&hdmi->audio_mutex);
 651 }
 652 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 653
 654 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 655 {
 656         unsigned long flags;
 657
 658         spin_lock_irqsave(&hdmi->audio_lock, flags);
 659         hdmi->audio_enable = true;
 660         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 661         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 662 }
 663 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 664
 665 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 666 {
 667         unsigned long flags;
 668
 669         spin_lock_irqsave(&hdmi->audio_lock, flags);
 670         hdmi->audio_enable = false;
 671         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 672         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 673 }
 674 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 675
 676 /*
 677  * this submodule is responsible for the video data synchronization.
 678  * for example, for RGB 4:4:4 input, the data map is defined as
 679  *                      pin{47~40} <==> R[7:0]
 680  *                      pin{31~24} <==> G[7:0]
 681  *                      pin{15~8}  <==> B[7:0]
 682  */
 683 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 684 {
 685         int color_format = 0;
 686         u8 val;
 687
 688         if (hdmi->hdmi_data.enc_in_format == RGB) {
 689                 if (hdmi->hdmi_data.enc_color_depth == 8)
 690                         color_format = 0x01;
 691                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 692                         color_format = 0x03;
 693                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 694                         color_format = 0x05;
 695                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 696                         color_format = 0x07;
 697                 else
 698                         return;
 699         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 700                 if (hdmi->hdmi_data.enc_color_depth == 8)
 701                         color_format = 0x09;
 702                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 703                         color_format = 0x0B;
 704                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 705                         color_format = 0x0D;
 706                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 707                         color_format = 0x0F;
 708                 else
 709                         return;
 710         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 711                 if (hdmi->hdmi_data.enc_color_depth == 8)
 712                         color_format = 0x16;
 713                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 714                         color_format = 0x14;
 715                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 716                         color_format = 0x12;
 717                 else
 718                         return;
 719         }
 720
 721         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 722                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 723                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 724         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 725
 726         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 727         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 728                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 729                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 730         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 731         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 732         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 733         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 734         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 735         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 736         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 737 }
 738
 739 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 740 {
 741         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 742 }
 743
 744 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 745 {
 746         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 747                 return 0;
 748         if (hdmi->hdmi_data.enc_in_format == RGB ||
 749             hdmi->hdmi_data.enc_in_format == YCBCR444)
 750                 return 1;
 751         return 0;
 752 }
 753
 754 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 755 {
 756         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 757                 return 0;
 758         if (hdmi->hdmi_data.enc_out_format == RGB ||
 759             hdmi->hdmi_data.enc_out_format == YCBCR444)
 760                 return 1;
 761         return 0;
 762 }
 763
 764 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 765 {
 766         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 767         unsigned i;
 768         u32 csc_scale = 1;
 769
 770         if (is_color_space_conversion(hdmi)) {
 771                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 772                         if (hdmi->hdmi_data.colorimetry ==
 773                                         HDMI_COLORIMETRY_ITU_601)
 774                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 775                         else
 776                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 777                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 778                         if (hdmi->hdmi_data.colorimetry ==
 779                                         HDMI_COLORIMETRY_ITU_601)
 780                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 781                         else
 782                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 783                         csc_scale = 0;
 784                 }
 785         }
 786
 787         /* The CSC registers are sequential, alternating MSB then LSB */
 788         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 789                 u16 coeff_a = (*csc_coeff)[0][i];
 790                 u16 coeff_b = (*csc_coeff)[1][i];
 791                 u16 coeff_c = (*csc_coeff)[2][i];
 792
 793                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 794                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 795                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 796                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 797                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 798                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 799         }
 800
 801         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 802                   HDMI_CSC_SCALE);
 803 }
 804
 805 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 806 {
 807         int color_depth = 0;
 808         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 809         int decimation = 0;
 810
 811         /* YCC422 interpolation to 444 mode */
 812         if (is_color_space_interpolation(hdmi))
 813                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 814         else if (is_color_space_decimation(hdmi))
 815                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 816
 817         if (hdmi->hdmi_data.enc_color_depth == 8)
 818                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 819         else if (hdmi->hdmi_data.enc_color_depth == 10)
 820                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 821         else if (hdmi->hdmi_data.enc_color_depth == 12)
 822                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 823         else if (hdmi->hdmi_data.enc_color_depth == 16)
 824                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 825         else
 826                 return;
 827
 828         /* Configure the CSC registers */
 829         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 830         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 831                   HDMI_CSC_SCALE);
 832
 833         dw_hdmi_update_csc_coeffs(hdmi);
 834 }
 835
 836 /*
 837  * HDMI video packetizer is used to packetize the data.
 838  * for example, if input is YCC422 mode or repeater is used,
 839  * data should be repacked this module can be bypassed.
 840  */
 841 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 842 {
 843         unsigned int color_depth = 0;
 844         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 845         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 846         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 847         u8 val, vp_conf;
 848
 849         if (hdmi_data->enc_out_format == RGB ||
 850             hdmi_data->enc_out_format == YCBCR444) {
 851                 if (!hdmi_data->enc_color_depth) {
 852                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 853                 } else if (hdmi_data->enc_color_depth == 8) {
 854                         color_depth = 4;
 855                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 856                 } else if (hdmi_data->enc_color_depth == 10) {
 857                         color_depth = 5;
 858                 } else if (hdmi_data->enc_color_depth == 12) {
 859                         color_depth = 6;
 860                 } else if (hdmi_data->enc_color_depth == 16) {
 861                         color_depth = 7;
 862                 } else {
 863                         return;
 864                 }
 865         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 866                 if (!hdmi_data->enc_color_depth ||
 867                     hdmi_data->enc_color_depth == 8)
 868                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 869                 else if (hdmi_data->enc_color_depth == 10)
 870                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 871                 else if (hdmi_data->enc_color_depth == 12)
 872                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 873                 else
 874                         return;
 875                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 876         } else {
 877                 return;
 878         }
 879
 880         /* set the packetizer registers */
 881         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 882                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 883                 ((hdmi_data->pix_repet_factor <<
 884                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 885                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 886         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 887
 888         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 889                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 890
 891         /* Data from pixel repeater block */
 892         if (hdmi_data->pix_repet_factor > 1) {
 893                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 894                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 895         } else { /* data from packetizer block */
 896                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 897                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 898         }
 899
 900         hdmi_modb(hdmi, vp_conf,
 901                   HDMI_VP_CONF_PR_EN_MASK |
 902                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 903
 904         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 905                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 906
 907         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 908
 909         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 910                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 911                           HDMI_VP_CONF_PP_EN_ENABLE |
 912                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 913         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 914                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 915                           HDMI_VP_CONF_PP_EN_DISABLE |
 916                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 917         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 918                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 919                           HDMI_VP_CONF_PP_EN_DISABLE |
 920                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 921         } else {
 922                 return;
 923         }
 924
 925         hdmi_modb(hdmi, vp_conf,
 926                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 927                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 928
 929         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 930                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 931                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 932                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 933
 934         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 935                   HDMI_VP_CONF);
 936 }
 937
 938 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 939                                        unsigned char bit)
 940 {
 941         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 942                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 943 }
 944
 945 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 946                                         unsigned char bit)
 947 {
 948         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 949                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 950 }
 951
 952 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 953                                        unsigned char bit)
 954 {
 955         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 956                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 957 }
 958
 959 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 960                                      unsigned char bit)
 961 {
 962         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 963 }
 964
 965 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 966                                       unsigned char bit)
 967 {
 968         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 969 }
 970
 971 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 972 {
 973         u32 val;
 974
 975         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 976                 if (msec-- == 0)
 977                         return false;
 978                 udelay(1000);
 979         }
 980         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 981
 982         return true;
 983 }
 984
 985 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 986                                  unsigned char addr)
 987 {
 988         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 989         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 990         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 991                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 992         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 993                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 994         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 995                     HDMI_PHY_I2CM_OPERATION_ADDR);
 996         hdmi_phy_wait_i2c_done(hdmi, 1000);
 997 }
 998
 999 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1000                               unsigned char addr)
1001 {
1002         __hdmi_phy_i2c_write(hdmi, data, addr);
1003         return 0;
1004 }
1005
1006 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1007 {
1008         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1009                          HDMI_PHY_CONF0_PDZ_OFFSET,
1010                          HDMI_PHY_CONF0_PDZ_MASK);
1011 }
1012
1013 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1014 {
1015         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1016                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1017                          HDMI_PHY_CONF0_ENTMDS_MASK);
1018 }
1019
1020 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1021 {
1022         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1023                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1024                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1025 }
1026
1027 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1028 {
1029         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1030                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1031                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1032 }
1033
1034 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1035 {
1036         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1037                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1038                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1039 }
1040
1041 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1042 {
1043         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1044                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1045                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1046 }
1047
1048 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1049 {
1050         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1051                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1052                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1053 }
1054
1055 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1056                               unsigned char res, int cscon)
1057 {
1058         unsigned res_idx;
1059         u8 val, msec;
1060         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1061         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1062         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1063         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1064
1065         if (prep)
1066                 return -EINVAL;
1067
1068         switch (res) {
1069         case 0: /* color resolution 0 is 8 bit colour depth */
1070         case 8:
1071                 res_idx = DW_HDMI_RES_8;
1072                 break;
1073         case 10:
1074                 res_idx = DW_HDMI_RES_10;
1075                 break;
1076         case 12:
1077                 res_idx = DW_HDMI_RES_12;
1078                 break;
1079         default:
1080                 return -EINVAL;
1081         }
1082
1083         /* PLL/MPLL Cfg - always match on final entry */
1084         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1085                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1086                     mpll_config->mpixelclock)
1087                         break;
1088
1089         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1090                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1091                     curr_ctrl->mpixelclock)
1092                         break;
1093
1094         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1095                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1096                     phy_config->mpixelclock)
1097                         break;
1098
1099         if (mpll_config->mpixelclock == ~0UL ||
1100             curr_ctrl->mpixelclock == ~0UL ||
1101             phy_config->mpixelclock == ~0UL) {
1102                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1103                         hdmi->hdmi_data.video_mode.mpixelclock);
1104                 return -EINVAL;
1105         }
1106
1107         /* Enable csc path */
1108         if (cscon)
1109                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1110         else
1111                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1112
1113         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1114
1115         /* gen2 tx power off */
1116         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1117
1118         /* gen2 pddq */
1119         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1120
1121         /* PHY reset */
1122         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1123         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1124
1125         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1126
1127         hdmi_phy_test_clear(hdmi, 1);
1128         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1129                     HDMI_PHY_I2CM_SLAVE_ADDR);
1130         hdmi_phy_test_clear(hdmi, 0);
1131
1132         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1133         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1134
1135         /* CURRCTRL */
1136         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1137
1138         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1139         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1140
1141         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1142         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1143         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1144
1145         /* REMOVE CLK TERM */
1146         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1147
1148         dw_hdmi_phy_enable_powerdown(hdmi, false);
1149
1150         /* toggle TMDS enable */
1151         dw_hdmi_phy_enable_tmds(hdmi, 0);
1152         dw_hdmi_phy_enable_tmds(hdmi, 1);
1153
1154         /* gen2 tx power on */
1155         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1156         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1157
1158         if (is_rockchip(hdmi->dev_type))
1159                 dw_hdmi_phy_enable_spare(hdmi, 1);
1160
1161         /*Wait for PHY PLL lock */
1162         msec = 5;
1163         do {
1164                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1165                 if (!val)
1166                         break;
1167
1168                 if (msec == 0) {
1169                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1170                         return -ETIMEDOUT;
1171                 }
1172
1173                 udelay(1000);
1174                 msec--;
1175         } while (1);
1176
1177         return 0;
1178 }
1179
1180 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1181 {
1182         int i, ret;
1183         bool cscon;
1184
1185         /*check csc whether needed activated in HDMI mode */
1186         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1187
1188         /* HDMI Phy spec says to do the phy initialization sequence twice */
1189         for (i = 0; i < 2; i++) {
1190                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1191                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1192                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1193                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1194
1195                 /* Enable CSC */
1196                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1197                 if (ret)
1198                         return ret;
1199         }
1200
1201         hdmi->phy_enabled = true;
1202         return 0;
1203 }
1204
1205 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1206 {
1207         u8 de;
1208
1209         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1210                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1211         else
1212                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1213
1214         /* disable rx detect */
1215         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1216                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1217
1218         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1219
1220         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1221                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1222 }
1223
1224 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1225 {
1226         struct hdmi_avi_infoframe frame;
1227         u8 val;
1228
1229         /* Initialise info frame from DRM mode */
1230         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1231
1232         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1233                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1234         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1235                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1236         else
1237                 frame.colorspace = HDMI_COLORSPACE_RGB;
1238
1239         /* Set up colorimetry */
1240         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1241                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1242                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1243                         frame.extended_colorimetry =
1244                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1245                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1246                         frame.extended_colorimetry =
1247                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1248         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1249                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1250                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1251         } else { /* Carries no data */
1252                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1253                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1254         }
1255
1256         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1257
1258         /*
1259          * The Designware IP uses a different byte format from standard
1260          * AVI info frames, though generally the bits are in the correct
1261          * bytes.
1262          */
1263
1264         /*
1265          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1266          * active aspect present in bit 6 rather than 4.
1267          */
1268         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1269         if (frame.active_aspect & 15)
1270                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1271         if (frame.top_bar || frame.bottom_bar)
1272                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1273         if (frame.left_bar || frame.right_bar)
1274                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1275         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1276
1277         /* AVI data byte 2 differences: none */
1278         val = ((frame.colorimetry & 0x3) << 6) |
1279               ((frame.picture_aspect & 0x3) << 4) |
1280               (frame.active_aspect & 0xf);
1281         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1282
1283         /* AVI data byte 3 differences: none */
1284         val = ((frame.extended_colorimetry & 0x7) << 4) |
1285               ((frame.quantization_range & 0x3) << 2) |
1286               (frame.nups & 0x3);
1287         if (frame.itc)
1288                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1289         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1290
1291         /* AVI data byte 4 differences: none */
1292         val = frame.video_code & 0x7f;
1293         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1294
1295         /* AVI Data Byte 5- set up input and output pixel repetition */
1296         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1297                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1298                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1299                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1300                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1301                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1302         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1303
1304         /*
1305          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1306          * ycc range in bits 2,3 rather than 6,7
1307          */
1308         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1309               (frame.content_type & 0x3);
1310         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1311
1312         /* AVI Data Bytes 6-13 */
1313         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1314         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1315         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1316         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1317         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1318         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1319         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1320         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1321 }
1322
1323 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1324                              const struct drm_display_mode *mode)
1325 {
1326         u8 inv_val;
1327         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1328         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1329         unsigned int vdisplay;
1330
1331         vmode->mpixelclock = mode->clock * 1000;
1332
1333         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1334
1335         /* Set up HDMI_FC_INVIDCONF */
1336         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1337                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1338                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1339
1340         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1341                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1342                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1343
1344         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1345                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1346                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1347
1348         inv_val |= (vmode->mdataenablepolarity ?
1349                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1350                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1351
1352         if (hdmi->vic == 39)
1353                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1354         else
1355                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1356                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1357                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1358
1359         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1360                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1361                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1362
1363         inv_val |= hdmi->sink_is_hdmi ?
1364                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1365                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1366
1367         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1368
1369         vdisplay = mode->vdisplay;
1370         vblank = mode->vtotal - mode->vdisplay;
1371         v_de_vs = mode->vsync_start - mode->vdisplay;
1372         vsync_len = mode->vsync_end - mode->vsync_start;
1373
1374         /*
1375          * When we're setting an interlaced mode, we need
1376          * to adjust the vertical timing to suit.
1377          */
1378         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1379                 vdisplay /= 2;
1380                 vblank /= 2;
1381                 v_de_vs /= 2;
1382                 vsync_len /= 2;
1383         }
1384
1385         /* Set up horizontal active pixel width */
1386         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1387         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1388
1389         /* Set up vertical active lines */
1390         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1391         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1392
1393         /* Set up horizontal blanking pixel region width */
1394         hblank = mode->htotal - mode->hdisplay;
1395         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1396         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1397
1398         /* Set up vertical blanking pixel region width */
1399         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1400
1401         /* Set up HSYNC active edge delay width (in pixel clks) */
1402         h_de_hs = mode->hsync_start - mode->hdisplay;
1403         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1404         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1405
1406         /* Set up VSYNC active edge delay (in lines) */
1407         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1408
1409         /* Set up HSYNC active pulse width (in pixel clks) */
1410         hsync_len = mode->hsync_end - mode->hsync_start;
1411         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1412         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1413
1414         /* Set up VSYNC active edge delay (in lines) */
1415         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1416 }
1417
1418 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1419 {
1420         if (!hdmi->phy_enabled)
1421                 return;
1422
1423         dw_hdmi_phy_enable_tmds(hdmi, 0);
1424         dw_hdmi_phy_enable_powerdown(hdmi, true);
1425
1426         hdmi->phy_enabled = false;
1427 }
1428
1429 /* HDMI Initialization Step B.4 */
1430 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1431 {
1432         u8 clkdis;
1433
1434         /* control period minimum duration */
1435         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1436         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1437         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1438
1439         /* Set to fill TMDS data channels */
1440         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1441         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1442         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1443
1444         /* Enable pixel clock and tmds data path */
1445         clkdis = 0x7F;
1446         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1447         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1448
1449         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1450         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1451
1452         /* Enable csc path */
1453         if (is_color_space_conversion(hdmi)) {
1454                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1455                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1456         }
1457 }
1458
1459 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1460 {
1461         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1462 }
1463
1464 /* Workaround to clear the overflow condition */
1465 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1466 {
1467         int count;
1468         u8 val;
1469
1470         /* TMDS software reset */
1471         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1472
1473         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1474         if (hdmi->dev_type == IMX6DL_HDMI) {
1475                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1476                 return;
1477         }
1478
1479         for (count = 0; count < 4; count++)
1480                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1481 }
1482
1483 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1484 {
1485         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1486         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1487 }
1488
1489 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1490 {
1491         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1492                     HDMI_IH_MUTE_FC_STAT2);
1493 }
1494
1495 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1496 {
1497         int ret;
1498
1499         hdmi_disable_overflow_interrupts(hdmi);
1500
1501         hdmi->vic = drm_match_cea_mode(mode);
1502
1503         if (!hdmi->vic) {
1504                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1505         } else {
1506                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1507         }
1508
1509         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1510             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1511             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1512             (hdmi->vic == 17) || (hdmi->vic == 18))
1513                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1514         else
1515                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1516
1517         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1518         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1519
1520         /* TODO: Get input format from IPU (via FB driver interface) */
1521         hdmi->hdmi_data.enc_in_format = RGB;
1522
1523         hdmi->hdmi_data.enc_out_format = RGB;
1524
1525         hdmi->hdmi_data.enc_color_depth = 8;
1526         hdmi->hdmi_data.pix_repet_factor = 0;
1527         hdmi->hdmi_data.hdcp_enable = 0;
1528         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1529
1530         /* HDMI Initialization Step B.1 */
1531         hdmi_av_composer(hdmi, mode);
1532
1533         /* HDMI Initializateion Step B.2 */
1534         ret = dw_hdmi_phy_init(hdmi);
1535         if (ret)
1536                 return ret;
1537
1538         /* HDMI Initialization Step B.3 */
1539         dw_hdmi_enable_video_path(hdmi);
1540
1541         if (hdmi->sink_has_audio) {
1542                 dev_dbg(hdmi->dev, "sink has audio support\n");
1543
1544                 /* HDMI Initialization Step E - Configure audio */
1545                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1546                 hdmi_enable_audio_clk(hdmi);
1547         }
1548
1549         /* not for DVI mode */
1550         if (hdmi->sink_is_hdmi) {
1551                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1552
1553                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1554                 hdmi_config_AVI(hdmi, mode);
1555         } else {
1556                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1557         }
1558
1559         hdmi_video_packetize(hdmi);
1560         hdmi_video_csc(hdmi);
1561         hdmi_video_sample(hdmi);
1562         hdmi_tx_hdcp_config(hdmi);
1563
1564         dw_hdmi_clear_overflow(hdmi);
1565         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1566                 hdmi_enable_overflow_interrupts(hdmi);
1567
1568         return 0;
1569 }
1570
1571 /* Wait until we are registered to enable interrupts */
1572 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1573 {
1574         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1575                     HDMI_PHY_I2CM_INT_ADDR);
1576
1577         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1578                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1579                     HDMI_PHY_I2CM_CTLINT_ADDR);
1580
1581         /* enable cable hot plug irq */
1582         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1583
1584         /* Clear Hotplug interrupts */
1585         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1586                     HDMI_IH_PHY_STAT0);
1587
1588         return 0;
1589 }
1590
1591 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1592 {
1593         u8 ih_mute;
1594
1595         /*
1596          * Boot up defaults are:
1597          * HDMI_IH_MUTE   = 0x03 (disabled)
1598          * HDMI_IH_MUTE_* = 0x00 (enabled)
1599          *
1600          * Disable top level interrupt bits in HDMI block
1601          */
1602         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1603                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1604                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1605
1606         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1607
1608         /* by default mask all interrupts */
1609         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1610         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1611         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1612         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1613         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1614         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1615         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1616         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1617         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1618         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1619         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1620         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1621         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1622         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1623         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1624
1625         /* Disable interrupts in the IH_MUTE_* registers */
1626         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1627         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1628         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1629         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1630         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1631         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1632         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1633         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1634         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1635         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1636
1637         /* Enable top level interrupt bits in HDMI block */
1638         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1639                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1640         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1641 }
1642
1643 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1644 {
1645         hdmi->bridge_is_on = true;
1646         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1647 }
1648
1649 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1650 {
1651         dw_hdmi_phy_disable(hdmi);
1652         hdmi->bridge_is_on = false;
1653 }
1654
1655 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1656 {
1657         int force = hdmi->force;
1658
1659         if (hdmi->disabled) {
1660                 force = DRM_FORCE_OFF;
1661         } else if (force == DRM_FORCE_UNSPECIFIED) {
1662                 if (hdmi->rxsense)
1663                         force = DRM_FORCE_ON;
1664                 else
1665                         force = DRM_FORCE_OFF;
1666         }
1667
1668         if (force == DRM_FORCE_OFF) {
1669                 if (hdmi->bridge_is_on)
1670                         dw_hdmi_poweroff(hdmi);
1671         } else {
1672                 if (!hdmi->bridge_is_on)
1673                         dw_hdmi_poweron(hdmi);
1674         }
1675 }
1676
1677 /*
1678  * Adjust the detection of RXSENSE according to whether we have a forced
1679  * connection mode enabled, or whether we have been disabled.  There is
1680  * no point processing RXSENSE interrupts if we have a forced connection
1681  * state, or DRM has us disabled.
1682  *
1683  * We also disable rxsense interrupts when we think we're disconnected
1684  * to avoid floating TDMS signals giving false rxsense interrupts.
1685  *
1686  * Note: we still need to listen for HPD interrupts even when DRM has us
1687  * disabled so that we can detect a connect event.
1688  */
1689 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1690 {
1691         u8 old_mask = hdmi->phy_mask;
1692
1693         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1694                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1695         else
1696                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1697
1698         if (old_mask != hdmi->phy_mask)
1699                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1700 }
1701
1702 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1703                                     struct drm_display_mode *orig_mode,
1704                                     struct drm_display_mode *mode)
1705 {
1706         struct dw_hdmi *hdmi = bridge->driver_private;
1707
1708         mutex_lock(&hdmi->mutex);
1709
1710         /* Store the display mode for plugin/DKMS poweron events */
1711         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1712
1713         mutex_unlock(&hdmi->mutex);
1714 }
1715
1716 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1717 {
1718         struct dw_hdmi *hdmi = bridge->driver_private;
1719
1720         mutex_lock(&hdmi->mutex);
1721         hdmi->disabled = true;
1722         dw_hdmi_update_power(hdmi);
1723         dw_hdmi_update_phy_mask(hdmi);
1724         mutex_unlock(&hdmi->mutex);
1725 }
1726
1727 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1728 {
1729         struct dw_hdmi *hdmi = bridge->driver_private;
1730
1731         mutex_lock(&hdmi->mutex);
1732         hdmi->disabled = false;
1733         dw_hdmi_update_power(hdmi);
1734         dw_hdmi_update_phy_mask(hdmi);
1735         mutex_unlock(&hdmi->mutex);
1736 }
1737
1738 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1739 {
1740         /* do nothing */
1741 }
1742
1743 static enum drm_connector_status
1744 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1745 {
1746         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1747                                              connector);
1748
1749         mutex_lock(&hdmi->mutex);
1750         hdmi->force = DRM_FORCE_UNSPECIFIED;
1751         dw_hdmi_update_power(hdmi);
1752         dw_hdmi_update_phy_mask(hdmi);
1753         mutex_unlock(&hdmi->mutex);
1754
1755         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1756                 connector_status_connected : connector_status_disconnected;
1757 }
1758
1759 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1760 {
1761         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1762                                              connector);
1763         struct edid *edid;
1764         int ret = 0;
1765
1766         if (!hdmi->ddc)
1767                 return 0;
1768
1769         edid = drm_get_edid(connector, hdmi->ddc);
1770         if (edid) {
1771                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1772                         edid->width_cm, edid->height_cm);
1773
1774                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1775                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1776                 drm_mode_connector_update_edid_property(connector, edid);
1777                 ret = drm_add_edid_modes(connector, edid);
1778                 /* Store the ELD */
1779                 drm_edid_to_eld(connector, edid);
1780                 kfree(edid);
1781         } else {
1782                 dev_dbg(hdmi->dev, "failed to get edid\n");
1783         }
1784
1785         return ret;
1786 }
1787
1788 static enum drm_mode_status
1789 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1790                              struct drm_display_mode *mode)
1791 {
1792         struct dw_hdmi *hdmi = container_of(connector,
1793                                            struct dw_hdmi, connector);
1794         enum drm_mode_status mode_status = MODE_OK;
1795
1796         /* We don't support double-clocked modes */
1797         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1798                 return MODE_BAD;
1799
1800         if (hdmi->plat_data->mode_valid)
1801                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1802
1803         return mode_status;
1804 }
1805
1806 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1807                                                            *connector)
1808 {
1809         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1810                                              connector);
1811
1812         return hdmi->encoder;
1813 }
1814
1815 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1816 {
1817         drm_connector_unregister(connector);
1818         drm_connector_cleanup(connector);
1819 }
1820
1821 static void dw_hdmi_connector_force(struct drm_connector *connector)
1822 {
1823         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1824                                              connector);
1825
1826         mutex_lock(&hdmi->mutex);
1827         hdmi->force = connector->force;
1828         dw_hdmi_update_power(hdmi);
1829         dw_hdmi_update_phy_mask(hdmi);
1830         mutex_unlock(&hdmi->mutex);
1831 }
1832
1833 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1834         .dpms = drm_helper_connector_dpms,
1835         .fill_modes = drm_helper_probe_single_connector_modes,
1836         .detect = dw_hdmi_connector_detect,
1837         .destroy = dw_hdmi_connector_destroy,
1838         .force = dw_hdmi_connector_force,
1839 };
1840
1841 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1842         .dpms = drm_atomic_helper_connector_dpms,
1843         .fill_modes = drm_helper_probe_single_connector_modes,
1844         .detect = dw_hdmi_connector_detect,
1845         .destroy = dw_hdmi_connector_destroy,
1846         .force = dw_hdmi_connector_force,
1847         .reset = drm_atomic_helper_connector_reset,
1848         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1849         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1850 };
1851
1852 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1853         .get_modes = dw_hdmi_connector_get_modes,
1854         .mode_valid = dw_hdmi_connector_mode_valid,
1855         .best_encoder = dw_hdmi_connector_best_encoder,
1856 };
1857
1858 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1859         .enable = dw_hdmi_bridge_enable,
1860         .disable = dw_hdmi_bridge_disable,
1861         .pre_enable = dw_hdmi_bridge_nop,
1862         .post_disable = dw_hdmi_bridge_nop,
1863         .mode_set = dw_hdmi_bridge_mode_set,
1864 };
1865
1866 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1867 {
1868         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1869         unsigned int stat;
1870
1871         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1872         if (!stat)
1873                 return IRQ_NONE;
1874
1875         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1876
1877         i2c->stat = stat;
1878
1879         complete(&i2c->cmp);
1880
1881         return IRQ_HANDLED;
1882 }
1883
1884 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1885 {
1886         struct dw_hdmi *hdmi = dev_id;
1887         u8 intr_stat;
1888         irqreturn_t ret = IRQ_NONE;
1889
1890         if (hdmi->i2c)
1891                 ret = dw_hdmi_i2c_irq(hdmi);
1892
1893         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1894         if (intr_stat) {
1895                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1896                 return IRQ_WAKE_THREAD;
1897         }
1898
1899         return ret;
1900 }
1901
1902 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1903 {
1904         struct dw_hdmi *hdmi = dev_id;
1905         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1906
1907         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1908         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1909         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1910
1911         phy_pol_mask = 0;
1912         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1913                 phy_pol_mask |= HDMI_PHY_HPD;
1914         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1915                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1916         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1917                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1918         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1919                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1920         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1921                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1922
1923         if (phy_pol_mask)
1924                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1925
1926         /*
1927          * RX sense tells us whether the TDMS transmitters are detecting
1928          * load - in other words, there's something listening on the
1929          * other end of the link.  Use this to decide whether we should
1930          * power on the phy as HPD may be toggled by the sink to merely
1931          * ask the source to re-read the EDID.
1932          */
1933         if (intr_stat &
1934             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1935                 mutex_lock(&hdmi->mutex);
1936                 if (!hdmi->bridge_is_on && !hdmi->force) {
1937                         /*
1938                          * If the RX sense status indicates we're disconnected,
1939                          * clear the software rxsense status.
1940                          */
1941                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1942                                 hdmi->rxsense = false;
1943
1944                         /*
1945                          * Only set the software rxsense status when both
1946                          * rxsense and hpd indicates we're connected.
1947                          * This avoids what seems to be bad behaviour in
1948                          * at least iMX6S versions of the phy.
1949                          */
1950                         if (phy_stat & HDMI_PHY_HPD)
1951                                 hdmi->rxsense = true;
1952
1953                         dw_hdmi_update_power(hdmi);
1954                         dw_hdmi_update_phy_mask(hdmi);
1955                 }
1956                 mutex_unlock(&hdmi->mutex);
1957         }
1958
1959         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1960                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1961                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1962                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1963         }
1964
1965         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1966         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1967                     HDMI_IH_MUTE_PHY_STAT0);
1968
1969         return IRQ_HANDLED;
1970 }
1971
1972 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1973 {
1974         struct drm_encoder *encoder = hdmi->encoder;
1975         struct drm_bridge *bridge;
1976         int ret;
1977
1978         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1979         if (!bridge) {
1980                 DRM_ERROR("Failed to allocate drm bridge\n");
1981                 return -ENOMEM;
1982         }
1983
1984         hdmi->bridge = bridge;
1985         bridge->driver_private = hdmi;
1986         bridge->funcs = &dw_hdmi_bridge_funcs;
1987         ret = drm_bridge_attach(drm, bridge);
1988         if (ret) {
1989                 DRM_ERROR("Failed to initialize bridge with drm\n");
1990                 return -EINVAL;
1991         }
1992
1993         encoder->bridge = bridge;
1994         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1995         hdmi->connector.port = hdmi->dev->of_node;
1996
1997         drm_connector_helper_add(&hdmi->connector,
1998                                  &dw_hdmi_connector_helper_funcs);
1999
2000         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2001                 drm_connector_init(drm, &hdmi->connector,
2002                                    &dw_hdmi_atomic_connector_funcs,
2003                                    DRM_MODE_CONNECTOR_HDMIA);
2004         else
2005                 drm_connector_init(drm, &hdmi->connector,
2006                                    &dw_hdmi_connector_funcs,
2007                                    DRM_MODE_CONNECTOR_HDMIA);
2008
2009         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2010
2011         return 0;
2012 }
2013
2014 int dw_hdmi_bind(struct device *dev, struct device *master,
2015                  void *data, struct drm_encoder *encoder,
2016                  struct resource *iores, int irq,
2017                  const struct dw_hdmi_plat_data *plat_data)
2018 {
2019         struct drm_device *drm = data;
2020         struct device_node *np = dev->of_node;
2021         struct platform_device_info pdevinfo;
2022         struct device_node *ddc_node;
2023         struct dw_hdmi *hdmi;
2024         int ret;
2025         u32 val = 1;
2026         u8 config0;
2027         u8 config1;
2028
2029         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2030         if (!hdmi)
2031                 return -ENOMEM;
2032
2033         hdmi->connector.interlace_allowed = 1;
2034
2035         hdmi->plat_data = plat_data;
2036         hdmi->dev = dev;
2037         hdmi->dev_type = plat_data->dev_type;
2038         hdmi->sample_rate = 48000;
2039         hdmi->encoder = encoder;
2040         hdmi->disabled = true;
2041         hdmi->rxsense = true;
2042         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2043
2044         mutex_init(&hdmi->mutex);
2045         mutex_init(&hdmi->audio_mutex);
2046         spin_lock_init(&hdmi->audio_lock);
2047
2048         of_property_read_u32(np, "reg-io-width", &val);
2049
2050         switch (val) {
2051         case 4:
2052                 hdmi->write = dw_hdmi_writel;
2053                 hdmi->read = dw_hdmi_readl;
2054                 break;
2055         case 1:
2056                 hdmi->write = dw_hdmi_writeb;
2057                 hdmi->read = dw_hdmi_readb;
2058                 break;
2059         default:
2060                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2061                 return -EINVAL;
2062         }
2063
2064         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2065         if (ddc_node) {
2066                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2067                 of_node_put(ddc_node);
2068                 if (!hdmi->ddc) {
2069                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2070                         return -EPROBE_DEFER;
2071                 }
2072
2073         } else {
2074                 dev_dbg(hdmi->dev, "no ddc property found\n");
2075         }
2076
2077         /* If DDC bus is not specified, try to register HDMI I2C bus */
2078         if (!hdmi->ddc) {
2079                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2080                 if (IS_ERR(hdmi->ddc))
2081                         hdmi->ddc = NULL;
2082         }
2083
2084         hdmi->regs = devm_ioremap_resource(dev, iores);
2085         if (IS_ERR(hdmi->regs))
2086                 return PTR_ERR(hdmi->regs);
2087
2088         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2089         if (IS_ERR(hdmi->isfr_clk)) {
2090                 ret = PTR_ERR(hdmi->isfr_clk);
2091                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2092                 return ret;
2093         }
2094
2095         ret = clk_prepare_enable(hdmi->isfr_clk);
2096         if (ret) {
2097                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2098                 return ret;
2099         }
2100
2101         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2102         if (IS_ERR(hdmi->iahb_clk)) {
2103                 ret = PTR_ERR(hdmi->iahb_clk);
2104                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2105                 goto err_isfr;
2106         }
2107
2108         ret = clk_prepare_enable(hdmi->iahb_clk);
2109         if (ret) {
2110                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2111                 goto err_isfr;
2112         }
2113
2114         /* Product and revision IDs */
2115         dev_info(dev,
2116                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2117                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2118                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2119                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2120                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2121
2122         initialize_hdmi_ih_mutes(hdmi);
2123
2124         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2125                                         dw_hdmi_irq, IRQF_SHARED,
2126                                         dev_name(dev), hdmi);
2127         if (ret)
2128                 goto err_iahb;
2129
2130         /*
2131          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2132          * N and cts values before enabling phy
2133          */
2134         hdmi_init_clk_regenerator(hdmi);
2135
2136         /*
2137          * Configure registers related to HDMI interrupt
2138          * generation before registering IRQ.
2139          */
2140         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2141
2142         /* Clear Hotplug interrupts */
2143         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
2144                     HDMI_IH_PHY_STAT0);
2145
2146         ret = dw_hdmi_fb_registered(hdmi);
2147         if (ret)
2148                 goto err_iahb;
2149
2150         ret = dw_hdmi_register(drm, hdmi);
2151         if (ret)
2152                 goto err_iahb;
2153
2154         /* Unmute interrupts */
2155         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2156                     HDMI_IH_MUTE_PHY_STAT0);
2157
2158         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2159         if (hdmi->i2c)
2160                 dw_hdmi_i2c_init(hdmi);
2161
2162         memset(&pdevinfo, 0, sizeof(pdevinfo));
2163         pdevinfo.parent = dev;
2164         pdevinfo.id = PLATFORM_DEVID_AUTO;
2165
2166         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2167         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2168
2169         if (config1 & HDMI_CONFIG1_AHB) {
2170                 struct dw_hdmi_audio_data audio;
2171
2172                 audio.phys = iores->start;
2173                 audio.base = hdmi->regs;
2174                 audio.irq = irq;
2175                 audio.hdmi = hdmi;
2176                 audio.eld = hdmi->connector.eld;
2177
2178                 pdevinfo.name = "dw-hdmi-ahb-audio";
2179                 pdevinfo.data = &audio;
2180                 pdevinfo.size_data = sizeof(audio);
2181                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2182                 hdmi->audio = platform_device_register_full(&pdevinfo);
2183         } else if (config0 & HDMI_CONFIG0_I2S) {
2184                 struct dw_hdmi_i2s_audio_data audio;
2185
2186                 audio.hdmi      = hdmi;
2187                 audio.write     = hdmi_writeb;
2188                 audio.read      = hdmi_readb;
2189
2190                 pdevinfo.name = "dw-hdmi-i2s-audio";
2191                 pdevinfo.data = &audio;
2192                 pdevinfo.size_data = sizeof(audio);
2193                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2194                 hdmi->audio = platform_device_register_full(&pdevinfo);
2195         }
2196
2197         dev_set_drvdata(dev, hdmi);
2198
2199         return 0;
2200
2201 err_iahb:
2202         if (hdmi->i2c)
2203                 i2c_del_adapter(&hdmi->i2c->adap);
2204
2205         clk_disable_unprepare(hdmi->iahb_clk);
2206 err_isfr:
2207         clk_disable_unprepare(hdmi->isfr_clk);
2208
2209         return ret;
2210 }
2211 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2212
2213 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2214 {
2215         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2216
2217         if (hdmi->audio && !IS_ERR(hdmi->audio))
2218                 platform_device_unregister(hdmi->audio);
2219
2220         /* Disable all interrupts */
2221         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2222
2223         hdmi->connector.funcs->destroy(&hdmi->connector);
2224         hdmi->encoder->funcs->destroy(hdmi->encoder);
2225
2226         clk_disable_unprepare(hdmi->iahb_clk);
2227         clk_disable_unprepare(hdmi->isfr_clk);
2228
2229         if (hdmi->i2c)
2230                 i2c_del_adapter(&hdmi->i2c->adap);
2231         else
2232                 i2c_put_adapter(hdmi->ddc);
2233 }
2234 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2235
2236 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2237 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2238 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2239 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2240 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2241 MODULE_LICENSE("GPL");
2242 MODULE_ALIAS("platform:dw-hdmi");