2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * Designware High-Definition Multimedia Interface (HDMI) driver
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
13 #include <linux/module.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/hdmi.h>
19 #include <linux/mutex.h>
20 #include <linux/of_device.h>
21 #include <linux/spinlock.h>
23 #include <drm/drm_of.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_encoder_slave.h>
29 #include <drm/bridge/dw_hdmi.h>
32 #include "dw-hdmi-audio.h"
34 #define HDMI_EDID_LEN 512
38 #define YCBCR422_16BITS 2
39 #define YCBCR422_8BITS 3
57 * Unless otherwise noted, entries in this table are 100% optimization.
58 * Values can be obtained from hdmi_compute_n() but that function is
59 * slow so we pre-compute values we expect to see.
61 * All 32k and 48k values are expected to be the same (due to the way
62 * the math works) for any rate that's an exact kHz.
64 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
65 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
66 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
67 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
68 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
69 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
70 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
71 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
72 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
73 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
74 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
75 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
76 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
77 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
78 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
79 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
80 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
81 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
82 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
83 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
84 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
85 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
86 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
87 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
88 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
89 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
90 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
91 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
93 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
94 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
95 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
96 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
97 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
98 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
99 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
100 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
101 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
103 /* For 297 MHz+ HDMI spec have some other rule for setting N */
104 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
105 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
108 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
112 static const u16 csc_coeff_default[3][4] = {
113 { 0x2000, 0x0000, 0x0000, 0x0000 },
114 { 0x0000, 0x2000, 0x0000, 0x0000 },
115 { 0x0000, 0x0000, 0x2000, 0x0000 }
118 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
119 { 0x2000, 0x6926, 0x74fd, 0x010e },
120 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
121 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
124 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
125 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
126 { 0x2000, 0x3264, 0x0000, 0x7e6d },
127 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
130 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
131 { 0x2591, 0x1322, 0x074b, 0x0000 },
132 { 0x6535, 0x2000, 0x7acc, 0x0200 },
133 { 0x6acd, 0x7534, 0x2000, 0x0200 }
136 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
137 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
138 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
139 { 0x6756, 0x78ab, 0x2000, 0x0200 }
143 bool mdataenablepolarity;
145 unsigned int mpixelclock;
146 unsigned int mpixelrepetitioninput;
147 unsigned int mpixelrepetitionoutput;
150 struct hdmi_data_info {
151 unsigned int enc_in_format;
152 unsigned int enc_out_format;
153 unsigned int enc_color_depth;
154 unsigned int colorimetry;
155 unsigned int pix_repet_factor;
156 unsigned int hdcp_enable;
157 struct hdmi_vmode video_mode;
161 struct drm_connector connector;
162 struct drm_encoder *encoder;
163 struct drm_bridge *bridge;
165 struct platform_device *audio;
166 enum dw_hdmi_devtype dev_type;
168 struct clk *isfr_clk;
169 struct clk *iahb_clk;
171 struct hdmi_data_info hdmi_data;
172 const struct dw_hdmi_plat_data *plat_data;
176 u8 edid[HDMI_EDID_LEN];
180 struct drm_display_mode previous_mode;
182 struct i2c_adapter *ddc;
187 struct mutex mutex; /* for state below and previous_mode */
188 enum drm_connector_force force; /* mutex-protected force state */
189 bool disabled; /* DRM has disabled our bridge */
190 bool bridge_is_on; /* indicates the bridge is on */
191 bool rxsense; /* rxsense state */
192 u8 phy_mask; /* desired phy int mask settings */
194 spinlock_t audio_lock;
195 struct mutex audio_mutex;
196 unsigned int sample_rate;
197 unsigned int audio_cts;
198 unsigned int audio_n;
201 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
202 u8 (*read)(struct dw_hdmi *hdmi, int offset);
205 #define HDMI_IH_PHY_STAT0_RX_SENSE \
206 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
207 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
209 #define HDMI_PHY_RX_SENSE \
210 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
211 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
213 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
215 writel(val, hdmi->regs + (offset << 2));
218 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
220 return readl(hdmi->regs + (offset << 2));
223 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
225 writeb(val, hdmi->regs + offset);
228 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
230 return readb(hdmi->regs + offset);
233 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
235 hdmi->write(hdmi, val, offset);
238 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
240 return hdmi->read(hdmi, offset);
243 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
245 u8 val = hdmi_readb(hdmi, reg) & ~mask;
248 hdmi_writeb(hdmi, val, reg);
251 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
254 hdmi_modb(hdmi, data << shift, mask, reg);
257 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
260 /* Must be set/cleared first */
261 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
263 /* nshift factor = 0 */
264 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
266 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
267 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
268 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
269 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
271 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
272 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
273 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
276 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
277 unsigned long pixel_clk,
280 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
281 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
284 if (plat_data->tmds_n_table) {
285 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
286 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
287 tmds_n = &plat_data->tmds_n_table[i];
293 if (tmds_n == NULL) {
294 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
295 if (pixel_clk == common_tmds_n_table[i].tmds) {
296 tmds_n = &common_tmds_n_table[i];
307 return tmds_n->n_32k;
311 return (freq / 44100) * tmds_n->n_44k1;
315 return (freq / 48000) * tmds_n->n_48k;
321 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
322 unsigned int pixel_clk)
327 final = (u64)pixel_clk * n;
330 do_div(cts, 128 * freq);
332 diff = final - (u64)cts * (128 * freq);
337 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
338 unsigned long pixel_clk,
341 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
342 unsigned int max_n = (128 * freq) / 300;
343 unsigned int ideal_n = (128 * freq) / 1000;
344 unsigned int best_n_distance = ideal_n;
345 unsigned int best_n = 0;
346 u64 best_diff = U64_MAX;
349 /* If the ideal N could satisfy the audio math, then just take it */
350 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
353 for (n = min_n; n <= max_n; n++) {
354 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
356 if (diff < best_diff || (diff == best_diff &&
357 abs(n - ideal_n) < best_n_distance)) {
360 best_n_distance = abs(best_n - ideal_n);
364 * The best N already satisfy the audio math, and also be
365 * the closest value to ideal N, so just cut the loop.
367 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
374 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
375 unsigned long sample_rate)
379 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
383 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
386 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
389 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
390 unsigned long pixel_clk, unsigned int sample_rate)
392 unsigned long ftdms = pixel_clk;
396 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
399 * Compute the CTS value from the N value. Note that CTS and N
400 * can be up to 20 bits in total, so we need 64-bit math. Also
401 * note that our TDMS clock is not fully accurate; it is accurate
402 * to kHz. This can introduce an unnecessary remainder in the
403 * calculation below, so we don't try to warn about that.
405 tmp = (u64)ftdms * n;
406 do_div(tmp, 128 * sample_rate);
409 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
410 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
413 spin_lock_irq(&hdmi->audio_lock);
415 hdmi->audio_cts = cts;
416 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
417 spin_unlock_irq(&hdmi->audio_lock);
420 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
422 mutex_lock(&hdmi->audio_mutex);
423 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
424 mutex_unlock(&hdmi->audio_mutex);
427 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
429 mutex_lock(&hdmi->audio_mutex);
430 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
432 mutex_unlock(&hdmi->audio_mutex);
435 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
437 mutex_lock(&hdmi->audio_mutex);
438 hdmi->sample_rate = rate;
439 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
441 mutex_unlock(&hdmi->audio_mutex);
443 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
445 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
449 spin_lock_irqsave(&hdmi->audio_lock, flags);
450 hdmi->audio_enable = true;
451 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
452 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
454 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
456 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
460 spin_lock_irqsave(&hdmi->audio_lock, flags);
461 hdmi->audio_enable = false;
462 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
463 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
465 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
468 * this submodule is responsible for the video data synchronization.
469 * for example, for RGB 4:4:4 input, the data map is defined as
470 * pin{47~40} <==> R[7:0]
471 * pin{31~24} <==> G[7:0]
472 * pin{15~8} <==> B[7:0]
474 static void hdmi_video_sample(struct dw_hdmi *hdmi)
476 int color_format = 0;
479 if (hdmi->hdmi_data.enc_in_format == RGB) {
480 if (hdmi->hdmi_data.enc_color_depth == 8)
482 else if (hdmi->hdmi_data.enc_color_depth == 10)
484 else if (hdmi->hdmi_data.enc_color_depth == 12)
486 else if (hdmi->hdmi_data.enc_color_depth == 16)
490 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
491 if (hdmi->hdmi_data.enc_color_depth == 8)
493 else if (hdmi->hdmi_data.enc_color_depth == 10)
495 else if (hdmi->hdmi_data.enc_color_depth == 12)
497 else if (hdmi->hdmi_data.enc_color_depth == 16)
501 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
502 if (hdmi->hdmi_data.enc_color_depth == 8)
504 else if (hdmi->hdmi_data.enc_color_depth == 10)
506 else if (hdmi->hdmi_data.enc_color_depth == 12)
512 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
513 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
514 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
515 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
517 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
518 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
519 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
520 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
521 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
522 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
523 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
524 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
525 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
526 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
527 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
530 static int is_color_space_conversion(struct dw_hdmi *hdmi)
532 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
535 static int is_color_space_decimation(struct dw_hdmi *hdmi)
537 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
539 if (hdmi->hdmi_data.enc_in_format == RGB ||
540 hdmi->hdmi_data.enc_in_format == YCBCR444)
545 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
547 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
549 if (hdmi->hdmi_data.enc_out_format == RGB ||
550 hdmi->hdmi_data.enc_out_format == YCBCR444)
555 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
557 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
561 if (is_color_space_conversion(hdmi)) {
562 if (hdmi->hdmi_data.enc_out_format == RGB) {
563 if (hdmi->hdmi_data.colorimetry ==
564 HDMI_COLORIMETRY_ITU_601)
565 csc_coeff = &csc_coeff_rgb_out_eitu601;
567 csc_coeff = &csc_coeff_rgb_out_eitu709;
568 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
569 if (hdmi->hdmi_data.colorimetry ==
570 HDMI_COLORIMETRY_ITU_601)
571 csc_coeff = &csc_coeff_rgb_in_eitu601;
573 csc_coeff = &csc_coeff_rgb_in_eitu709;
578 /* The CSC registers are sequential, alternating MSB then LSB */
579 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
580 u16 coeff_a = (*csc_coeff)[0][i];
581 u16 coeff_b = (*csc_coeff)[1][i];
582 u16 coeff_c = (*csc_coeff)[2][i];
584 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
585 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
586 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
587 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
588 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
589 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
592 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
596 static void hdmi_video_csc(struct dw_hdmi *hdmi)
599 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
602 /* YCC422 interpolation to 444 mode */
603 if (is_color_space_interpolation(hdmi))
604 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
605 else if (is_color_space_decimation(hdmi))
606 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
608 if (hdmi->hdmi_data.enc_color_depth == 8)
609 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
610 else if (hdmi->hdmi_data.enc_color_depth == 10)
611 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
612 else if (hdmi->hdmi_data.enc_color_depth == 12)
613 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
614 else if (hdmi->hdmi_data.enc_color_depth == 16)
615 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
619 /* Configure the CSC registers */
620 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
621 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
624 dw_hdmi_update_csc_coeffs(hdmi);
628 * HDMI video packetizer is used to packetize the data.
629 * for example, if input is YCC422 mode or repeater is used,
630 * data should be repacked this module can be bypassed.
632 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
634 unsigned int color_depth = 0;
635 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
636 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
637 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
640 if (hdmi_data->enc_out_format == RGB ||
641 hdmi_data->enc_out_format == YCBCR444) {
642 if (!hdmi_data->enc_color_depth) {
643 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
644 } else if (hdmi_data->enc_color_depth == 8) {
646 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
647 } else if (hdmi_data->enc_color_depth == 10) {
649 } else if (hdmi_data->enc_color_depth == 12) {
651 } else if (hdmi_data->enc_color_depth == 16) {
656 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
657 if (!hdmi_data->enc_color_depth ||
658 hdmi_data->enc_color_depth == 8)
659 remap_size = HDMI_VP_REMAP_YCC422_16bit;
660 else if (hdmi_data->enc_color_depth == 10)
661 remap_size = HDMI_VP_REMAP_YCC422_20bit;
662 else if (hdmi_data->enc_color_depth == 12)
663 remap_size = HDMI_VP_REMAP_YCC422_24bit;
666 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
671 /* set the packetizer registers */
672 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
673 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
674 ((hdmi_data->pix_repet_factor <<
675 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
676 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
677 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
679 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
680 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
682 /* Data from pixel repeater block */
683 if (hdmi_data->pix_repet_factor > 1) {
684 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
685 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
686 } else { /* data from packetizer block */
687 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
688 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
691 hdmi_modb(hdmi, vp_conf,
692 HDMI_VP_CONF_PR_EN_MASK |
693 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
695 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
696 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
698 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
700 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
701 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
702 HDMI_VP_CONF_PP_EN_ENABLE |
703 HDMI_VP_CONF_YCC422_EN_DISABLE;
704 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
705 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
706 HDMI_VP_CONF_PP_EN_DISABLE |
707 HDMI_VP_CONF_YCC422_EN_ENABLE;
708 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
709 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
710 HDMI_VP_CONF_PP_EN_DISABLE |
711 HDMI_VP_CONF_YCC422_EN_DISABLE;
716 hdmi_modb(hdmi, vp_conf,
717 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
718 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
720 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
721 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
722 HDMI_VP_STUFF_PP_STUFFING_MASK |
723 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
725 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
729 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
732 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
733 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
736 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
739 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
740 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
743 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
746 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
747 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
750 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
753 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
756 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
759 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
762 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
766 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
771 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
776 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
779 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
780 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
781 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
782 HDMI_PHY_I2CM_DATAO_1_ADDR);
783 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
784 HDMI_PHY_I2CM_DATAO_0_ADDR);
785 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
786 HDMI_PHY_I2CM_OPERATION_ADDR);
787 hdmi_phy_wait_i2c_done(hdmi, 1000);
790 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
793 __hdmi_phy_i2c_write(hdmi, data, addr);
797 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
799 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
800 HDMI_PHY_CONF0_PDZ_OFFSET,
801 HDMI_PHY_CONF0_PDZ_MASK);
804 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
806 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
807 HDMI_PHY_CONF0_ENTMDS_OFFSET,
808 HDMI_PHY_CONF0_ENTMDS_MASK);
811 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
813 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
814 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
815 HDMI_PHY_CONF0_SPARECTRL_MASK);
818 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
820 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
821 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
822 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
825 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
827 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
828 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
829 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
832 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
834 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
835 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
836 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
839 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
841 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
842 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
843 HDMI_PHY_CONF0_SELDIPIF_MASK);
846 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
847 unsigned char res, int cscon)
851 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
852 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
853 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
854 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
860 case 0: /* color resolution 0 is 8 bit colour depth */
862 res_idx = DW_HDMI_RES_8;
865 res_idx = DW_HDMI_RES_10;
868 res_idx = DW_HDMI_RES_12;
874 /* PLL/MPLL Cfg - always match on final entry */
875 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
876 if (hdmi->hdmi_data.video_mode.mpixelclock <=
877 mpll_config->mpixelclock)
880 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
881 if (hdmi->hdmi_data.video_mode.mpixelclock <=
882 curr_ctrl->mpixelclock)
885 for (; phy_config->mpixelclock != ~0UL; phy_config++)
886 if (hdmi->hdmi_data.video_mode.mpixelclock <=
887 phy_config->mpixelclock)
890 if (mpll_config->mpixelclock == ~0UL ||
891 curr_ctrl->mpixelclock == ~0UL ||
892 phy_config->mpixelclock == ~0UL) {
893 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
894 hdmi->hdmi_data.video_mode.mpixelclock);
898 /* Enable csc path */
900 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
902 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
904 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
906 /* gen2 tx power off */
907 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
910 dw_hdmi_phy_gen2_pddq(hdmi, 1);
913 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
914 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
916 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
918 hdmi_phy_test_clear(hdmi, 1);
919 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
920 HDMI_PHY_I2CM_SLAVE_ADDR);
921 hdmi_phy_test_clear(hdmi, 0);
923 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
924 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
927 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
929 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
930 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
932 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
933 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
934 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
936 /* REMOVE CLK TERM */
937 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
939 dw_hdmi_phy_enable_powerdown(hdmi, false);
941 /* toggle TMDS enable */
942 dw_hdmi_phy_enable_tmds(hdmi, 0);
943 dw_hdmi_phy_enable_tmds(hdmi, 1);
945 /* gen2 tx power on */
946 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
947 dw_hdmi_phy_gen2_pddq(hdmi, 0);
949 if (is_rockchip(hdmi->dev_type))
950 dw_hdmi_phy_enable_spare(hdmi, 1);
952 /*Wait for PHY PLL lock */
955 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
960 dev_err(hdmi->dev, "PHY PLL not locked\n");
971 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
976 /*check csc whether needed activated in HDMI mode */
977 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
979 /* HDMI Phy spec says to do the phy initialization sequence twice */
980 for (i = 0; i < 2; i++) {
981 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
982 dw_hdmi_phy_sel_interface_control(hdmi, 0);
983 dw_hdmi_phy_enable_tmds(hdmi, 0);
984 dw_hdmi_phy_enable_powerdown(hdmi, true);
987 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
992 hdmi->phy_enabled = true;
996 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1000 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1001 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1003 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1005 /* disable rx detect */
1006 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1007 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1009 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1011 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1012 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1015 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1017 struct hdmi_avi_infoframe frame;
1020 /* Initialise info frame from DRM mode */
1021 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1023 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1024 frame.colorspace = HDMI_COLORSPACE_YUV444;
1025 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1026 frame.colorspace = HDMI_COLORSPACE_YUV422;
1028 frame.colorspace = HDMI_COLORSPACE_RGB;
1030 /* Set up colorimetry */
1031 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1032 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1033 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1034 frame.extended_colorimetry =
1035 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1036 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1037 frame.extended_colorimetry =
1038 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1039 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1040 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1041 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1042 } else { /* Carries no data */
1043 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1044 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1047 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1050 * The Designware IP uses a different byte format from standard
1051 * AVI info frames, though generally the bits are in the correct
1056 * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1057 * active aspect present in bit 6 rather than 4.
1059 val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1060 if (frame.active_aspect & 15)
1061 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1062 if (frame.top_bar || frame.bottom_bar)
1063 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1064 if (frame.left_bar || frame.right_bar)
1065 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1066 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1068 /* AVI data byte 2 differences: none */
1069 val = ((frame.colorimetry & 0x3) << 6) |
1070 ((frame.picture_aspect & 0x3) << 4) |
1071 (frame.active_aspect & 0xf);
1072 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1074 /* AVI data byte 3 differences: none */
1075 val = ((frame.extended_colorimetry & 0x7) << 4) |
1076 ((frame.quantization_range & 0x3) << 2) |
1079 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1080 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1082 /* AVI data byte 4 differences: none */
1083 val = frame.video_code & 0x7f;
1084 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1086 /* AVI Data Byte 5- set up input and output pixel repetition */
1087 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1088 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1089 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1090 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1091 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1092 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1093 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1096 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1097 * ycc range in bits 2,3 rather than 6,7
1099 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1100 (frame.content_type & 0x3);
1101 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1103 /* AVI Data Bytes 6-13 */
1104 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1105 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1106 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1107 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1108 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1109 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1110 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1111 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1114 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1115 const struct drm_display_mode *mode)
1118 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1119 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1120 unsigned int vdisplay;
1122 vmode->mpixelclock = mode->clock * 1000;
1124 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1126 /* Set up HDMI_FC_INVIDCONF */
1127 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1128 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1129 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1131 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1132 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1133 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1135 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1136 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1137 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1139 inv_val |= (vmode->mdataenablepolarity ?
1140 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1141 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1143 if (hdmi->vic == 39)
1144 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1146 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1147 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1148 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1150 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1151 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1152 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1154 inv_val |= hdmi->sink_is_hdmi ?
1155 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1156 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1158 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1160 vdisplay = mode->vdisplay;
1161 vblank = mode->vtotal - mode->vdisplay;
1162 v_de_vs = mode->vsync_start - mode->vdisplay;
1163 vsync_len = mode->vsync_end - mode->vsync_start;
1166 * When we're setting an interlaced mode, we need
1167 * to adjust the vertical timing to suit.
1169 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1176 /* Set up horizontal active pixel width */
1177 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1178 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1180 /* Set up vertical active lines */
1181 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1182 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1184 /* Set up horizontal blanking pixel region width */
1185 hblank = mode->htotal - mode->hdisplay;
1186 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1187 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1189 /* Set up vertical blanking pixel region width */
1190 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1192 /* Set up HSYNC active edge delay width (in pixel clks) */
1193 h_de_hs = mode->hsync_start - mode->hdisplay;
1194 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1195 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1197 /* Set up VSYNC active edge delay (in lines) */
1198 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1200 /* Set up HSYNC active pulse width (in pixel clks) */
1201 hsync_len = mode->hsync_end - mode->hsync_start;
1202 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1203 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1205 /* Set up VSYNC active edge delay (in lines) */
1206 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1209 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1211 if (!hdmi->phy_enabled)
1214 dw_hdmi_phy_enable_tmds(hdmi, 0);
1215 dw_hdmi_phy_enable_powerdown(hdmi, true);
1217 hdmi->phy_enabled = false;
1220 /* HDMI Initialization Step B.4 */
1221 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1225 /* control period minimum duration */
1226 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1227 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1228 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1230 /* Set to fill TMDS data channels */
1231 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1232 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1233 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1235 /* Enable pixel clock and tmds data path */
1237 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1238 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1240 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1241 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1243 /* Enable csc path */
1244 if (is_color_space_conversion(hdmi)) {
1245 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1246 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1250 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1252 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1255 /* Workaround to clear the overflow condition */
1256 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1261 /* TMDS software reset */
1262 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1264 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1265 if (hdmi->dev_type == IMX6DL_HDMI) {
1266 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1270 for (count = 0; count < 4; count++)
1271 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1274 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1276 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1277 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1280 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1282 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1283 HDMI_IH_MUTE_FC_STAT2);
1286 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1290 hdmi_disable_overflow_interrupts(hdmi);
1292 hdmi->vic = drm_match_cea_mode(mode);
1295 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1297 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1300 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1301 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1302 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1303 (hdmi->vic == 17) || (hdmi->vic == 18))
1304 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1306 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1308 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1309 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1311 /* TODO: Get input format from IPU (via FB driver interface) */
1312 hdmi->hdmi_data.enc_in_format = RGB;
1314 hdmi->hdmi_data.enc_out_format = RGB;
1316 hdmi->hdmi_data.enc_color_depth = 8;
1317 hdmi->hdmi_data.pix_repet_factor = 0;
1318 hdmi->hdmi_data.hdcp_enable = 0;
1319 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1321 /* HDMI Initialization Step B.1 */
1322 hdmi_av_composer(hdmi, mode);
1324 /* HDMI Initializateion Step B.2 */
1325 ret = dw_hdmi_phy_init(hdmi);
1329 /* HDMI Initialization Step B.3 */
1330 dw_hdmi_enable_video_path(hdmi);
1332 if (hdmi->sink_has_audio) {
1333 dev_dbg(hdmi->dev, "sink has audio support\n");
1335 /* HDMI Initialization Step E - Configure audio */
1336 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1337 hdmi_enable_audio_clk(hdmi);
1340 /* not for DVI mode */
1341 if (hdmi->sink_is_hdmi) {
1342 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1344 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1345 hdmi_config_AVI(hdmi, mode);
1347 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1350 hdmi_video_packetize(hdmi);
1351 hdmi_video_csc(hdmi);
1352 hdmi_video_sample(hdmi);
1353 hdmi_tx_hdcp_config(hdmi);
1355 dw_hdmi_clear_overflow(hdmi);
1356 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1357 hdmi_enable_overflow_interrupts(hdmi);
1362 /* Wait until we are registered to enable interrupts */
1363 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1365 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1366 HDMI_PHY_I2CM_INT_ADDR);
1368 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1369 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1370 HDMI_PHY_I2CM_CTLINT_ADDR);
1372 /* enable cable hot plug irq */
1373 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1375 /* Clear Hotplug interrupts */
1376 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1382 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1387 * Boot up defaults are:
1388 * HDMI_IH_MUTE = 0x03 (disabled)
1389 * HDMI_IH_MUTE_* = 0x00 (enabled)
1391 * Disable top level interrupt bits in HDMI block
1393 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1394 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1395 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1397 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1399 /* by default mask all interrupts */
1400 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1401 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1402 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1403 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1404 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1405 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1406 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1407 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1408 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1409 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1410 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1411 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1412 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1413 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1414 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1416 /* Disable interrupts in the IH_MUTE_* registers */
1417 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1418 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1419 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1420 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1421 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1422 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1423 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1424 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1425 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1426 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1428 /* Enable top level interrupt bits in HDMI block */
1429 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1430 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1431 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1434 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1436 hdmi->bridge_is_on = true;
1437 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1440 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1442 dw_hdmi_phy_disable(hdmi);
1443 hdmi->bridge_is_on = false;
1446 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1448 int force = hdmi->force;
1450 if (hdmi->disabled) {
1451 force = DRM_FORCE_OFF;
1452 } else if (force == DRM_FORCE_UNSPECIFIED) {
1454 force = DRM_FORCE_ON;
1456 force = DRM_FORCE_OFF;
1459 if (force == DRM_FORCE_OFF) {
1460 if (hdmi->bridge_is_on)
1461 dw_hdmi_poweroff(hdmi);
1463 if (!hdmi->bridge_is_on)
1464 dw_hdmi_poweron(hdmi);
1469 * Adjust the detection of RXSENSE according to whether we have a forced
1470 * connection mode enabled, or whether we have been disabled. There is
1471 * no point processing RXSENSE interrupts if we have a forced connection
1472 * state, or DRM has us disabled.
1474 * We also disable rxsense interrupts when we think we're disconnected
1475 * to avoid floating TDMS signals giving false rxsense interrupts.
1477 * Note: we still need to listen for HPD interrupts even when DRM has us
1478 * disabled so that we can detect a connect event.
1480 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1482 u8 old_mask = hdmi->phy_mask;
1484 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1485 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1487 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1489 if (old_mask != hdmi->phy_mask)
1490 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1493 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1494 struct drm_display_mode *orig_mode,
1495 struct drm_display_mode *mode)
1497 struct dw_hdmi *hdmi = bridge->driver_private;
1499 mutex_lock(&hdmi->mutex);
1501 /* Store the display mode for plugin/DKMS poweron events */
1502 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1504 mutex_unlock(&hdmi->mutex);
1507 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1509 struct dw_hdmi *hdmi = bridge->driver_private;
1511 mutex_lock(&hdmi->mutex);
1512 hdmi->disabled = true;
1513 dw_hdmi_update_power(hdmi);
1514 dw_hdmi_update_phy_mask(hdmi);
1515 mutex_unlock(&hdmi->mutex);
1518 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1520 struct dw_hdmi *hdmi = bridge->driver_private;
1522 mutex_lock(&hdmi->mutex);
1523 hdmi->disabled = false;
1524 dw_hdmi_update_power(hdmi);
1525 dw_hdmi_update_phy_mask(hdmi);
1526 mutex_unlock(&hdmi->mutex);
1529 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1534 static enum drm_connector_status
1535 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1537 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1540 mutex_lock(&hdmi->mutex);
1541 hdmi->force = DRM_FORCE_UNSPECIFIED;
1542 dw_hdmi_update_power(hdmi);
1543 dw_hdmi_update_phy_mask(hdmi);
1544 mutex_unlock(&hdmi->mutex);
1546 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1547 connector_status_connected : connector_status_disconnected;
1550 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1552 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1560 edid = drm_get_edid(connector, hdmi->ddc);
1562 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1563 edid->width_cm, edid->height_cm);
1565 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1566 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1567 drm_mode_connector_update_edid_property(connector, edid);
1568 ret = drm_add_edid_modes(connector, edid);
1570 drm_edid_to_eld(connector, edid);
1573 dev_dbg(hdmi->dev, "failed to get edid\n");
1579 static enum drm_mode_status
1580 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1581 struct drm_display_mode *mode)
1583 struct dw_hdmi *hdmi = container_of(connector,
1584 struct dw_hdmi, connector);
1585 enum drm_mode_status mode_status = MODE_OK;
1587 /* We don't support double-clocked modes */
1588 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1591 if (hdmi->plat_data->mode_valid)
1592 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1597 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1600 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1603 return hdmi->encoder;
1606 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1608 drm_connector_unregister(connector);
1609 drm_connector_cleanup(connector);
1612 static void dw_hdmi_connector_force(struct drm_connector *connector)
1614 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1617 mutex_lock(&hdmi->mutex);
1618 hdmi->force = connector->force;
1619 dw_hdmi_update_power(hdmi);
1620 dw_hdmi_update_phy_mask(hdmi);
1621 mutex_unlock(&hdmi->mutex);
1624 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1625 .dpms = drm_helper_connector_dpms,
1626 .fill_modes = drm_helper_probe_single_connector_modes,
1627 .detect = dw_hdmi_connector_detect,
1628 .destroy = dw_hdmi_connector_destroy,
1629 .force = dw_hdmi_connector_force,
1632 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1633 .dpms = drm_atomic_helper_connector_dpms,
1634 .fill_modes = drm_helper_probe_single_connector_modes,
1635 .detect = dw_hdmi_connector_detect,
1636 .destroy = dw_hdmi_connector_destroy,
1637 .force = dw_hdmi_connector_force,
1638 .reset = drm_atomic_helper_connector_reset,
1639 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1640 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1643 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1644 .get_modes = dw_hdmi_connector_get_modes,
1645 .mode_valid = dw_hdmi_connector_mode_valid,
1646 .best_encoder = dw_hdmi_connector_best_encoder,
1649 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1650 .enable = dw_hdmi_bridge_enable,
1651 .disable = dw_hdmi_bridge_disable,
1652 .pre_enable = dw_hdmi_bridge_nop,
1653 .post_disable = dw_hdmi_bridge_nop,
1654 .mode_set = dw_hdmi_bridge_mode_set,
1657 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1659 struct dw_hdmi *hdmi = dev_id;
1662 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1664 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1666 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1669 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1671 struct dw_hdmi *hdmi = dev_id;
1672 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1674 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1675 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1676 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1679 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1680 phy_pol_mask |= HDMI_PHY_HPD;
1681 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1682 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1683 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1684 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1685 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1686 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1687 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1688 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1691 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1694 * RX sense tells us whether the TDMS transmitters are detecting
1695 * load - in other words, there's something listening on the
1696 * other end of the link. Use this to decide whether we should
1697 * power on the phy as HPD may be toggled by the sink to merely
1698 * ask the source to re-read the EDID.
1701 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1702 mutex_lock(&hdmi->mutex);
1703 if (!hdmi->disabled && !hdmi->force) {
1705 * If the RX sense status indicates we're disconnected,
1706 * clear the software rxsense status.
1708 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1709 hdmi->rxsense = false;
1712 * Only set the software rxsense status when both
1713 * rxsense and hpd indicates we're connected.
1714 * This avoids what seems to be bad behaviour in
1715 * at least iMX6S versions of the phy.
1717 if (phy_stat & HDMI_PHY_HPD)
1718 hdmi->rxsense = true;
1720 dw_hdmi_update_power(hdmi);
1721 dw_hdmi_update_phy_mask(hdmi);
1723 mutex_unlock(&hdmi->mutex);
1726 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1727 dev_dbg(hdmi->dev, "EVENT=%s\n",
1728 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1729 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1732 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1733 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1734 HDMI_IH_MUTE_PHY_STAT0);
1739 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1741 struct drm_encoder *encoder = hdmi->encoder;
1742 struct drm_bridge *bridge;
1745 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1747 DRM_ERROR("Failed to allocate drm bridge\n");
1751 hdmi->bridge = bridge;
1752 bridge->driver_private = hdmi;
1753 bridge->funcs = &dw_hdmi_bridge_funcs;
1754 ret = drm_bridge_attach(drm, bridge);
1756 DRM_ERROR("Failed to initialize bridge with drm\n");
1760 encoder->bridge = bridge;
1761 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1762 hdmi->connector.port = hdmi->dev->of_node;
1764 drm_connector_helper_add(&hdmi->connector,
1765 &dw_hdmi_connector_helper_funcs);
1767 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
1768 drm_connector_init(drm, &hdmi->connector,
1769 &dw_hdmi_atomic_connector_funcs,
1770 DRM_MODE_CONNECTOR_HDMIA);
1772 drm_connector_init(drm, &hdmi->connector,
1773 &dw_hdmi_connector_funcs,
1774 DRM_MODE_CONNECTOR_HDMIA);
1776 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1781 int dw_hdmi_bind(struct device *dev, struct device *master,
1782 void *data, struct drm_encoder *encoder,
1783 struct resource *iores, int irq,
1784 const struct dw_hdmi_plat_data *plat_data)
1786 struct drm_device *drm = data;
1787 struct device_node *np = dev->of_node;
1788 struct platform_device_info pdevinfo;
1789 struct device_node *ddc_node;
1790 struct dw_hdmi *hdmi;
1796 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1800 hdmi->connector.interlace_allowed = 1;
1802 hdmi->plat_data = plat_data;
1804 hdmi->dev_type = plat_data->dev_type;
1805 hdmi->sample_rate = 48000;
1806 hdmi->encoder = encoder;
1807 hdmi->disabled = true;
1808 hdmi->rxsense = true;
1809 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1811 mutex_init(&hdmi->mutex);
1812 mutex_init(&hdmi->audio_mutex);
1813 spin_lock_init(&hdmi->audio_lock);
1815 of_property_read_u32(np, "reg-io-width", &val);
1819 hdmi->write = dw_hdmi_writel;
1820 hdmi->read = dw_hdmi_readl;
1823 hdmi->write = dw_hdmi_writeb;
1824 hdmi->read = dw_hdmi_readb;
1827 dev_err(dev, "reg-io-width must be 1 or 4\n");
1831 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1833 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1834 of_node_put(ddc_node);
1836 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1837 return -EPROBE_DEFER;
1841 dev_dbg(hdmi->dev, "no ddc property found\n");
1844 hdmi->regs = devm_ioremap_resource(dev, iores);
1845 if (IS_ERR(hdmi->regs))
1846 return PTR_ERR(hdmi->regs);
1848 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1849 if (IS_ERR(hdmi->isfr_clk)) {
1850 ret = PTR_ERR(hdmi->isfr_clk);
1851 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1855 ret = clk_prepare_enable(hdmi->isfr_clk);
1857 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1861 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1862 if (IS_ERR(hdmi->iahb_clk)) {
1863 ret = PTR_ERR(hdmi->iahb_clk);
1864 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1868 ret = clk_prepare_enable(hdmi->iahb_clk);
1870 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1874 /* Product and revision IDs */
1876 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1877 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1878 hdmi_readb(hdmi, HDMI_REVISION_ID),
1879 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1880 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1882 initialize_hdmi_ih_mutes(hdmi);
1884 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1885 dw_hdmi_irq, IRQF_SHARED,
1886 dev_name(dev), hdmi);
1891 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1892 * N and cts values before enabling phy
1894 hdmi_init_clk_regenerator(hdmi);
1897 * Configure registers related to HDMI interrupt
1898 * generation before registering IRQ.
1900 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1902 /* Clear Hotplug interrupts */
1903 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1906 ret = dw_hdmi_fb_registered(hdmi);
1910 ret = dw_hdmi_register(drm, hdmi);
1914 /* Unmute interrupts */
1915 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1916 HDMI_IH_MUTE_PHY_STAT0);
1918 memset(&pdevinfo, 0, sizeof(pdevinfo));
1919 pdevinfo.parent = dev;
1920 pdevinfo.id = PLATFORM_DEVID_AUTO;
1922 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
1923 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
1925 if (config1 & HDMI_CONFIG1_AHB) {
1926 struct dw_hdmi_audio_data audio;
1928 audio.phys = iores->start;
1929 audio.base = hdmi->regs;
1932 audio.eld = hdmi->connector.eld;
1934 pdevinfo.name = "dw-hdmi-ahb-audio";
1935 pdevinfo.data = &audio;
1936 pdevinfo.size_data = sizeof(audio);
1937 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1938 hdmi->audio = platform_device_register_full(&pdevinfo);
1939 } else if (config0 & HDMI_CONFIG0_I2S) {
1940 struct dw_hdmi_i2s_audio_data audio;
1943 audio.write = hdmi_writeb;
1944 audio.read = hdmi_readb;
1946 pdevinfo.name = "dw-hdmi-i2s-audio";
1947 pdevinfo.data = &audio;
1948 pdevinfo.size_data = sizeof(audio);
1949 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1950 hdmi->audio = platform_device_register_full(&pdevinfo);
1953 dev_set_drvdata(dev, hdmi);
1958 clk_disable_unprepare(hdmi->iahb_clk);
1960 clk_disable_unprepare(hdmi->isfr_clk);
1964 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1966 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1968 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1970 if (hdmi->audio && !IS_ERR(hdmi->audio))
1971 platform_device_unregister(hdmi->audio);
1973 /* Disable all interrupts */
1974 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1976 hdmi->connector.funcs->destroy(&hdmi->connector);
1977 hdmi->encoder->funcs->destroy(hdmi->encoder);
1979 clk_disable_unprepare(hdmi->iahb_clk);
1980 clk_disable_unprepare(hdmi->isfr_clk);
1981 i2c_put_adapter(hdmi->ddc);
1983 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1985 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1986 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1987 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1988 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1989 MODULE_LICENSE("GPL");
1990 MODULE_ALIAS("platform:dw-hdmi");