2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * Designware High-Definition Multimedia Interface (HDMI) driver
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/hdmi.h>
22 #include <linux/mutex.h>
23 #include <linux/of_device.h>
24 #include <linux/spinlock.h>
26 #include <drm/drm_of.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_encoder_slave.h>
32 #include <drm/bridge/dw_hdmi.h>
35 #include "dw-hdmi-audio.h"
37 #define HDMI_EDID_LEN 512
41 #define YCBCR422_16BITS 2
42 #define YCBCR422_8BITS 3
60 * Unless otherwise noted, entries in this table are 100% optimization.
61 * Values can be obtained from hdmi_compute_n() but that function is
62 * slow so we pre-compute values we expect to see.
64 * All 32k and 48k values are expected to be the same (due to the way
65 * the math works) for any rate that's an exact kHz.
67 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
68 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
69 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
70 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
71 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
72 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
73 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
74 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
75 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
76 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
77 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
78 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
79 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
80 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
81 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
82 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
83 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
84 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
85 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
86 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
87 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
88 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
89 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
90 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
91 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
92 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
93 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
94 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
95 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
96 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
98 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
99 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
100 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
101 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
102 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
103 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
104 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
106 /* For 297 MHz+ HDMI spec have some other rule for setting N */
107 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
108 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
111 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
115 static const u16 csc_coeff_default[3][4] = {
116 { 0x2000, 0x0000, 0x0000, 0x0000 },
117 { 0x0000, 0x2000, 0x0000, 0x0000 },
118 { 0x0000, 0x0000, 0x2000, 0x0000 }
121 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
122 { 0x2000, 0x6926, 0x74fd, 0x010e },
123 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
124 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
127 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
128 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
129 { 0x2000, 0x3264, 0x0000, 0x7e6d },
130 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
133 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
134 { 0x2591, 0x1322, 0x074b, 0x0000 },
135 { 0x6535, 0x2000, 0x7acc, 0x0200 },
136 { 0x6acd, 0x7534, 0x2000, 0x0200 }
139 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
140 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
141 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
142 { 0x6756, 0x78ab, 0x2000, 0x0200 }
146 bool mdataenablepolarity;
148 unsigned int mpixelclock;
149 unsigned int mpixelrepetitioninput;
150 unsigned int mpixelrepetitionoutput;
153 struct hdmi_data_info {
154 unsigned int enc_in_format;
155 unsigned int enc_out_format;
156 unsigned int enc_color_depth;
157 unsigned int colorimetry;
158 unsigned int pix_repet_factor;
159 unsigned int hdcp_enable;
160 struct hdmi_vmode video_mode;
164 struct i2c_adapter adap;
167 struct completion cmp;
175 struct drm_connector connector;
176 struct drm_encoder *encoder;
177 struct drm_bridge *bridge;
179 struct platform_device *audio;
180 enum dw_hdmi_devtype dev_type;
182 struct clk *isfr_clk;
183 struct clk *iahb_clk;
184 struct dw_hdmi_i2c *i2c;
186 struct hdmi_data_info hdmi_data;
187 const struct dw_hdmi_plat_data *plat_data;
191 u8 edid[HDMI_EDID_LEN];
195 struct drm_display_mode previous_mode;
197 struct i2c_adapter *ddc;
202 struct mutex mutex; /* for state below and previous_mode */
203 enum drm_connector_force force; /* mutex-protected force state */
204 bool disabled; /* DRM has disabled our bridge */
205 bool bridge_is_on; /* indicates the bridge is on */
206 bool rxsense; /* rxsense state */
207 u8 phy_mask; /* desired phy int mask settings */
209 spinlock_t audio_lock;
210 struct mutex audio_mutex;
211 unsigned int sample_rate;
212 unsigned int audio_cts;
213 unsigned int audio_n;
216 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
217 u8 (*read)(struct dw_hdmi *hdmi, int offset);
220 #define HDMI_IH_PHY_STAT0_RX_SENSE \
221 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
222 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
224 #define HDMI_PHY_RX_SENSE \
225 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
226 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
228 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
230 writel(val, hdmi->regs + (offset << 2));
233 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
235 return readl(hdmi->regs + (offset << 2));
238 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
240 writeb(val, hdmi->regs + offset);
243 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
245 return readb(hdmi->regs + offset);
248 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
250 hdmi->write(hdmi, val, offset);
253 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
255 return hdmi->read(hdmi, offset);
258 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
260 u8 val = hdmi_readb(hdmi, reg) & ~mask;
263 hdmi_writeb(hdmi, val, reg);
266 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
269 hdmi_modb(hdmi, data << shift, mask, reg);
272 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
274 /* Set Standard Mode speed */
275 hdmi_writeb(hdmi, 0x03, HDMI_I2CM_DIV);
278 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
280 /* Set done, not acknowledged and arbitration interrupt polarities */
281 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
282 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
285 /* Clear DONE and ERROR interrupts */
286 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
289 /* Mute DONE and ERROR interrupts */
290 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
291 HDMI_IH_MUTE_I2CM_STAT0);
294 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
295 unsigned char *buf, unsigned int length)
297 struct dw_hdmi_i2c *i2c = hdmi->i2c;
300 if (!i2c->is_regaddr) {
301 dev_dbg(hdmi->dev, "set read register address to 0\n");
302 i2c->slave_reg = 0x00;
303 i2c->is_regaddr = true;
307 reinit_completion(&i2c->cmp);
309 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
310 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
311 HDMI_I2CM_OPERATION);
313 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
317 /* Check for error condition on the bus */
318 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
321 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
327 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
328 unsigned char *buf, unsigned int length)
330 struct dw_hdmi_i2c *i2c = hdmi->i2c;
333 if (!i2c->is_regaddr) {
334 /* Use the first write byte as register address */
335 i2c->slave_reg = buf[0];
338 i2c->is_regaddr = true;
342 reinit_completion(&i2c->cmp);
344 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
345 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
346 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
347 HDMI_I2CM_OPERATION);
349 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
353 /* Check for error condition on the bus */
354 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
361 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
362 struct i2c_msg *msgs, int num)
364 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
365 struct dw_hdmi_i2c *i2c = hdmi->i2c;
366 u8 addr = msgs[0].addr;
369 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
371 for (i = 0; i < num; i++) {
372 if (msgs[i].addr != addr) {
374 "unsupported transfer, changed slave address\n");
378 if (msgs[i].len == 0) {
380 "unsupported transfer %d/%d, no data\n",
386 mutex_lock(&i2c->lock);
388 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
390 /* Set slave device address taken from the first I2C message */
391 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
393 /* Set slave device register address on transfer */
394 i2c->is_regaddr = false;
396 for (i = 0; i < num; i++) {
397 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
398 i + 1, num, msgs[i].len, msgs[i].flags);
400 if (msgs[i].flags & I2C_M_RD)
401 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
403 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
412 /* Mute DONE and ERROR interrupts */
413 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
414 HDMI_IH_MUTE_I2CM_STAT0);
416 mutex_unlock(&i2c->lock);
421 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
423 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
426 static const struct i2c_algorithm dw_hdmi_algorithm = {
427 .master_xfer = dw_hdmi_i2c_xfer,
428 .functionality = dw_hdmi_i2c_func,
431 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
433 struct i2c_adapter *adap;
434 struct dw_hdmi_i2c *i2c;
437 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
439 return ERR_PTR(-ENOMEM);
441 mutex_init(&i2c->lock);
442 init_completion(&i2c->cmp);
445 adap->class = I2C_CLASS_DDC;
446 adap->owner = THIS_MODULE;
447 adap->dev.parent = hdmi->dev;
448 adap->dev.of_node = hdmi->dev->of_node;
449 adap->algo = &dw_hdmi_algorithm;
450 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
451 i2c_set_adapdata(adap, hdmi);
453 ret = i2c_add_adapter(adap);
455 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
456 devm_kfree(hdmi->dev, i2c);
462 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
467 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
470 /* Must be set/cleared first */
471 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
473 /* nshift factor = 0 */
474 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
476 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
477 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
478 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
479 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
481 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
482 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
483 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
486 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
487 unsigned long pixel_clk,
490 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
491 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
494 if (plat_data->tmds_n_table) {
495 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
496 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
497 tmds_n = &plat_data->tmds_n_table[i];
503 if (tmds_n == NULL) {
504 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
505 if (pixel_clk == common_tmds_n_table[i].tmds) {
506 tmds_n = &common_tmds_n_table[i];
517 return tmds_n->n_32k;
521 return (freq / 44100) * tmds_n->n_44k1;
525 return (freq / 48000) * tmds_n->n_48k;
531 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
532 unsigned int pixel_clk)
537 final = (u64)pixel_clk * n;
540 do_div(cts, 128 * freq);
542 diff = final - (u64)cts * (128 * freq);
547 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
548 unsigned long pixel_clk,
551 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
552 unsigned int max_n = (128 * freq) / 300;
553 unsigned int ideal_n = (128 * freq) / 1000;
554 unsigned int best_n_distance = ideal_n;
555 unsigned int best_n = 0;
556 u64 best_diff = U64_MAX;
559 /* If the ideal N could satisfy the audio math, then just take it */
560 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
563 for (n = min_n; n <= max_n; n++) {
564 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
566 if (diff < best_diff || (diff == best_diff &&
567 abs(n - ideal_n) < best_n_distance)) {
570 best_n_distance = abs(best_n - ideal_n);
574 * The best N already satisfy the audio math, and also be
575 * the closest value to ideal N, so just cut the loop.
577 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
584 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
585 unsigned long sample_rate)
589 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
593 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
596 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
599 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
600 unsigned long pixel_clk, unsigned int sample_rate)
602 unsigned long ftdms = pixel_clk;
606 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
609 * Compute the CTS value from the N value. Note that CTS and N
610 * can be up to 20 bits in total, so we need 64-bit math. Also
611 * note that our TDMS clock is not fully accurate; it is accurate
612 * to kHz. This can introduce an unnecessary remainder in the
613 * calculation below, so we don't try to warn about that.
615 tmp = (u64)ftdms * n;
616 do_div(tmp, 128 * sample_rate);
619 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
620 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
623 spin_lock_irq(&hdmi->audio_lock);
625 hdmi->audio_cts = cts;
626 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
627 spin_unlock_irq(&hdmi->audio_lock);
630 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
632 mutex_lock(&hdmi->audio_mutex);
633 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
634 mutex_unlock(&hdmi->audio_mutex);
637 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
639 mutex_lock(&hdmi->audio_mutex);
640 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
642 mutex_unlock(&hdmi->audio_mutex);
645 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
647 mutex_lock(&hdmi->audio_mutex);
648 hdmi->sample_rate = rate;
649 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
651 mutex_unlock(&hdmi->audio_mutex);
653 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
655 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
659 spin_lock_irqsave(&hdmi->audio_lock, flags);
660 hdmi->audio_enable = true;
661 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
662 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
664 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
666 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
670 spin_lock_irqsave(&hdmi->audio_lock, flags);
671 hdmi->audio_enable = false;
672 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
673 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
675 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
678 * this submodule is responsible for the video data synchronization.
679 * for example, for RGB 4:4:4 input, the data map is defined as
680 * pin{47~40} <==> R[7:0]
681 * pin{31~24} <==> G[7:0]
682 * pin{15~8} <==> B[7:0]
684 static void hdmi_video_sample(struct dw_hdmi *hdmi)
686 int color_format = 0;
689 if (hdmi->hdmi_data.enc_in_format == RGB) {
690 if (hdmi->hdmi_data.enc_color_depth == 8)
692 else if (hdmi->hdmi_data.enc_color_depth == 10)
694 else if (hdmi->hdmi_data.enc_color_depth == 12)
696 else if (hdmi->hdmi_data.enc_color_depth == 16)
700 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
701 if (hdmi->hdmi_data.enc_color_depth == 8)
703 else if (hdmi->hdmi_data.enc_color_depth == 10)
705 else if (hdmi->hdmi_data.enc_color_depth == 12)
707 else if (hdmi->hdmi_data.enc_color_depth == 16)
711 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
712 if (hdmi->hdmi_data.enc_color_depth == 8)
714 else if (hdmi->hdmi_data.enc_color_depth == 10)
716 else if (hdmi->hdmi_data.enc_color_depth == 12)
722 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
723 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
724 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
725 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
727 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
728 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
729 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
730 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
731 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
732 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
733 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
734 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
735 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
736 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
737 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
740 static int is_color_space_conversion(struct dw_hdmi *hdmi)
742 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
745 static int is_color_space_decimation(struct dw_hdmi *hdmi)
747 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
749 if (hdmi->hdmi_data.enc_in_format == RGB ||
750 hdmi->hdmi_data.enc_in_format == YCBCR444)
755 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
757 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
759 if (hdmi->hdmi_data.enc_out_format == RGB ||
760 hdmi->hdmi_data.enc_out_format == YCBCR444)
765 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
767 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
771 if (is_color_space_conversion(hdmi)) {
772 if (hdmi->hdmi_data.enc_out_format == RGB) {
773 if (hdmi->hdmi_data.colorimetry ==
774 HDMI_COLORIMETRY_ITU_601)
775 csc_coeff = &csc_coeff_rgb_out_eitu601;
777 csc_coeff = &csc_coeff_rgb_out_eitu709;
778 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
779 if (hdmi->hdmi_data.colorimetry ==
780 HDMI_COLORIMETRY_ITU_601)
781 csc_coeff = &csc_coeff_rgb_in_eitu601;
783 csc_coeff = &csc_coeff_rgb_in_eitu709;
788 /* The CSC registers are sequential, alternating MSB then LSB */
789 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
790 u16 coeff_a = (*csc_coeff)[0][i];
791 u16 coeff_b = (*csc_coeff)[1][i];
792 u16 coeff_c = (*csc_coeff)[2][i];
794 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
795 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
796 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
797 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
798 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
799 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
802 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
806 static void hdmi_video_csc(struct dw_hdmi *hdmi)
809 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
812 /* YCC422 interpolation to 444 mode */
813 if (is_color_space_interpolation(hdmi))
814 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
815 else if (is_color_space_decimation(hdmi))
816 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
818 if (hdmi->hdmi_data.enc_color_depth == 8)
819 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
820 else if (hdmi->hdmi_data.enc_color_depth == 10)
821 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
822 else if (hdmi->hdmi_data.enc_color_depth == 12)
823 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
824 else if (hdmi->hdmi_data.enc_color_depth == 16)
825 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
829 /* Configure the CSC registers */
830 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
831 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
834 dw_hdmi_update_csc_coeffs(hdmi);
838 * HDMI video packetizer is used to packetize the data.
839 * for example, if input is YCC422 mode or repeater is used,
840 * data should be repacked this module can be bypassed.
842 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
844 unsigned int color_depth = 0;
845 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
846 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
847 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
850 if (hdmi_data->enc_out_format == RGB ||
851 hdmi_data->enc_out_format == YCBCR444) {
852 if (!hdmi_data->enc_color_depth) {
853 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
854 } else if (hdmi_data->enc_color_depth == 8) {
856 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
857 } else if (hdmi_data->enc_color_depth == 10) {
859 } else if (hdmi_data->enc_color_depth == 12) {
861 } else if (hdmi_data->enc_color_depth == 16) {
866 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
867 if (!hdmi_data->enc_color_depth ||
868 hdmi_data->enc_color_depth == 8)
869 remap_size = HDMI_VP_REMAP_YCC422_16bit;
870 else if (hdmi_data->enc_color_depth == 10)
871 remap_size = HDMI_VP_REMAP_YCC422_20bit;
872 else if (hdmi_data->enc_color_depth == 12)
873 remap_size = HDMI_VP_REMAP_YCC422_24bit;
876 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
881 /* set the packetizer registers */
882 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
883 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
884 ((hdmi_data->pix_repet_factor <<
885 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
886 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
887 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
889 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
890 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
892 /* Data from pixel repeater block */
893 if (hdmi_data->pix_repet_factor > 1) {
894 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
895 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
896 } else { /* data from packetizer block */
897 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
898 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
901 hdmi_modb(hdmi, vp_conf,
902 HDMI_VP_CONF_PR_EN_MASK |
903 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
905 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
906 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
908 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
910 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
911 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
912 HDMI_VP_CONF_PP_EN_ENABLE |
913 HDMI_VP_CONF_YCC422_EN_DISABLE;
914 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
915 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
916 HDMI_VP_CONF_PP_EN_DISABLE |
917 HDMI_VP_CONF_YCC422_EN_ENABLE;
918 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
919 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
920 HDMI_VP_CONF_PP_EN_DISABLE |
921 HDMI_VP_CONF_YCC422_EN_DISABLE;
926 hdmi_modb(hdmi, vp_conf,
927 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
928 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
930 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
931 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
932 HDMI_VP_STUFF_PP_STUFFING_MASK |
933 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
935 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
939 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
942 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
943 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
946 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
949 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
950 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
953 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
956 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
957 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
960 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
963 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
966 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
969 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
972 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
976 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
981 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
986 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
989 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
990 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
991 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
992 HDMI_PHY_I2CM_DATAO_1_ADDR);
993 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
994 HDMI_PHY_I2CM_DATAO_0_ADDR);
995 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
996 HDMI_PHY_I2CM_OPERATION_ADDR);
997 hdmi_phy_wait_i2c_done(hdmi, 1000);
1000 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1003 __hdmi_phy_i2c_write(hdmi, data, addr);
1007 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1009 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1010 HDMI_PHY_CONF0_PDZ_OFFSET,
1011 HDMI_PHY_CONF0_PDZ_MASK);
1014 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1016 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1017 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1018 HDMI_PHY_CONF0_ENTMDS_MASK);
1021 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1023 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1024 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1025 HDMI_PHY_CONF0_SPARECTRL_MASK);
1028 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1030 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1031 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1032 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1035 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1037 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1038 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1039 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1042 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1044 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1045 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1046 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1049 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1051 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1052 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1053 HDMI_PHY_CONF0_SELDIPIF_MASK);
1056 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1057 unsigned char res, int cscon)
1061 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1062 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1063 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1064 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1070 case 0: /* color resolution 0 is 8 bit colour depth */
1072 res_idx = DW_HDMI_RES_8;
1075 res_idx = DW_HDMI_RES_10;
1078 res_idx = DW_HDMI_RES_12;
1084 /* PLL/MPLL Cfg - always match on final entry */
1085 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1086 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1087 mpll_config->mpixelclock)
1090 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1091 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1092 curr_ctrl->mpixelclock)
1095 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1096 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1097 phy_config->mpixelclock)
1100 if (mpll_config->mpixelclock == ~0UL ||
1101 curr_ctrl->mpixelclock == ~0UL ||
1102 phy_config->mpixelclock == ~0UL) {
1103 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1104 hdmi->hdmi_data.video_mode.mpixelclock);
1108 /* Enable csc path */
1110 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1112 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1114 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1116 /* gen2 tx power off */
1117 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1120 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1123 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1124 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1126 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1128 hdmi_phy_test_clear(hdmi, 1);
1129 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1130 HDMI_PHY_I2CM_SLAVE_ADDR);
1131 hdmi_phy_test_clear(hdmi, 0);
1133 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1134 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1137 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1139 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1140 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1142 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
1143 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1144 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1146 /* REMOVE CLK TERM */
1147 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1149 dw_hdmi_phy_enable_powerdown(hdmi, false);
1151 /* toggle TMDS enable */
1152 dw_hdmi_phy_enable_tmds(hdmi, 0);
1153 dw_hdmi_phy_enable_tmds(hdmi, 1);
1155 /* gen2 tx power on */
1156 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1157 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1159 if (is_rockchip(hdmi->dev_type))
1160 dw_hdmi_phy_enable_spare(hdmi, 1);
1162 /*Wait for PHY PLL lock */
1165 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1170 dev_err(hdmi->dev, "PHY PLL not locked\n");
1181 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1186 /*check csc whether needed activated in HDMI mode */
1187 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1189 /* HDMI Phy spec says to do the phy initialization sequence twice */
1190 for (i = 0; i < 2; i++) {
1191 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1192 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1193 dw_hdmi_phy_enable_tmds(hdmi, 0);
1194 dw_hdmi_phy_enable_powerdown(hdmi, true);
1197 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1202 hdmi->phy_enabled = true;
1206 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1210 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1211 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1213 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1215 /* disable rx detect */
1216 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1217 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1219 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1221 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1222 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1225 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1227 struct hdmi_avi_infoframe frame;
1230 /* Initialise info frame from DRM mode */
1231 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1233 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1234 frame.colorspace = HDMI_COLORSPACE_YUV444;
1235 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1236 frame.colorspace = HDMI_COLORSPACE_YUV422;
1238 frame.colorspace = HDMI_COLORSPACE_RGB;
1240 /* Set up colorimetry */
1241 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1242 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1243 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1244 frame.extended_colorimetry =
1245 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1246 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1247 frame.extended_colorimetry =
1248 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1249 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1250 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1251 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1252 } else { /* Carries no data */
1253 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1254 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1257 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1260 * The Designware IP uses a different byte format from standard
1261 * AVI info frames, though generally the bits are in the correct
1266 * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1267 * active aspect present in bit 6 rather than 4.
1269 val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1270 if (frame.active_aspect & 15)
1271 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1272 if (frame.top_bar || frame.bottom_bar)
1273 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1274 if (frame.left_bar || frame.right_bar)
1275 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1276 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1278 /* AVI data byte 2 differences: none */
1279 val = ((frame.colorimetry & 0x3) << 6) |
1280 ((frame.picture_aspect & 0x3) << 4) |
1281 (frame.active_aspect & 0xf);
1282 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1284 /* AVI data byte 3 differences: none */
1285 val = ((frame.extended_colorimetry & 0x7) << 4) |
1286 ((frame.quantization_range & 0x3) << 2) |
1289 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1290 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1292 /* AVI data byte 4 differences: none */
1293 val = frame.video_code & 0x7f;
1294 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1296 /* AVI Data Byte 5- set up input and output pixel repetition */
1297 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1298 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1299 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1300 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1301 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1302 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1303 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1306 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1307 * ycc range in bits 2,3 rather than 6,7
1309 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1310 (frame.content_type & 0x3);
1311 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1313 /* AVI Data Bytes 6-13 */
1314 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1315 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1316 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1317 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1318 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1319 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1320 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1321 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1324 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1325 const struct drm_display_mode *mode)
1328 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1329 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1330 unsigned int vdisplay;
1332 vmode->mpixelclock = mode->clock * 1000;
1334 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1336 /* Set up HDMI_FC_INVIDCONF */
1337 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1338 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1339 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1341 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1342 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1343 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1345 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1346 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1347 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1349 inv_val |= (vmode->mdataenablepolarity ?
1350 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1351 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1353 if (hdmi->vic == 39)
1354 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1356 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1357 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1358 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1360 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1361 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1362 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1364 inv_val |= hdmi->sink_is_hdmi ?
1365 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1366 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1368 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1370 vdisplay = mode->vdisplay;
1371 vblank = mode->vtotal - mode->vdisplay;
1372 v_de_vs = mode->vsync_start - mode->vdisplay;
1373 vsync_len = mode->vsync_end - mode->vsync_start;
1376 * When we're setting an interlaced mode, we need
1377 * to adjust the vertical timing to suit.
1379 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1386 /* Set up horizontal active pixel width */
1387 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1388 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1390 /* Set up vertical active lines */
1391 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1392 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1394 /* Set up horizontal blanking pixel region width */
1395 hblank = mode->htotal - mode->hdisplay;
1396 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1397 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1399 /* Set up vertical blanking pixel region width */
1400 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1402 /* Set up HSYNC active edge delay width (in pixel clks) */
1403 h_de_hs = mode->hsync_start - mode->hdisplay;
1404 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1405 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1407 /* Set up VSYNC active edge delay (in lines) */
1408 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1410 /* Set up HSYNC active pulse width (in pixel clks) */
1411 hsync_len = mode->hsync_end - mode->hsync_start;
1412 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1413 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1415 /* Set up VSYNC active edge delay (in lines) */
1416 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1419 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1421 if (!hdmi->phy_enabled)
1424 dw_hdmi_phy_enable_tmds(hdmi, 0);
1425 dw_hdmi_phy_enable_powerdown(hdmi, true);
1427 hdmi->phy_enabled = false;
1430 /* HDMI Initialization Step B.4 */
1431 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1435 /* control period minimum duration */
1436 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1437 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1438 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1440 /* Set to fill TMDS data channels */
1441 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1442 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1443 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1445 /* Enable pixel clock and tmds data path */
1447 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1448 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1450 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1451 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1453 /* Enable csc path */
1454 if (is_color_space_conversion(hdmi)) {
1455 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1456 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1460 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1462 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1465 /* Workaround to clear the overflow condition */
1466 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1471 /* TMDS software reset */
1472 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1474 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1475 if (hdmi->dev_type == IMX6DL_HDMI) {
1476 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1480 for (count = 0; count < 4; count++)
1481 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1484 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1486 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1487 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1490 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1492 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1493 HDMI_IH_MUTE_FC_STAT2);
1496 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1500 hdmi_disable_overflow_interrupts(hdmi);
1502 hdmi->vic = drm_match_cea_mode(mode);
1505 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1507 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1510 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1511 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1512 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1513 (hdmi->vic == 17) || (hdmi->vic == 18))
1514 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1516 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1518 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1519 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1521 /* TODO: Get input format from IPU (via FB driver interface) */
1522 hdmi->hdmi_data.enc_in_format = RGB;
1524 hdmi->hdmi_data.enc_out_format = RGB;
1526 hdmi->hdmi_data.enc_color_depth = 8;
1527 hdmi->hdmi_data.pix_repet_factor = 0;
1528 hdmi->hdmi_data.hdcp_enable = 0;
1529 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1531 /* HDMI Initialization Step B.1 */
1532 hdmi_av_composer(hdmi, mode);
1534 /* HDMI Initializateion Step B.2 */
1535 ret = dw_hdmi_phy_init(hdmi);
1539 /* HDMI Initialization Step B.3 */
1540 dw_hdmi_enable_video_path(hdmi);
1542 if (hdmi->sink_has_audio) {
1543 dev_dbg(hdmi->dev, "sink has audio support\n");
1545 /* HDMI Initialization Step E - Configure audio */
1546 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1547 hdmi_enable_audio_clk(hdmi);
1550 /* not for DVI mode */
1551 if (hdmi->sink_is_hdmi) {
1552 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1554 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1555 hdmi_config_AVI(hdmi, mode);
1557 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1560 hdmi_video_packetize(hdmi);
1561 hdmi_video_csc(hdmi);
1562 hdmi_video_sample(hdmi);
1563 hdmi_tx_hdcp_config(hdmi);
1565 dw_hdmi_clear_overflow(hdmi);
1566 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1567 hdmi_enable_overflow_interrupts(hdmi);
1572 /* Wait until we are registered to enable interrupts */
1573 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1575 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1576 HDMI_PHY_I2CM_INT_ADDR);
1578 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1579 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1580 HDMI_PHY_I2CM_CTLINT_ADDR);
1582 /* enable cable hot plug irq */
1583 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1585 /* Clear Hotplug interrupts */
1586 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1592 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1597 * Boot up defaults are:
1598 * HDMI_IH_MUTE = 0x03 (disabled)
1599 * HDMI_IH_MUTE_* = 0x00 (enabled)
1601 * Disable top level interrupt bits in HDMI block
1603 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1604 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1605 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1607 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1609 /* by default mask all interrupts */
1610 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1611 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1612 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1613 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1614 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1615 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1616 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1617 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1618 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1619 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1620 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1621 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1622 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1623 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1624 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1626 /* Disable interrupts in the IH_MUTE_* registers */
1627 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1628 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1629 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1630 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1631 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1632 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1633 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1634 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1635 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1636 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1638 /* Enable top level interrupt bits in HDMI block */
1639 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1640 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1641 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1644 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1646 hdmi->bridge_is_on = true;
1647 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1650 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1652 dw_hdmi_phy_disable(hdmi);
1653 hdmi->bridge_is_on = false;
1656 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1658 int force = hdmi->force;
1660 if (hdmi->disabled) {
1661 force = DRM_FORCE_OFF;
1662 } else if (force == DRM_FORCE_UNSPECIFIED) {
1664 force = DRM_FORCE_ON;
1666 force = DRM_FORCE_OFF;
1669 if (force == DRM_FORCE_OFF) {
1670 if (hdmi->bridge_is_on)
1671 dw_hdmi_poweroff(hdmi);
1673 if (!hdmi->bridge_is_on)
1674 dw_hdmi_poweron(hdmi);
1679 * Adjust the detection of RXSENSE according to whether we have a forced
1680 * connection mode enabled, or whether we have been disabled. There is
1681 * no point processing RXSENSE interrupts if we have a forced connection
1682 * state, or DRM has us disabled.
1684 * We also disable rxsense interrupts when we think we're disconnected
1685 * to avoid floating TDMS signals giving false rxsense interrupts.
1687 * Note: we still need to listen for HPD interrupts even when DRM has us
1688 * disabled so that we can detect a connect event.
1690 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1692 u8 old_mask = hdmi->phy_mask;
1694 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1695 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1697 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1699 if (old_mask != hdmi->phy_mask)
1700 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1703 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1704 struct drm_display_mode *orig_mode,
1705 struct drm_display_mode *mode)
1707 struct dw_hdmi *hdmi = bridge->driver_private;
1709 mutex_lock(&hdmi->mutex);
1711 /* Store the display mode for plugin/DKMS poweron events */
1712 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1714 mutex_unlock(&hdmi->mutex);
1717 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1719 struct dw_hdmi *hdmi = bridge->driver_private;
1721 mutex_lock(&hdmi->mutex);
1722 hdmi->disabled = true;
1723 dw_hdmi_update_power(hdmi);
1724 dw_hdmi_update_phy_mask(hdmi);
1725 mutex_unlock(&hdmi->mutex);
1728 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1730 struct dw_hdmi *hdmi = bridge->driver_private;
1732 mutex_lock(&hdmi->mutex);
1733 hdmi->disabled = false;
1734 dw_hdmi_update_power(hdmi);
1735 dw_hdmi_update_phy_mask(hdmi);
1736 mutex_unlock(&hdmi->mutex);
1739 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1744 static enum drm_connector_status
1745 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1747 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1750 mutex_lock(&hdmi->mutex);
1751 hdmi->force = DRM_FORCE_UNSPECIFIED;
1752 dw_hdmi_update_power(hdmi);
1753 dw_hdmi_update_phy_mask(hdmi);
1754 mutex_unlock(&hdmi->mutex);
1756 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1757 connector_status_connected : connector_status_disconnected;
1760 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1762 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1770 edid = drm_get_edid(connector, hdmi->ddc);
1772 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1773 edid->width_cm, edid->height_cm);
1775 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1776 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1777 drm_mode_connector_update_edid_property(connector, edid);
1778 ret = drm_add_edid_modes(connector, edid);
1780 drm_edid_to_eld(connector, edid);
1783 dev_dbg(hdmi->dev, "failed to get edid\n");
1789 static enum drm_mode_status
1790 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1791 struct drm_display_mode *mode)
1793 struct dw_hdmi *hdmi = container_of(connector,
1794 struct dw_hdmi, connector);
1795 enum drm_mode_status mode_status = MODE_OK;
1797 /* We don't support double-clocked modes */
1798 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1801 if (hdmi->plat_data->mode_valid)
1802 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1807 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1810 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1813 return hdmi->encoder;
1816 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1818 drm_connector_unregister(connector);
1819 drm_connector_cleanup(connector);
1822 static void dw_hdmi_connector_force(struct drm_connector *connector)
1824 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1827 mutex_lock(&hdmi->mutex);
1828 hdmi->force = connector->force;
1829 dw_hdmi_update_power(hdmi);
1830 dw_hdmi_update_phy_mask(hdmi);
1831 mutex_unlock(&hdmi->mutex);
1834 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1835 .dpms = drm_helper_connector_dpms,
1836 .fill_modes = drm_helper_probe_single_connector_modes,
1837 .detect = dw_hdmi_connector_detect,
1838 .destroy = dw_hdmi_connector_destroy,
1839 .force = dw_hdmi_connector_force,
1842 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1843 .dpms = drm_atomic_helper_connector_dpms,
1844 .fill_modes = drm_helper_probe_single_connector_modes,
1845 .detect = dw_hdmi_connector_detect,
1846 .destroy = dw_hdmi_connector_destroy,
1847 .force = dw_hdmi_connector_force,
1848 .reset = drm_atomic_helper_connector_reset,
1849 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1850 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1853 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1854 .get_modes = dw_hdmi_connector_get_modes,
1855 .mode_valid = dw_hdmi_connector_mode_valid,
1856 .best_encoder = dw_hdmi_connector_best_encoder,
1859 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1860 .enable = dw_hdmi_bridge_enable,
1861 .disable = dw_hdmi_bridge_disable,
1862 .pre_enable = dw_hdmi_bridge_nop,
1863 .post_disable = dw_hdmi_bridge_nop,
1864 .mode_set = dw_hdmi_bridge_mode_set,
1867 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1869 struct dw_hdmi_i2c *i2c = hdmi->i2c;
1872 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1876 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1880 complete(&i2c->cmp);
1885 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1887 struct dw_hdmi *hdmi = dev_id;
1889 irqreturn_t ret = IRQ_NONE;
1892 ret = dw_hdmi_i2c_irq(hdmi);
1894 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1896 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1897 return IRQ_WAKE_THREAD;
1903 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1905 struct dw_hdmi *hdmi = dev_id;
1906 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1908 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1909 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1910 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1913 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1914 phy_pol_mask |= HDMI_PHY_HPD;
1915 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1916 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1917 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1918 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1919 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1920 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1921 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1922 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1925 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1928 * RX sense tells us whether the TDMS transmitters are detecting
1929 * load - in other words, there's something listening on the
1930 * other end of the link. Use this to decide whether we should
1931 * power on the phy as HPD may be toggled by the sink to merely
1932 * ask the source to re-read the EDID.
1935 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1936 mutex_lock(&hdmi->mutex);
1937 if (!hdmi->bridge_is_on && !hdmi->force) {
1939 * If the RX sense status indicates we're disconnected,
1940 * clear the software rxsense status.
1942 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1943 hdmi->rxsense = false;
1946 * Only set the software rxsense status when both
1947 * rxsense and hpd indicates we're connected.
1948 * This avoids what seems to be bad behaviour in
1949 * at least iMX6S versions of the phy.
1951 if (phy_stat & HDMI_PHY_HPD)
1952 hdmi->rxsense = true;
1954 dw_hdmi_update_power(hdmi);
1955 dw_hdmi_update_phy_mask(hdmi);
1957 mutex_unlock(&hdmi->mutex);
1960 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1961 dev_dbg(hdmi->dev, "EVENT=%s\n",
1962 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1963 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1966 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1967 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1968 HDMI_IH_MUTE_PHY_STAT0);
1973 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1975 struct drm_encoder *encoder = hdmi->encoder;
1976 struct drm_bridge *bridge;
1979 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1981 DRM_ERROR("Failed to allocate drm bridge\n");
1985 hdmi->bridge = bridge;
1986 bridge->driver_private = hdmi;
1987 bridge->funcs = &dw_hdmi_bridge_funcs;
1988 ret = drm_bridge_attach(drm, bridge);
1990 DRM_ERROR("Failed to initialize bridge with drm\n");
1994 encoder->bridge = bridge;
1995 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1996 hdmi->connector.port = hdmi->dev->of_node;
1998 drm_connector_helper_add(&hdmi->connector,
1999 &dw_hdmi_connector_helper_funcs);
2001 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2002 drm_connector_init(drm, &hdmi->connector,
2003 &dw_hdmi_atomic_connector_funcs,
2004 DRM_MODE_CONNECTOR_HDMIA);
2006 drm_connector_init(drm, &hdmi->connector,
2007 &dw_hdmi_connector_funcs,
2008 DRM_MODE_CONNECTOR_HDMIA);
2010 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2015 int dw_hdmi_bind(struct device *dev, struct device *master,
2016 void *data, struct drm_encoder *encoder,
2017 struct resource *iores, int irq,
2018 const struct dw_hdmi_plat_data *plat_data)
2020 struct drm_device *drm = data;
2021 struct device_node *np = dev->of_node;
2022 struct platform_device_info pdevinfo;
2023 struct device_node *ddc_node;
2024 struct dw_hdmi *hdmi;
2030 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2034 hdmi->connector.interlace_allowed = 1;
2036 hdmi->plat_data = plat_data;
2038 hdmi->dev_type = plat_data->dev_type;
2039 hdmi->sample_rate = 48000;
2040 hdmi->encoder = encoder;
2041 hdmi->disabled = true;
2042 hdmi->rxsense = true;
2043 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2045 mutex_init(&hdmi->mutex);
2046 mutex_init(&hdmi->audio_mutex);
2047 spin_lock_init(&hdmi->audio_lock);
2049 of_property_read_u32(np, "reg-io-width", &val);
2053 hdmi->write = dw_hdmi_writel;
2054 hdmi->read = dw_hdmi_readl;
2057 hdmi->write = dw_hdmi_writeb;
2058 hdmi->read = dw_hdmi_readb;
2061 dev_err(dev, "reg-io-width must be 1 or 4\n");
2065 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2067 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2068 of_node_put(ddc_node);
2070 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2071 return -EPROBE_DEFER;
2075 dev_dbg(hdmi->dev, "no ddc property found\n");
2078 /* If DDC bus is not specified, try to register HDMI I2C bus */
2080 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2081 if (IS_ERR(hdmi->ddc))
2085 hdmi->regs = devm_ioremap_resource(dev, iores);
2086 if (IS_ERR(hdmi->regs))
2087 return PTR_ERR(hdmi->regs);
2089 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2090 if (IS_ERR(hdmi->isfr_clk)) {
2091 ret = PTR_ERR(hdmi->isfr_clk);
2092 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2096 ret = clk_prepare_enable(hdmi->isfr_clk);
2098 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2102 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2103 if (IS_ERR(hdmi->iahb_clk)) {
2104 ret = PTR_ERR(hdmi->iahb_clk);
2105 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2109 ret = clk_prepare_enable(hdmi->iahb_clk);
2111 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2115 /* Product and revision IDs */
2117 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2118 hdmi_readb(hdmi, HDMI_DESIGN_ID),
2119 hdmi_readb(hdmi, HDMI_REVISION_ID),
2120 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2121 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2123 initialize_hdmi_ih_mutes(hdmi);
2125 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2126 dw_hdmi_irq, IRQF_SHARED,
2127 dev_name(dev), hdmi);
2132 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2133 * N and cts values before enabling phy
2135 hdmi_init_clk_regenerator(hdmi);
2138 * Configure registers related to HDMI interrupt
2139 * generation before registering IRQ.
2141 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2143 /* Clear Hotplug interrupts */
2144 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
2147 ret = dw_hdmi_fb_registered(hdmi);
2151 ret = dw_hdmi_register(drm, hdmi);
2155 /* Unmute interrupts */
2156 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2157 HDMI_IH_MUTE_PHY_STAT0);
2159 /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2161 dw_hdmi_i2c_init(hdmi);
2163 memset(&pdevinfo, 0, sizeof(pdevinfo));
2164 pdevinfo.parent = dev;
2165 pdevinfo.id = PLATFORM_DEVID_AUTO;
2167 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2168 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2170 if (config1 & HDMI_CONFIG1_AHB) {
2171 struct dw_hdmi_audio_data audio;
2173 audio.phys = iores->start;
2174 audio.base = hdmi->regs;
2177 audio.eld = hdmi->connector.eld;
2179 pdevinfo.name = "dw-hdmi-ahb-audio";
2180 pdevinfo.data = &audio;
2181 pdevinfo.size_data = sizeof(audio);
2182 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2183 hdmi->audio = platform_device_register_full(&pdevinfo);
2184 } else if (config0 & HDMI_CONFIG0_I2S) {
2185 struct dw_hdmi_i2s_audio_data audio;
2188 audio.write = hdmi_writeb;
2189 audio.read = hdmi_readb;
2191 pdevinfo.name = "dw-hdmi-i2s-audio";
2192 pdevinfo.data = &audio;
2193 pdevinfo.size_data = sizeof(audio);
2194 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2195 hdmi->audio = platform_device_register_full(&pdevinfo);
2198 dev_set_drvdata(dev, hdmi);
2204 i2c_del_adapter(&hdmi->i2c->adap);
2206 clk_disable_unprepare(hdmi->iahb_clk);
2208 clk_disable_unprepare(hdmi->isfr_clk);
2212 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2214 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2216 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2218 if (hdmi->audio && !IS_ERR(hdmi->audio))
2219 platform_device_unregister(hdmi->audio);
2221 /* Disable all interrupts */
2222 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2224 hdmi->connector.funcs->destroy(&hdmi->connector);
2225 hdmi->encoder->funcs->destroy(hdmi->encoder);
2227 clk_disable_unprepare(hdmi->iahb_clk);
2228 clk_disable_unprepare(hdmi->isfr_clk);
2231 i2c_del_adapter(&hdmi->i2c->adap);
2233 i2c_put_adapter(hdmi->ddc);
2235 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2237 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2238 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2239 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2240 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2241 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2242 MODULE_LICENSE("GPL");
2243 MODULE_ALIAS("platform:dw-hdmi");