Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / armada / armada_crtc.c
1 /*
2  * Copyright (C) 2012 Russell King
3  *  Rewritten from the dovefb driver, and Armada510 manuals.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include "armada_crtc.h"
16 #include "armada_drm.h"
17 #include "armada_fb.h"
18 #include "armada_gem.h"
19 #include "armada_hw.h"
20
21 struct armada_frame_work {
22         struct drm_pending_vblank_event *event;
23         struct armada_regs regs[4];
24         struct drm_framebuffer *old_fb;
25 };
26
27 enum csc_mode {
28         CSC_AUTO = 0,
29         CSC_YUV_CCIR601 = 1,
30         CSC_YUV_CCIR709 = 2,
31         CSC_RGB_COMPUTER = 1,
32         CSC_RGB_STUDIO = 2,
33 };
34
35 /*
36  * A note about interlacing.  Let's consider HDMI 1920x1080i.
37  * The timing parameters we have from X are:
38  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
39  *  1920 2448 2492 2640  1080 1084 1094 1125
40  * Which get translated to:
41  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
42  *  1920 2448 2492 2640   540  542  547  562
43  *
44  * This is how it is defined by CEA-861-D - line and pixel numbers are
45  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
46  * line: 2640.  The odd frame, the first active line is at line 21, and
47  * the even frame, the first active line is 584.
48  *
49  * LN:    560     561     562     563             567     568    569
50  * DE:    ~~~|____________________________//__________________________
51  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
52  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
53  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
54  *
55  * LN:    1123   1124    1125      1               5       6      7
56  * DE:    ~~~|____________________________//__________________________
57  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
58  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
59  *  23 blanking lines
60  *
61  * The Armada LCD Controller line and pixel numbers are, like X timings,
62  * referenced to the top left of the active frame.
63  *
64  * So, translating these to our LCD controller:
65  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
66  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
67  * Note: Vsync front porch remains constant!
68  *
69  * if (odd_frame) {
70  *   vtotal = mode->crtc_vtotal + 1;
71  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
72  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
73  * } else {
74  *   vtotal = mode->crtc_vtotal;
75  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
76  *   vhorizpos = mode->crtc_hsync_start;
77  * }
78  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
79  *
80  * So, we need to reprogram these registers on each vsync event:
81  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
82  *
83  * Note: we do not use the frame done interrupts because these appear
84  * to happen too early, and lead to jitter on the display (presumably
85  * they occur at the end of the last active line, before the vsync back
86  * porch, which we're reprogramming.)
87  */
88
89 void
90 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
91 {
92         while (regs->offset != ~0) {
93                 void __iomem *reg = dcrtc->base + regs->offset;
94                 uint32_t val;
95
96                 val = regs->mask;
97                 if (val != 0)
98                         val &= readl_relaxed(reg);
99                 writel_relaxed(val | regs->val, reg);
100                 ++regs;
101         }
102 }
103
104 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
105
106 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
107 {
108         uint32_t dumb_ctrl;
109
110         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
111
112         if (!dpms_blanked(dcrtc->dpms))
113                 dumb_ctrl |= CFG_DUMB_ENA;
114
115         /*
116          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
117          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
118          * force LCD_D[23:0] to output blank color, overriding the GPIO or
119          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
120          */
121         if (dpms_blanked(dcrtc->dpms) &&
122             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
123                 dumb_ctrl &= ~DUMB_MASK;
124                 dumb_ctrl |= DUMB_BLANK;
125         }
126
127         /*
128          * The documentation doesn't indicate what the normal state of
129          * the sync signals are.  Sebastian Hesselbart kindly probed
130          * these signals on his board to determine their state.
131          *
132          * The non-inverted state of the sync signals is active high.
133          * Setting these bits makes the appropriate signal active low.
134          */
135         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
136                 dumb_ctrl |= CFG_INV_CSYNC;
137         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
138                 dumb_ctrl |= CFG_INV_HSYNC;
139         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
140                 dumb_ctrl |= CFG_INV_VSYNC;
141
142         if (dcrtc->dumb_ctrl != dumb_ctrl) {
143                 dcrtc->dumb_ctrl = dumb_ctrl;
144                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
145         }
146 }
147
148 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
149         int x, int y, struct armada_regs *regs, bool interlaced)
150 {
151         struct armada_gem_object *obj = drm_fb_obj(fb);
152         unsigned pitch = fb->pitches[0];
153         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
154         uint32_t addr_odd, addr_even;
155         unsigned i = 0;
156
157         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
158                 pitch, x, y, fb->bits_per_pixel);
159
160         addr_odd = addr_even = obj->dev_addr + offset;
161
162         if (interlaced) {
163                 addr_even += pitch;
164                 pitch *= 2;
165         }
166
167         /* write offset, base, and pitch */
168         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
169         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
170         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
171
172         return i;
173 }
174
175 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
176         struct armada_frame_work *work)
177 {
178         struct drm_device *dev = dcrtc->crtc.dev;
179         unsigned long flags;
180         int ret;
181
182         ret = drm_vblank_get(dev, dcrtc->num);
183         if (ret) {
184                 DRM_ERROR("failed to acquire vblank counter\n");
185                 return ret;
186         }
187
188         spin_lock_irqsave(&dev->event_lock, flags);
189         if (!dcrtc->frame_work)
190                 dcrtc->frame_work = work;
191         else
192                 ret = -EBUSY;
193         spin_unlock_irqrestore(&dev->event_lock, flags);
194
195         if (ret)
196                 drm_vblank_put(dev, dcrtc->num);
197
198         return ret;
199 }
200
201 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
202 {
203         struct drm_device *dev = dcrtc->crtc.dev;
204         struct armada_frame_work *work = dcrtc->frame_work;
205
206         dcrtc->frame_work = NULL;
207
208         armada_drm_crtc_update_regs(dcrtc, work->regs);
209
210         if (work->event)
211                 drm_send_vblank_event(dev, dcrtc->num, work->event);
212
213         drm_vblank_put(dev, dcrtc->num);
214
215         /* Finally, queue the process-half of the cleanup. */
216         __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
217         kfree(work);
218 }
219
220 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
221         struct drm_framebuffer *fb, bool force)
222 {
223         struct armada_frame_work *work;
224
225         if (!fb)
226                 return;
227
228         if (force) {
229                 /* Display is disabled, so just drop the old fb */
230                 drm_framebuffer_unreference(fb);
231                 return;
232         }
233
234         work = kmalloc(sizeof(*work), GFP_KERNEL);
235         if (work) {
236                 int i = 0;
237                 work->event = NULL;
238                 work->old_fb = fb;
239                 armada_reg_queue_end(work->regs, i);
240
241                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
242                         return;
243
244                 kfree(work);
245         }
246
247         /*
248          * Oops - just drop the reference immediately and hope for
249          * the best.  The worst that will happen is the buffer gets
250          * reused before it has finished being displayed.
251          */
252         drm_framebuffer_unreference(fb);
253 }
254
255 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
256 {
257         struct drm_device *dev = dcrtc->crtc.dev;
258
259         /*
260          * Tell the DRM core that vblank IRQs aren't going to happen for
261          * a while.  This cleans up any pending vblank events for us.
262          */
263         drm_vblank_off(dev, dcrtc->num);
264
265         /* Handle any pending flip event. */
266         spin_lock_irq(&dev->event_lock);
267         if (dcrtc->frame_work)
268                 armada_drm_crtc_complete_frame_work(dcrtc);
269         spin_unlock_irq(&dev->event_lock);
270 }
271
272 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
273         int idx)
274 {
275 }
276
277 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
278         int idx)
279 {
280 }
281
282 /* The mode_config.mutex will be held for this call */
283 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
284 {
285         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
286
287         if (dcrtc->dpms != dpms) {
288                 dcrtc->dpms = dpms;
289                 armada_drm_crtc_update(dcrtc);
290                 if (dpms_blanked(dpms))
291                         armada_drm_vblank_off(dcrtc);
292         }
293 }
294
295 /*
296  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
297  * up with the overlay size being bigger than the active screen size.
298  * We rely upon X refreshing this state after the mode set has completed.
299  *
300  * The mode_config.mutex will be held for this call
301  */
302 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
303 {
304         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
305         struct drm_plane *plane;
306
307         /*
308          * If we have an overlay plane associated with this CRTC, disable
309          * it before the modeset to avoid its coordinates being outside
310          * the new mode parameters.  DRM doesn't provide help with this.
311          */
312         plane = dcrtc->plane;
313         if (plane) {
314                 struct drm_framebuffer *fb = plane->fb;
315
316                 plane->funcs->disable_plane(plane);
317                 plane->fb = NULL;
318                 plane->crtc = NULL;
319                 drm_framebuffer_unreference(fb);
320         }
321 }
322
323 /* The mode_config.mutex will be held for this call */
324 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
325 {
326         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
327
328         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
329                 dcrtc->dpms = DRM_MODE_DPMS_ON;
330                 armada_drm_crtc_update(dcrtc);
331         }
332 }
333
334 /* The mode_config.mutex will be held for this call */
335 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
336         const struct drm_display_mode *mode, struct drm_display_mode *adj)
337 {
338         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
339         int ret;
340
341         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
342         if (!dcrtc->variant->has_spu_adv_reg &&
343             adj->flags & DRM_MODE_FLAG_INTERLACE)
344                 return false;
345
346         /* Check whether the display mode is possible */
347         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
348         if (ret)
349                 return false;
350
351         return true;
352 }
353
354 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
355 {
356         struct armada_vbl_event *e, *n;
357         void __iomem *base = dcrtc->base;
358
359         if (stat & DMA_FF_UNDERFLOW)
360                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
361         if (stat & GRA_FF_UNDERFLOW)
362                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
363
364         if (stat & VSYNC_IRQ)
365                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
366
367         spin_lock(&dcrtc->irq_lock);
368
369         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
370                 list_del_init(&e->node);
371                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
372                 e->fn(dcrtc, e->data);
373         }
374
375         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
376                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
377                 uint32_t val;
378
379                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
380                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
381                                base + LCD_SPUT_V_H_TOTAL);
382
383                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
384                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
385                 val |= dcrtc->v[i].spu_adv_reg;
386                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
387         }
388
389         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
390                 writel_relaxed(dcrtc->cursor_hw_pos,
391                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
392                 writel_relaxed(dcrtc->cursor_hw_sz,
393                                base + LCD_SPU_HWC_HPXL_VLN);
394                 armada_updatel(CFG_HWC_ENA,
395                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
396                                base + LCD_SPU_DMA_CTRL0);
397                 dcrtc->cursor_update = false;
398                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
399         }
400
401         spin_unlock(&dcrtc->irq_lock);
402
403         if (stat & GRA_FRAME_IRQ) {
404                 struct drm_device *dev = dcrtc->crtc.dev;
405
406                 spin_lock(&dev->event_lock);
407                 if (dcrtc->frame_work)
408                         armada_drm_crtc_complete_frame_work(dcrtc);
409                 spin_unlock(&dev->event_lock);
410
411                 wake_up(&dcrtc->frame_wait);
412         }
413 }
414
415 static irqreturn_t armada_drm_irq(int irq, void *arg)
416 {
417         struct armada_crtc *dcrtc = arg;
418         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
419
420         /*
421          * This is rediculous - rather than writing bits to clear, we
422          * have to set the actual status register value.  This is racy.
423          */
424         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
425
426         /* Mask out those interrupts we haven't enabled */
427         v = stat & dcrtc->irq_ena;
428
429         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
430                 armada_drm_crtc_irq(dcrtc, stat);
431                 return IRQ_HANDLED;
432         }
433         return IRQ_NONE;
434 }
435
436 /* These are locked by dev->vbl_lock */
437 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
438 {
439         if (dcrtc->irq_ena & mask) {
440                 dcrtc->irq_ena &= ~mask;
441                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
442         }
443 }
444
445 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
446 {
447         if ((dcrtc->irq_ena & mask) != mask) {
448                 dcrtc->irq_ena |= mask;
449                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
450                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
451                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
452         }
453 }
454
455 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
456 {
457         struct drm_display_mode *adj = &dcrtc->crtc.mode;
458         uint32_t val = 0;
459
460         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
461                 val |= CFG_CSC_YUV_CCIR709;
462         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
463                 val |= CFG_CSC_RGB_STUDIO;
464
465         /*
466          * In auto mode, set the colorimetry, based upon the HDMI spec.
467          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
468          * ITU601.  It may be more appropriate to set this depending on
469          * the source - but what if the graphic frame is YUV and the
470          * video frame is RGB?
471          */
472         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
473              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
474             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
475                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
476                         val |= CFG_CSC_YUV_CCIR709;
477         }
478
479         /*
480          * We assume we're connected to a TV-like device, so the YUV->RGB
481          * conversion should produce a limited range.  We should set this
482          * depending on the connectors attached to this CRTC, and what
483          * kind of device they report being connected.
484          */
485         if (dcrtc->csc_rgb_mode == CSC_AUTO)
486                 val |= CFG_CSC_RGB_STUDIO;
487
488         return val;
489 }
490
491 /* The mode_config.mutex will be held for this call */
492 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
493         struct drm_display_mode *mode, struct drm_display_mode *adj,
494         int x, int y, struct drm_framebuffer *old_fb)
495 {
496         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
497         struct armada_regs regs[17];
498         uint32_t lm, rm, tm, bm, val, sclk;
499         unsigned long flags;
500         unsigned i;
501         bool interlaced;
502
503         drm_framebuffer_reference(crtc->primary->fb);
504
505         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
506
507         i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
508                                     x, y, regs, interlaced);
509
510         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
511         lm = adj->crtc_htotal - adj->crtc_hsync_end;
512         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
513         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
514
515         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
516                 adj->crtc_hdisplay,
517                 adj->crtc_hsync_start,
518                 adj->crtc_hsync_end,
519                 adj->crtc_htotal, lm, rm);
520         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
521                 adj->crtc_vdisplay,
522                 adj->crtc_vsync_start,
523                 adj->crtc_vsync_end,
524                 adj->crtc_vtotal, tm, bm);
525
526         /* Wait for pending flips to complete */
527         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
528
529         drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
530
531         crtc->mode = *adj;
532
533         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
534         if (val != dcrtc->dumb_ctrl) {
535                 dcrtc->dumb_ctrl = val;
536                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
537         }
538
539         /* Now compute the divider for real */
540         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
541
542         /* Ensure graphic fifo is enabled */
543         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
544         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
545
546         if (interlaced ^ dcrtc->interlaced) {
547                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
548                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
549                 else
550                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
551                 dcrtc->interlaced = interlaced;
552         }
553
554         spin_lock_irqsave(&dcrtc->irq_lock, flags);
555
556         /* Even interlaced/progressive frame */
557         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
558                                     adj->crtc_htotal;
559         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
560         val = adj->crtc_hsync_start;
561         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
562                 dcrtc->variant->spu_adv_reg;
563
564         if (interlaced) {
565                 /* Odd interlaced frame */
566                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
567                                                 (1 << 16);
568                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
569                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
570                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
571                         dcrtc->variant->spu_adv_reg;
572         } else {
573                 dcrtc->v[0] = dcrtc->v[1];
574         }
575
576         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
577
578         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
579         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
580         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
581         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
582         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
583         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
584                            LCD_SPUT_V_H_TOTAL);
585
586         if (dcrtc->variant->has_spu_adv_reg) {
587                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
588                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
589                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
590         }
591
592         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
593         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
594         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
595
596         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
597                 val |= CFG_PALETTE_ENA;
598
599         if (interlaced)
600                 val |= CFG_GRA_FTOGGLE;
601
602         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
603                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
604                                          CFG_SWAPYU | CFG_YUV2RGB) |
605                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
606                              LCD_SPU_DMA_CTRL0);
607
608         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
609         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
610
611         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
612         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
613         armada_reg_queue_end(regs, i);
614
615         armada_drm_crtc_update_regs(dcrtc, regs);
616         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
617
618         armada_drm_crtc_update(dcrtc);
619
620         drm_vblank_post_modeset(crtc->dev, dcrtc->num);
621         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
622
623         return 0;
624 }
625
626 /* The mode_config.mutex will be held for this call */
627 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
628         struct drm_framebuffer *old_fb)
629 {
630         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
631         struct armada_regs regs[4];
632         unsigned i;
633
634         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
635                                     dcrtc->interlaced);
636         armada_reg_queue_end(regs, i);
637
638         /* Wait for pending flips to complete */
639         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
640
641         /* Take a reference to the new fb as we're using it */
642         drm_framebuffer_reference(crtc->primary->fb);
643
644         /* Update the base in the CRTC */
645         armada_drm_crtc_update_regs(dcrtc, regs);
646
647         /* Drop our previously held reference */
648         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
649
650         return 0;
651 }
652
653 static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
654 {
655 }
656
657 /* The mode_config.mutex will be held for this call */
658 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
659 {
660         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
661
662         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
663         armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
664
665         /* Power down most RAMs and FIFOs */
666         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
667                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
668                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
669 }
670
671 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
672         .dpms           = armada_drm_crtc_dpms,
673         .prepare        = armada_drm_crtc_prepare,
674         .commit         = armada_drm_crtc_commit,
675         .mode_fixup     = armada_drm_crtc_mode_fixup,
676         .mode_set       = armada_drm_crtc_mode_set,
677         .mode_set_base  = armada_drm_crtc_mode_set_base,
678         .load_lut       = armada_drm_crtc_load_lut,
679         .disable        = armada_drm_crtc_disable,
680 };
681
682 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
683         unsigned stride, unsigned width, unsigned height)
684 {
685         uint32_t addr;
686         unsigned y;
687
688         addr = SRAM_HWC32_RAM1;
689         for (y = 0; y < height; y++) {
690                 uint32_t *p = &pix[y * stride];
691                 unsigned x;
692
693                 for (x = 0; x < width; x++, p++) {
694                         uint32_t val = *p;
695
696                         val = (val & 0xff00ff00) |
697                               (val & 0x000000ff) << 16 |
698                               (val & 0x00ff0000) >> 16;
699
700                         writel_relaxed(val,
701                                        base + LCD_SPU_SRAM_WRDAT);
702                         writel_relaxed(addr | SRAM_WRITE,
703                                        base + LCD_SPU_SRAM_CTRL);
704                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
705                         addr += 1;
706                         if ((addr & 0x00ff) == 0)
707                                 addr += 0xf00;
708                         if ((addr & 0x30ff) == 0)
709                                 addr = SRAM_HWC32_RAM2;
710                 }
711         }
712 }
713
714 static void armada_drm_crtc_cursor_tran(void __iomem *base)
715 {
716         unsigned addr;
717
718         for (addr = 0; addr < 256; addr++) {
719                 /* write the default value */
720                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
721                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
722                                base + LCD_SPU_SRAM_CTRL);
723         }
724 }
725
726 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
727 {
728         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
729         uint32_t yoff, yscr, h = dcrtc->cursor_h;
730         uint32_t para1;
731
732         /*
733          * Calculate the visible width and height of the cursor,
734          * screen position, and the position in the cursor bitmap.
735          */
736         if (dcrtc->cursor_x < 0) {
737                 xoff = -dcrtc->cursor_x;
738                 xscr = 0;
739                 w -= min(xoff, w);
740         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
741                 xoff = 0;
742                 xscr = dcrtc->cursor_x;
743                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
744         } else {
745                 xoff = 0;
746                 xscr = dcrtc->cursor_x;
747         }
748
749         if (dcrtc->cursor_y < 0) {
750                 yoff = -dcrtc->cursor_y;
751                 yscr = 0;
752                 h -= min(yoff, h);
753         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
754                 yoff = 0;
755                 yscr = dcrtc->cursor_y;
756                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
757         } else {
758                 yoff = 0;
759                 yscr = dcrtc->cursor_y;
760         }
761
762         /* On interlaced modes, the vertical cursor size must be halved */
763         s = dcrtc->cursor_w;
764         if (dcrtc->interlaced) {
765                 s *= 2;
766                 yscr /= 2;
767                 h /= 2;
768         }
769
770         if (!dcrtc->cursor_obj || !h || !w) {
771                 spin_lock_irq(&dcrtc->irq_lock);
772                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
773                 dcrtc->cursor_update = false;
774                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
775                 spin_unlock_irq(&dcrtc->irq_lock);
776                 return 0;
777         }
778
779         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
780         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
781                        dcrtc->base + LCD_SPU_SRAM_PARA1);
782
783         /*
784          * Initialize the transparency if the SRAM was powered down.
785          * We must also reload the cursor data as well.
786          */
787         if (!(para1 & CFG_CSB_256x32)) {
788                 armada_drm_crtc_cursor_tran(dcrtc->base);
789                 reload = true;
790         }
791
792         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
793                 spin_lock_irq(&dcrtc->irq_lock);
794                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
795                 dcrtc->cursor_update = false;
796                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
797                 spin_unlock_irq(&dcrtc->irq_lock);
798                 reload = true;
799         }
800         if (reload) {
801                 struct armada_gem_object *obj = dcrtc->cursor_obj;
802                 uint32_t *pix;
803                 /* Set the top-left corner of the cursor image */
804                 pix = obj->addr;
805                 pix += yoff * s + xoff;
806                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
807         }
808
809         /* Reload the cursor position, size and enable in the IRQ handler */
810         spin_lock_irq(&dcrtc->irq_lock);
811         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
812         dcrtc->cursor_hw_sz = h << 16 | w;
813         dcrtc->cursor_update = true;
814         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
815         spin_unlock_irq(&dcrtc->irq_lock);
816
817         return 0;
818 }
819
820 static void cursor_update(void *data)
821 {
822         armada_drm_crtc_cursor_update(data, true);
823 }
824
825 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
826         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
827 {
828         struct drm_device *dev = crtc->dev;
829         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
830         struct armada_gem_object *obj = NULL;
831         int ret;
832
833         /* If no cursor support, replicate drm's return value */
834         if (!dcrtc->variant->has_spu_adv_reg)
835                 return -ENXIO;
836
837         if (handle && w > 0 && h > 0) {
838                 /* maximum size is 64x32 or 32x64 */
839                 if (w > 64 || h > 64 || (w > 32 && h > 32))
840                         return -ENOMEM;
841
842                 obj = armada_gem_object_lookup(dev, file, handle);
843                 if (!obj)
844                         return -ENOENT;
845
846                 /* Must be a kernel-mapped object */
847                 if (!obj->addr) {
848                         drm_gem_object_unreference_unlocked(&obj->obj);
849                         return -EINVAL;
850                 }
851
852                 if (obj->obj.size < w * h * 4) {
853                         DRM_ERROR("buffer is too small\n");
854                         drm_gem_object_unreference_unlocked(&obj->obj);
855                         return -ENOMEM;
856                 }
857         }
858
859         mutex_lock(&dev->struct_mutex);
860         if (dcrtc->cursor_obj) {
861                 dcrtc->cursor_obj->update = NULL;
862                 dcrtc->cursor_obj->update_data = NULL;
863                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
864         }
865         dcrtc->cursor_obj = obj;
866         dcrtc->cursor_w = w;
867         dcrtc->cursor_h = h;
868         ret = armada_drm_crtc_cursor_update(dcrtc, true);
869         if (obj) {
870                 obj->update_data = dcrtc;
871                 obj->update = cursor_update;
872         }
873         mutex_unlock(&dev->struct_mutex);
874
875         return ret;
876 }
877
878 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
879 {
880         struct drm_device *dev = crtc->dev;
881         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
882         int ret;
883
884         /* If no cursor support, replicate drm's return value */
885         if (!dcrtc->variant->has_spu_adv_reg)
886                 return -EFAULT;
887
888         mutex_lock(&dev->struct_mutex);
889         dcrtc->cursor_x = x;
890         dcrtc->cursor_y = y;
891         ret = armada_drm_crtc_cursor_update(dcrtc, false);
892         mutex_unlock(&dev->struct_mutex);
893
894         return ret;
895 }
896
897 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
898 {
899         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
900         struct armada_private *priv = crtc->dev->dev_private;
901
902         if (dcrtc->cursor_obj)
903                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
904
905         priv->dcrtc[dcrtc->num] = NULL;
906         drm_crtc_cleanup(&dcrtc->crtc);
907
908         if (!IS_ERR(dcrtc->clk))
909                 clk_disable_unprepare(dcrtc->clk);
910
911         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
912
913         of_node_put(dcrtc->crtc.port);
914
915         kfree(dcrtc);
916 }
917
918 /*
919  * The mode_config lock is held here, to prevent races between this
920  * and a mode_set.
921  */
922 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
923         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
924 {
925         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
926         struct armada_frame_work *work;
927         struct drm_device *dev = crtc->dev;
928         unsigned long flags;
929         unsigned i;
930         int ret;
931
932         /* We don't support changing the pixel format */
933         if (fb->pixel_format != crtc->primary->fb->pixel_format)
934                 return -EINVAL;
935
936         work = kmalloc(sizeof(*work), GFP_KERNEL);
937         if (!work)
938                 return -ENOMEM;
939
940         work->event = event;
941         work->old_fb = dcrtc->crtc.primary->fb;
942
943         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
944                                     dcrtc->interlaced);
945         armada_reg_queue_end(work->regs, i);
946
947         /*
948          * Hold the old framebuffer for the work - DRM appears to drop our
949          * reference to the old framebuffer in drm_mode_page_flip_ioctl().
950          */
951         drm_framebuffer_reference(work->old_fb);
952
953         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
954         if (ret) {
955                 /*
956                  * Undo our reference above; DRM does not drop the reference
957                  * to this object on error, so that's okay.
958                  */
959                 drm_framebuffer_unreference(work->old_fb);
960                 kfree(work);
961                 return ret;
962         }
963
964         /*
965          * Don't take a reference on the new framebuffer;
966          * drm_mode_page_flip_ioctl() has already grabbed a reference and
967          * will _not_ drop that reference on successful return from this
968          * function.  Simply mark this new framebuffer as the current one.
969          */
970         dcrtc->crtc.primary->fb = fb;
971
972         /*
973          * Finally, if the display is blanked, we won't receive an
974          * interrupt, so complete it now.
975          */
976         if (dpms_blanked(dcrtc->dpms)) {
977                 spin_lock_irqsave(&dev->event_lock, flags);
978                 if (dcrtc->frame_work)
979                         armada_drm_crtc_complete_frame_work(dcrtc);
980                 spin_unlock_irqrestore(&dev->event_lock, flags);
981         }
982
983         return 0;
984 }
985
986 static int
987 armada_drm_crtc_set_property(struct drm_crtc *crtc,
988         struct drm_property *property, uint64_t val)
989 {
990         struct armada_private *priv = crtc->dev->dev_private;
991         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
992         bool update_csc = false;
993
994         if (property == priv->csc_yuv_prop) {
995                 dcrtc->csc_yuv_mode = val;
996                 update_csc = true;
997         } else if (property == priv->csc_rgb_prop) {
998                 dcrtc->csc_rgb_mode = val;
999                 update_csc = true;
1000         }
1001
1002         if (update_csc) {
1003                 uint32_t val;
1004
1005                 val = dcrtc->spu_iopad_ctrl |
1006                       armada_drm_crtc_calculate_csc(dcrtc);
1007                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1008         }
1009
1010         return 0;
1011 }
1012
1013 static struct drm_crtc_funcs armada_crtc_funcs = {
1014         .cursor_set     = armada_drm_crtc_cursor_set,
1015         .cursor_move    = armada_drm_crtc_cursor_move,
1016         .destroy        = armada_drm_crtc_destroy,
1017         .set_config     = drm_crtc_helper_set_config,
1018         .page_flip      = armada_drm_crtc_page_flip,
1019         .set_property   = armada_drm_crtc_set_property,
1020 };
1021
1022 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1023         { CSC_AUTO,        "Auto" },
1024         { CSC_YUV_CCIR601, "CCIR601" },
1025         { CSC_YUV_CCIR709, "CCIR709" },
1026 };
1027
1028 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1029         { CSC_AUTO,         "Auto" },
1030         { CSC_RGB_COMPUTER, "Computer system" },
1031         { CSC_RGB_STUDIO,   "Studio" },
1032 };
1033
1034 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1035 {
1036         struct armada_private *priv = dev->dev_private;
1037
1038         if (priv->csc_yuv_prop)
1039                 return 0;
1040
1041         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1042                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1043                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1044         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1045                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1046                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1047
1048         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1049                 return -ENOMEM;
1050
1051         return 0;
1052 }
1053
1054 int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1055         struct resource *res, int irq, const struct armada_variant *variant,
1056         struct device_node *port)
1057 {
1058         struct armada_private *priv = drm->dev_private;
1059         struct armada_crtc *dcrtc;
1060         void __iomem *base;
1061         int ret;
1062
1063         ret = armada_drm_crtc_create_properties(drm);
1064         if (ret)
1065                 return ret;
1066
1067         base = devm_ioremap_resource(dev, res);
1068         if (IS_ERR(base))
1069                 return PTR_ERR(base);
1070
1071         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1072         if (!dcrtc) {
1073                 DRM_ERROR("failed to allocate Armada crtc\n");
1074                 return -ENOMEM;
1075         }
1076
1077         if (dev != drm->dev)
1078                 dev_set_drvdata(dev, dcrtc);
1079
1080         dcrtc->variant = variant;
1081         dcrtc->base = base;
1082         dcrtc->num = drm->mode_config.num_crtc;
1083         dcrtc->clk = ERR_PTR(-EINVAL);
1084         dcrtc->csc_yuv_mode = CSC_AUTO;
1085         dcrtc->csc_rgb_mode = CSC_AUTO;
1086         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1087         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1088         spin_lock_init(&dcrtc->irq_lock);
1089         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1090         INIT_LIST_HEAD(&dcrtc->vbl_list);
1091         init_waitqueue_head(&dcrtc->frame_wait);
1092
1093         /* Initialize some registers which we don't otherwise set */
1094         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1095         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1096         writel_relaxed(dcrtc->spu_iopad_ctrl,
1097                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1098         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1099         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1100                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1101                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1102         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1103         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1104         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1105         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1106
1107         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1108                                dcrtc);
1109         if (ret < 0) {
1110                 kfree(dcrtc);
1111                 return ret;
1112         }
1113
1114         if (dcrtc->variant->init) {
1115                 ret = dcrtc->variant->init(dcrtc, dev);
1116                 if (ret) {
1117                         kfree(dcrtc);
1118                         return ret;
1119                 }
1120         }
1121
1122         /* Ensure AXI pipeline is enabled */
1123         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1124
1125         priv->dcrtc[dcrtc->num] = dcrtc;
1126
1127         dcrtc->crtc.port = port;
1128         drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs);
1129         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1130
1131         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1132                                    dcrtc->csc_yuv_mode);
1133         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1134                                    dcrtc->csc_rgb_mode);
1135
1136         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1137 }
1138
1139 static int
1140 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1141 {
1142         struct platform_device *pdev = to_platform_device(dev);
1143         struct drm_device *drm = data;
1144         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145         int irq = platform_get_irq(pdev, 0);
1146         const struct armada_variant *variant;
1147         struct device_node *port = NULL;
1148
1149         if (irq < 0)
1150                 return irq;
1151
1152         if (!dev->of_node) {
1153                 const struct platform_device_id *id;
1154
1155                 id = platform_get_device_id(pdev);
1156                 if (!id)
1157                         return -ENXIO;
1158
1159                 variant = (const struct armada_variant *)id->driver_data;
1160         } else {
1161                 const struct of_device_id *match;
1162                 struct device_node *np, *parent = dev->of_node;
1163
1164                 match = of_match_device(dev->driver->of_match_table, dev);
1165                 if (!match)
1166                         return -ENXIO;
1167
1168                 np = of_get_child_by_name(parent, "ports");
1169                 if (np)
1170                         parent = np;
1171                 port = of_get_child_by_name(parent, "port");
1172                 of_node_put(np);
1173                 if (!port) {
1174                         dev_err(dev, "no port node found in %s\n",
1175                                 parent->full_name);
1176                         return -ENXIO;
1177                 }
1178
1179                 variant = match->data;
1180         }
1181
1182         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1183 }
1184
1185 static void
1186 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1187 {
1188         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1189
1190         armada_drm_crtc_destroy(&dcrtc->crtc);
1191 }
1192
1193 static const struct component_ops armada_lcd_ops = {
1194         .bind = armada_lcd_bind,
1195         .unbind = armada_lcd_unbind,
1196 };
1197
1198 static int armada_lcd_probe(struct platform_device *pdev)
1199 {
1200         return component_add(&pdev->dev, &armada_lcd_ops);
1201 }
1202
1203 static int armada_lcd_remove(struct platform_device *pdev)
1204 {
1205         component_del(&pdev->dev, &armada_lcd_ops);
1206         return 0;
1207 }
1208
1209 static struct of_device_id armada_lcd_of_match[] = {
1210         {
1211                 .compatible     = "marvell,dove-lcd",
1212                 .data           = &armada510_ops,
1213         },
1214         {}
1215 };
1216 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1217
1218 static const struct platform_device_id armada_lcd_platform_ids[] = {
1219         {
1220                 .name           = "armada-lcd",
1221                 .driver_data    = (unsigned long)&armada510_ops,
1222         }, {
1223                 .name           = "armada-510-lcd",
1224                 .driver_data    = (unsigned long)&armada510_ops,
1225         },
1226         { },
1227 };
1228 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1229
1230 struct platform_driver armada_lcd_platform_driver = {
1231         .probe  = armada_lcd_probe,
1232         .remove = armada_lcd_remove,
1233         .driver = {
1234                 .name   = "armada-lcd",
1235                 .owner  =  THIS_MODULE,
1236                 .of_match_table = armada_lcd_of_match,
1237         },
1238         .id_table = armada_lcd_platform_ids,
1239 };