2 * Copyright 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
31 #include "amdgpu_vce.h"
33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
37 #include "gca/gfx_8_0_d.h"
38 #include "smu/smu_7_1_2_d.h"
39 #include "smu/smu_7_1_2_sh_mask.h"
41 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
42 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
44 #define VCE_V3_0_FW_SIZE (384 * 1024)
45 #define VCE_V3_0_STACK_SIZE (64 * 1024)
46 #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
48 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
49 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
50 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
53 * vce_v3_0_ring_get_rptr - get read pointer
55 * @ring: amdgpu_ring pointer
57 * Returns the current hardware read pointer
59 static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
61 struct amdgpu_device *adev = ring->adev;
63 if (ring == &adev->vce.ring[0])
64 return RREG32(mmVCE_RB_RPTR);
66 return RREG32(mmVCE_RB_RPTR2);
70 * vce_v3_0_ring_get_wptr - get write pointer
72 * @ring: amdgpu_ring pointer
74 * Returns the current hardware write pointer
76 static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
78 struct amdgpu_device *adev = ring->adev;
80 if (ring == &adev->vce.ring[0])
81 return RREG32(mmVCE_RB_WPTR);
83 return RREG32(mmVCE_RB_WPTR2);
87 * vce_v3_0_ring_set_wptr - set write pointer
89 * @ring: amdgpu_ring pointer
91 * Commits the write pointer to the hardware
93 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
95 struct amdgpu_device *adev = ring->adev;
97 if (ring == &adev->vce.ring[0])
98 WREG32(mmVCE_RB_WPTR, ring->wptr);
100 WREG32(mmVCE_RB_WPTR2, ring->wptr);
104 * vce_v3_0_start - start VCE block
106 * @adev: amdgpu_device pointer
108 * Setup and start the VCE block
110 static int vce_v3_0_start(struct amdgpu_device *adev)
112 struct amdgpu_ring *ring;
115 mutex_lock(&adev->grbm_idx_mutex);
116 for (idx = 0; idx < 2; ++idx) {
118 if (adev->vce.harvest_config & (1 << idx))
122 WREG32_P(mmGRBM_GFX_INDEX, 0,
123 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
125 WREG32_P(mmGRBM_GFX_INDEX,
126 GRBM_GFX_INDEX__VCE_INSTANCE_MASK,
127 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
129 vce_v3_0_mc_resume(adev, idx);
132 WREG32_P(mmVCE_STATUS, 1, ~1);
134 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
135 ~VCE_VCPU_CNTL__CLK_EN_MASK);
137 WREG32_P(mmVCE_SOFT_RESET,
138 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
139 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
143 WREG32_P(mmVCE_SOFT_RESET, 0,
144 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
146 for (i = 0; i < 10; ++i) {
148 for (j = 0; j < 100; ++j) {
149 status = RREG32(mmVCE_STATUS);
158 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
159 WREG32_P(mmVCE_SOFT_RESET,
160 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
161 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
163 WREG32_P(mmVCE_SOFT_RESET, 0,
164 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
169 /* clear BUSY flag */
170 WREG32_P(mmVCE_STATUS, 0, ~1);
173 DRM_ERROR("VCE not responding, giving up!!!\n");
174 mutex_unlock(&adev->grbm_idx_mutex);
179 WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
180 mutex_unlock(&adev->grbm_idx_mutex);
182 ring = &adev->vce.ring[0];
183 WREG32(mmVCE_RB_RPTR, ring->wptr);
184 WREG32(mmVCE_RB_WPTR, ring->wptr);
185 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
186 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
187 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
189 ring = &adev->vce.ring[1];
190 WREG32(mmVCE_RB_RPTR2, ring->wptr);
191 WREG32(mmVCE_RB_WPTR2, ring->wptr);
192 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
193 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
194 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
199 #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
200 #define VCE_HARVEST_FUSE_MACRO__SHIFT 27
201 #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
203 static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
208 /* Fiji, Stoney are single pipe */
209 if ((adev->asic_type == CHIP_FIJI) ||
210 (adev->asic_type == CHIP_STONEY)){
211 ret = AMDGPU_VCE_HARVEST_VCE1;
215 /* Tonga and CZ are dual or single pipe */
216 if (adev->flags & AMD_IS_APU)
217 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
218 VCE_HARVEST_FUSE_MACRO__MASK) >>
219 VCE_HARVEST_FUSE_MACRO__SHIFT;
221 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
222 CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
223 CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
227 ret = AMDGPU_VCE_HARVEST_VCE0;
230 ret = AMDGPU_VCE_HARVEST_VCE1;
233 ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
242 static int vce_v3_0_early_init(void *handle)
244 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
246 adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
248 if ((adev->vce.harvest_config &
249 (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
250 (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
253 vce_v3_0_set_ring_funcs(adev);
254 vce_v3_0_set_irq_funcs(adev);
259 static int vce_v3_0_sw_init(void *handle)
261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
262 struct amdgpu_ring *ring;
266 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
270 r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE +
271 (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
275 r = amdgpu_vce_resume(adev);
279 ring = &adev->vce.ring[0];
280 sprintf(ring->name, "vce0");
281 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
282 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
286 ring = &adev->vce.ring[1];
287 sprintf(ring->name, "vce1");
288 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
289 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
296 static int vce_v3_0_sw_fini(void *handle)
299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
301 r = amdgpu_vce_suspend(adev);
305 r = amdgpu_vce_sw_fini(adev);
312 static int vce_v3_0_hw_init(void *handle)
314 struct amdgpu_ring *ring;
316 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
318 r = vce_v3_0_start(adev);
322 ring = &adev->vce.ring[0];
324 r = amdgpu_ring_test_ring(ring);
330 ring = &adev->vce.ring[1];
332 r = amdgpu_ring_test_ring(ring);
338 DRM_INFO("VCE initialized successfully.\n");
343 static int vce_v3_0_hw_fini(void *handle)
348 static int vce_v3_0_suspend(void *handle)
351 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353 r = vce_v3_0_hw_fini(adev);
357 r = amdgpu_vce_suspend(adev);
364 static int vce_v3_0_resume(void *handle)
367 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
369 r = amdgpu_vce_resume(adev);
373 r = vce_v3_0_hw_init(adev);
380 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
382 uint32_t offset, size;
384 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
385 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
386 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
387 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
389 WREG32(mmVCE_LMI_CTRL, 0x00398000);
390 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
391 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
392 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
393 WREG32(mmVCE_LMI_VM_CTRL, 0);
395 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
396 offset = AMDGPU_VCE_FIRMWARE_OFFSET;
397 size = VCE_V3_0_FW_SIZE;
398 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
399 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
403 size = VCE_V3_0_STACK_SIZE;
404 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
405 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
407 size = VCE_V3_0_DATA_SIZE;
408 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
409 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
411 offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE;
412 size = VCE_V3_0_STACK_SIZE;
413 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
414 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
416 size = VCE_V3_0_DATA_SIZE;
417 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
418 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
421 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
423 WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
424 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
427 static bool vce_v3_0_is_idle(void *handle)
429 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
433 for (idx = 0; idx < 2; ++idx) {
434 if (adev->vce.harvest_config & (1 << idx))
438 mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
440 mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
443 return !(RREG32(mmSRBM_STATUS2) & mask);
446 static int vce_v3_0_wait_for_idle(void *handle)
449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
453 for (idx = 0; idx < 2; ++idx) {
454 if (adev->vce.harvest_config & (1 << idx))
458 mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
460 mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
463 for (i = 0; i < adev->usec_timeout; i++) {
464 if (!(RREG32(mmSRBM_STATUS2) & mask))
470 static int vce_v3_0_soft_reset(void *handle)
472 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
476 for (idx = 0; idx < 2; ++idx) {
477 if (adev->vce.harvest_config & (1 << idx))
481 mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
483 mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
485 WREG32_P(mmSRBM_SOFT_RESET, mask,
486 ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK |
487 SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK));
490 return vce_v3_0_start(adev);
493 static void vce_v3_0_print_status(void *handle)
495 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
497 dev_info(adev->dev, "VCE 3.0 registers\n");
498 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
499 RREG32(mmVCE_STATUS));
500 dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
501 RREG32(mmVCE_VCPU_CNTL));
502 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
503 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
504 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
505 RREG32(mmVCE_VCPU_CACHE_SIZE0));
506 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
507 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
508 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
509 RREG32(mmVCE_VCPU_CACHE_SIZE1));
510 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
511 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
512 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
513 RREG32(mmVCE_VCPU_CACHE_SIZE2));
514 dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
515 RREG32(mmVCE_SOFT_RESET));
516 dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
517 RREG32(mmVCE_RB_BASE_LO2));
518 dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
519 RREG32(mmVCE_RB_BASE_HI2));
520 dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
521 RREG32(mmVCE_RB_SIZE2));
522 dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
523 RREG32(mmVCE_RB_RPTR2));
524 dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
525 RREG32(mmVCE_RB_WPTR2));
526 dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
527 RREG32(mmVCE_RB_BASE_LO));
528 dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
529 RREG32(mmVCE_RB_BASE_HI));
530 dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
531 RREG32(mmVCE_RB_SIZE));
532 dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
533 RREG32(mmVCE_RB_RPTR));
534 dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
535 RREG32(mmVCE_RB_WPTR));
536 dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
537 RREG32(mmVCE_CLOCK_GATING_A));
538 dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
539 RREG32(mmVCE_CLOCK_GATING_B));
540 dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
541 RREG32(mmVCE_UENC_CLOCK_GATING));
542 dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
543 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
544 dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
545 RREG32(mmVCE_SYS_INT_EN));
546 dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
547 RREG32(mmVCE_LMI_CTRL2));
548 dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
549 RREG32(mmVCE_LMI_CTRL));
550 dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
551 RREG32(mmVCE_LMI_VM_CTRL));
552 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
553 RREG32(mmVCE_LMI_SWAP_CNTL));
554 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
555 RREG32(mmVCE_LMI_SWAP_CNTL1));
556 dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
557 RREG32(mmVCE_LMI_CACHE_CTRL));
560 static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
561 struct amdgpu_irq_src *source,
563 enum amdgpu_interrupt_state state)
567 if (state == AMDGPU_IRQ_STATE_ENABLE)
568 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
570 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
574 static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
575 struct amdgpu_irq_src *source,
576 struct amdgpu_iv_entry *entry)
578 DRM_DEBUG("IH: VCE\n");
579 switch (entry->src_data) {
581 amdgpu_fence_process(&adev->vce.ring[0]);
584 amdgpu_fence_process(&adev->vce.ring[1]);
587 DRM_ERROR("Unhandled interrupt: %d %d\n",
588 entry->src_id, entry->src_data);
595 static int vce_v3_0_set_clockgating_state(void *handle,
596 enum amd_clockgating_state state)
601 static int vce_v3_0_set_powergating_state(void *handle,
602 enum amd_powergating_state state)
604 /* This doesn't actually powergate the VCE block.
605 * That's done in the dpm code via the SMC. This
606 * just re-inits the block as necessary. The actual
607 * gating still happens in the dpm code. We should
608 * revisit this when there is a cleaner line between
609 * the smc and the hw blocks
611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613 if (state == AMD_PG_STATE_GATE)
614 /* XXX do we need a vce_v3_0_stop()? */
617 return vce_v3_0_start(adev);
620 const struct amd_ip_funcs vce_v3_0_ip_funcs = {
621 .early_init = vce_v3_0_early_init,
623 .sw_init = vce_v3_0_sw_init,
624 .sw_fini = vce_v3_0_sw_fini,
625 .hw_init = vce_v3_0_hw_init,
626 .hw_fini = vce_v3_0_hw_fini,
627 .suspend = vce_v3_0_suspend,
628 .resume = vce_v3_0_resume,
629 .is_idle = vce_v3_0_is_idle,
630 .wait_for_idle = vce_v3_0_wait_for_idle,
631 .soft_reset = vce_v3_0_soft_reset,
632 .print_status = vce_v3_0_print_status,
633 .set_clockgating_state = vce_v3_0_set_clockgating_state,
634 .set_powergating_state = vce_v3_0_set_powergating_state,
637 static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
638 .get_rptr = vce_v3_0_ring_get_rptr,
639 .get_wptr = vce_v3_0_ring_get_wptr,
640 .set_wptr = vce_v3_0_ring_set_wptr,
641 .parse_cs = amdgpu_vce_ring_parse_cs,
642 .emit_ib = amdgpu_vce_ring_emit_ib,
643 .emit_fence = amdgpu_vce_ring_emit_fence,
644 .emit_semaphore = amdgpu_vce_ring_emit_semaphore,
645 .test_ring = amdgpu_vce_ring_test_ring,
646 .test_ib = amdgpu_vce_ring_test_ib,
647 .insert_nop = amdgpu_ring_insert_nop,
650 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
652 adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs;
653 adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs;
656 static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
657 .set = vce_v3_0_set_interrupt_state,
658 .process = vce_v3_0_process_interrupt,
661 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
663 adev->vce.irq.num_types = 1;
664 adev->vce.irq.funcs = &vce_v3_0_irq_funcs;