drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  93 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
  96
  97 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  98 {
  99         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 100         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 101         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 102         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 103         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 104         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 105         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 106         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 107         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 108         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 109         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 110         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 111         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 112         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 113         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 114         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 115 };
 116
 117 static const u32 golden_settings_tonga_a11[] =
 118 {
 119         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 120         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 121         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 122         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 123         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 124         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 125         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 126         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 127         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 128         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 129         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 130         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 131         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 132         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 133         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 134 };
 135
 136 static const u32 tonga_golden_common_all[] =
 137 {
 138         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 139         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 140         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 141         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 142         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 143         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 144         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 145         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 146 };
 147
 148 static const u32 tonga_mgcg_cgcg_init[] =
 149 {
 150         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 151         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 152         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 157         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 158         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 159         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 160         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 161         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 162         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 165         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 166         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 167         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 168         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 169         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 170         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 171         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 172         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 173         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 174         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 175         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 176         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 177         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 178         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 179         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 180         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 181         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 212         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 213         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 214         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 215         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 216         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 217         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 218         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 219         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 220         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 221         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 222         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 223         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 224         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 225 };
 226
 227 static const u32 fiji_golden_common_all[] =
 228 {
 229         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 230         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 231         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 232         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 233         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 234         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 235         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 236         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 237 };
 238
 239 static const u32 golden_settings_fiji_a10[] =
 240 {
 241         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 242         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 243         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 244         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
 245         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 246         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 247         mmTCC_CTRL, 0x00100000, 0xf30fff7f,
 248         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 249         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
 250         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
 251 };
 252
 253 static const u32 fiji_mgcg_cgcg_init[] =
 254 {
 255         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
 256         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 257         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 259         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 262         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 264         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 266         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 267         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 268         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 269         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 270         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 271         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 273         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 274         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 275         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 276         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 277         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 278         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 279         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 280         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 281         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 282         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 283         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 284         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 285         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 286         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 287         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 288         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 289         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 290 };
 291
 292 static const u32 golden_settings_iceland_a11[] =
 293 {
 294         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 295         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 296         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 297         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 298         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 299         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 300         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 301         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 302         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 303         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 304         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 305         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 306         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 307         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 308         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 309 };
 310
 311 static const u32 iceland_golden_common_all[] =
 312 {
 313         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 314         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 315         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 316         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 317         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 318         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 319         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 320         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 321 };
 322
 323 static const u32 iceland_mgcg_cgcg_init[] =
 324 {
 325         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 326         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 327         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 328         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 329         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 330         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 331         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 332         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 333         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 334         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 335         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 336         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 337         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 338         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 339         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 340         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 341         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 342         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 343         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 344         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 345         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 346         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 347         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 348         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 349         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 350         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 351         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 352         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 353         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 354         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 355         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 356         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 357         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 358         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 359         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 360         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 361         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 362         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 363         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 364         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 365         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 366         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 367         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 368         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 369         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 370         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 371         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 379         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 387         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 388         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 389 };
 390
 391 static const u32 cz_golden_settings_a11[] =
 392 {
 393         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 394         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 395         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 396         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 397         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 398         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 399         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 400         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 401         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 402         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 403 };
 404
 405 static const u32 cz_golden_common_all[] =
 406 {
 407         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 408         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 409         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 410         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 411         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 412         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 413         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 414         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 415 };
 416
 417 static const u32 cz_mgcg_cgcg_init[] =
 418 {
 419         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 420         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 421         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 422         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 423         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 424         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 425         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 426         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 427         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 428         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 429         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 430         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 431         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 432         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 433         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 434         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 435         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 437         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 438         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 439         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 440         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 441         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 442         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 445         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 446         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 447         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 448         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 449         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 450         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 451         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 452         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 453         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 454         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 455         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 456         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 457         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 458         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 459         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 460         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 461         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 462         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 463         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 464         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 465         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 466         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 467         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 468         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 469         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 470         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 471         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 472         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 473         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 474         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 475         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 476         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 477         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 478         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 479         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 480         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 481         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 482         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 483         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 484         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 485         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 486         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 487         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 488         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 489         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 490         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 491         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 492         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 493         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 494 };
 495
 496 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 497 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 498 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 499
 500 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 501 {
 502         switch (adev->asic_type) {
 503         case CHIP_TOPAZ:
 504                 amdgpu_program_register_sequence(adev,
 505                                                  iceland_mgcg_cgcg_init,
 506                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 507                 amdgpu_program_register_sequence(adev,
 508                                                  golden_settings_iceland_a11,
 509                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 510                 amdgpu_program_register_sequence(adev,
 511                                                  iceland_golden_common_all,
 512                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 513                 break;
 514         case CHIP_FIJI:
 515                 amdgpu_program_register_sequence(adev,
 516                                                  fiji_mgcg_cgcg_init,
 517                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 518                 amdgpu_program_register_sequence(adev,
 519                                                  golden_settings_fiji_a10,
 520                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 521                 amdgpu_program_register_sequence(adev,
 522                                                  fiji_golden_common_all,
 523                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 524                 break;
 525
 526         case CHIP_TONGA:
 527                 amdgpu_program_register_sequence(adev,
 528                                                  tonga_mgcg_cgcg_init,
 529                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 530                 amdgpu_program_register_sequence(adev,
 531                                                  golden_settings_tonga_a11,
 532                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 533                 amdgpu_program_register_sequence(adev,
 534                                                  tonga_golden_common_all,
 535                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 536                 break;
 537         case CHIP_CARRIZO:
 538                 amdgpu_program_register_sequence(adev,
 539                                                  cz_mgcg_cgcg_init,
 540                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 541                 amdgpu_program_register_sequence(adev,
 542                                                  cz_golden_settings_a11,
 543                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 544                 amdgpu_program_register_sequence(adev,
 545                                                  cz_golden_common_all,
 546                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 547                 break;
 548         default:
 549                 break;
 550         }
 551 }
 552
 553 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 554 {
 555         int i;
 556
 557         adev->gfx.scratch.num_reg = 7;
 558         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 559         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 560                 adev->gfx.scratch.free[i] = true;
 561                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 562         }
 563 }
 564
 565 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 566 {
 567         struct amdgpu_device *adev = ring->adev;
 568         uint32_t scratch;
 569         uint32_t tmp = 0;
 570         unsigned i;
 571         int r;
 572
 573         r = amdgpu_gfx_scratch_get(adev, &scratch);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 576                 return r;
 577         }
 578         WREG32(scratch, 0xCAFEDEAD);
 579         r = amdgpu_ring_lock(ring, 3);
 580         if (r) {
 581                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 582                           ring->idx, r);
 583                 amdgpu_gfx_scratch_free(adev, scratch);
 584                 return r;
 585         }
 586         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 587         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 588         amdgpu_ring_write(ring, 0xDEADBEEF);
 589         amdgpu_ring_unlock_commit(ring);
 590
 591         for (i = 0; i < adev->usec_timeout; i++) {
 592                 tmp = RREG32(scratch);
 593                 if (tmp == 0xDEADBEEF)
 594                         break;
 595                 DRM_UDELAY(1);
 596         }
 597         if (i < adev->usec_timeout) {
 598                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 599                          ring->idx, i);
 600         } else {
 601                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 602                           ring->idx, scratch, tmp);
 603                 r = -EINVAL;
 604         }
 605         amdgpu_gfx_scratch_free(adev, scratch);
 606         return r;
 607 }
 608
 609 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 610 {
 611         struct amdgpu_device *adev = ring->adev;
 612         struct amdgpu_ib ib;
 613         struct fence *f = NULL;
 614         uint32_t scratch;
 615         uint32_t tmp = 0;
 616         unsigned i;
 617         int r;
 618
 619         r = amdgpu_gfx_scratch_get(adev, &scratch);
 620         if (r) {
 621                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 622                 return r;
 623         }
 624         WREG32(scratch, 0xCAFEDEAD);
 625         memset(&ib, 0, sizeof(ib));
 626         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 627         if (r) {
 628                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 629                 goto err1;
 630         }
 631         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 632         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 633         ib.ptr[2] = 0xDEADBEEF;
 634         ib.length_dw = 3;
 635
 636         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 637                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 638                                                  &f);
 639         if (r)
 640                 goto err2;
 641
 642         r = fence_wait(f, false);
 643         if (r) {
 644                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 645                 goto err2;
 646         }
 647         for (i = 0; i < adev->usec_timeout; i++) {
 648                 tmp = RREG32(scratch);
 649                 if (tmp == 0xDEADBEEF)
 650                         break;
 651                 DRM_UDELAY(1);
 652         }
 653         if (i < adev->usec_timeout) {
 654                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 655                          ring->idx, i);
 656                 goto err2;
 657         } else {
 658                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 659                           scratch, tmp);
 660                 r = -EINVAL;
 661         }
 662 err2:
 663         fence_put(f);
 664         amdgpu_ib_free(adev, &ib);
 665 err1:
 666         amdgpu_gfx_scratch_free(adev, scratch);
 667         return r;
 668 }
 669
 670 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 671 {
 672         const char *chip_name;
 673         char fw_name[30];
 674         int err;
 675         struct amdgpu_firmware_info *info = NULL;
 676         const struct common_firmware_header *header = NULL;
 677         const struct gfx_firmware_header_v1_0 *cp_hdr;
 678
 679         DRM_DEBUG("\n");
 680
 681         switch (adev->asic_type) {
 682         case CHIP_TOPAZ:
 683                 chip_name = "topaz";
 684                 break;
 685         case CHIP_TONGA:
 686                 chip_name = "tonga";
 687                 break;
 688         case CHIP_CARRIZO:
 689                 chip_name = "carrizo";
 690                 break;
 691         case CHIP_FIJI:
 692                 chip_name = "fiji";
 693                 break;
 694         default:
 695                 BUG();
 696         }
 697
 698         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 699         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 700         if (err)
 701                 goto out;
 702         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 703         if (err)
 704                 goto out;
 705         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 706         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 707         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 708
 709         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 710         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 711         if (err)
 712                 goto out;
 713         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 714         if (err)
 715                 goto out;
 716         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 717         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 718         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 719
 720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 721         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 722         if (err)
 723                 goto out;
 724         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 725         if (err)
 726                 goto out;
 727         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 728         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 729         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 730
 731         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 732         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 733         if (err)
 734                 goto out;
 735         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 736         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 737         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 738         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 739
 740         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 741         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 742         if (err)
 743                 goto out;
 744         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 745         if (err)
 746                 goto out;
 747         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 748         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 749         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 750
 751         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 752         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 753         if (!err) {
 754                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 755                 if (err)
 756                         goto out;
 757                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 758                                                 adev->gfx.mec2_fw->data;
 759                 adev->gfx.mec2_fw_version = le32_to_cpu(
 760                                                 cp_hdr->header.ucode_version);
 761                 adev->gfx.mec2_feature_version = le32_to_cpu(
 762                                                 cp_hdr->ucode_feature_version);
 763         } else {
 764                 err = 0;
 765                 adev->gfx.mec2_fw = NULL;
 766         }
 767
 768         if (adev->firmware.smu_load) {
 769                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 770                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 771                 info->fw = adev->gfx.pfp_fw;
 772                 header = (const struct common_firmware_header *)info->fw->data;
 773                 adev->firmware.fw_size +=
 774                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 775
 776                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 777                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 778                 info->fw = adev->gfx.me_fw;
 779                 header = (const struct common_firmware_header *)info->fw->data;
 780                 adev->firmware.fw_size +=
 781                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 782
 783                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 784                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 785                 info->fw = adev->gfx.ce_fw;
 786                 header = (const struct common_firmware_header *)info->fw->data;
 787                 adev->firmware.fw_size +=
 788                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 789
 790                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 791                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 792                 info->fw = adev->gfx.rlc_fw;
 793                 header = (const struct common_firmware_header *)info->fw->data;
 794                 adev->firmware.fw_size +=
 795                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 796
 797                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 798                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 799                 info->fw = adev->gfx.mec_fw;
 800                 header = (const struct common_firmware_header *)info->fw->data;
 801                 adev->firmware.fw_size +=
 802                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 803
 804                 if (adev->gfx.mec2_fw) {
 805                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 806                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 807                         info->fw = adev->gfx.mec2_fw;
 808                         header = (const struct common_firmware_header *)info->fw->data;
 809                         adev->firmware.fw_size +=
 810                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 811                 }
 812
 813         }
 814
 815 out:
 816         if (err) {
 817                 dev_err(adev->dev,
 818                         "gfx8: Failed to load firmware \"%s\"\n",
 819                         fw_name);
 820                 release_firmware(adev->gfx.pfp_fw);
 821                 adev->gfx.pfp_fw = NULL;
 822                 release_firmware(adev->gfx.me_fw);
 823                 adev->gfx.me_fw = NULL;
 824                 release_firmware(adev->gfx.ce_fw);
 825                 adev->gfx.ce_fw = NULL;
 826                 release_firmware(adev->gfx.rlc_fw);
 827                 adev->gfx.rlc_fw = NULL;
 828                 release_firmware(adev->gfx.mec_fw);
 829                 adev->gfx.mec_fw = NULL;
 830                 release_firmware(adev->gfx.mec2_fw);
 831                 adev->gfx.mec2_fw = NULL;
 832         }
 833         return err;
 834 }
 835
 836 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 837 {
 838         int r;
 839
 840         if (adev->gfx.mec.hpd_eop_obj) {
 841                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 842                 if (unlikely(r != 0))
 843                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 844                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 845                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 846
 847                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 848                 adev->gfx.mec.hpd_eop_obj = NULL;
 849         }
 850 }
 851
 852 #define MEC_HPD_SIZE 2048
 853
 854 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 855 {
 856         int r;
 857         u32 *hpd;
 858
 859         /*
 860          * we assign only 1 pipe because all other pipes will
 861          * be handled by KFD
 862          */
 863         adev->gfx.mec.num_mec = 1;
 864         adev->gfx.mec.num_pipe = 1;
 865         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 866
 867         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 868                 r = amdgpu_bo_create(adev,
 869                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 870                                      PAGE_SIZE, true,
 871                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
 872                                      &adev->gfx.mec.hpd_eop_obj);
 873                 if (r) {
 874                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 875                         return r;
 876                 }
 877         }
 878
 879         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 880         if (unlikely(r != 0)) {
 881                 gfx_v8_0_mec_fini(adev);
 882                 return r;
 883         }
 884         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 885                           &adev->gfx.mec.hpd_eop_gpu_addr);
 886         if (r) {
 887                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 888                 gfx_v8_0_mec_fini(adev);
 889                 return r;
 890         }
 891         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 892         if (r) {
 893                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 894                 gfx_v8_0_mec_fini(adev);
 895                 return r;
 896         }
 897
 898         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 899
 900         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 901         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 902
 903         return 0;
 904 }
 905
 906 static int gfx_v8_0_sw_init(void *handle)
 907 {
 908         int i, r;
 909         struct amdgpu_ring *ring;
 910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 911
 912         /* EOP Event */
 913         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
 914         if (r)
 915                 return r;
 916
 917         /* Privileged reg */
 918         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
 919         if (r)
 920                 return r;
 921
 922         /* Privileged inst */
 923         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
 924         if (r)
 925                 return r;
 926
 927         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 928
 929         gfx_v8_0_scratch_init(adev);
 930
 931         r = gfx_v8_0_init_microcode(adev);
 932         if (r) {
 933                 DRM_ERROR("Failed to load gfx firmware!\n");
 934                 return r;
 935         }
 936
 937         r = gfx_v8_0_mec_init(adev);
 938         if (r) {
 939                 DRM_ERROR("Failed to init MEC BOs!\n");
 940                 return r;
 941         }
 942
 943         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
 944         if (r) {
 945                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
 946                 return r;
 947         }
 948
 949         /* set up the gfx ring */
 950         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 951                 ring = &adev->gfx.gfx_ring[i];
 952                 ring->ring_obj = NULL;
 953                 sprintf(ring->name, "gfx");
 954                 /* no gfx doorbells on iceland */
 955                 if (adev->asic_type != CHIP_TOPAZ) {
 956                         ring->use_doorbell = true;
 957                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 958                 }
 959
 960                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 961                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 962                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 963                                      AMDGPU_RING_TYPE_GFX);
 964                 if (r)
 965                         return r;
 966         }
 967
 968         /* set up the compute queues */
 969         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 970                 unsigned irq_type;
 971
 972                 /* max 32 queues per MEC */
 973                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
 974                         DRM_ERROR("Too many (%d) compute rings!\n", i);
 975                         break;
 976                 }
 977                 ring = &adev->gfx.compute_ring[i];
 978                 ring->ring_obj = NULL;
 979                 ring->use_doorbell = true;
 980                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
 981                 ring->me = 1; /* first MEC */
 982                 ring->pipe = i / 8;
 983                 ring->queue = i % 8;
 984                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 985                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
 986                 /* type-2 packets are deprecated on MEC, use type-3 instead */
 987                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 988                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 989                                      &adev->gfx.eop_irq, irq_type,
 990                                      AMDGPU_RING_TYPE_COMPUTE);
 991                 if (r)
 992                         return r;
 993         }
 994
 995         /* reserve GDS, GWS and OA resource for gfx */
 996         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
 997                         PAGE_SIZE, true,
 998                         AMDGPU_GEM_DOMAIN_GDS, 0,
 999                         NULL, &adev->gds.gds_gfx_bo);
1000         if (r)
1001                 return r;
1002
1003         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1004                 PAGE_SIZE, true,
1005                 AMDGPU_GEM_DOMAIN_GWS, 0,
1006                 NULL, &adev->gds.gws_gfx_bo);
1007         if (r)
1008                 return r;
1009
1010         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1011                         PAGE_SIZE, true,
1012                         AMDGPU_GEM_DOMAIN_OA, 0,
1013                         NULL, &adev->gds.oa_gfx_bo);
1014         if (r)
1015                 return r;
1016
1017         adev->gfx.ce_ram_size = 0x8000;
1018
1019         return 0;
1020 }
1021
1022 static int gfx_v8_0_sw_fini(void *handle)
1023 {
1024         int i;
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1028         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1029         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1030
1031         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1032                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1033         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1034                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1035
1036         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
1037
1038         gfx_v8_0_mec_fini(adev);
1039
1040         return 0;
1041 }
1042
1043 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1044 {
1045         const u32 num_tile_mode_states = 32;
1046         const u32 num_secondary_tile_mode_states = 16;
1047         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1048
1049         switch (adev->gfx.config.mem_row_size_in_kb) {
1050         case 1:
1051                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1052                 break;
1053         case 2:
1054         default:
1055                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1056                 break;
1057         case 4:
1058                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1059                 break;
1060         }
1061
1062         switch (adev->asic_type) {
1063         case CHIP_TOPAZ:
1064                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1065                         switch (reg_offset) {
1066                         case 0:
1067                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1069                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1070                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1071                                 break;
1072                         case 1:
1073                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1074                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1075                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1076                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1077                                 break;
1078                         case 2:
1079                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1080                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1081                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1082                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1083                                 break;
1084                         case 3:
1085                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1087                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1088                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1089                                 break;
1090                         case 4:
1091                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1092                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1093                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1094                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1095                                 break;
1096                         case 5:
1097                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1098                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1099                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1100                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1101                                 break;
1102                         case 6:
1103                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1104                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1105                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1106                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1107                                 break;
1108                         case 8:
1109                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1110                                                 PIPE_CONFIG(ADDR_SURF_P2));
1111                                 break;
1112                         case 9:
1113                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1115                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1116                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1117                                 break;
1118                         case 10:
1119                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1120                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1121                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1122                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1123                                 break;
1124                         case 11:
1125                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1126                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1127                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1128                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1129                                 break;
1130                         case 13:
1131                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1132                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1133                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1135                                 break;
1136                         case 14:
1137                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1138                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1139                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1141                                 break;
1142                         case 15:
1143                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1144                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1145                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1146                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1147                                 break;
1148                         case 16:
1149                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1150                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1151                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1152                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1153                                 break;
1154                         case 18:
1155                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1156                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1157                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1158                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1159                                 break;
1160                         case 19:
1161                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1162                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1163                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1164                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1165                                 break;
1166                         case 20:
1167                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1168                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1169                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1170                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1171                                 break;
1172                         case 21:
1173                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1174                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1175                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1176                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1177                                 break;
1178                         case 22:
1179                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1180                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1181                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1182                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1183                                 break;
1184                         case 24:
1185                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1186                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1187                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1188                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1189                                 break;
1190                         case 25:
1191                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1192                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1193                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1194                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1195                                 break;
1196                         case 26:
1197                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1198                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1199                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1200                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1201                                 break;
1202                         case 27:
1203                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1204                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1205                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1206                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1207                                 break;
1208                         case 28:
1209                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1210                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1211                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1212                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1213                                 break;
1214                         case 29:
1215                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1216                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1217                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1218                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1219                                 break;
1220                         case 7:
1221                         case 12:
1222                         case 17:
1223                         case 23:
1224                                 /* unused idx */
1225                                 continue;
1226                         default:
1227                                 gb_tile_moden = 0;
1228                                 break;
1229                         };
1230                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1231                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1232                 }
1233                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1234                         switch (reg_offset) {
1235                         case 0:
1236                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1237                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1239                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1240                                 break;
1241                         case 1:
1242                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1243                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1244                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1245                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1246                                 break;
1247                         case 2:
1248                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1249                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1250                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1251                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1252                                 break;
1253                         case 3:
1254                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1255                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1256                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1257                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1258                                 break;
1259                         case 4:
1260                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1262                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1263                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1264                                 break;
1265                         case 5:
1266                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1267                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1268                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1269                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1270                                 break;
1271                         case 6:
1272                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1273                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1274                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1275                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1276                                 break;
1277                         case 8:
1278                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1279                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1280                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1281                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1282                                 break;
1283                         case 9:
1284                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1285                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1286                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1287                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1288                                 break;
1289                         case 10:
1290                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1291                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1292                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1293                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1294                                 break;
1295                         case 11:
1296                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1297                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1298                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1299                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1300                                 break;
1301                         case 12:
1302                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1303                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1304                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1305                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1306                                 break;
1307                         case 13:
1308                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1309                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1310                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1311                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1312                                 break;
1313                         case 14:
1314                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1315                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1316                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1317                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1318                                 break;
1319                         case 7:
1320                                 /* unused idx */
1321                                 continue;
1322                         default:
1323                                 gb_tile_moden = 0;
1324                                 break;
1325                         };
1326                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1327                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1328                 }
1329         case CHIP_FIJI:
1330         case CHIP_TONGA:
1331                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1332                         switch (reg_offset) {
1333                         case 0:
1334                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1336                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1337                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1338                                 break;
1339                         case 1:
1340                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1341                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1342                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1343                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1344                                 break;
1345                         case 2:
1346                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1347                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1348                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1349                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1350                                 break;
1351                         case 3:
1352                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1353                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1354                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1355                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1356                                 break;
1357                         case 4:
1358                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1359                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1360                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1361                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1362                                 break;
1363                         case 5:
1364                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1365                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1366                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1367                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1368                                 break;
1369                         case 6:
1370                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1371                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1372                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1373                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1374                                 break;
1375                         case 7:
1376                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1377                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1378                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1379                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1380                                 break;
1381                         case 8:
1382                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1383                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1384                                 break;
1385                         case 9:
1386                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1387                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1388                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1389                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1390                                 break;
1391                         case 10:
1392                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1393                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1394                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1395                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1396                                 break;
1397                         case 11:
1398                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1399                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1400                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1401                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1402                                 break;
1403                         case 12:
1404                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1405                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1406                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1407                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1408                                 break;
1409                         case 13:
1410                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1412                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1413                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1414                                 break;
1415                         case 14:
1416                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1417                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1418                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1419                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1420                                 break;
1421                         case 15:
1422                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1423                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1424                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1425                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1426                                 break;
1427                         case 16:
1428                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1429                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1430                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1431                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1432                                 break;
1433                         case 17:
1434                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1435                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1436                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1437                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1438                                 break;
1439                         case 18:
1440                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1441                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1442                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1443                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1444                                 break;
1445                         case 19:
1446                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1447                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1448                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1449                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1450                                 break;
1451                         case 20:
1452                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1453                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1454                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1455                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1456                                 break;
1457                         case 21:
1458                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1459                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1460                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1461                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1462                                 break;
1463                         case 22:
1464                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1465                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1466                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1467                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468                                 break;
1469                         case 23:
1470                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1471                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1472                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1473                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1474                                 break;
1475                         case 24:
1476                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1477                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1478                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1479                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480                                 break;
1481                         case 25:
1482                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1483                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1484                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1485                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1486                                 break;
1487                         case 26:
1488                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1489                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1490                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492                                 break;
1493                         case 27:
1494                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1495                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1496                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1497                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1498                                 break;
1499                         case 28:
1500                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1501                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1502                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1503                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1504                                 break;
1505                         case 29:
1506                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1507                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1508                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1509                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1510                                 break;
1511                         case 30:
1512                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1513                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1514                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1515                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1516                                 break;
1517                         default:
1518                                 gb_tile_moden = 0;
1519                                 break;
1520                         };
1521                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1522                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1523                 }
1524                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1525                         switch (reg_offset) {
1526                         case 0:
1527                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1528                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1529                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1530                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1531                                 break;
1532                         case 1:
1533                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1535                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1537                                 break;
1538                         case 2:
1539                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1540                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1541                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1542                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1543                                 break;
1544                         case 3:
1545                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1549                                 break;
1550                         case 4:
1551                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1552                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1553                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1554                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1555                                 break;
1556                         case 5:
1557                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1560                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1561                                 break;
1562                         case 6:
1563                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1564                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1565                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1566                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1567                                 break;
1568                         case 8:
1569                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1570                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1571                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1572                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1573                                 break;
1574                         case 9:
1575                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1576                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1577                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1578                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1579                                 break;
1580                         case 10:
1581                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1582                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1583                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1584                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1585                                 break;
1586                         case 11:
1587                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1588                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1589                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1590                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1591                                 break;
1592                         case 12:
1593                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1594                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1595                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1596                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1597                                 break;
1598                         case 13:
1599                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1600                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1601                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1602                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1603                                 break;
1604                         case 14:
1605                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1606                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1607                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1608                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1609                                 break;
1610                         case 7:
1611                                 /* unused idx */
1612                                 continue;
1613                         default:
1614                                 gb_tile_moden = 0;
1615                                 break;
1616                         };
1617                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1618                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1619                 }
1620                 break;
1621         case CHIP_CARRIZO:
1622         default:
1623                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1624                         switch (reg_offset) {
1625                         case 0:
1626                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1627                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1628                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1629                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1630                                 break;
1631                         case 1:
1632                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1633                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1634                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1635                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1636                                 break;
1637                         case 2:
1638                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1639                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1640                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1641                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1642                                 break;
1643                         case 3:
1644                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1645                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1646                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1647                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1648                                 break;
1649                         case 4:
1650                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1651                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1652                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1653                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1654                                 break;
1655                         case 5:
1656                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1657                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1658                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1659                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1660                                 break;
1661                         case 6:
1662                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1663                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1664                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1665                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1666                                 break;
1667                         case 8:
1668                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1669                                                 PIPE_CONFIG(ADDR_SURF_P2));
1670                                 break;
1671                         case 9:
1672                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1673                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1674                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1675                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1676                                 break;
1677                         case 10:
1678                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1679                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1680                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1681                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1682                                 break;
1683                         case 11:
1684                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1685                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1686                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1687                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1688                                 break;
1689                         case 13:
1690                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1691                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1692                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1693                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1694                                 break;
1695                         case 14:
1696                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1697                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1698                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1699                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1700                                 break;
1701                         case 15:
1702                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1703                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1704                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1705                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1706                                 break;
1707                         case 16:
1708                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1709                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1710                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1711                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1712                                 break;
1713                         case 18:
1714                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1715                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1716                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1717                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1718                                 break;
1719                         case 19:
1720                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1721                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1722                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1723                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1724                                 break;
1725                         case 20:
1726                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1727                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1728                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1729                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1730                                 break;
1731                         case 21:
1732                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1733                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1734                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1735                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1736                                 break;
1737                         case 22:
1738                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1739                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1740                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1741                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1742                                 break;
1743                         case 24:
1744                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1745                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1746                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1747                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1748                                 break;
1749                         case 25:
1750                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1751                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1752                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1753                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1754                                 break;
1755                         case 26:
1756                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1757                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1758                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1759                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1760                                 break;
1761                         case 27:
1762                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1763                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1764                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1765                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1766                                 break;
1767                         case 28:
1768                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1769                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1770                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1771                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1772                                 break;
1773                         case 29:
1774                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1775                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1776                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1777                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1778                                 break;
1779                         case 7:
1780                         case 12:
1781                         case 17:
1782                         case 23:
1783                                 /* unused idx */
1784                                 continue;
1785                         default:
1786                                 gb_tile_moden = 0;
1787                                 break;
1788                         };
1789                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1790                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1791                 }
1792                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1793                         switch (reg_offset) {
1794                         case 0:
1795                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1796                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1797                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1798                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1799                                 break;
1800                         case 1:
1801                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1802                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1803                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1804                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1805                                 break;
1806                         case 2:
1807                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1808                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1809                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1810                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1811                                 break;
1812                         case 3:
1813                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1814                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1815                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1816                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1817                                 break;
1818                         case 4:
1819                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1820                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1821                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1822                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1823                                 break;
1824                         case 5:
1825                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1826                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1827                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1828                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1829                                 break;
1830                         case 6:
1831                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1832                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1833                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1834                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1835                                 break;
1836                         case 8:
1837                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1838                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1839                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1840                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1841                                 break;
1842                         case 9:
1843                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1844                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1845                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1846                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1847                                 break;
1848                         case 10:
1849                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1850                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1851                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1852                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1853                                 break;
1854                         case 11:
1855                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1856                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1857                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1858                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1859                                 break;
1860                         case 12:
1861                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1862                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1863                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1864                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1865                                 break;
1866                         case 13:
1867                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1868                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1869                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1870                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1871                                 break;
1872                         case 14:
1873                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1874                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1875                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1876                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1877                                 break;
1878                         case 7:
1879                                 /* unused idx */
1880                                 continue;
1881                         default:
1882                                 gb_tile_moden = 0;
1883                                 break;
1884                         };
1885                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1886                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1887                 }
1888         }
1889 }
1890
1891 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1892 {
1893         u32 i, mask = 0;
1894
1895         for (i = 0; i < bit_width; i++) {
1896                 mask <<= 1;
1897                 mask |= 1;
1898         }
1899         return mask;
1900 }
1901
1902 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1903 {
1904         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1905
1906         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1907                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1908                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1909         } else if (se_num == 0xffffffff) {
1910                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1911                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1912         } else if (sh_num == 0xffffffff) {
1913                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1914                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1915         } else {
1916                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1917                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1918         }
1919         WREG32(mmGRBM_GFX_INDEX, data);
1920 }
1921
1922 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1923                                     u32 max_rb_num_per_se,
1924                                     u32 sh_per_se)
1925 {
1926         u32 data, mask;
1927
1928         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1929         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1930
1931         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1932
1933         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1934
1935         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1936
1937         return data & mask;
1938 }
1939
1940 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1941                               u32 se_num, u32 sh_per_se,
1942                               u32 max_rb_num_per_se)
1943 {
1944         int i, j;
1945         u32 data, mask;
1946         u32 disabled_rbs = 0;
1947         u32 enabled_rbs = 0;
1948
1949         mutex_lock(&adev->grbm_idx_mutex);
1950         for (i = 0; i < se_num; i++) {
1951                 for (j = 0; j < sh_per_se; j++) {
1952                         gfx_v8_0_select_se_sh(adev, i, j);
1953                         data = gfx_v8_0_get_rb_disabled(adev,
1954                                               max_rb_num_per_se, sh_per_se);
1955                         disabled_rbs |= data << ((i * sh_per_se + j) *
1956                                                  RB_BITMAP_WIDTH_PER_SH);
1957                 }
1958         }
1959         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1960         mutex_unlock(&adev->grbm_idx_mutex);
1961
1962         mask = 1;
1963         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1964                 if (!(disabled_rbs & mask))
1965                         enabled_rbs |= mask;
1966                 mask <<= 1;
1967         }
1968
1969         adev->gfx.config.backend_enable_mask = enabled_rbs;
1970
1971         mutex_lock(&adev->grbm_idx_mutex);
1972         for (i = 0; i < se_num; i++) {
1973                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1974                 data = 0;
1975                 for (j = 0; j < sh_per_se; j++) {
1976                         switch (enabled_rbs & 3) {
1977                         case 0:
1978                                 if (j == 0)
1979                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1980                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1981                                 else
1982                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1983                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1984                                 break;
1985                         case 1:
1986                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
1987                                          (i * sh_per_se + j) * 2);
1988                                 break;
1989                         case 2:
1990                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
1991                                          (i * sh_per_se + j) * 2);
1992                                 break;
1993                         case 3:
1994                         default:
1995                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
1996                                          (i * sh_per_se + j) * 2);
1997                                 break;
1998                         }
1999                         enabled_rbs >>= 2;
2000                 }
2001                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2002         }
2003         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2004         mutex_unlock(&adev->grbm_idx_mutex);
2005 }
2006
2007 /**
2008  * gfx_v8_0_init_compute_vmid - gart enable
2009  *
2010  * @rdev: amdgpu_device pointer
2011  *
2012  * Initialize compute vmid sh_mem registers
2013  *
2014  */
2015 #define DEFAULT_SH_MEM_BASES    (0x6000)
2016 #define FIRST_COMPUTE_VMID      (8)
2017 #define LAST_COMPUTE_VMID       (16)
2018 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2019 {
2020         int i;
2021         uint32_t sh_mem_config;
2022         uint32_t sh_mem_bases;
2023
2024         /*
2025          * Configure apertures:
2026          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2027          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2028          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2029          */
2030         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2031
2032         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2033                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2034                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2035                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2036                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2037                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2038
2039         mutex_lock(&adev->srbm_mutex);
2040         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2041                 vi_srbm_select(adev, 0, 0, 0, i);
2042                 /* CP and shaders */
2043                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2044                 WREG32(mmSH_MEM_APE1_BASE, 1);
2045                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2046                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2047         }
2048         vi_srbm_select(adev, 0, 0, 0, 0);
2049         mutex_unlock(&adev->srbm_mutex);
2050 }
2051
2052 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2053 {
2054         u32 gb_addr_config;
2055         u32 mc_shared_chmap, mc_arb_ramcfg;
2056         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2057         u32 tmp;
2058         int i;
2059
2060         switch (adev->asic_type) {
2061         case CHIP_TOPAZ:
2062                 adev->gfx.config.max_shader_engines = 1;
2063                 adev->gfx.config.max_tile_pipes = 2;
2064                 adev->gfx.config.max_cu_per_sh = 6;
2065                 adev->gfx.config.max_sh_per_se = 1;
2066                 adev->gfx.config.max_backends_per_se = 2;
2067                 adev->gfx.config.max_texture_channel_caches = 2;
2068                 adev->gfx.config.max_gprs = 256;
2069                 adev->gfx.config.max_gs_threads = 32;
2070                 adev->gfx.config.max_hw_contexts = 8;
2071
2072                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2073                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2074                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2075                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2076                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
2077                 break;
2078         case CHIP_FIJI:
2079                 adev->gfx.config.max_shader_engines = 4;
2080                 adev->gfx.config.max_tile_pipes = 16;
2081                 adev->gfx.config.max_cu_per_sh = 16;
2082                 adev->gfx.config.max_sh_per_se = 1;
2083                 adev->gfx.config.max_backends_per_se = 4;
2084                 adev->gfx.config.max_texture_channel_caches = 8;
2085                 adev->gfx.config.max_gprs = 256;
2086                 adev->gfx.config.max_gs_threads = 32;
2087                 adev->gfx.config.max_hw_contexts = 8;
2088
2089                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2090                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2091                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2092                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2093                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2094                 break;
2095         case CHIP_TONGA:
2096                 adev->gfx.config.max_shader_engines = 4;
2097                 adev->gfx.config.max_tile_pipes = 8;
2098                 adev->gfx.config.max_cu_per_sh = 8;
2099                 adev->gfx.config.max_sh_per_se = 1;
2100                 adev->gfx.config.max_backends_per_se = 2;
2101                 adev->gfx.config.max_texture_channel_caches = 8;
2102                 adev->gfx.config.max_gprs = 256;
2103                 adev->gfx.config.max_gs_threads = 32;
2104                 adev->gfx.config.max_hw_contexts = 8;
2105
2106                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2107                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2108                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2109                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2110                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2111                 break;
2112         case CHIP_CARRIZO:
2113                 adev->gfx.config.max_shader_engines = 1;
2114                 adev->gfx.config.max_tile_pipes = 2;
2115                 adev->gfx.config.max_sh_per_se = 1;
2116                 adev->gfx.config.max_backends_per_se = 2;
2117
2118                 switch (adev->pdev->revision) {
2119                 case 0xc4:
2120                 case 0x84:
2121                 case 0xc8:
2122                 case 0xcc:
2123                         /* B10 */
2124                         adev->gfx.config.max_cu_per_sh = 8;
2125                         break;
2126                 case 0xc5:
2127                 case 0x81:
2128                 case 0x85:
2129                 case 0xc9:
2130                 case 0xcd:
2131                         /* B8 */
2132                         adev->gfx.config.max_cu_per_sh = 6;
2133                         break;
2134                 case 0xc6:
2135                 case 0xca:
2136                 case 0xce:
2137                         /* B6 */
2138                         adev->gfx.config.max_cu_per_sh = 6;
2139                         break;
2140                 case 0xc7:
2141                 case 0x87:
2142                 case 0xcb:
2143                 default:
2144                         /* B4 */
2145                         adev->gfx.config.max_cu_per_sh = 4;
2146                         break;
2147                 }
2148
2149                 adev->gfx.config.max_texture_channel_caches = 2;
2150                 adev->gfx.config.max_gprs = 256;
2151                 adev->gfx.config.max_gs_threads = 32;
2152                 adev->gfx.config.max_hw_contexts = 8;
2153
2154                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2155                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2156                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2157                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2158                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2159                 break;
2160         default:
2161                 adev->gfx.config.max_shader_engines = 2;
2162                 adev->gfx.config.max_tile_pipes = 4;
2163                 adev->gfx.config.max_cu_per_sh = 2;
2164                 adev->gfx.config.max_sh_per_se = 1;
2165                 adev->gfx.config.max_backends_per_se = 2;
2166                 adev->gfx.config.max_texture_channel_caches = 4;
2167                 adev->gfx.config.max_gprs = 256;
2168                 adev->gfx.config.max_gs_threads = 32;
2169                 adev->gfx.config.max_hw_contexts = 8;
2170
2171                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2172                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2173                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2174                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2175                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2176                 break;
2177         }
2178
2179         tmp = RREG32(mmGRBM_CNTL);
2180         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2181         WREG32(mmGRBM_CNTL, tmp);
2182
2183         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2184         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2185         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2186
2187         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2188         adev->gfx.config.mem_max_burst_length_bytes = 256;
2189         if (adev->flags & AMD_IS_APU) {
2190                 /* Get memory bank mapping mode. */
2191                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2192                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2193                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2194
2195                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2196                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2197                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2198
2199                 /* Validate settings in case only one DIMM installed. */
2200                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2201                         dimm00_addr_map = 0;
2202                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2203                         dimm01_addr_map = 0;
2204                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2205                         dimm10_addr_map = 0;
2206                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2207                         dimm11_addr_map = 0;
2208
2209                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2210                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2211                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2212                         adev->gfx.config.mem_row_size_in_kb = 2;
2213                 else
2214                         adev->gfx.config.mem_row_size_in_kb = 1;
2215         } else {
2216                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2217                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2218                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2219                         adev->gfx.config.mem_row_size_in_kb = 4;
2220         }
2221
2222         adev->gfx.config.shader_engine_tile_size = 32;
2223         adev->gfx.config.num_gpus = 1;
2224         adev->gfx.config.multi_gpu_tile_size = 64;
2225
2226         /* fix up row size */
2227         switch (adev->gfx.config.mem_row_size_in_kb) {
2228         case 1:
2229         default:
2230                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2231                 break;
2232         case 2:
2233                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2234                 break;
2235         case 4:
2236                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2237                 break;
2238         }
2239         adev->gfx.config.gb_addr_config = gb_addr_config;
2240
2241         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2242         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2243         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2244         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2245                gb_addr_config & 0x70);
2246         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2247                gb_addr_config & 0x70);
2248         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2249         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2250         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2251
2252         gfx_v8_0_tiling_mode_table_init(adev);
2253
2254         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2255                                  adev->gfx.config.max_sh_per_se,
2256                                  adev->gfx.config.max_backends_per_se);
2257
2258         /* XXX SH_MEM regs */
2259         /* where to put LDS, scratch, GPUVM in FSA64 space */
2260         mutex_lock(&adev->srbm_mutex);
2261         for (i = 0; i < 16; i++) {
2262                 vi_srbm_select(adev, 0, 0, 0, i);
2263                 /* CP and shaders */
2264                 if (i == 0) {
2265                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2266                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2267                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2268                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2269                         WREG32(mmSH_MEM_CONFIG, tmp);
2270                 } else {
2271                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2272                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2273                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2274                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2275                         WREG32(mmSH_MEM_CONFIG, tmp);
2276                 }
2277
2278                 WREG32(mmSH_MEM_APE1_BASE, 1);
2279                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2280                 WREG32(mmSH_MEM_BASES, 0);
2281         }
2282         vi_srbm_select(adev, 0, 0, 0, 0);
2283         mutex_unlock(&adev->srbm_mutex);
2284
2285         gfx_v8_0_init_compute_vmid(adev);
2286
2287         mutex_lock(&adev->grbm_idx_mutex);
2288         /*
2289          * making sure that the following register writes will be broadcasted
2290          * to all the shaders
2291          */
2292         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2293
2294         WREG32(mmPA_SC_FIFO_SIZE,
2295                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2296                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2297                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2298                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2299                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2300                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2301                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2302                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2303         mutex_unlock(&adev->grbm_idx_mutex);
2304
2305 }
2306
2307 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2308 {
2309         u32 i, j, k;
2310         u32 mask;
2311
2312         mutex_lock(&adev->grbm_idx_mutex);
2313         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2314                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2315                         gfx_v8_0_select_se_sh(adev, i, j);
2316                         for (k = 0; k < adev->usec_timeout; k++) {
2317                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2318                                         break;
2319                                 udelay(1);
2320                         }
2321                 }
2322         }
2323         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2324         mutex_unlock(&adev->grbm_idx_mutex);
2325
2326         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2327                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2328                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2329                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2330         for (k = 0; k < adev->usec_timeout; k++) {
2331                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2332                         break;
2333                 udelay(1);
2334         }
2335 }
2336
2337 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2338                                                bool enable)
2339 {
2340         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2341
2342         if (enable) {
2343                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2344                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2345                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2346                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2347         } else {
2348                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2349                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2350                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2351                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2352         }
2353         WREG32(mmCP_INT_CNTL_RING0, tmp);
2354 }
2355
2356 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2357 {
2358         u32 tmp = RREG32(mmRLC_CNTL);
2359
2360         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2361         WREG32(mmRLC_CNTL, tmp);
2362
2363         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2364
2365         gfx_v8_0_wait_for_rlc_serdes(adev);
2366 }
2367
2368 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2369 {
2370         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2371
2372         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2373         WREG32(mmGRBM_SOFT_RESET, tmp);
2374         udelay(50);
2375         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2376         WREG32(mmGRBM_SOFT_RESET, tmp);
2377         udelay(50);
2378 }
2379
2380 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2381 {
2382         u32 tmp = RREG32(mmRLC_CNTL);
2383
2384         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2385         WREG32(mmRLC_CNTL, tmp);
2386
2387         /* carrizo do enable cp interrupt after cp inited */
2388         if (adev->asic_type != CHIP_CARRIZO)
2389                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2390
2391         udelay(50);
2392 }
2393
2394 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2395 {
2396         const struct rlc_firmware_header_v2_0 *hdr;
2397         const __le32 *fw_data;
2398         unsigned i, fw_size;
2399
2400         if (!adev->gfx.rlc_fw)
2401                 return -EINVAL;
2402
2403         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2404         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2405
2406         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2407                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2408         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2409
2410         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2411         for (i = 0; i < fw_size; i++)
2412                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2413         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2414
2415         return 0;
2416 }
2417
2418 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2419 {
2420         int r;
2421
2422         gfx_v8_0_rlc_stop(adev);
2423
2424         /* disable CG */
2425         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2426
2427         /* disable PG */
2428         WREG32(mmRLC_PG_CNTL, 0);
2429
2430         gfx_v8_0_rlc_reset(adev);
2431
2432         if (!adev->firmware.smu_load) {
2433                 /* legacy rlc firmware loading */
2434                 r = gfx_v8_0_rlc_load_microcode(adev);
2435                 if (r)
2436                         return r;
2437         } else {
2438                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2439                                                 AMDGPU_UCODE_ID_RLC_G);
2440                 if (r)
2441                         return -EINVAL;
2442         }
2443
2444         gfx_v8_0_rlc_start(adev);
2445
2446         return 0;
2447 }
2448
2449 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2450 {
2451         int i;
2452         u32 tmp = RREG32(mmCP_ME_CNTL);
2453
2454         if (enable) {
2455                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2456                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2457                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2458         } else {
2459                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2460                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2461                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2462                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2463                         adev->gfx.gfx_ring[i].ready = false;
2464         }
2465         WREG32(mmCP_ME_CNTL, tmp);
2466         udelay(50);
2467 }
2468
2469 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2470 {
2471         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2472         const struct gfx_firmware_header_v1_0 *ce_hdr;
2473         const struct gfx_firmware_header_v1_0 *me_hdr;
2474         const __le32 *fw_data;
2475         unsigned i, fw_size;
2476
2477         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2478                 return -EINVAL;
2479
2480         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2481                 adev->gfx.pfp_fw->data;
2482         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2483                 adev->gfx.ce_fw->data;
2484         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2485                 adev->gfx.me_fw->data;
2486
2487         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2488         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2489         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2490
2491         gfx_v8_0_cp_gfx_enable(adev, false);
2492
2493         /* PFP */
2494         fw_data = (const __le32 *)
2495                 (adev->gfx.pfp_fw->data +
2496                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2497         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2498         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2499         for (i = 0; i < fw_size; i++)
2500                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2501         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2502
2503         /* CE */
2504         fw_data = (const __le32 *)
2505                 (adev->gfx.ce_fw->data +
2506                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2507         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2508         WREG32(mmCP_CE_UCODE_ADDR, 0);
2509         for (i = 0; i < fw_size; i++)
2510                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2511         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2512
2513         /* ME */
2514         fw_data = (const __le32 *)
2515                 (adev->gfx.me_fw->data +
2516                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2517         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2518         WREG32(mmCP_ME_RAM_WADDR, 0);
2519         for (i = 0; i < fw_size; i++)
2520                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2521         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2522
2523         return 0;
2524 }
2525
2526 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2527 {
2528         u32 count = 0;
2529         const struct cs_section_def *sect = NULL;
2530         const struct cs_extent_def *ext = NULL;
2531
2532         /* begin clear state */
2533         count += 2;
2534         /* context control state */
2535         count += 3;
2536
2537         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2538                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2539                         if (sect->id == SECT_CONTEXT)
2540                                 count += 2 + ext->reg_count;
2541                         else
2542                                 return 0;
2543                 }
2544         }
2545         /* pa_sc_raster_config/pa_sc_raster_config1 */
2546         count += 4;
2547         /* end clear state */
2548         count += 2;
2549         /* clear state */
2550         count += 2;
2551
2552         return count;
2553 }
2554
2555 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2556 {
2557         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2558         const struct cs_section_def *sect = NULL;
2559         const struct cs_extent_def *ext = NULL;
2560         int r, i;
2561
2562         /* init the CP */
2563         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2564         WREG32(mmCP_ENDIAN_SWAP, 0);
2565         WREG32(mmCP_DEVICE_ID, 1);
2566
2567         gfx_v8_0_cp_gfx_enable(adev, true);
2568
2569         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2570         if (r) {
2571                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2572                 return r;
2573         }
2574
2575         /* clear state buffer */
2576         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2577         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2578
2579         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2580         amdgpu_ring_write(ring, 0x80000000);
2581         amdgpu_ring_write(ring, 0x80000000);
2582
2583         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2584                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2585                         if (sect->id == SECT_CONTEXT) {
2586                                 amdgpu_ring_write(ring,
2587                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2588                                                ext->reg_count));
2589                                 amdgpu_ring_write(ring,
2590                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2591                                 for (i = 0; i < ext->reg_count; i++)
2592                                         amdgpu_ring_write(ring, ext->extent[i]);
2593                         }
2594                 }
2595         }
2596
2597         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2598         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2599         switch (adev->asic_type) {
2600         case CHIP_TONGA:
2601         case CHIP_FIJI:
2602                 amdgpu_ring_write(ring, 0x16000012);
2603                 amdgpu_ring_write(ring, 0x0000002A);
2604                 break;
2605         case CHIP_TOPAZ:
2606         case CHIP_CARRIZO:
2607                 amdgpu_ring_write(ring, 0x00000002);
2608                 amdgpu_ring_write(ring, 0x00000000);
2609                 break;
2610         default:
2611                 BUG();
2612         }
2613
2614         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2615         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2616
2617         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2618         amdgpu_ring_write(ring, 0);
2619
2620         /* init the CE partitions */
2621         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2622         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2623         amdgpu_ring_write(ring, 0x8000);
2624         amdgpu_ring_write(ring, 0x8000);
2625
2626         amdgpu_ring_unlock_commit(ring);
2627
2628         return 0;
2629 }
2630
2631 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2632 {
2633         struct amdgpu_ring *ring;
2634         u32 tmp;
2635         u32 rb_bufsz;
2636         u64 rb_addr, rptr_addr;
2637         int r;
2638
2639         /* Set the write pointer delay */
2640         WREG32(mmCP_RB_WPTR_DELAY, 0);
2641
2642         /* set the RB to use vmid 0 */
2643         WREG32(mmCP_RB_VMID, 0);
2644
2645         /* Set ring buffer size */
2646         ring = &adev->gfx.gfx_ring[0];
2647         rb_bufsz = order_base_2(ring->ring_size / 8);
2648         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2649         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2650         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2651         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2652 #ifdef __BIG_ENDIAN
2653         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2654 #endif
2655         WREG32(mmCP_RB0_CNTL, tmp);
2656
2657         /* Initialize the ring buffer's read and write pointers */
2658         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2659         ring->wptr = 0;
2660         WREG32(mmCP_RB0_WPTR, ring->wptr);
2661
2662         /* set the wb address wether it's enabled or not */
2663         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2664         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2665         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2666
2667         mdelay(1);
2668         WREG32(mmCP_RB0_CNTL, tmp);
2669
2670         rb_addr = ring->gpu_addr >> 8;
2671         WREG32(mmCP_RB0_BASE, rb_addr);
2672         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2673
2674         /* no gfx doorbells on iceland */
2675         if (adev->asic_type != CHIP_TOPAZ) {
2676                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2677                 if (ring->use_doorbell) {
2678                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2679                                             DOORBELL_OFFSET, ring->doorbell_index);
2680                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2681                                             DOORBELL_EN, 1);
2682                 } else {
2683                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2684                                             DOORBELL_EN, 0);
2685                 }
2686                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2687
2688                 if (adev->asic_type == CHIP_TONGA) {
2689                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2690                                             DOORBELL_RANGE_LOWER,
2691                                             AMDGPU_DOORBELL_GFX_RING0);
2692                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2693
2694                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2695                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2696                 }
2697
2698         }
2699
2700         /* start the ring */
2701         gfx_v8_0_cp_gfx_start(adev);
2702         ring->ready = true;
2703         r = amdgpu_ring_test_ring(ring);
2704         if (r) {
2705                 ring->ready = false;
2706                 return r;
2707         }
2708
2709         return 0;
2710 }
2711
2712 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2713 {
2714         int i;
2715
2716         if (enable) {
2717                 WREG32(mmCP_MEC_CNTL, 0);
2718         } else {
2719                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2720                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2721                         adev->gfx.compute_ring[i].ready = false;
2722         }
2723         udelay(50);
2724 }
2725
2726 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2727 {
2728         gfx_v8_0_cp_compute_enable(adev, true);
2729
2730         return 0;
2731 }
2732
2733 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2734 {
2735         const struct gfx_firmware_header_v1_0 *mec_hdr;
2736         const __le32 *fw_data;
2737         unsigned i, fw_size;
2738
2739         if (!adev->gfx.mec_fw)
2740                 return -EINVAL;
2741
2742         gfx_v8_0_cp_compute_enable(adev, false);
2743
2744         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2745         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2746
2747         fw_data = (const __le32 *)
2748                 (adev->gfx.mec_fw->data +
2749                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2750         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2751
2752         /* MEC1 */
2753         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2754         for (i = 0; i < fw_size; i++)
2755                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2756         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2757
2758         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2759         if (adev->gfx.mec2_fw) {
2760                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2761
2762                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2763                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2764
2765                 fw_data = (const __le32 *)
2766                         (adev->gfx.mec2_fw->data +
2767                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2768                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2769
2770                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2771                 for (i = 0; i < fw_size; i++)
2772                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2773                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2774         }
2775
2776         return 0;
2777 }
2778
2779 struct vi_mqd {
2780         uint32_t header;  /* ordinal0 */
2781         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2782         uint32_t compute_dim_x;  /* ordinal2 */
2783         uint32_t compute_dim_y;  /* ordinal3 */
2784         uint32_t compute_dim_z;  /* ordinal4 */
2785         uint32_t compute_start_x;  /* ordinal5 */
2786         uint32_t compute_start_y;  /* ordinal6 */
2787         uint32_t compute_start_z;  /* ordinal7 */
2788         uint32_t compute_num_thread_x;  /* ordinal8 */
2789         uint32_t compute_num_thread_y;  /* ordinal9 */
2790         uint32_t compute_num_thread_z;  /* ordinal10 */
2791         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2792         uint32_t compute_perfcount_enable;  /* ordinal12 */
2793         uint32_t compute_pgm_lo;  /* ordinal13 */
2794         uint32_t compute_pgm_hi;  /* ordinal14 */
2795         uint32_t compute_tba_lo;  /* ordinal15 */
2796         uint32_t compute_tba_hi;  /* ordinal16 */
2797         uint32_t compute_tma_lo;  /* ordinal17 */
2798         uint32_t compute_tma_hi;  /* ordinal18 */
2799         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2800         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2801         uint32_t compute_vmid;  /* ordinal21 */
2802         uint32_t compute_resource_limits;  /* ordinal22 */
2803         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2804         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2805         uint32_t compute_tmpring_size;  /* ordinal25 */
2806         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2807         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2808         uint32_t compute_restart_x;  /* ordinal28 */
2809         uint32_t compute_restart_y;  /* ordinal29 */
2810         uint32_t compute_restart_z;  /* ordinal30 */
2811         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2812         uint32_t compute_misc_reserved;  /* ordinal32 */
2813         uint32_t compute_dispatch_id;  /* ordinal33 */
2814         uint32_t compute_threadgroup_id;  /* ordinal34 */
2815         uint32_t compute_relaunch;  /* ordinal35 */
2816         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2817         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2818         uint32_t compute_wave_restore_control;  /* ordinal38 */
2819         uint32_t reserved9;  /* ordinal39 */
2820         uint32_t reserved10;  /* ordinal40 */
2821         uint32_t reserved11;  /* ordinal41 */
2822         uint32_t reserved12;  /* ordinal42 */
2823         uint32_t reserved13;  /* ordinal43 */
2824         uint32_t reserved14;  /* ordinal44 */
2825         uint32_t reserved15;  /* ordinal45 */
2826         uint32_t reserved16;  /* ordinal46 */
2827         uint32_t reserved17;  /* ordinal47 */
2828         uint32_t reserved18;  /* ordinal48 */
2829         uint32_t reserved19;  /* ordinal49 */
2830         uint32_t reserved20;  /* ordinal50 */
2831         uint32_t reserved21;  /* ordinal51 */
2832         uint32_t reserved22;  /* ordinal52 */
2833         uint32_t reserved23;  /* ordinal53 */
2834         uint32_t reserved24;  /* ordinal54 */
2835         uint32_t reserved25;  /* ordinal55 */
2836         uint32_t reserved26;  /* ordinal56 */
2837         uint32_t reserved27;  /* ordinal57 */
2838         uint32_t reserved28;  /* ordinal58 */
2839         uint32_t reserved29;  /* ordinal59 */
2840         uint32_t reserved30;  /* ordinal60 */
2841         uint32_t reserved31;  /* ordinal61 */
2842         uint32_t reserved32;  /* ordinal62 */
2843         uint32_t reserved33;  /* ordinal63 */
2844         uint32_t reserved34;  /* ordinal64 */
2845         uint32_t compute_user_data_0;  /* ordinal65 */
2846         uint32_t compute_user_data_1;  /* ordinal66 */
2847         uint32_t compute_user_data_2;  /* ordinal67 */
2848         uint32_t compute_user_data_3;  /* ordinal68 */
2849         uint32_t compute_user_data_4;  /* ordinal69 */
2850         uint32_t compute_user_data_5;  /* ordinal70 */
2851         uint32_t compute_user_data_6;  /* ordinal71 */
2852         uint32_t compute_user_data_7;  /* ordinal72 */
2853         uint32_t compute_user_data_8;  /* ordinal73 */
2854         uint32_t compute_user_data_9;  /* ordinal74 */
2855         uint32_t compute_user_data_10;  /* ordinal75 */
2856         uint32_t compute_user_data_11;  /* ordinal76 */
2857         uint32_t compute_user_data_12;  /* ordinal77 */
2858         uint32_t compute_user_data_13;  /* ordinal78 */
2859         uint32_t compute_user_data_14;  /* ordinal79 */
2860         uint32_t compute_user_data_15;  /* ordinal80 */
2861         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2862         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2863         uint32_t reserved35;  /* ordinal83 */
2864         uint32_t reserved36;  /* ordinal84 */
2865         uint32_t reserved37;  /* ordinal85 */
2866         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2867         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2868         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2869         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2870         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2871         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2872         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2873         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2874         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2875         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2876         uint32_t reserved38;  /* ordinal96 */
2877         uint32_t reserved39;  /* ordinal97 */
2878         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2879         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2880         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2881         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2882         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2883         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2884         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2885         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2886         uint32_t reserved40;  /* ordinal106 */
2887         uint32_t reserved41;  /* ordinal107 */
2888         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2889         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2890         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2891         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2892         uint32_t reserved42;  /* ordinal112 */
2893         uint32_t reserved43;  /* ordinal113 */
2894         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2895         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2896         uint32_t cp_packet_id_lo;  /* ordinal116 */
2897         uint32_t cp_packet_id_hi;  /* ordinal117 */
2898         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2899         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2900         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2901         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2902         uint32_t gds_save_mask_lo;  /* ordinal122 */
2903         uint32_t gds_save_mask_hi;  /* ordinal123 */
2904         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2905         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2906         uint32_t reserved44;  /* ordinal126 */
2907         uint32_t reserved45;  /* ordinal127 */
2908         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2909         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2910         uint32_t cp_hqd_active;  /* ordinal130 */
2911         uint32_t cp_hqd_vmid;  /* ordinal131 */
2912         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2913         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2914         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2915         uint32_t cp_hqd_quantum;  /* ordinal135 */
2916         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2917         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2918         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2919         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2920         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2921         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2922         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2923         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2924         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2925         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2926         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2927         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2928         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2929         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2930         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2931         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2932         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2933         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2934         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2935         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2936         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2937         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2938         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2939         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2940         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2941         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2942         uint32_t cp_mqd_control;  /* ordinal162 */
2943         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2944         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2945         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2946         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2947         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2948         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2949         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2950         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2951         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2952         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2953         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2954         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2955         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2956         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2957         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2958         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2959         uint32_t cp_hqd_error;  /* ordinal179 */
2960         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2961         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2962         uint32_t reserved46;  /* ordinal182 */
2963         uint32_t reserved47;  /* ordinal183 */
2964         uint32_t reserved48;  /* ordinal184 */
2965         uint32_t reserved49;  /* ordinal185 */
2966         uint32_t reserved50;  /* ordinal186 */
2967         uint32_t reserved51;  /* ordinal187 */
2968         uint32_t reserved52;  /* ordinal188 */
2969         uint32_t reserved53;  /* ordinal189 */
2970         uint32_t reserved54;  /* ordinal190 */
2971         uint32_t reserved55;  /* ordinal191 */
2972         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2973         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2974         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2975         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2976         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2977         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2978         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2979         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2980         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2981         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2982         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2983         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2984         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2985         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2986         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2987         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2988         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2989         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2990         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2991         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2992         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2993         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2994         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2995         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2996         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2997         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2998         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2999         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
3000         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
3001         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
3002         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
3003         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
3004         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
3005         uint32_t reserved56;  /* ordinal225 */
3006         uint32_t reserved57;  /* ordinal226 */
3007         uint32_t reserved58;  /* ordinal227 */
3008         uint32_t set_resources_header;  /* ordinal228 */
3009         uint32_t set_resources_dw1;  /* ordinal229 */
3010         uint32_t set_resources_dw2;  /* ordinal230 */
3011         uint32_t set_resources_dw3;  /* ordinal231 */
3012         uint32_t set_resources_dw4;  /* ordinal232 */
3013         uint32_t set_resources_dw5;  /* ordinal233 */
3014         uint32_t set_resources_dw6;  /* ordinal234 */
3015         uint32_t set_resources_dw7;  /* ordinal235 */
3016         uint32_t reserved59;  /* ordinal236 */
3017         uint32_t reserved60;  /* ordinal237 */
3018         uint32_t reserved61;  /* ordinal238 */
3019         uint32_t reserved62;  /* ordinal239 */
3020         uint32_t reserved63;  /* ordinal240 */
3021         uint32_t reserved64;  /* ordinal241 */
3022         uint32_t reserved65;  /* ordinal242 */
3023         uint32_t reserved66;  /* ordinal243 */
3024         uint32_t reserved67;  /* ordinal244 */
3025         uint32_t reserved68;  /* ordinal245 */
3026         uint32_t reserved69;  /* ordinal246 */
3027         uint32_t reserved70;  /* ordinal247 */
3028         uint32_t reserved71;  /* ordinal248 */
3029         uint32_t reserved72;  /* ordinal249 */
3030         uint32_t reserved73;  /* ordinal250 */
3031         uint32_t reserved74;  /* ordinal251 */
3032         uint32_t reserved75;  /* ordinal252 */
3033         uint32_t reserved76;  /* ordinal253 */
3034         uint32_t reserved77;  /* ordinal254 */
3035         uint32_t reserved78;  /* ordinal255 */
3036
3037         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3038 };
3039
3040 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3041 {
3042         int i, r;
3043
3044         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3045                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3046
3047                 if (ring->mqd_obj) {
3048                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3049                         if (unlikely(r != 0))
3050                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3051
3052                         amdgpu_bo_unpin(ring->mqd_obj);
3053                         amdgpu_bo_unreserve(ring->mqd_obj);
3054
3055                         amdgpu_bo_unref(&ring->mqd_obj);
3056                         ring->mqd_obj = NULL;
3057                 }
3058         }
3059 }
3060
3061 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3062 {
3063         int r, i, j;
3064         u32 tmp;
3065         bool use_doorbell = true;
3066         u64 hqd_gpu_addr;
3067         u64 mqd_gpu_addr;
3068         u64 eop_gpu_addr;
3069         u64 wb_gpu_addr;
3070         u32 *buf;
3071         struct vi_mqd *mqd;
3072
3073         /* init the pipes */
3074         mutex_lock(&adev->srbm_mutex);
3075         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3076                 int me = (i < 4) ? 1 : 2;
3077                 int pipe = (i < 4) ? i : (i - 4);
3078
3079                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3080                 eop_gpu_addr >>= 8;
3081
3082                 vi_srbm_select(adev, me, pipe, 0, 0);
3083
3084                 /* write the EOP addr */
3085                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3086                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3087
3088                 /* set the VMID assigned */
3089                 WREG32(mmCP_HQD_VMID, 0);
3090
3091                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3092                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3093                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3094                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3095                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3096         }
3097         vi_srbm_select(adev, 0, 0, 0, 0);
3098         mutex_unlock(&adev->srbm_mutex);
3099
3100         /* init the queues.  Just two for now. */
3101         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3102                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3103
3104                 if (ring->mqd_obj == NULL) {
3105                         r = amdgpu_bo_create(adev,
3106                                              sizeof(struct vi_mqd),
3107                                              PAGE_SIZE, true,
3108                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3109                                              &ring->mqd_obj);
3110                         if (r) {
3111                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3112                                 return r;
3113                         }
3114                 }
3115
3116                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3117                 if (unlikely(r != 0)) {
3118                         gfx_v8_0_cp_compute_fini(adev);
3119                         return r;
3120                 }
3121                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3122                                   &mqd_gpu_addr);
3123                 if (r) {
3124                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3125                         gfx_v8_0_cp_compute_fini(adev);
3126                         return r;
3127                 }
3128                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3129                 if (r) {
3130                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3131                         gfx_v8_0_cp_compute_fini(adev);
3132                         return r;
3133                 }
3134
3135                 /* init the mqd struct */
3136                 memset(buf, 0, sizeof(struct vi_mqd));
3137
3138                 mqd = (struct vi_mqd *)buf;
3139                 mqd->header = 0xC0310800;
3140                 mqd->compute_pipelinestat_enable = 0x00000001;
3141                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3142                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3143                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3144                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3145                 mqd->compute_misc_reserved = 0x00000003;
3146
3147                 mutex_lock(&adev->srbm_mutex);
3148                 vi_srbm_select(adev, ring->me,
3149                                ring->pipe,
3150                                ring->queue, 0);
3151
3152                 /* disable wptr polling */
3153                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3154                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3155                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3156
3157                 mqd->cp_hqd_eop_base_addr_lo =
3158                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3159                 mqd->cp_hqd_eop_base_addr_hi =
3160                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3161
3162                 /* enable doorbell? */
3163                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3164                 if (use_doorbell) {
3165                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3166                 } else {
3167                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3168                 }
3169                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3170                 mqd->cp_hqd_pq_doorbell_control = tmp;
3171
3172                 /* disable the queue if it's active */
3173                 mqd->cp_hqd_dequeue_request = 0;
3174                 mqd->cp_hqd_pq_rptr = 0;
3175                 mqd->cp_hqd_pq_wptr= 0;
3176                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3177                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3178                         for (j = 0; j < adev->usec_timeout; j++) {
3179                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3180                                         break;
3181                                 udelay(1);
3182                         }
3183                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3184                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3185                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3186                 }
3187
3188                 /* set the pointer to the MQD */
3189                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3190                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3191                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3192                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3193
3194                 /* set MQD vmid to 0 */
3195                 tmp = RREG32(mmCP_MQD_CONTROL);
3196                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3197                 WREG32(mmCP_MQD_CONTROL, tmp);
3198                 mqd->cp_mqd_control = tmp;
3199
3200                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3201                 hqd_gpu_addr = ring->gpu_addr >> 8;
3202                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3203                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3204                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3205                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3206
3207                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3208                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3209                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3210                                     (order_base_2(ring->ring_size / 4) - 1));
3211                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3212                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3213 #ifdef __BIG_ENDIAN
3214                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3215 #endif
3216                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3217                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3218                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3219                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3220                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3221                 mqd->cp_hqd_pq_control = tmp;
3222
3223                 /* set the wb address wether it's enabled or not */
3224                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3225                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3226                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3227                         upper_32_bits(wb_gpu_addr) & 0xffff;
3228                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3229                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3230                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3231                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3232
3233                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3234                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3235                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3236                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3237                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3238                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3239                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3240
3241                 /* enable the doorbell if requested */
3242                 if (use_doorbell) {
3243                         if ((adev->asic_type == CHIP_CARRIZO) ||
3244                             (adev->asic_type == CHIP_FIJI)) {
3245                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3246                                        AMDGPU_DOORBELL_KIQ << 2);
3247                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3248                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3249                         }
3250                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3251                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3252                                             DOORBELL_OFFSET, ring->doorbell_index);
3253                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3254                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3255                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3256                         mqd->cp_hqd_pq_doorbell_control = tmp;
3257
3258                 } else {
3259                         mqd->cp_hqd_pq_doorbell_control = 0;
3260                 }
3261                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3262                        mqd->cp_hqd_pq_doorbell_control);
3263
3264                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3265                 ring->wptr = 0;
3266                 mqd->cp_hqd_pq_wptr = ring->wptr;
3267                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3268                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3269
3270                 /* set the vmid for the queue */
3271                 mqd->cp_hqd_vmid = 0;
3272                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3273
3274                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3275                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3276                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3277                 mqd->cp_hqd_persistent_state = tmp;
3278
3279                 /* activate the queue */
3280                 mqd->cp_hqd_active = 1;
3281                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3282
3283                 vi_srbm_select(adev, 0, 0, 0, 0);
3284                 mutex_unlock(&adev->srbm_mutex);
3285
3286                 amdgpu_bo_kunmap(ring->mqd_obj);
3287                 amdgpu_bo_unreserve(ring->mqd_obj);
3288         }
3289
3290         if (use_doorbell) {
3291                 tmp = RREG32(mmCP_PQ_STATUS);
3292                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3293                 WREG32(mmCP_PQ_STATUS, tmp);
3294         }
3295
3296         r = gfx_v8_0_cp_compute_start(adev);
3297         if (r)
3298                 return r;
3299
3300         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3301                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3302
3303                 ring->ready = true;
3304                 r = amdgpu_ring_test_ring(ring);
3305                 if (r)
3306                         ring->ready = false;
3307         }
3308
3309         return 0;
3310 }
3311
3312 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3313 {
3314         int r;
3315
3316         if (adev->asic_type != CHIP_CARRIZO)
3317                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3318
3319         if (!adev->firmware.smu_load) {
3320                 /* legacy firmware loading */
3321                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3322                 if (r)
3323                         return r;
3324
3325                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3326                 if (r)
3327                         return r;
3328         } else {
3329                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3330                                                 AMDGPU_UCODE_ID_CP_CE);
3331                 if (r)
3332                         return -EINVAL;
3333
3334                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3335                                                 AMDGPU_UCODE_ID_CP_PFP);
3336                 if (r)
3337                         return -EINVAL;
3338
3339                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3340                                                 AMDGPU_UCODE_ID_CP_ME);
3341                 if (r)
3342                         return -EINVAL;
3343
3344                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3345                                                 AMDGPU_UCODE_ID_CP_MEC1);
3346                 if (r)
3347                         return -EINVAL;
3348         }
3349
3350         r = gfx_v8_0_cp_gfx_resume(adev);
3351         if (r)
3352                 return r;
3353
3354         r = gfx_v8_0_cp_compute_resume(adev);
3355         if (r)
3356                 return r;
3357
3358         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3359
3360         return 0;
3361 }
3362
3363 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3364 {
3365         gfx_v8_0_cp_gfx_enable(adev, enable);
3366         gfx_v8_0_cp_compute_enable(adev, enable);
3367 }
3368
3369 static int gfx_v8_0_hw_init(void *handle)
3370 {
3371         int r;
3372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3373
3374         gfx_v8_0_init_golden_registers(adev);
3375
3376         gfx_v8_0_gpu_init(adev);
3377
3378         r = gfx_v8_0_rlc_resume(adev);
3379         if (r)
3380                 return r;
3381
3382         r = gfx_v8_0_cp_resume(adev);
3383         if (r)
3384                 return r;
3385
3386         return r;
3387 }
3388
3389 static int gfx_v8_0_hw_fini(void *handle)
3390 {
3391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3392
3393         gfx_v8_0_cp_enable(adev, false);
3394         gfx_v8_0_rlc_stop(adev);
3395         gfx_v8_0_cp_compute_fini(adev);
3396
3397         return 0;
3398 }
3399
3400 static int gfx_v8_0_suspend(void *handle)
3401 {
3402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403
3404         return gfx_v8_0_hw_fini(adev);
3405 }
3406
3407 static int gfx_v8_0_resume(void *handle)
3408 {
3409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3410
3411         return gfx_v8_0_hw_init(adev);
3412 }
3413
3414 static bool gfx_v8_0_is_idle(void *handle)
3415 {
3416         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3417
3418         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3419                 return false;
3420         else
3421                 return true;
3422 }
3423
3424 static int gfx_v8_0_wait_for_idle(void *handle)
3425 {
3426         unsigned i;
3427         u32 tmp;
3428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3429
3430         for (i = 0; i < adev->usec_timeout; i++) {
3431                 /* read MC_STATUS */
3432                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3433
3434                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3435                         return 0;
3436                 udelay(1);
3437         }
3438         return -ETIMEDOUT;
3439 }
3440
3441 static void gfx_v8_0_print_status(void *handle)
3442 {
3443         int i;
3444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3445
3446         dev_info(adev->dev, "GFX 8.x registers\n");
3447         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3448                  RREG32(mmGRBM_STATUS));
3449         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3450                  RREG32(mmGRBM_STATUS2));
3451         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3452                  RREG32(mmGRBM_STATUS_SE0));
3453         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3454                  RREG32(mmGRBM_STATUS_SE1));
3455         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3456                  RREG32(mmGRBM_STATUS_SE2));
3457         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3458                  RREG32(mmGRBM_STATUS_SE3));
3459         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3460         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3461                  RREG32(mmCP_STALLED_STAT1));
3462         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3463                  RREG32(mmCP_STALLED_STAT2));
3464         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3465                  RREG32(mmCP_STALLED_STAT3));
3466         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3467                  RREG32(mmCP_CPF_BUSY_STAT));
3468         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3469                  RREG32(mmCP_CPF_STALLED_STAT1));
3470         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3471         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3472         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3473                  RREG32(mmCP_CPC_STALLED_STAT1));
3474         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3475
3476         for (i = 0; i < 32; i++) {
3477                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3478                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3479         }
3480         for (i = 0; i < 16; i++) {
3481                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3482                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3483         }
3484         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3485                 dev_info(adev->dev, "  se: %d\n", i);
3486                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3487                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3488                          RREG32(mmPA_SC_RASTER_CONFIG));
3489                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3490                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3491         }
3492         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3493
3494         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3495                  RREG32(mmGB_ADDR_CONFIG));
3496         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3497                  RREG32(mmHDP_ADDR_CONFIG));
3498         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3499                  RREG32(mmDMIF_ADDR_CALC));
3500         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3501                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3502         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3503                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3504         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3505                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3506         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3507                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3508         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3509                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3510
3511         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3512                  RREG32(mmCP_MEQ_THRESHOLDS));
3513         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3514                  RREG32(mmSX_DEBUG_1));
3515         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3516                  RREG32(mmTA_CNTL_AUX));
3517         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3518                  RREG32(mmSPI_CONFIG_CNTL));
3519         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3520                  RREG32(mmSQ_CONFIG));
3521         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3522                  RREG32(mmDB_DEBUG));
3523         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3524                  RREG32(mmDB_DEBUG2));
3525         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3526                  RREG32(mmDB_DEBUG3));
3527         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3528                  RREG32(mmCB_HW_CONTROL));
3529         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3530                  RREG32(mmSPI_CONFIG_CNTL_1));
3531         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3532                  RREG32(mmPA_SC_FIFO_SIZE));
3533         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3534                  RREG32(mmVGT_NUM_INSTANCES));
3535         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3536                  RREG32(mmCP_PERFMON_CNTL));
3537         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3538                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3539         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3540                  RREG32(mmVGT_CACHE_INVALIDATION));
3541         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3542                  RREG32(mmVGT_GS_VERTEX_REUSE));
3543         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3544                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3545         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3546                  RREG32(mmPA_CL_ENHANCE));
3547         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3548                  RREG32(mmPA_SC_ENHANCE));
3549
3550         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3551                  RREG32(mmCP_ME_CNTL));
3552         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3553                  RREG32(mmCP_MAX_CONTEXT));
3554         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3555                  RREG32(mmCP_ENDIAN_SWAP));
3556         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3557                  RREG32(mmCP_DEVICE_ID));
3558
3559         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3560                  RREG32(mmCP_SEM_WAIT_TIMER));
3561
3562         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3563                  RREG32(mmCP_RB_WPTR_DELAY));
3564         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3565                  RREG32(mmCP_RB_VMID));
3566         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3567                  RREG32(mmCP_RB0_CNTL));
3568         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3569                  RREG32(mmCP_RB0_WPTR));
3570         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3571                  RREG32(mmCP_RB0_RPTR_ADDR));
3572         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3573                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3574         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3575                  RREG32(mmCP_RB0_CNTL));
3576         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3577                  RREG32(mmCP_RB0_BASE));
3578         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3579                  RREG32(mmCP_RB0_BASE_HI));
3580         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3581                  RREG32(mmCP_MEC_CNTL));
3582         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3583                  RREG32(mmCP_CPF_DEBUG));
3584
3585         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3586                  RREG32(mmSCRATCH_ADDR));
3587         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3588                  RREG32(mmSCRATCH_UMSK));
3589
3590         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3591                  RREG32(mmCP_INT_CNTL_RING0));
3592         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3593                  RREG32(mmRLC_LB_CNTL));
3594         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3595                  RREG32(mmRLC_CNTL));
3596         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3597                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3598         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3599                  RREG32(mmRLC_LB_CNTR_INIT));
3600         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3601                  RREG32(mmRLC_LB_CNTR_MAX));
3602         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3603                  RREG32(mmRLC_LB_INIT_CU_MASK));
3604         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3605                  RREG32(mmRLC_LB_PARAMS));
3606         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3607                  RREG32(mmRLC_LB_CNTL));
3608         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3609                  RREG32(mmRLC_MC_CNTL));
3610         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3611                  RREG32(mmRLC_UCODE_CNTL));
3612
3613         mutex_lock(&adev->srbm_mutex);
3614         for (i = 0; i < 16; i++) {
3615                 vi_srbm_select(adev, 0, 0, 0, i);
3616                 dev_info(adev->dev, "  VM %d:\n", i);
3617                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3618                          RREG32(mmSH_MEM_CONFIG));
3619                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3620                          RREG32(mmSH_MEM_APE1_BASE));
3621                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3622                          RREG32(mmSH_MEM_APE1_LIMIT));
3623                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3624                          RREG32(mmSH_MEM_BASES));
3625         }
3626         vi_srbm_select(adev, 0, 0, 0, 0);
3627         mutex_unlock(&adev->srbm_mutex);
3628 }
3629
3630 static int gfx_v8_0_soft_reset(void *handle)
3631 {
3632         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3633         u32 tmp;
3634         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3635
3636         /* GRBM_STATUS */
3637         tmp = RREG32(mmGRBM_STATUS);
3638         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3639                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3640                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3641                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3642                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3643                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3644                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3645                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3646                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3647                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3648         }
3649
3650         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3651                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3652                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3653                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3654                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3655         }
3656
3657         /* GRBM_STATUS2 */
3658         tmp = RREG32(mmGRBM_STATUS2);
3659         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3660                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3661                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3662
3663         /* SRBM_STATUS */
3664         tmp = RREG32(mmSRBM_STATUS);
3665         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3666                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3667                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3668
3669         if (grbm_soft_reset || srbm_soft_reset) {
3670                 gfx_v8_0_print_status((void *)adev);
3671                 /* stop the rlc */
3672                 gfx_v8_0_rlc_stop(adev);
3673
3674                 /* Disable GFX parsing/prefetching */
3675                 gfx_v8_0_cp_gfx_enable(adev, false);
3676
3677                 /* Disable MEC parsing/prefetching */
3678                 /* XXX todo */
3679
3680                 if (grbm_soft_reset) {
3681                         tmp = RREG32(mmGRBM_SOFT_RESET);
3682                         tmp |= grbm_soft_reset;
3683                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3684                         WREG32(mmGRBM_SOFT_RESET, tmp);
3685                         tmp = RREG32(mmGRBM_SOFT_RESET);
3686
3687                         udelay(50);
3688
3689                         tmp &= ~grbm_soft_reset;
3690                         WREG32(mmGRBM_SOFT_RESET, tmp);
3691                         tmp = RREG32(mmGRBM_SOFT_RESET);
3692                 }
3693
3694                 if (srbm_soft_reset) {
3695                         tmp = RREG32(mmSRBM_SOFT_RESET);
3696                         tmp |= srbm_soft_reset;
3697                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3698                         WREG32(mmSRBM_SOFT_RESET, tmp);
3699                         tmp = RREG32(mmSRBM_SOFT_RESET);
3700
3701                         udelay(50);
3702
3703                         tmp &= ~srbm_soft_reset;
3704                         WREG32(mmSRBM_SOFT_RESET, tmp);
3705                         tmp = RREG32(mmSRBM_SOFT_RESET);
3706                 }
3707                 /* Wait a little for things to settle down */
3708                 udelay(50);
3709                 gfx_v8_0_print_status((void *)adev);
3710         }
3711         return 0;
3712 }
3713
3714 /**
3715  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3716  *
3717  * @adev: amdgpu_device pointer
3718  *
3719  * Fetches a GPU clock counter snapshot.
3720  * Returns the 64 bit clock counter snapshot.
3721  */
3722 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3723 {
3724         uint64_t clock;
3725
3726         mutex_lock(&adev->gfx.gpu_clock_mutex);
3727         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3728         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3729                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3730         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3731         return clock;
3732 }
3733
3734 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3735                                           uint32_t vmid,
3736                                           uint32_t gds_base, uint32_t gds_size,
3737                                           uint32_t gws_base, uint32_t gws_size,
3738                                           uint32_t oa_base, uint32_t oa_size)
3739 {
3740         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3741         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3742
3743         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3744         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3745
3746         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3747         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3748
3749         /* GDS Base */
3750         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3752                                 WRITE_DATA_DST_SEL(0)));
3753         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3754         amdgpu_ring_write(ring, 0);
3755         amdgpu_ring_write(ring, gds_base);
3756
3757         /* GDS Size */
3758         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3759         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3760                                 WRITE_DATA_DST_SEL(0)));
3761         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3762         amdgpu_ring_write(ring, 0);
3763         amdgpu_ring_write(ring, gds_size);
3764
3765         /* GWS */
3766         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3767         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3768                                 WRITE_DATA_DST_SEL(0)));
3769         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3770         amdgpu_ring_write(ring, 0);
3771         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3772
3773         /* OA */
3774         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3775         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3776                                 WRITE_DATA_DST_SEL(0)));
3777         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3778         amdgpu_ring_write(ring, 0);
3779         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3780 }
3781
3782 static int gfx_v8_0_early_init(void *handle)
3783 {
3784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3785
3786         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3787         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3788         gfx_v8_0_set_ring_funcs(adev);
3789         gfx_v8_0_set_irq_funcs(adev);
3790         gfx_v8_0_set_gds_init(adev);
3791
3792         return 0;
3793 }
3794
3795 static int gfx_v8_0_set_powergating_state(void *handle,
3796                                           enum amd_powergating_state state)
3797 {
3798         return 0;
3799 }
3800
3801 static int gfx_v8_0_set_clockgating_state(void *handle,
3802                                           enum amd_clockgating_state state)
3803 {
3804         return 0;
3805 }
3806
3807 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3808 {
3809         u32 rptr;
3810
3811         rptr = ring->adev->wb.wb[ring->rptr_offs];
3812
3813         return rptr;
3814 }
3815
3816 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3817 {
3818         struct amdgpu_device *adev = ring->adev;
3819         u32 wptr;
3820
3821         if (ring->use_doorbell)
3822                 /* XXX check if swapping is necessary on BE */
3823                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3824         else
3825                 wptr = RREG32(mmCP_RB0_WPTR);
3826
3827         return wptr;
3828 }
3829
3830 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3831 {
3832         struct amdgpu_device *adev = ring->adev;
3833
3834         if (ring->use_doorbell) {
3835                 /* XXX check if swapping is necessary on BE */
3836                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3837                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3838         } else {
3839                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3840                 (void)RREG32(mmCP_RB0_WPTR);
3841         }
3842 }
3843
3844 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3845 {
3846         u32 ref_and_mask, reg_mem_engine;
3847
3848         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3849                 switch (ring->me) {
3850                 case 1:
3851                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3852                         break;
3853                 case 2:
3854                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3855                         break;
3856                 default:
3857                         return;
3858                 }
3859                 reg_mem_engine = 0;
3860         } else {
3861                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3862                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3863         }
3864
3865         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3866         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3867                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3868                                  reg_mem_engine));
3869         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3870         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3871         amdgpu_ring_write(ring, ref_and_mask);
3872         amdgpu_ring_write(ring, ref_and_mask);
3873         amdgpu_ring_write(ring, 0x20); /* poll interval */
3874 }
3875
3876 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3877                                   struct amdgpu_ib *ib)
3878 {
3879         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3880         u32 header, control = 0;
3881         u32 next_rptr = ring->wptr + 5;
3882
3883         /* drop the CE preamble IB for the same context */
3884         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3885                 return;
3886
3887         if (need_ctx_switch)
3888                 next_rptr += 2;
3889
3890         next_rptr += 4;
3891         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3892         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3893         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3894         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3895         amdgpu_ring_write(ring, next_rptr);
3896
3897         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3898         if (need_ctx_switch) {
3899                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3900                 amdgpu_ring_write(ring, 0);
3901         }
3902
3903         if (ib->flags & AMDGPU_IB_FLAG_CE)
3904                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3905         else
3906                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3907
3908         control |= ib->length_dw |
3909                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3910
3911         amdgpu_ring_write(ring, header);
3912         amdgpu_ring_write(ring,
3913 #ifdef __BIG_ENDIAN
3914                           (2 << 0) |
3915 #endif
3916                           (ib->gpu_addr & 0xFFFFFFFC));
3917         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3918         amdgpu_ring_write(ring, control);
3919 }
3920
3921 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3922                                   struct amdgpu_ib *ib)
3923 {
3924         u32 header, control = 0;
3925         u32 next_rptr = ring->wptr + 5;
3926
3927         control |= INDIRECT_BUFFER_VALID;
3928
3929         next_rptr += 4;
3930         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3931         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3932         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3933         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3934         amdgpu_ring_write(ring, next_rptr);
3935
3936         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3937
3938         control |= ib->length_dw |
3939                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3940
3941         amdgpu_ring_write(ring, header);
3942         amdgpu_ring_write(ring,
3943 #ifdef __BIG_ENDIAN
3944                                           (2 << 0) |
3945 #endif
3946                                           (ib->gpu_addr & 0xFFFFFFFC));
3947         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3948         amdgpu_ring_write(ring, control);
3949 }
3950
3951 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3952                                          u64 seq, unsigned flags)
3953 {
3954         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3955         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3956
3957         /* EVENT_WRITE_EOP - flush caches, send int */
3958         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3959         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3960                                  EOP_TC_ACTION_EN |
3961                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3962                                  EVENT_INDEX(5)));
3963         amdgpu_ring_write(ring, addr & 0xfffffffc);
3964         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3965                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3966         amdgpu_ring_write(ring, lower_32_bits(seq));
3967         amdgpu_ring_write(ring, upper_32_bits(seq));
3968 }
3969
3970 /**
3971  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3972  *
3973  * @ring: amdgpu ring buffer object
3974  * @semaphore: amdgpu semaphore object
3975  * @emit_wait: Is this a sempahore wait?
3976  *
3977  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3978  * from running ahead of semaphore waits.
3979  */
3980 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3981                                          struct amdgpu_semaphore *semaphore,
3982                                          bool emit_wait)
3983 {
3984         uint64_t addr = semaphore->gpu_addr;
3985         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3986
3987         if (ring->adev->asic_type == CHIP_TOPAZ ||
3988             ring->adev->asic_type == CHIP_TONGA ||
3989             ring->adev->asic_type == CHIP_FIJI)
3990                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3991                 return false;
3992         else {
3993                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3994                 amdgpu_ring_write(ring, lower_32_bits(addr));
3995                 amdgpu_ring_write(ring, upper_32_bits(addr));
3996                 amdgpu_ring_write(ring, sel);
3997         }
3998
3999         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
4000                 /* Prevent the PFP from running ahead of the semaphore wait */
4001                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4002                 amdgpu_ring_write(ring, 0x0);
4003         }
4004
4005         return true;
4006 }
4007
4008 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
4009 {
4010         struct amdgpu_device *adev = ring->adev;
4011         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
4012
4013         /* instruct DE to set a magic number */
4014         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4015         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4016                                                          WRITE_DATA_DST_SEL(5)));
4017         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4018         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4019         amdgpu_ring_write(ring, 1);
4020
4021         /* let CE wait till condition satisfied */
4022         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4023         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4024                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4025                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
4026                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
4027         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4028         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4029         amdgpu_ring_write(ring, 1);
4030         amdgpu_ring_write(ring, 0xffffffff);
4031         amdgpu_ring_write(ring, 4); /* poll interval */
4032
4033         /* instruct CE to reset wb of ce_sync to zero */
4034         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4035         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4036                                                          WRITE_DATA_DST_SEL(5) |
4037                                                          WR_CONFIRM));
4038         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4039         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4040         amdgpu_ring_write(ring, 0);
4041 }
4042
4043 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4044                                         unsigned vm_id, uint64_t pd_addr)
4045 {
4046         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4047
4048         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4049         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4050                                  WRITE_DATA_DST_SEL(0)));
4051         if (vm_id < 8) {
4052                 amdgpu_ring_write(ring,
4053                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4054         } else {
4055                 amdgpu_ring_write(ring,
4056                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4057         }
4058         amdgpu_ring_write(ring, 0);
4059         amdgpu_ring_write(ring, pd_addr >> 12);
4060
4061         /* bits 0-15 are the VM contexts0-15 */
4062         /* invalidate the cache */
4063         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4064         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4065                                  WRITE_DATA_DST_SEL(0)));
4066         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4067         amdgpu_ring_write(ring, 0);
4068         amdgpu_ring_write(ring, 1 << vm_id);
4069
4070         /* wait for the invalidate to complete */
4071         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4072         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4073                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4074                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4075         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4076         amdgpu_ring_write(ring, 0);
4077         amdgpu_ring_write(ring, 0); /* ref */
4078         amdgpu_ring_write(ring, 0); /* mask */
4079         amdgpu_ring_write(ring, 0x20); /* poll interval */
4080
4081         /* compute doesn't have PFP */
4082         if (usepfp) {
4083                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4084                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4085                 amdgpu_ring_write(ring, 0x0);
4086
4087                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4088                 gfx_v8_0_ce_sync_me(ring);
4089         }
4090 }
4091
4092 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4093 {
4094         if (gfx_v8_0_is_idle(ring->adev)) {
4095                 amdgpu_ring_lockup_update(ring);
4096                 return false;
4097         }
4098         return amdgpu_ring_test_lockup(ring);
4099 }
4100
4101 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4102 {
4103         return ring->adev->wb.wb[ring->rptr_offs];
4104 }
4105
4106 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4107 {
4108         return ring->adev->wb.wb[ring->wptr_offs];
4109 }
4110
4111 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4112 {
4113         struct amdgpu_device *adev = ring->adev;
4114
4115         /* XXX check if swapping is necessary on BE */
4116         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4117         WDOORBELL32(ring->doorbell_index, ring->wptr);
4118 }
4119
4120 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4121                                              u64 addr, u64 seq,
4122                                              unsigned flags)
4123 {
4124         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4125         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4126
4127         /* RELEASE_MEM - flush caches, send int */
4128         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4129         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4130                                  EOP_TC_ACTION_EN |
4131                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4132                                  EVENT_INDEX(5)));
4133         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4134         amdgpu_ring_write(ring, addr & 0xfffffffc);
4135         amdgpu_ring_write(ring, upper_32_bits(addr));
4136         amdgpu_ring_write(ring, lower_32_bits(seq));
4137         amdgpu_ring_write(ring, upper_32_bits(seq));
4138 }
4139
4140 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4141                                                  enum amdgpu_interrupt_state state)
4142 {
4143         u32 cp_int_cntl;
4144
4145         switch (state) {
4146         case AMDGPU_IRQ_STATE_DISABLE:
4147                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4148                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4149                                             TIME_STAMP_INT_ENABLE, 0);
4150                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4151                 break;
4152         case AMDGPU_IRQ_STATE_ENABLE:
4153                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4154                 cp_int_cntl =
4155                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4156                                       TIME_STAMP_INT_ENABLE, 1);
4157                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4158                 break;
4159         default:
4160                 break;
4161         }
4162 }
4163
4164 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4165                                                      int me, int pipe,
4166                                                      enum amdgpu_interrupt_state state)
4167 {
4168         u32 mec_int_cntl, mec_int_cntl_reg;
4169
4170         /*
4171          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4172          * handles the setting of interrupts for this specific pipe. All other
4173          * pipes' interrupts are set by amdkfd.
4174          */
4175
4176         if (me == 1) {
4177                 switch (pipe) {
4178                 case 0:
4179                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4180                         break;
4181                 default:
4182                         DRM_DEBUG("invalid pipe %d\n", pipe);
4183                         return;
4184                 }
4185         } else {
4186                 DRM_DEBUG("invalid me %d\n", me);
4187                 return;
4188         }
4189
4190         switch (state) {
4191         case AMDGPU_IRQ_STATE_DISABLE:
4192                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4193                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4194                                              TIME_STAMP_INT_ENABLE, 0);
4195                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4196                 break;
4197         case AMDGPU_IRQ_STATE_ENABLE:
4198                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4199                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4200                                              TIME_STAMP_INT_ENABLE, 1);
4201                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4202                 break;
4203         default:
4204                 break;
4205         }
4206 }
4207
4208 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4209                                              struct amdgpu_irq_src *source,
4210                                              unsigned type,
4211                                              enum amdgpu_interrupt_state state)
4212 {
4213         u32 cp_int_cntl;
4214
4215         switch (state) {
4216         case AMDGPU_IRQ_STATE_DISABLE:
4217                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4218                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4219                                             PRIV_REG_INT_ENABLE, 0);
4220                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4221                 break;
4222         case AMDGPU_IRQ_STATE_ENABLE:
4223                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4224                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4225                                             PRIV_REG_INT_ENABLE, 0);
4226                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4227                 break;
4228         default:
4229                 break;
4230         }
4231
4232         return 0;
4233 }
4234
4235 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4236                                               struct amdgpu_irq_src *source,
4237                                               unsigned type,
4238                                               enum amdgpu_interrupt_state state)
4239 {
4240         u32 cp_int_cntl;
4241
4242         switch (state) {
4243         case AMDGPU_IRQ_STATE_DISABLE:
4244                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4245                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4246                                             PRIV_INSTR_INT_ENABLE, 0);
4247                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4248                 break;
4249         case AMDGPU_IRQ_STATE_ENABLE:
4250                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4251                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4252                                             PRIV_INSTR_INT_ENABLE, 1);
4253                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4254                 break;
4255         default:
4256                 break;
4257         }
4258
4259         return 0;
4260 }
4261
4262 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4263                                             struct amdgpu_irq_src *src,
4264                                             unsigned type,
4265                                             enum amdgpu_interrupt_state state)
4266 {
4267         switch (type) {
4268         case AMDGPU_CP_IRQ_GFX_EOP:
4269                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4270                 break;
4271         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4272                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4273                 break;
4274         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4275                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4276                 break;
4277         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4278                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4279                 break;
4280         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4281                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4282                 break;
4283         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4284                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4285                 break;
4286         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4287                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4288                 break;
4289         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4290                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4291                 break;
4292         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4293                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4294                 break;
4295         default:
4296                 break;
4297         }
4298         return 0;
4299 }
4300
4301 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4302                             struct amdgpu_irq_src *source,
4303                             struct amdgpu_iv_entry *entry)
4304 {
4305         int i;
4306         u8 me_id, pipe_id, queue_id;
4307         struct amdgpu_ring *ring;
4308
4309         DRM_DEBUG("IH: CP EOP\n");
4310         me_id = (entry->ring_id & 0x0c) >> 2;
4311         pipe_id = (entry->ring_id & 0x03) >> 0;
4312         queue_id = (entry->ring_id & 0x70) >> 4;
4313
4314         switch (me_id) {
4315         case 0:
4316                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4317                 break;
4318         case 1:
4319         case 2:
4320                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4321                         ring = &adev->gfx.compute_ring[i];
4322                         /* Per-queue interrupt is supported for MEC starting from VI.
4323                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4324                           */
4325                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4326                                 amdgpu_fence_process(ring);
4327                 }
4328                 break;
4329         }
4330         return 0;
4331 }
4332
4333 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4334                                  struct amdgpu_irq_src *source,
4335                                  struct amdgpu_iv_entry *entry)
4336 {
4337         DRM_ERROR("Illegal register access in command stream\n");
4338         schedule_work(&adev->reset_work);
4339         return 0;
4340 }
4341
4342 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4343                                   struct amdgpu_irq_src *source,
4344                                   struct amdgpu_iv_entry *entry)
4345 {
4346         DRM_ERROR("Illegal instruction in command stream\n");
4347         schedule_work(&adev->reset_work);
4348         return 0;
4349 }
4350
4351 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4352         .early_init = gfx_v8_0_early_init,
4353         .late_init = NULL,
4354         .sw_init = gfx_v8_0_sw_init,
4355         .sw_fini = gfx_v8_0_sw_fini,
4356         .hw_init = gfx_v8_0_hw_init,
4357         .hw_fini = gfx_v8_0_hw_fini,
4358         .suspend = gfx_v8_0_suspend,
4359         .resume = gfx_v8_0_resume,
4360         .is_idle = gfx_v8_0_is_idle,
4361         .wait_for_idle = gfx_v8_0_wait_for_idle,
4362         .soft_reset = gfx_v8_0_soft_reset,
4363         .print_status = gfx_v8_0_print_status,
4364         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4365         .set_powergating_state = gfx_v8_0_set_powergating_state,
4366 };
4367
4368 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4369         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4370         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4371         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4372         .parse_cs = NULL,
4373         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4374         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4375         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4376         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4377         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4378         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4379         .test_ring = gfx_v8_0_ring_test_ring,
4380         .test_ib = gfx_v8_0_ring_test_ib,
4381         .is_lockup = gfx_v8_0_ring_is_lockup,
4382         .insert_nop = amdgpu_ring_insert_nop,
4383 };
4384
4385 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4386         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4387         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4388         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4389         .parse_cs = NULL,
4390         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4391         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4392         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4393         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4394         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4395         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4396         .test_ring = gfx_v8_0_ring_test_ring,
4397         .test_ib = gfx_v8_0_ring_test_ib,
4398         .is_lockup = gfx_v8_0_ring_is_lockup,
4399         .insert_nop = amdgpu_ring_insert_nop,
4400 };
4401
4402 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4403 {
4404         int i;
4405
4406         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4407                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4408
4409         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4410                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4411 }
4412
4413 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4414         .set = gfx_v8_0_set_eop_interrupt_state,
4415         .process = gfx_v8_0_eop_irq,
4416 };
4417
4418 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4419         .set = gfx_v8_0_set_priv_reg_fault_state,
4420         .process = gfx_v8_0_priv_reg_irq,
4421 };
4422
4423 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4424         .set = gfx_v8_0_set_priv_inst_fault_state,
4425         .process = gfx_v8_0_priv_inst_irq,
4426 };
4427
4428 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4429 {
4430         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4431         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4432
4433         adev->gfx.priv_reg_irq.num_types = 1;
4434         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4435
4436         adev->gfx.priv_inst_irq.num_types = 1;
4437         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4438 }
4439
4440 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4441 {
4442         /* init asci gds info */
4443         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4444         adev->gds.gws.total_size = 64;
4445         adev->gds.oa.total_size = 16;
4446
4447         if (adev->gds.mem.total_size == 64 * 1024) {
4448                 adev->gds.mem.gfx_partition_size = 4096;
4449                 adev->gds.mem.cs_partition_size = 4096;
4450
4451                 adev->gds.gws.gfx_partition_size = 4;
4452                 adev->gds.gws.cs_partition_size = 4;
4453
4454                 adev->gds.oa.gfx_partition_size = 4;
4455                 adev->gds.oa.cs_partition_size = 1;
4456         } else {
4457                 adev->gds.mem.gfx_partition_size = 1024;
4458                 adev->gds.mem.cs_partition_size = 1024;
4459
4460                 adev->gds.gws.gfx_partition_size = 16;
4461                 adev->gds.gws.cs_partition_size = 16;
4462
4463                 adev->gds.oa.gfx_partition_size = 4;
4464                 adev->gds.oa.cs_partition_size = 4;
4465         }
4466 }
4467
4468 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4469                 u32 se, u32 sh)
4470 {
4471         u32 mask = 0, tmp, tmp1;
4472         int i;
4473
4474         gfx_v8_0_select_se_sh(adev, se, sh);
4475         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4476         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4477         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4478
4479         tmp &= 0xffff0000;
4480
4481         tmp |= tmp1;
4482         tmp >>= 16;
4483
4484         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4485                 mask <<= 1;
4486                 mask |= 1;
4487         }
4488
4489         return (~tmp) & mask;
4490 }
4491
4492 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4493                                                  struct amdgpu_cu_info *cu_info)
4494 {
4495         int i, j, k, counter, active_cu_number = 0;
4496         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4497
4498         if (!adev || !cu_info)
4499                 return -EINVAL;
4500
4501         mutex_lock(&adev->grbm_idx_mutex);
4502         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4503                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4504                         mask = 1;
4505                         ao_bitmap = 0;
4506                         counter = 0;
4507                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4508                         cu_info->bitmap[i][j] = bitmap;
4509
4510                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4511                                 if (bitmap & mask) {
4512                                         if (counter < 2)
4513                                                 ao_bitmap |= mask;
4514                                         counter ++;
4515                                 }
4516                                 mask <<= 1;
4517                         }
4518                         active_cu_number += counter;
4519                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4520                 }
4521         }
4522
4523         cu_info->number = active_cu_number;
4524         cu_info->ao_cu_mask = ao_cu_mask;
4525         mutex_unlock(&adev->grbm_idx_mutex);
4526         return 0;
4527 }