2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
62 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
88 struct list_head *head)
90 struct amdgpu_bo_list_entry *list;
93 list = drm_malloc_ab(vm->max_pde_used + 2,
94 sizeof(struct amdgpu_bo_list_entry));
99 /* add the vm page table to the list */
100 list[0].robj = vm->page_directory;
101 list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
102 list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
103 list[0].priority = 0;
104 list[0].tv.bo = &vm->page_directory->tbo;
105 list[0].tv.shared = true;
106 list_add(&list[0].tv.head, head);
108 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
109 if (!vm->page_tables[i].bo)
112 list[idx].robj = vm->page_tables[i].bo;
113 list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
114 list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
115 list[idx].priority = 0;
116 list[idx].tv.bo = &list[idx].robj->tbo;
117 list[idx].tv.shared = true;
118 list_add(&list[idx++].tv.head, head);
125 * amdgpu_vm_grab_id - allocate the next free VMID
127 * @vm: vm to allocate id for
128 * @ring: ring we want to submit job to
129 * @sync: sync object where we add dependencies
131 * Allocate an id for the vm, adding fences to the sync obj as necessary.
133 * Global mutex must be locked!
135 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
136 struct amdgpu_sync *sync)
138 struct fence *best[AMDGPU_MAX_RINGS] = {};
139 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
140 struct amdgpu_device *adev = ring->adev;
142 unsigned choices[2] = {};
145 /* check if the id is still valid */
147 unsigned id = vm_id->id;
150 owner = atomic_long_read(&adev->vm_manager.ids[id].owner);
151 if (owner == (long)vm) {
152 trace_amdgpu_vm_grab_id(vm_id->id, ring->idx);
157 /* we definately need to flush */
158 vm_id->pd_gpu_addr = ~0ll;
160 /* skip over VMID 0, since it is the system VM */
161 for (i = 1; i < adev->vm_manager.nvm; ++i) {
162 struct fence *fence = adev->vm_manager.ids[i].active;
163 struct amdgpu_ring *fring;
166 /* found a free one */
168 trace_amdgpu_vm_grab_id(i, ring->idx);
172 fring = amdgpu_ring_from_fence(fence);
173 if (best[fring->idx] == NULL ||
174 fence_is_later(best[fring->idx], fence)) {
175 best[fring->idx] = fence;
176 choices[fring == ring ? 0 : 1] = i;
180 for (i = 0; i < 2; ++i) {
184 fence = adev->vm_manager.ids[choices[i]].active;
185 vm_id->id = choices[i];
187 trace_amdgpu_vm_grab_id(choices[i], ring->idx);
188 return amdgpu_sync_fence(ring->adev, sync, fence);
192 /* should never happen */
198 * amdgpu_vm_flush - hardware flush the vm
200 * @ring: ring to use for flush
201 * @vm: vm we want to flush
202 * @updates: last vm update that we waited for
204 * Flush the vm (cayman+).
206 * Global and local mutex must be locked!
208 void amdgpu_vm_flush(struct amdgpu_ring *ring,
209 struct amdgpu_vm *vm,
210 struct fence *updates)
212 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
213 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
214 struct fence *flushed_updates = vm_id->flushed_updates;
217 if (!flushed_updates)
222 is_later = fence_is_later(updates, flushed_updates);
224 if (pd_addr != vm_id->pd_gpu_addr || is_later) {
225 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
227 vm_id->flushed_updates = fence_get(updates);
228 fence_put(flushed_updates);
230 vm_id->pd_gpu_addr = pd_addr;
231 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
236 * amdgpu_vm_fence - remember fence for vm
238 * @adev: amdgpu_device pointer
239 * @vm: vm we want to fence
240 * @fence: fence to remember
242 * Fence the vm (cayman+).
243 * Set the fence used to protect page table and id.
245 * Global and local mutex must be locked!
247 void amdgpu_vm_fence(struct amdgpu_device *adev,
248 struct amdgpu_vm *vm,
251 struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence);
252 unsigned vm_id = vm->ids[ring->idx].id;
254 fence_put(adev->vm_manager.ids[vm_id].active);
255 adev->vm_manager.ids[vm_id].active = fence_get(fence);
256 atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm);
260 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
263 * @bo: requested buffer object
265 * Find @bo inside the requested vm (cayman+).
266 * Search inside the @bos vm list for the requested vm
267 * Returns the found bo_va or NULL if none is found
269 * Object has to be reserved!
271 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
272 struct amdgpu_bo *bo)
274 struct amdgpu_bo_va *bo_va;
276 list_for_each_entry(bo_va, &bo->va, bo_list) {
277 if (bo_va->vm == vm) {
285 * amdgpu_vm_update_pages - helper to call the right asic function
287 * @adev: amdgpu_device pointer
288 * @ib: indirect buffer to fill with commands
289 * @pe: addr of the page entry
290 * @addr: dst addr to write into pe
291 * @count: number of page entries to update
292 * @incr: increase next addr by incr bytes
293 * @flags: hw access flags
294 * @gtt_flags: GTT hw access flags
296 * Traces the parameters and calls the right asic functions
297 * to setup the page table using the DMA.
299 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
300 struct amdgpu_ib *ib,
301 uint64_t pe, uint64_t addr,
302 unsigned count, uint32_t incr,
303 uint32_t flags, uint32_t gtt_flags)
305 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
307 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
308 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
309 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
311 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
312 amdgpu_vm_write_pte(adev, ib, pe, addr,
316 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
321 int amdgpu_vm_free_job(struct amdgpu_job *job)
324 for (i = 0; i < job->num_ibs; i++)
325 amdgpu_ib_free(job->adev, &job->ibs[i]);
331 * amdgpu_vm_clear_bo - initially clear the page dir/table
333 * @adev: amdgpu_device pointer
336 * need to reserve bo first before calling it.
338 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
339 struct amdgpu_bo *bo)
341 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
342 struct fence *fence = NULL;
343 struct amdgpu_ib *ib;
348 r = reservation_object_reserve_shared(bo->tbo.resv);
352 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
356 addr = amdgpu_bo_gpu_offset(bo);
357 entries = amdgpu_bo_size(bo) / 8;
359 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
363 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
369 amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
370 amdgpu_vm_pad_ib(adev, ib);
371 WARN_ON(ib->length_dw > 64);
372 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
374 AMDGPU_FENCE_OWNER_VM,
377 amdgpu_bo_fence(bo, fence, true);
379 if (amdgpu_enable_scheduler)
383 amdgpu_ib_free(adev, ib);
391 * amdgpu_vm_map_gart - get the physical address of a gart page
393 * @adev: amdgpu_device pointer
394 * @addr: the unmapped addr
396 * Look up the physical address of the page that the pte resolves
398 * Returns the physical address of the page.
400 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
404 /* page table offset */
405 result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
407 /* in case cpu page size != gpu page size*/
408 result |= addr & (~PAGE_MASK);
414 * amdgpu_vm_update_pdes - make sure that page directory is valid
416 * @adev: amdgpu_device pointer
418 * @start: start of GPU address range
419 * @end: end of GPU address range
421 * Allocates new page tables if necessary
422 * and updates the page directory (cayman+).
423 * Returns 0 for success, error for failure.
425 * Global and local mutex must be locked!
427 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
428 struct amdgpu_vm *vm)
430 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
431 struct amdgpu_bo *pd = vm->page_directory;
432 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
433 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
434 uint64_t last_pde = ~0, last_pt = ~0;
435 unsigned count = 0, pt_idx, ndw;
436 struct amdgpu_ib *ib;
437 struct fence *fence = NULL;
444 /* assume the worst case */
445 ndw += vm->max_pde_used * 6;
447 /* update too big for an IB */
451 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
455 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
462 /* walk over the address space and update the page directory */
463 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
464 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
470 pt = amdgpu_bo_gpu_offset(bo);
471 if (vm->page_tables[pt_idx].addr == pt)
473 vm->page_tables[pt_idx].addr = pt;
475 pde = pd_addr + pt_idx * 8;
476 if (((last_pde + 8 * count) != pde) ||
477 ((last_pt + incr * count) != pt)) {
480 amdgpu_vm_update_pages(adev, ib, last_pde,
481 last_pt, count, incr,
482 AMDGPU_PTE_VALID, 0);
494 amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
495 incr, AMDGPU_PTE_VALID, 0);
497 if (ib->length_dw != 0) {
498 amdgpu_vm_pad_ib(adev, ib);
499 amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
500 WARN_ON(ib->length_dw > ndw);
501 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
503 AMDGPU_FENCE_OWNER_VM,
508 amdgpu_bo_fence(pd, fence, true);
509 fence_put(vm->page_directory_fence);
510 vm->page_directory_fence = fence_get(fence);
514 if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
515 amdgpu_ib_free(adev, ib);
522 amdgpu_ib_free(adev, ib);
528 * amdgpu_vm_frag_ptes - add fragment information to PTEs
530 * @adev: amdgpu_device pointer
531 * @ib: IB for the update
532 * @pe_start: first PTE to handle
533 * @pe_end: last PTE to handle
534 * @addr: addr those PTEs should point to
535 * @flags: hw mapping flags
536 * @gtt_flags: GTT hw mapping flags
538 * Global and local mutex must be locked!
540 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
541 struct amdgpu_ib *ib,
542 uint64_t pe_start, uint64_t pe_end,
543 uint64_t addr, uint32_t flags,
547 * The MC L1 TLB supports variable sized pages, based on a fragment
548 * field in the PTE. When this field is set to a non-zero value, page
549 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
550 * flags are considered valid for all PTEs within the fragment range
551 * and corresponding mappings are assumed to be physically contiguous.
553 * The L1 TLB can store a single PTE for the whole fragment,
554 * significantly increasing the space available for translation
555 * caching. This leads to large improvements in throughput when the
556 * TLB is under pressure.
558 * The L2 TLB distributes small and large fragments into two
559 * asymmetric partitions. The large fragment cache is significantly
560 * larger. Thus, we try to use large fragments wherever possible.
561 * Userspace can support this by aligning virtual base address and
562 * allocation size to the fragment size.
565 /* SI and newer are optimized for 64KB */
566 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
567 uint64_t frag_align = 0x80;
569 uint64_t frag_start = ALIGN(pe_start, frag_align);
570 uint64_t frag_end = pe_end & ~(frag_align - 1);
574 /* system pages are non continuously */
575 if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
576 (frag_start >= frag_end)) {
578 count = (pe_end - pe_start) / 8;
579 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
580 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
584 /* handle the 4K area at the beginning */
585 if (pe_start != frag_start) {
586 count = (frag_start - pe_start) / 8;
587 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
588 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
589 addr += AMDGPU_GPU_PAGE_SIZE * count;
592 /* handle the area in the middle */
593 count = (frag_end - frag_start) / 8;
594 amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
595 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
598 /* handle the 4K area at the end */
599 if (frag_end != pe_end) {
600 addr += AMDGPU_GPU_PAGE_SIZE * count;
601 count = (pe_end - frag_end) / 8;
602 amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
603 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
608 * amdgpu_vm_update_ptes - make sure that page tables are valid
610 * @adev: amdgpu_device pointer
612 * @start: start of GPU address range
613 * @end: end of GPU address range
614 * @dst: destination address to map to
615 * @flags: mapping flags
617 * Update the page tables in the range @start - @end (cayman+).
619 * Global and local mutex must be locked!
621 static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
622 struct amdgpu_vm *vm,
623 struct amdgpu_ib *ib,
624 uint64_t start, uint64_t end,
625 uint64_t dst, uint32_t flags,
628 uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
629 uint64_t last_pte = ~0, last_dst = ~0;
630 void *owner = AMDGPU_FENCE_OWNER_VM;
634 /* sync to everything on unmapping */
635 if (!(flags & AMDGPU_PTE_VALID))
636 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
638 /* walk over the address space and update the page tables */
639 for (addr = start; addr < end; ) {
640 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
641 struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
646 amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
647 r = reservation_object_reserve_shared(pt->tbo.resv);
651 if ((addr & ~mask) == (end & ~mask))
654 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
656 pte = amdgpu_bo_gpu_offset(pt);
657 pte += (addr & mask) * 8;
659 if ((last_pte + 8 * count) != pte) {
662 amdgpu_vm_frag_ptes(adev, ib, last_pte,
663 last_pte + 8 * count,
676 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
680 amdgpu_vm_frag_ptes(adev, ib, last_pte,
681 last_pte + 8 * count,
682 last_dst, flags, gtt_flags);
689 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
691 * @adev: amdgpu_device pointer
693 * @mapping: mapped range and flags to use for the update
694 * @addr: addr to set the area to
695 * @gtt_flags: flags as they are used for GTT
696 * @fence: optional resulting fence
698 * Fill in the page table entries for @mapping.
699 * Returns 0 for success, -EINVAL for failure.
701 * Object have to be reserved and mutex must be locked!
703 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
704 struct amdgpu_vm *vm,
705 struct amdgpu_bo_va_mapping *mapping,
706 uint64_t addr, uint32_t gtt_flags,
707 struct fence **fence)
709 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
710 unsigned nptes, ncmds, ndw;
711 uint32_t flags = gtt_flags;
712 struct amdgpu_ib *ib;
713 struct fence *f = NULL;
716 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
717 * but in case of something, we filter the flags in first place
719 if (!(mapping->flags & AMDGPU_PTE_READABLE))
720 flags &= ~AMDGPU_PTE_READABLE;
721 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
722 flags &= ~AMDGPU_PTE_WRITEABLE;
724 trace_amdgpu_vm_bo_update(mapping);
726 nptes = mapping->it.last - mapping->it.start + 1;
729 * reserve space for one command every (1 << BLOCK_SIZE)
730 * entries or 2k dwords (whatever is smaller)
732 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
737 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
738 /* only copy commands needed */
741 } else if (flags & AMDGPU_PTE_SYSTEM) {
742 /* header for write data commands */
745 /* body of write data command */
749 /* set page commands needed */
752 /* two extra commands for begin/end of fragment */
756 /* update too big for an IB */
760 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
764 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
772 r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
773 mapping->it.last + 1, addr + mapping->offset,
777 amdgpu_ib_free(adev, ib);
782 amdgpu_vm_pad_ib(adev, ib);
783 WARN_ON(ib->length_dw > ndw);
784 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
786 AMDGPU_FENCE_OWNER_VM,
791 amdgpu_bo_fence(vm->page_directory, f, true);
794 *fence = fence_get(f);
797 if (!amdgpu_enable_scheduler) {
798 amdgpu_ib_free(adev, ib);
804 amdgpu_ib_free(adev, ib);
810 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
812 * @adev: amdgpu_device pointer
813 * @bo_va: requested BO and VM object
816 * Fill in the page table entries for @bo_va.
817 * Returns 0 for success, -EINVAL for failure.
819 * Object have to be reserved and mutex must be locked!
821 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
822 struct amdgpu_bo_va *bo_va,
823 struct ttm_mem_reg *mem)
825 struct amdgpu_vm *vm = bo_va->vm;
826 struct amdgpu_bo_va_mapping *mapping;
832 addr = (u64)mem->start << PAGE_SHIFT;
833 if (mem->mem_type != TTM_PL_TT)
834 addr += adev->vm_manager.vram_base_offset;
839 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
841 spin_lock(&vm->status_lock);
842 if (!list_empty(&bo_va->vm_status))
843 list_splice_init(&bo_va->valids, &bo_va->invalids);
844 spin_unlock(&vm->status_lock);
846 list_for_each_entry(mapping, &bo_va->invalids, list) {
847 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
848 flags, &bo_va->last_pt_update);
853 if (trace_amdgpu_vm_bo_mapping_enabled()) {
854 list_for_each_entry(mapping, &bo_va->valids, list)
855 trace_amdgpu_vm_bo_mapping(mapping);
857 list_for_each_entry(mapping, &bo_va->invalids, list)
858 trace_amdgpu_vm_bo_mapping(mapping);
861 spin_lock(&vm->status_lock);
862 list_splice_init(&bo_va->invalids, &bo_va->valids);
863 list_del_init(&bo_va->vm_status);
865 list_add(&bo_va->vm_status, &vm->cleared);
866 spin_unlock(&vm->status_lock);
872 * amdgpu_vm_clear_freed - clear freed BOs in the PT
874 * @adev: amdgpu_device pointer
877 * Make sure all freed BOs are cleared in the PT.
878 * Returns 0 for success.
880 * PTs have to be reserved and mutex must be locked!
882 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
883 struct amdgpu_vm *vm)
885 struct amdgpu_bo_va_mapping *mapping;
888 while (!list_empty(&vm->freed)) {
889 mapping = list_first_entry(&vm->freed,
890 struct amdgpu_bo_va_mapping, list);
891 list_del(&mapping->list);
893 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
904 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
906 * @adev: amdgpu_device pointer
909 * Make sure all invalidated BOs are cleared in the PT.
910 * Returns 0 for success.
912 * PTs have to be reserved and mutex must be locked!
914 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
915 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
917 struct amdgpu_bo_va *bo_va = NULL;
920 spin_lock(&vm->status_lock);
921 while (!list_empty(&vm->invalidated)) {
922 bo_va = list_first_entry(&vm->invalidated,
923 struct amdgpu_bo_va, vm_status);
924 spin_unlock(&vm->status_lock);
925 mutex_lock(&bo_va->mutex);
926 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
927 mutex_unlock(&bo_va->mutex);
931 spin_lock(&vm->status_lock);
933 spin_unlock(&vm->status_lock);
936 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
942 * amdgpu_vm_bo_add - add a bo to a specific vm
944 * @adev: amdgpu_device pointer
946 * @bo: amdgpu buffer object
948 * Add @bo into the requested vm (cayman+).
949 * Add @bo to the list of bos associated with the vm
950 * Returns newly added bo_va or NULL for failure
952 * Object has to be reserved!
954 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
955 struct amdgpu_vm *vm,
956 struct amdgpu_bo *bo)
958 struct amdgpu_bo_va *bo_va;
960 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
966 bo_va->ref_count = 1;
967 INIT_LIST_HEAD(&bo_va->bo_list);
968 INIT_LIST_HEAD(&bo_va->valids);
969 INIT_LIST_HEAD(&bo_va->invalids);
970 INIT_LIST_HEAD(&bo_va->vm_status);
971 mutex_init(&bo_va->mutex);
972 list_add_tail(&bo_va->bo_list, &bo->va);
978 * amdgpu_vm_bo_map - map bo inside a vm
980 * @adev: amdgpu_device pointer
981 * @bo_va: bo_va to store the address
982 * @saddr: where to map the BO
983 * @offset: requested offset in the BO
984 * @flags: attributes of pages (read/write/valid/etc.)
986 * Add a mapping of the BO at the specefied addr into the VM.
987 * Returns 0 for success, error for failure.
989 * Object has to be reserved and unreserved outside!
991 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
992 struct amdgpu_bo_va *bo_va,
993 uint64_t saddr, uint64_t offset,
994 uint64_t size, uint32_t flags)
996 struct amdgpu_bo_va_mapping *mapping;
997 struct amdgpu_vm *vm = bo_va->vm;
998 struct interval_tree_node *it;
999 unsigned last_pfn, pt_idx;
1003 /* validate the parameters */
1004 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1005 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1008 /* make sure object fit at this offset */
1009 eaddr = saddr + size;
1010 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
1013 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1014 if (last_pfn > adev->vm_manager.max_pfn) {
1015 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
1016 last_pfn, adev->vm_manager.max_pfn);
1020 saddr /= AMDGPU_GPU_PAGE_SIZE;
1021 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1023 spin_lock(&vm->it_lock);
1024 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
1025 spin_unlock(&vm->it_lock);
1027 struct amdgpu_bo_va_mapping *tmp;
1028 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1029 /* bo and tmp overlap, invalid addr */
1030 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1031 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1032 tmp->it.start, tmp->it.last + 1);
1037 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1043 INIT_LIST_HEAD(&mapping->list);
1044 mapping->it.start = saddr;
1045 mapping->it.last = eaddr - 1;
1046 mapping->offset = offset;
1047 mapping->flags = flags;
1049 mutex_lock(&bo_va->mutex);
1050 list_add(&mapping->list, &bo_va->invalids);
1051 mutex_unlock(&bo_va->mutex);
1052 spin_lock(&vm->it_lock);
1053 interval_tree_insert(&mapping->it, &vm->va);
1054 spin_unlock(&vm->it_lock);
1055 trace_amdgpu_vm_bo_map(bo_va, mapping);
1057 /* Make sure the page tables are allocated */
1058 saddr >>= amdgpu_vm_block_size;
1059 eaddr >>= amdgpu_vm_block_size;
1061 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1063 if (eaddr > vm->max_pde_used)
1064 vm->max_pde_used = eaddr;
1066 /* walk over the address space and allocate the page tables */
1067 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1068 struct reservation_object *resv = vm->page_directory->tbo.resv;
1069 struct amdgpu_bo *pt;
1071 if (vm->page_tables[pt_idx].bo)
1074 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1075 AMDGPU_GPU_PAGE_SIZE, true,
1076 AMDGPU_GEM_DOMAIN_VRAM,
1077 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1082 r = amdgpu_vm_clear_bo(adev, pt);
1084 amdgpu_bo_unref(&pt);
1088 vm->page_tables[pt_idx].addr = 0;
1089 vm->page_tables[pt_idx].bo = pt;
1095 list_del(&mapping->list);
1096 spin_lock(&vm->it_lock);
1097 interval_tree_remove(&mapping->it, &vm->va);
1098 spin_unlock(&vm->it_lock);
1099 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1107 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1109 * @adev: amdgpu_device pointer
1110 * @bo_va: bo_va to remove the address from
1111 * @saddr: where to the BO is mapped
1113 * Remove a mapping of the BO at the specefied addr from the VM.
1114 * Returns 0 for success, error for failure.
1116 * Object has to be reserved and unreserved outside!
1118 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1119 struct amdgpu_bo_va *bo_va,
1122 struct amdgpu_bo_va_mapping *mapping;
1123 struct amdgpu_vm *vm = bo_va->vm;
1126 saddr /= AMDGPU_GPU_PAGE_SIZE;
1127 mutex_lock(&bo_va->mutex);
1128 list_for_each_entry(mapping, &bo_va->valids, list) {
1129 if (mapping->it.start == saddr)
1133 if (&mapping->list == &bo_va->valids) {
1136 list_for_each_entry(mapping, &bo_va->invalids, list) {
1137 if (mapping->it.start == saddr)
1141 if (&mapping->list == &bo_va->invalids) {
1142 mutex_unlock(&bo_va->mutex);
1146 mutex_unlock(&bo_va->mutex);
1147 list_del(&mapping->list);
1148 spin_lock(&vm->it_lock);
1149 interval_tree_remove(&mapping->it, &vm->va);
1150 spin_unlock(&vm->it_lock);
1151 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1154 list_add(&mapping->list, &vm->freed);
1162 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1164 * @adev: amdgpu_device pointer
1165 * @bo_va: requested bo_va
1167 * Remove @bo_va->bo from the requested vm (cayman+).
1169 * Object have to be reserved!
1171 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1172 struct amdgpu_bo_va *bo_va)
1174 struct amdgpu_bo_va_mapping *mapping, *next;
1175 struct amdgpu_vm *vm = bo_va->vm;
1177 list_del(&bo_va->bo_list);
1179 spin_lock(&vm->status_lock);
1180 list_del(&bo_va->vm_status);
1181 spin_unlock(&vm->status_lock);
1183 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1184 list_del(&mapping->list);
1185 spin_lock(&vm->it_lock);
1186 interval_tree_remove(&mapping->it, &vm->va);
1187 spin_unlock(&vm->it_lock);
1188 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1189 list_add(&mapping->list, &vm->freed);
1191 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1192 list_del(&mapping->list);
1193 spin_lock(&vm->it_lock);
1194 interval_tree_remove(&mapping->it, &vm->va);
1195 spin_unlock(&vm->it_lock);
1198 fence_put(bo_va->last_pt_update);
1199 mutex_destroy(&bo_va->mutex);
1204 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1206 * @adev: amdgpu_device pointer
1208 * @bo: amdgpu buffer object
1210 * Mark @bo as invalid (cayman+).
1212 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1213 struct amdgpu_bo *bo)
1215 struct amdgpu_bo_va *bo_va;
1217 list_for_each_entry(bo_va, &bo->va, bo_list) {
1218 spin_lock(&bo_va->vm->status_lock);
1219 if (list_empty(&bo_va->vm_status))
1220 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1221 spin_unlock(&bo_va->vm->status_lock);
1226 * amdgpu_vm_init - initialize a vm instance
1228 * @adev: amdgpu_device pointer
1231 * Init @vm fields (cayman+).
1233 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1235 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1236 AMDGPU_VM_PTE_COUNT * 8);
1237 unsigned pd_size, pd_entries, pts_size;
1240 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1242 vm->ids[i].flushed_updates = NULL;
1245 spin_lock_init(&vm->status_lock);
1246 INIT_LIST_HEAD(&vm->invalidated);
1247 INIT_LIST_HEAD(&vm->cleared);
1248 INIT_LIST_HEAD(&vm->freed);
1249 spin_lock_init(&vm->it_lock);
1250 pd_size = amdgpu_vm_directory_size(adev);
1251 pd_entries = amdgpu_vm_num_pdes(adev);
1253 /* allocate page table array */
1254 pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
1255 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1256 if (vm->page_tables == NULL) {
1257 DRM_ERROR("Cannot allocate memory for page table array\n");
1261 vm->page_directory_fence = NULL;
1263 r = amdgpu_bo_create(adev, pd_size, align, true,
1264 AMDGPU_GEM_DOMAIN_VRAM,
1265 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1266 NULL, NULL, &vm->page_directory);
1269 r = amdgpu_bo_reserve(vm->page_directory, false);
1271 amdgpu_bo_unref(&vm->page_directory);
1272 vm->page_directory = NULL;
1275 r = amdgpu_vm_clear_bo(adev, vm->page_directory);
1276 amdgpu_bo_unreserve(vm->page_directory);
1278 amdgpu_bo_unref(&vm->page_directory);
1279 vm->page_directory = NULL;
1287 * amdgpu_vm_fini - tear down a vm instance
1289 * @adev: amdgpu_device pointer
1292 * Tear down @vm (cayman+).
1293 * Unbind the VM and remove all bos from the vm bo list
1295 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1297 struct amdgpu_bo_va_mapping *mapping, *tmp;
1300 if (!RB_EMPTY_ROOT(&vm->va)) {
1301 dev_err(adev->dev, "still active bo inside vm\n");
1303 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1304 list_del(&mapping->list);
1305 interval_tree_remove(&mapping->it, &vm->va);
1308 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1309 list_del(&mapping->list);
1313 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1314 amdgpu_bo_unref(&vm->page_tables[i].bo);
1315 kfree(vm->page_tables);
1317 amdgpu_bo_unref(&vm->page_directory);
1318 fence_put(vm->page_directory_fence);
1319 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1320 unsigned id = vm->ids[i].id;
1322 atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner,
1324 fence_put(vm->ids[i].flushed_updates);
1330 * amdgpu_vm_manager_fini - cleanup VM manager
1332 * @adev: amdgpu_device pointer
1334 * Cleanup the VM manager and free resources.
1336 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1340 for (i = 0; i < AMDGPU_NUM_VM; ++i)
1341 fence_put(adev->vm_manager.ids[i].active);