2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/amdgpu_drm.h>
27 #include "atombios_encoders.h"
28 #include <asm/div64.h>
29 #include <linux/gcd.h>
32 * amdgpu_pll_reduce_ratio - fractional number reduction
36 * @nom_min: minimum value for nominator
37 * @den_min: minimum value for denominator
39 * Find the greatest common divisor and apply it on both nominator and
40 * denominator, but make nominator and denominator are at least as large
41 * as their minimum values.
43 static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
44 unsigned nom_min, unsigned den_min)
48 /* reduce the numbers to a simpler ratio */
49 tmp = gcd(*nom, *den);
53 /* make sure nominator is large enough */
55 tmp = DIV_ROUND_UP(nom_min, *nom);
60 /* make sure the denominator is large enough */
62 tmp = DIV_ROUND_UP(den_min, *den);
69 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
73 * @post_div: post divider
74 * @fb_div_max: feedback divider maximum
75 * @ref_div_max: reference divider maximum
76 * @fb_div: resulting feedback divider
77 * @ref_div: resulting reference divider
79 * Calculate feedback and reference divider for a given post divider. Makes
80 * sure we stay within the limits.
82 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
83 unsigned fb_div_max, unsigned ref_div_max,
84 unsigned *fb_div, unsigned *ref_div)
86 /* limit reference * post divider to a maximum */
87 ref_div_max = min(128 / post_div, ref_div_max);
89 /* get matching reference and feedback divider */
90 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
91 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
93 /* limit fb divider to its maximum */
94 if (*fb_div > fb_div_max) {
95 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
101 * amdgpu_pll_compute - compute PLL paramaters
103 * @pll: information about the PLL
104 * @dot_clock_p: resulting pixel clock
105 * fb_div_p: resulting feedback divider
106 * frac_fb_div_p: fractional part of the feedback divider
107 * ref_div_p: resulting reference divider
108 * post_div_p: resulting reference divider
110 * Try to calculate the PLL parameters to generate the given frequency:
111 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
113 void amdgpu_pll_compute(struct amdgpu_pll *pll,
121 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
124 unsigned fb_div_min, fb_div_max, fb_div;
125 unsigned post_div_min, post_div_max, post_div;
126 unsigned ref_div_min, ref_div_max, ref_div;
127 unsigned post_div_best, diff_best;
130 /* determine allowed feedback divider range */
131 fb_div_min = pll->min_feedback_div;
132 fb_div_max = pll->max_feedback_div;
134 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
139 /* determine allowed ref divider range */
140 if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
141 ref_div_min = pll->reference_div;
143 ref_div_min = pll->min_ref_div;
145 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
146 pll->flags & AMDGPU_PLL_USE_REF_DIV)
147 ref_div_max = pll->reference_div;
149 ref_div_max = pll->max_ref_div;
151 /* determine allowed post divider range */
152 if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
153 post_div_min = pll->post_div;
154 post_div_max = pll->post_div;
156 unsigned vco_min, vco_max;
158 if (pll->flags & AMDGPU_PLL_IS_LCD) {
159 vco_min = pll->lcd_pll_out_min;
160 vco_max = pll->lcd_pll_out_max;
162 vco_min = pll->pll_out_min;
163 vco_max = pll->pll_out_max;
166 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
171 post_div_min = vco_min / target_clock;
172 if ((target_clock * post_div_min) < vco_min)
174 if (post_div_min < pll->min_post_div)
175 post_div_min = pll->min_post_div;
177 post_div_max = vco_max / target_clock;
178 if ((target_clock * post_div_max) > vco_max)
180 if (post_div_max > pll->max_post_div)
181 post_div_max = pll->max_post_div;
184 /* represent the searched ratio as fractional number */
186 den = pll->reference_freq;
188 /* reduce the numbers to a simpler ratio */
189 amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
191 /* now search for a post divider */
192 if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
193 post_div_best = post_div_min;
195 post_div_best = post_div_max;
198 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
200 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max,
201 ref_div_max, &fb_div, &ref_div);
202 diff = abs(target_clock - (pll->reference_freq * fb_div) /
203 (ref_div * post_div));
205 if (diff < diff_best || (diff == diff_best &&
206 !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
208 post_div_best = post_div;
212 post_div = post_div_best;
214 /* get the feedback and reference divider for the optimal value */
215 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
218 /* reduce the numbers to a simpler ratio once more */
219 /* this also makes sure that the reference divider is large enough */
220 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
222 /* avoid high jitter with small fractional dividers */
223 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
224 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
225 if (fb_div < fb_div_min) {
226 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
232 /* and finally save the result */
233 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
234 *fb_div_p = fb_div / 10;
235 *frac_fb_div_p = fb_div % 10;
241 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
242 (pll->reference_freq * *frac_fb_div_p)) /
243 (ref_div * post_div * 10);
244 *ref_div_p = ref_div;
245 *post_div_p = post_div;
247 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
248 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
253 * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
257 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
259 u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)
261 struct drm_device *dev = crtc->dev;
262 struct drm_crtc *test_crtc;
263 struct amdgpu_crtc *test_amdgpu_crtc;
266 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
267 if (crtc == test_crtc)
270 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
271 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
272 pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
278 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
282 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
283 * also in DP mode. For DP, a single PPLL can be used for all DP
286 int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
288 struct drm_device *dev = crtc->dev;
289 struct drm_crtc *test_crtc;
290 struct amdgpu_crtc *test_amdgpu_crtc;
292 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
293 if (crtc == test_crtc)
295 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
296 if (test_amdgpu_crtc->encoder &&
297 ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
298 /* for DP use the same PLL for all */
299 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
300 return test_amdgpu_crtc->pll_id;
303 return ATOM_PPLL_INVALID;
307 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
310 * @encoder: drm encoder
312 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
313 * be shared (i.e., same clock).
315 int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc)
317 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct drm_crtc *test_crtc;
320 struct amdgpu_crtc *test_amdgpu_crtc;
321 u32 adjusted_clock, test_adjusted_clock;
323 adjusted_clock = amdgpu_crtc->adjusted_clock;
325 if (adjusted_clock == 0)
326 return ATOM_PPLL_INVALID;
328 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
329 if (crtc == test_crtc)
331 test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
332 if (test_amdgpu_crtc->encoder &&
333 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
334 /* check if we are already driving this connector with another crtc */
335 if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
336 /* if we are, return that pll */
337 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
338 return test_amdgpu_crtc->pll_id;
340 /* for non-DP check the clock */
341 test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;
342 if ((crtc->mode.clock == test_crtc->mode.clock) &&
343 (adjusted_clock == test_adjusted_clock) &&
344 (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
345 (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
346 return test_amdgpu_crtc->pll_id;
349 return ATOM_PPLL_INVALID;