2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include <drm/drm_edid.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_i2c.h"
33 #include "amdgpu_atombios.h"
35 #include "atombios_dp.h"
36 #include "atombios_i2c.h"
39 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
41 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
42 struct amdgpu_device *adev = i2c->dev->dev_private;
43 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
46 mutex_lock(&i2c->mutex);
48 /* switch the pads to ddc mode */
49 if (rec->hw_capable) {
50 temp = RREG32(rec->mask_clk_reg);
52 WREG32(rec->mask_clk_reg, temp);
55 /* clear the output pin values */
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
57 WREG32(rec->a_clk_reg, temp);
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
60 WREG32(rec->a_data_reg, temp);
62 /* set the pins to input */
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
64 WREG32(rec->en_clk_reg, temp);
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
67 WREG32(rec->en_data_reg, temp);
69 /* mask the gpio pins for software use */
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
71 WREG32(rec->mask_clk_reg, temp);
72 temp = RREG32(rec->mask_clk_reg);
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
75 WREG32(rec->mask_data_reg, temp);
76 temp = RREG32(rec->mask_data_reg);
81 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
83 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
84 struct amdgpu_device *adev = i2c->dev->dev_private;
85 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
88 /* unmask the gpio pins for software use */
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
90 WREG32(rec->mask_clk_reg, temp);
91 temp = RREG32(rec->mask_clk_reg);
93 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
94 WREG32(rec->mask_data_reg, temp);
95 temp = RREG32(rec->mask_data_reg);
97 mutex_unlock(&i2c->mutex);
100 static int amdgpu_i2c_get_clock(void *i2c_priv)
102 struct amdgpu_i2c_chan *i2c = i2c_priv;
103 struct amdgpu_device *adev = i2c->dev->dev_private;
104 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
107 /* read the value off the pin */
108 val = RREG32(rec->y_clk_reg);
109 val &= rec->y_clk_mask;
115 static int amdgpu_i2c_get_data(void *i2c_priv)
117 struct amdgpu_i2c_chan *i2c = i2c_priv;
118 struct amdgpu_device *adev = i2c->dev->dev_private;
119 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
122 /* read the value off the pin */
123 val = RREG32(rec->y_data_reg);
124 val &= rec->y_data_mask;
129 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
131 struct amdgpu_i2c_chan *i2c = i2c_priv;
132 struct amdgpu_device *adev = i2c->dev->dev_private;
133 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
136 /* set pin direction */
137 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
138 val |= clock ? 0 : rec->en_clk_mask;
139 WREG32(rec->en_clk_reg, val);
142 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
144 struct amdgpu_i2c_chan *i2c = i2c_priv;
145 struct amdgpu_device *adev = i2c->dev->dev_private;
146 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
149 /* set pin direction */
150 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
151 val |= data ? 0 : rec->en_data_mask;
152 WREG32(rec->en_data_reg, val);
155 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
156 .master_xfer = amdgpu_atombios_i2c_xfer,
157 .functionality = amdgpu_atombios_i2c_func,
160 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
161 struct amdgpu_i2c_bus_rec *rec,
164 struct amdgpu_i2c_chan *i2c;
167 /* don't add the mm_i2c bus unless hw_i2c is enabled */
168 if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
171 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
176 i2c->adapter.owner = THIS_MODULE;
177 i2c->adapter.class = I2C_CLASS_DDC;
178 i2c->adapter.dev.parent = &dev->pdev->dev;
180 i2c_set_adapdata(&i2c->adapter, i2c);
181 mutex_init(&i2c->mutex);
182 if (rec->hw_capable &&
184 /* hw i2c using atom */
185 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
186 "AMDGPU i2c hw bus %s", name);
187 i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
188 ret = i2c_add_adapter(&i2c->adapter);
190 DRM_ERROR("Failed to register hw i2c %s\n", name);
194 /* set the amdgpu bit adapter */
195 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
196 "AMDGPU i2c bit bus %s", name);
197 i2c->adapter.algo_data = &i2c->bit;
198 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
199 i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
200 i2c->bit.setsda = amdgpu_i2c_set_data;
201 i2c->bit.setscl = amdgpu_i2c_set_clock;
202 i2c->bit.getsda = amdgpu_i2c_get_data;
203 i2c->bit.getscl = amdgpu_i2c_get_clock;
204 i2c->bit.udelay = 10;
205 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
207 ret = i2c_bit_add_bus(&i2c->adapter);
209 DRM_ERROR("Failed to register bit i2c %s\n", name);
221 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
225 i2c_del_adapter(&i2c->adapter);
229 /* Add the default buses */
230 void amdgpu_i2c_init(struct amdgpu_device *adev)
233 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
235 if (adev->is_atom_bios)
236 amdgpu_atombios_i2c_init(adev);
239 /* remove all the buses */
240 void amdgpu_i2c_fini(struct amdgpu_device *adev)
244 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
245 if (adev->i2c_bus[i]) {
246 amdgpu_i2c_destroy(adev->i2c_bus[i]);
247 adev->i2c_bus[i] = NULL;
252 /* Add additional buses */
253 void amdgpu_i2c_add(struct amdgpu_device *adev,
254 struct amdgpu_i2c_bus_rec *rec,
257 struct drm_device *dev = adev->ddev;
260 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
261 if (!adev->i2c_bus[i]) {
262 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
268 /* looks up bus based on id */
269 struct amdgpu_i2c_chan *
270 amdgpu_i2c_lookup(struct amdgpu_device *adev,
271 struct amdgpu_i2c_bus_rec *i2c_bus)
275 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
276 if (adev->i2c_bus[i] &&
277 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
278 return adev->i2c_bus[i];
284 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
291 struct i2c_msg msgs[] = {
309 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
311 DRM_DEBUG("val = 0x%02x\n", *val);
313 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
318 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
324 struct i2c_msg msg = {
334 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
335 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
339 /* ddc router switching */
341 amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector)
345 if (!amdgpu_connector->router.ddc_valid)
348 if (!amdgpu_connector->router_bus)
351 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
352 amdgpu_connector->router.i2c_addr,
354 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
355 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
356 amdgpu_connector->router.i2c_addr,
358 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
359 amdgpu_connector->router.i2c_addr,
361 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
362 val |= amdgpu_connector->router.ddc_mux_state;
363 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
364 amdgpu_connector->router.i2c_addr,
368 /* clock/data router switching */
370 amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector)
374 if (!amdgpu_connector->router.cd_valid)
377 if (!amdgpu_connector->router_bus)
380 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
381 amdgpu_connector->router.i2c_addr,
383 val &= ~amdgpu_connector->router.cd_mux_control_pin;
384 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
385 amdgpu_connector->router.i2c_addr,
387 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
388 amdgpu_connector->router.i2c_addr,
390 val &= ~amdgpu_connector->router.cd_mux_control_pin;
391 val |= amdgpu_connector->router.cd_mux_state;
392 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
393 amdgpu_connector->router.i2c_addr,