drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < adev->sdma.num_instances) {
 108                         *out_ring = &adev->sdma.instance[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only %d SDMA rings are supported\n",
 111                                   adev->sdma.num_instances);
 112                         return -EINVAL;
 113                 }
 114                 break;
 115         case AMDGPU_HW_IP_UVD:
 116                 *out_ring = &adev->uvd.ring;
 117                 break;
 118         case AMDGPU_HW_IP_VCE:
 119                 if (ring < 2){
 120                         *out_ring = &adev->vce.ring[ring];
 121                 } else {
 122                         DRM_ERROR("only two VCE rings are supported\n");
 123                         return -EINVAL;
 124                 }
 125                 break;
 126         }
 127         return 0;
 128 }
 129
 130 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 131 {
 132         union drm_amdgpu_cs *cs = data;
 133         uint64_t *chunk_array_user;
 134         uint64_t *chunk_array;
 135         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 136         unsigned size;
 137         int i;
 138         int ret;
 139
 140         if (cs->in.num_chunks == 0)
 141                 return 0;
 142
 143         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 144         if (!chunk_array)
 145                 return -ENOMEM;
 146
 147         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 148         if (!p->ctx) {
 149                 ret = -EINVAL;
 150                 goto free_chunk;
 151         }
 152
 153         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 154
 155         /* get chunks */
 156         INIT_LIST_HEAD(&p->validated);
 157         chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
 158         if (copy_from_user(chunk_array, chunk_array_user,
 159                            sizeof(uint64_t)*cs->in.num_chunks)) {
 160                 ret = -EFAULT;
 161                 goto put_bo_list;
 162         }
 163
 164         p->nchunks = cs->in.num_chunks;
 165         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 166                             GFP_KERNEL);
 167         if (!p->chunks) {
 168                 ret = -ENOMEM;
 169                 goto put_bo_list;
 170         }
 171
 172         for (i = 0; i < p->nchunks; i++) {
 173                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 174                 struct drm_amdgpu_cs_chunk user_chunk;
 175                 uint32_t __user *cdata;
 176
 177                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 178                 if (copy_from_user(&user_chunk, chunk_ptr,
 179                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 180                         ret = -EFAULT;
 181                         i--;
 182                         goto free_partial_kdata;
 183                 }
 184                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 185                 p->chunks[i].length_dw = user_chunk.length_dw;
 186
 187                 size = p->chunks[i].length_dw;
 188                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 189                 p->chunks[i].user_ptr = cdata;
 190
 191                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 192                 if (p->chunks[i].kdata == NULL) {
 193                         ret = -ENOMEM;
 194                         i--;
 195                         goto free_partial_kdata;
 196                 }
 197                 size *= sizeof(uint32_t);
 198                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 199                         ret = -EFAULT;
 200                         goto free_partial_kdata;
 201                 }
 202
 203                 switch (p->chunks[i].chunk_id) {
 204                 case AMDGPU_CHUNK_ID_IB:
 205                         p->num_ibs++;
 206                         break;
 207
 208                 case AMDGPU_CHUNK_ID_FENCE:
 209                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 210                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 211                                 uint32_t handle;
 212                                 struct drm_gem_object *gobj;
 213                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 214
 215                                 fence_data = (void *)p->chunks[i].kdata;
 216                                 handle = fence_data->handle;
 217                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 218                                                              p->filp, handle);
 219                                 if (gobj == NULL) {
 220                                         ret = -EINVAL;
 221                                         goto free_partial_kdata;
 222                                 }
 223
 224                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 225                                 p->uf.offset = fence_data->offset;
 226                         } else {
 227                                 ret = -EINVAL;
 228                                 goto free_partial_kdata;
 229                         }
 230                         break;
 231
 232                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 233                         break;
 234
 235                 default:
 236                         ret = -EINVAL;
 237                         goto free_partial_kdata;
 238                 }
 239         }
 240
 241
 242         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 243         if (!p->ibs) {
 244                 ret = -ENOMEM;
 245                 goto free_all_kdata;
 246         }
 247
 248         kfree(chunk_array);
 249         return 0;
 250
 251 free_all_kdata:
 252         i = p->nchunks - 1;
 253 free_partial_kdata:
 254         for (; i >= 0; i--)
 255                 drm_free_large(p->chunks[i].kdata);
 256         kfree(p->chunks);
 257 put_bo_list:
 258         if (p->bo_list)
 259                 amdgpu_bo_list_put(p->bo_list);
 260         amdgpu_ctx_put(p->ctx);
 261 free_chunk:
 262         kfree(chunk_array);
 263
 264         return ret;
 265 }
 266
 267 /* Returns how many bytes TTM can move per IB.
 268  */
 269 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 270 {
 271         u64 real_vram_size = adev->mc.real_vram_size;
 272         u64 vram_usage = atomic64_read(&adev->vram_usage);
 273
 274         /* This function is based on the current VRAM usage.
 275          *
 276          * - If all of VRAM is free, allow relocating the number of bytes that
 277          *   is equal to 1/4 of the size of VRAM for this IB.
 278
 279          * - If more than one half of VRAM is occupied, only allow relocating
 280          *   1 MB of data for this IB.
 281          *
 282          * - From 0 to one half of used VRAM, the threshold decreases
 283          *   linearly.
 284          *         __________________
 285          * 1/4 of -|\               |
 286          * VRAM    | \              |
 287          *         |  \             |
 288          *         |   \            |
 289          *         |    \           |
 290          *         |     \          |
 291          *         |      \         |
 292          *         |       \________|1 MB
 293          *         |----------------|
 294          *    VRAM 0 %             100 %
 295          *         used            used
 296          *
 297          * Note: It's a threshold, not a limit. The threshold must be crossed
 298          * for buffer relocations to stop, so any buffer of an arbitrary size
 299          * can be moved as long as the threshold isn't crossed before
 300          * the relocation takes place. We don't want to disable buffer
 301          * relocations completely.
 302          *
 303          * The idea is that buffers should be placed in VRAM at creation time
 304          * and TTM should only do a minimum number of relocations during
 305          * command submission. In practice, you need to submit at least
 306          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 307          *
 308          * Also, things can get pretty crazy under memory pressure and actual
 309          * VRAM usage can change a lot, so playing safe even at 50% does
 310          * consistently increase performance.
 311          */
 312
 313         u64 half_vram = real_vram_size >> 1;
 314         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 315         u64 bytes_moved_threshold = half_free_vram >> 1;
 316         return max(bytes_moved_threshold, 1024*1024ull);
 317 }
 318
 319 int amdgpu_cs_list_validate(struct amdgpu_device *adev,
 320                             struct amdgpu_vm *vm,
 321                             struct list_head *validated)
 322 {
 323         struct amdgpu_bo_list_entry *lobj;
 324         struct amdgpu_bo *bo;
 325         u64 bytes_moved = 0, initial_bytes_moved;
 326         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 327         int r;
 328
 329         list_for_each_entry(lobj, validated, tv.head) {
 330                 bo = lobj->robj;
 331                 if (!bo->pin_count) {
 332                         u32 domain = lobj->prefered_domains;
 333                         u32 current_domain =
 334                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 335
 336                         /* Check if this buffer will be moved and don't move it
 337                          * if we have moved too many buffers for this IB already.
 338                          *
 339                          * Note that this allows moving at least one buffer of
 340                          * any size, because it doesn't take the current "bo"
 341                          * into account. We don't want to disallow buffer moves
 342                          * completely.
 343                          */
 344                         if ((lobj->allowed_domains & current_domain) != 0 &&
 345                             (domain & current_domain) == 0 && /* will be moved */
 346                             bytes_moved > bytes_moved_threshold) {
 347                                 /* don't move it */
 348                                 domain = current_domain;
 349                         }
 350
 351                 retry:
 352                         amdgpu_ttm_placement_from_domain(bo, domain);
 353                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 354                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 355                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 356                                        initial_bytes_moved;
 357
 358                         if (unlikely(r)) {
 359                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 360                                         domain = lobj->allowed_domains;
 361                                         goto retry;
 362                                 }
 363                                 return r;
 364                         }
 365                 }
 366                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 367         }
 368         return 0;
 369 }
 370
 371 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 372 {
 373         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 374         struct amdgpu_cs_buckets buckets;
 375         struct list_head duplicates;
 376         bool need_mmap_lock = false;
 377         int i, r;
 378
 379         if (p->bo_list) {
 380                 need_mmap_lock = p->bo_list->has_userptr;
 381                 amdgpu_cs_buckets_init(&buckets);
 382                 for (i = 0; i < p->bo_list->num_entries; i++)
 383                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 384                                                                   p->bo_list->array[i].priority);
 385
 386                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 387         }
 388
 389         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 390                                       &p->validated);
 391
 392         if (need_mmap_lock)
 393                 down_read(&current->mm->mmap_sem);
 394
 395         INIT_LIST_HEAD(&duplicates);
 396         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 397         if (unlikely(r != 0))
 398                 goto error_reserve;
 399
 400         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
 401         if (r)
 402                 goto error_validate;
 403
 404         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
 405
 406 error_validate:
 407         if (r)
 408                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 409
 410 error_reserve:
 411         if (need_mmap_lock)
 412                 up_read(&current->mm->mmap_sem);
 413
 414         return r;
 415 }
 416
 417 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 418 {
 419         struct amdgpu_bo_list_entry *e;
 420         int r;
 421
 422         list_for_each_entry(e, &p->validated, tv.head) {
 423                 struct reservation_object *resv = e->robj->tbo.resv;
 424                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 425
 426                 if (r)
 427                         return r;
 428         }
 429         return 0;
 430 }
 431
 432 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 433                                   struct list_head *b)
 434 {
 435         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 436         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 437
 438         /* Sort A before B if A is smaller. */
 439         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 440 }
 441
 442 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
 443 {
 444         if (!error) {
 445                 /* Sort the buffer list from the smallest to largest buffer,
 446                  * which affects the order of buffers in the LRU list.
 447                  * This assures that the smallest buffers are added first
 448                  * to the LRU list, so they are likely to be later evicted
 449                  * first, instead of large buffers whose eviction is more
 450                  * expensive.
 451                  *
 452                  * This slightly lowers the number of bytes moved by TTM
 453                  * per frame under memory pressure.
 454                  */
 455                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 456
 457                 ttm_eu_fence_buffer_objects(&parser->ticket,
 458                                 &parser->validated,
 459                                 &parser->ibs[parser->num_ibs-1].fence->base);
 460         } else if (backoff) {
 461                 ttm_eu_backoff_reservation(&parser->ticket,
 462                                            &parser->validated);
 463         }
 464 }
 465
 466 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
 467 {
 468         unsigned i;
 469
 470         if (parser->ctx)
 471                 amdgpu_ctx_put(parser->ctx);
 472         if (parser->bo_list)
 473                 amdgpu_bo_list_put(parser->bo_list);
 474
 475         drm_free_large(parser->vm_bos);
 476         for (i = 0; i < parser->nchunks; i++)
 477                 drm_free_large(parser->chunks[i].kdata);
 478         kfree(parser->chunks);
 479         if (parser->ibs)
 480                 for (i = 0; i < parser->num_ibs; i++)
 481                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 482         kfree(parser->ibs);
 483         if (parser->uf.bo)
 484                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 485 }
 486
 487 /**
 488  * cs_parser_fini() - clean parser states
 489  * @parser:     parser structure holding parsing context.
 490  * @error:      error number
 491  *
 492  * If error is set than unvalidate buffer, otherwise just free memory
 493  * used by parsing context.
 494  **/
 495 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 496 {
 497        amdgpu_cs_parser_fini_early(parser, error, backoff);
 498        amdgpu_cs_parser_fini_late(parser);
 499 }
 500
 501 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 502                                    struct amdgpu_vm *vm)
 503 {
 504         struct amdgpu_device *adev = p->adev;
 505         struct amdgpu_bo_va *bo_va;
 506         struct amdgpu_bo *bo;
 507         int i, r;
 508
 509         r = amdgpu_vm_update_page_directory(adev, vm);
 510         if (r)
 511                 return r;
 512
 513         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
 514         if (r)
 515                 return r;
 516
 517         r = amdgpu_vm_clear_freed(adev, vm);
 518         if (r)
 519                 return r;
 520
 521         if (p->bo_list) {
 522                 for (i = 0; i < p->bo_list->num_entries; i++) {
 523                         struct fence *f;
 524
 525                         /* ignore duplicates */
 526                         bo = p->bo_list->array[i].robj;
 527                         if (!bo)
 528                                 continue;
 529
 530                         bo_va = p->bo_list->array[i].bo_va;
 531                         if (bo_va == NULL)
 532                                 continue;
 533
 534                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 535                         if (r)
 536                                 return r;
 537
 538                         f = bo_va->last_pt_update;
 539                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 540                         if (r)
 541                                 return r;
 542                 }
 543
 544         }
 545
 546         r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 547
 548         if (amdgpu_vm_debug && p->bo_list) {
 549                 /* Invalidate all BOs to test for userspace bugs */
 550                 for (i = 0; i < p->bo_list->num_entries; i++) {
 551                         /* ignore duplicates */
 552                         bo = p->bo_list->array[i].robj;
 553                         if (!bo)
 554                                 continue;
 555
 556                         amdgpu_vm_bo_invalidate(adev, bo);
 557                 }
 558         }
 559
 560         return r;
 561 }
 562
 563 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 564                                  struct amdgpu_cs_parser *parser)
 565 {
 566         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 567         struct amdgpu_vm *vm = &fpriv->vm;
 568         struct amdgpu_ring *ring;
 569         int i, r;
 570
 571         if (parser->num_ibs == 0)
 572                 return 0;
 573
 574         /* Only for UVD/VCE VM emulation */
 575         for (i = 0; i < parser->num_ibs; i++) {
 576                 ring = parser->ibs[i].ring;
 577                 if (ring->funcs->parse_cs) {
 578                         r = amdgpu_ring_parse_cs(ring, parser, i);
 579                         if (r)
 580                                 return r;
 581                 }
 582         }
 583
 584         r = amdgpu_bo_vm_update_pte(parser, vm);
 585         if (r) {
 586                 goto out;
 587         }
 588         amdgpu_cs_sync_rings(parser);
 589         if (!amdgpu_enable_scheduler)
 590                 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 591                                        parser->filp);
 592
 593 out:
 594         return r;
 595 }
 596
 597 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 598 {
 599         if (r == -EDEADLK) {
 600                 r = amdgpu_gpu_reset(adev);
 601                 if (!r)
 602                         r = -EAGAIN;
 603         }
 604         return r;
 605 }
 606
 607 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 608                              struct amdgpu_cs_parser *parser)
 609 {
 610         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 611         struct amdgpu_vm *vm = &fpriv->vm;
 612         int i, j;
 613         int r;
 614
 615         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 616                 struct amdgpu_cs_chunk *chunk;
 617                 struct amdgpu_ib *ib;
 618                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 619                 struct amdgpu_ring *ring;
 620
 621                 chunk = &parser->chunks[i];
 622                 ib = &parser->ibs[j];
 623                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 624
 625                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 626                         continue;
 627
 628                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 629                                        chunk_ib->ip_instance, chunk_ib->ring,
 630                                        &ring);
 631                 if (r)
 632                         return r;
 633
 634                 if (ring->funcs->parse_cs) {
 635                         struct amdgpu_bo_va_mapping *m;
 636                         struct amdgpu_bo *aobj = NULL;
 637                         uint64_t offset;
 638                         uint8_t *kptr;
 639
 640                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 641                                                    &aobj);
 642                         if (!aobj) {
 643                                 DRM_ERROR("IB va_start is invalid\n");
 644                                 return -EINVAL;
 645                         }
 646
 647                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 648                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 649                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 650                                 return -EINVAL;
 651                         }
 652
 653                         /* the IB should be reserved at this point */
 654                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 655                         if (r) {
 656                                 return r;
 657                         }
 658
 659                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 660                         kptr += chunk_ib->va_start - offset;
 661
 662                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 663                         if (r) {
 664                                 DRM_ERROR("Failed to get ib !\n");
 665                                 return r;
 666                         }
 667
 668                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 669                         amdgpu_bo_kunmap(aobj);
 670                 } else {
 671                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 672                         if (r) {
 673                                 DRM_ERROR("Failed to get ib !\n");
 674                                 return r;
 675                         }
 676
 677                         ib->gpu_addr = chunk_ib->va_start;
 678                 }
 679
 680                 ib->length_dw = chunk_ib->ib_bytes / 4;
 681                 ib->flags = chunk_ib->flags;
 682                 ib->ctx = parser->ctx;
 683                 j++;
 684         }
 685
 686         if (!parser->num_ibs)
 687                 return 0;
 688
 689         /* add GDS resources to first IB */
 690         if (parser->bo_list) {
 691                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 692                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 693                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 694                 struct amdgpu_ib *ib = &parser->ibs[0];
 695
 696                 if (gds) {
 697                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 698                         ib->gds_size = amdgpu_bo_size(gds);
 699                 }
 700                 if (gws) {
 701                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 702                         ib->gws_size = amdgpu_bo_size(gws);
 703                 }
 704                 if (oa) {
 705                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 706                         ib->oa_size = amdgpu_bo_size(oa);
 707                 }
 708         }
 709         /* wrap the last IB with user fence */
 710         if (parser->uf.bo) {
 711                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 712
 713                 /* UVD & VCE fw doesn't support user fences */
 714                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 715                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 716                         return -EINVAL;
 717
 718                 ib->user = &parser->uf;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 725                                   struct amdgpu_cs_parser *p)
 726 {
 727         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 728         struct amdgpu_ib *ib;
 729         int i, j, r;
 730
 731         if (!p->num_ibs)
 732                 return 0;
 733
 734         /* Add dependencies to first IB */
 735         ib = &p->ibs[0];
 736         for (i = 0; i < p->nchunks; ++i) {
 737                 struct drm_amdgpu_cs_chunk_dep *deps;
 738                 struct amdgpu_cs_chunk *chunk;
 739                 unsigned num_deps;
 740
 741                 chunk = &p->chunks[i];
 742
 743                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 744                         continue;
 745
 746                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 747                 num_deps = chunk->length_dw * 4 /
 748                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 749
 750                 for (j = 0; j < num_deps; ++j) {
 751                         struct amdgpu_ring *ring;
 752                         struct amdgpu_ctx *ctx;
 753                         struct fence *fence;
 754
 755                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 756                                                deps[j].ip_instance,
 757                                                deps[j].ring, &ring);
 758                         if (r)
 759                                 return r;
 760
 761                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 762                         if (ctx == NULL)
 763                                 return -EINVAL;
 764
 765                         fence = amdgpu_ctx_get_fence(ctx, ring,
 766                                                      deps[j].handle);
 767                         if (IS_ERR(fence)) {
 768                                 r = PTR_ERR(fence);
 769                                 amdgpu_ctx_put(ctx);
 770                                 return r;
 771
 772                         } else if (fence) {
 773                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 774                                 fence_put(fence);
 775                                 amdgpu_ctx_put(ctx);
 776                                 if (r)
 777                                         return r;
 778                         }
 779                 }
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int amdgpu_cs_free_job(struct amdgpu_job *job)
 786 {
 787         int i;
 788         if (job->ibs)
 789                 for (i = 0; i < job->num_ibs; i++)
 790                         amdgpu_ib_free(job->adev, &job->ibs[i]);
 791         kfree(job->ibs);
 792         if (job->uf.bo)
 793                 drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base);
 794         return 0;
 795 }
 796
 797 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 798 {
 799         struct amdgpu_device *adev = dev->dev_private;
 800         union drm_amdgpu_cs *cs = data;
 801         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 802         struct amdgpu_vm *vm = &fpriv->vm;
 803         struct amdgpu_cs_parser parser = {};
 804         bool reserved_buffers = false;
 805         int i, r;
 806
 807         if (!adev->accel_working)
 808                 return -EBUSY;
 809
 810         parser.adev = adev;
 811         parser.filp = filp;
 812
 813         r = amdgpu_cs_parser_init(&parser, data);
 814         if (r) {
 815                 DRM_ERROR("Failed to initialize parser !\n");
 816                 amdgpu_cs_parser_fini(&parser, r, false);
 817                 r = amdgpu_cs_handle_lockup(adev, r);
 818                 return r;
 819         }
 820         mutex_lock(&vm->mutex);
 821         r = amdgpu_cs_parser_relocs(&parser);
 822         if (r == -ENOMEM)
 823                 DRM_ERROR("Not enough memory for command submission!\n");
 824         else if (r && r != -ERESTARTSYS)
 825                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 826         else if (!r) {
 827                 reserved_buffers = true;
 828                 r = amdgpu_cs_ib_fill(adev, &parser);
 829         }
 830
 831         if (!r) {
 832                 r = amdgpu_cs_dependencies(adev, &parser);
 833                 if (r)
 834                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 835         }
 836
 837         if (r)
 838                 goto out;
 839
 840         for (i = 0; i < parser.num_ibs; i++)
 841                 trace_amdgpu_cs(&parser, i);
 842
 843         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 844         if (r)
 845                 goto out;
 846
 847         if (amdgpu_enable_scheduler && parser.num_ibs) {
 848                 struct amdgpu_job *job;
 849                 struct amdgpu_ring * ring = parser.ibs->ring;
 850
 851                 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
 852                 if (!job) {
 853                         r = -ENOMEM;
 854                         goto out;
 855                 }
 856
 857                 job->base.sched = &ring->sched;
 858                 job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
 859                 job->adev = parser.adev;
 860                 job->ibs = parser.ibs;
 861                 job->num_ibs = parser.num_ibs;
 862                 job->base.owner = parser.filp;
 863                 mutex_init(&job->job_lock);
 864                 if (job->ibs[job->num_ibs - 1].user) {
 865                         job->uf = parser.uf;
 866                         job->ibs[job->num_ibs - 1].user = &job->uf;
 867                         parser.uf.bo = NULL;
 868                 }
 869
 870                 parser.ibs = NULL;
 871                 parser.num_ibs = 0;
 872
 873                 job->free_job = amdgpu_cs_free_job;
 874                 mutex_lock(&job->job_lock);
 875                 r = amd_sched_entity_push_job(&job->base);
 876                 if (r) {
 877                         mutex_unlock(&job->job_lock);
 878                         amdgpu_cs_free_job(job);
 879                         kfree(job);
 880                         goto out;
 881                 }
 882                 cs->out.handle =
 883                         amdgpu_ctx_add_fence(parser.ctx, ring,
 884                                              &job->base.s_fence->base);
 885                 job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
 886
 887                 list_sort(NULL, &parser.validated, cmp_size_smaller_first);
 888                 ttm_eu_fence_buffer_objects(&parser.ticket,
 889                                 &parser.validated,
 890                                 &job->base.s_fence->base);
 891
 892                 mutex_unlock(&job->job_lock);
 893                 amdgpu_cs_parser_fini_late(&parser);
 894                 mutex_unlock(&vm->mutex);
 895                 return 0;
 896         }
 897
 898         cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
 899 out:
 900         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 901         mutex_unlock(&vm->mutex);
 902         r = amdgpu_cs_handle_lockup(adev, r);
 903         return r;
 904 }
 905
 906 /**
 907  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 908  *
 909  * @dev: drm device
 910  * @data: data from userspace
 911  * @filp: file private
 912  *
 913  * Wait for the command submission identified by handle to finish.
 914  */
 915 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 916                          struct drm_file *filp)
 917 {
 918         union drm_amdgpu_wait_cs *wait = data;
 919         struct amdgpu_device *adev = dev->dev_private;
 920         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 921         struct amdgpu_ring *ring = NULL;
 922         struct amdgpu_ctx *ctx;
 923         struct fence *fence;
 924         long r;
 925
 926         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 927                                wait->in.ring, &ring);
 928         if (r)
 929                 return r;
 930
 931         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 932         if (ctx == NULL)
 933                 return -EINVAL;
 934
 935         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 936         if (IS_ERR(fence))
 937                 r = PTR_ERR(fence);
 938         else if (fence) {
 939                 r = fence_wait_timeout(fence, true, timeout);
 940                 fence_put(fence);
 941         } else
 942                 r = 1;
 943
 944         amdgpu_ctx_put(ctx);
 945         if (r < 0)
 946                 return r;
 947
 948         memset(wait, 0, sizeof(*wait));
 949         wait->out.status = (r == 0);
 950
 951         return 0;
 952 }
 953
 954 /**
 955  * amdgpu_cs_find_bo_va - find bo_va for VM address
 956  *
 957  * @parser: command submission parser context
 958  * @addr: VM address
 959  * @bo: resulting BO of the mapping found
 960  *
 961  * Search the buffer objects in the command submission context for a certain
 962  * virtual memory address. Returns allocation structure when found, NULL
 963  * otherwise.
 964  */
 965 struct amdgpu_bo_va_mapping *
 966 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 967                        uint64_t addr, struct amdgpu_bo **bo)
 968 {
 969         struct amdgpu_bo_list_entry *reloc;
 970         struct amdgpu_bo_va_mapping *mapping;
 971
 972         addr /= AMDGPU_GPU_PAGE_SIZE;
 973
 974         list_for_each_entry(reloc, &parser->validated, tv.head) {
 975                 if (!reloc->bo_va)
 976                         continue;
 977
 978                 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
 979                         if (mapping->it.start > addr ||
 980                             addr > mapping->it.last)
 981                                 continue;
 982
 983                         *bo = reloc->bo_va->bo;
 984                         return mapping;
 985                 }
 986
 987                 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
 988                         if (mapping->it.start > addr ||
 989                             addr > mapping->it.last)
 990                                 continue;
 991
 992                         *bo = reloc->bo_va->bo;
 993                         return mapping;
 994                 }
 995         }
 996
 997         return NULL;
 998 }