drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev,
 238                                          uint32_t supported_device,
 239                                          int *connector_type,
 240                                          struct amdgpu_i2c_bus_rec *i2c_bus,
 241                                          uint16_t *line_mux,
 242                                          struct amdgpu_hpd *hpd)
 243 {
 244         return true;
 245 }
 246
 247 static const int object_connector_convert[] = {
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_DVII,
 250         DRM_MODE_CONNECTOR_DVII,
 251         DRM_MODE_CONNECTOR_DVID,
 252         DRM_MODE_CONNECTOR_DVID,
 253         DRM_MODE_CONNECTOR_VGA,
 254         DRM_MODE_CONNECTOR_Composite,
 255         DRM_MODE_CONNECTOR_SVIDEO,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_Unknown,
 258         DRM_MODE_CONNECTOR_9PinDIN,
 259         DRM_MODE_CONNECTOR_Unknown,
 260         DRM_MODE_CONNECTOR_HDMIA,
 261         DRM_MODE_CONNECTOR_HDMIB,
 262         DRM_MODE_CONNECTOR_LVDS,
 263         DRM_MODE_CONNECTOR_9PinDIN,
 264         DRM_MODE_CONNECTOR_Unknown,
 265         DRM_MODE_CONNECTOR_Unknown,
 266         DRM_MODE_CONNECTOR_Unknown,
 267         DRM_MODE_CONNECTOR_DisplayPort,
 268         DRM_MODE_CONNECTOR_eDP,
 269         DRM_MODE_CONNECTOR_Unknown
 270 };
 271
 272 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 273 {
 274         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 275         struct atom_context *ctx = mode_info->atom_context;
 276         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 277         u16 size, data_offset;
 278         u8 frev, crev;
 279         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 280         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 281         ATOM_OBJECT_TABLE *router_obj;
 282         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 283         ATOM_OBJECT_HEADER *obj_header;
 284         int i, j, k, path_size, device_support;
 285         int connector_type;
 286         u16 conn_id, connector_object_id;
 287         struct amdgpu_i2c_bus_rec ddc_bus;
 288         struct amdgpu_router router;
 289         struct amdgpu_gpio_rec gpio;
 290         struct amdgpu_hpd hpd;
 291
 292         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 293                 return false;
 294
 295         if (crev < 2)
 296                 return false;
 297
 298         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 299         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 300             (ctx->bios + data_offset +
 301              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 302         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 303             (ctx->bios + data_offset +
 304              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 305         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 306             (ctx->bios + data_offset +
 307              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 308         router_obj = (ATOM_OBJECT_TABLE *)
 309                 (ctx->bios + data_offset +
 310                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 311         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 312
 313         path_size = 0;
 314         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 315                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 316                 ATOM_DISPLAY_OBJECT_PATH *path;
 317                 addr += path_size;
 318                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 319                 path_size += le16_to_cpu(path->usSize);
 320
 321                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 322                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 323
 324                         con_obj_id =
 325                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 326                             >> OBJECT_ID_SHIFT;
 327                         con_obj_num =
 328                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 329                             >> ENUM_ID_SHIFT;
 330                         con_obj_type =
 331                             (le16_to_cpu(path->usConnObjectId) &
 332                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 333
 334                         connector_type =
 335                                 object_connector_convert[con_obj_id];
 336                         connector_object_id = con_obj_id;
 337
 338                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 339                                 continue;
 340
 341                         router.ddc_valid = false;
 342                         router.cd_valid = false;
 343                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 344                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 345
 346                                 grph_obj_id =
 347                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 348                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 349                                 grph_obj_num =
 350                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 351                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 352                                 grph_obj_type =
 353                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 354                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 355
 356                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 357                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 358                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 359                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 360                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 361                                                                 (ctx->bios + data_offset +
 362                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 363                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 364                                                         u16 caps = 0;
 365
 366                                                         while (record->ucRecordSize > 0 &&
 367                                                                record->ucRecordType > 0 &&
 368                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 369                                                                 switch (record->ucRecordType) {
 370                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 371                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 372                                                                                 record;
 373                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 374                                                                         break;
 375                                                                 }
 376                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 377                                                                         ((char *)record + record->ucRecordSize);
 378                                                         }
 379                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 380                                                                                     le16_to_cpu(path->usDeviceTag),
 381                                                                                     caps);
 382                                                 }
 383                                         }
 384                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 385                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 386                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 387                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 388                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 389                                                                 (ctx->bios + data_offset +
 390                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 391                                                         ATOM_I2C_RECORD *i2c_record;
 392                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 393                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 394                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 395                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 396                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 397                                                                 (ctx->bios + data_offset +
 398                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 399                                                         u8 *num_dst_objs = (u8 *)
 400                                                                 ((u8 *)router_src_dst_table + 1 +
 401                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 402                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 403                                                         int enum_id;
 404
 405                                                         router.router_id = router_obj_id;
 406                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 407                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 408                                                                     le16_to_cpu(dst_objs[enum_id]))
 409                                                                         break;
 410                                                         }
 411
 412                                                         while (record->ucRecordSize > 0 &&
 413                                                                record->ucRecordType > 0 &&
 414                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 415                                                                 switch (record->ucRecordType) {
 416                                                                 case ATOM_I2C_RECORD_TYPE:
 417                                                                         i2c_record =
 418                                                                                 (ATOM_I2C_RECORD *)
 419                                                                                 record;
 420                                                                         i2c_config =
 421                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 422                                                                                 &i2c_record->sucI2cId;
 423                                                                         router.i2c_info =
 424                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 425                                                                                                        i2c_config->
 426                                                                                                        ucAccess);
 427                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 428                                                                         break;
 429                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 430                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 431                                                                                 record;
 432                                                                         router.ddc_valid = true;
 433                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 434                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 435                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 436                                                                         break;
 437                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 438                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 439                                                                                 record;
 440                                                                         router.cd_valid = true;
 441                                                                         router.cd_mux_type = cd_path->ucMuxType;
 442                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 443                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 444                                                                         break;
 445                                                                 }
 446                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 447                                                                         ((char *)record + record->ucRecordSize);
 448                                                         }
 449                                                 }
 450                                         }
 451                                 }
 452                         }
 453
 454                         /* look up gpio for ddc, hpd */
 455                         ddc_bus.valid = false;
 456                         hpd.hpd = AMDGPU_HPD_NONE;
 457                         if ((le16_to_cpu(path->usDeviceTag) &
 458                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 459                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 460                                         if (le16_to_cpu(path->usConnObjectId) ==
 461                                             le16_to_cpu(con_obj->asObjects[j].
 462                                                         usObjectID)) {
 463                                                 ATOM_COMMON_RECORD_HEADER
 464                                                     *record =
 465                                                     (ATOM_COMMON_RECORD_HEADER
 466                                                      *)
 467                                                     (ctx->bios + data_offset +
 468                                                      le16_to_cpu(con_obj->
 469                                                                  asObjects[j].
 470                                                                  usRecordOffset));
 471                                                 ATOM_I2C_RECORD *i2c_record;
 472                                                 ATOM_HPD_INT_RECORD *hpd_record;
 473                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 474
 475                                                 while (record->ucRecordSize > 0 &&
 476                                                        record->ucRecordType > 0 &&
 477                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 478                                                         switch (record->ucRecordType) {
 479                                                         case ATOM_I2C_RECORD_TYPE:
 480                                                                 i2c_record =
 481                                                                     (ATOM_I2C_RECORD *)
 482                                                                         record;
 483                                                                 i2c_config =
 484                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 485                                                                         &i2c_record->sucI2cId;
 486                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 487                                                                                                  i2c_config->
 488                                                                                                  ucAccess);
 489                                                                 break;
 490                                                         case ATOM_HPD_INT_RECORD_TYPE:
 491                                                                 hpd_record =
 492                                                                         (ATOM_HPD_INT_RECORD *)
 493                                                                         record;
 494                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 495                                                                                           hpd_record->ucHPDIntGPIOID);
 496                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 497                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 498                                                                 break;
 499                                                         }
 500                                                         record =
 501                                                             (ATOM_COMMON_RECORD_HEADER
 502                                                              *) ((char *)record
 503                                                                  +
 504                                                                  record->
 505                                                                  ucRecordSize);
 506                                                 }
 507                                                 break;
 508                                         }
 509                                 }
 510                         }
 511
 512                         /* needed for aux chan transactions */
 513                         ddc_bus.hpd = hpd.hpd;
 514
 515                         conn_id = le16_to_cpu(path->usConnObjectId);
 516
 517                         if (!amdgpu_atombios_apply_quirks
 518                             (adev, le16_to_cpu(path->usDeviceTag), &connector_type,
 519                              &ddc_bus, &conn_id, &hpd))
 520                                 continue;
 521
 522                         amdgpu_display_add_connector(adev,
 523                                                       conn_id,
 524                                                       le16_to_cpu(path->usDeviceTag),
 525                                                       connector_type, &ddc_bus,
 526                                                       connector_object_id,
 527                                                       &hpd,
 528                                                       &router);
 529
 530                 }
 531         }
 532
 533         amdgpu_link_encoder_connector(adev->ddev);
 534
 535         return true;
 536 }
 537
 538 union firmware_info {
 539         ATOM_FIRMWARE_INFO info;
 540         ATOM_FIRMWARE_INFO_V1_2 info_12;
 541         ATOM_FIRMWARE_INFO_V1_3 info_13;
 542         ATOM_FIRMWARE_INFO_V1_4 info_14;
 543         ATOM_FIRMWARE_INFO_V2_1 info_21;
 544         ATOM_FIRMWARE_INFO_V2_2 info_22;
 545 };
 546
 547 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 548 {
 549         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 550         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 551         uint8_t frev, crev;
 552         uint16_t data_offset;
 553         int ret = -EINVAL;
 554
 555         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 556                                    &frev, &crev, &data_offset)) {
 557                 int i;
 558                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 559                 struct amdgpu_pll *spll = &adev->clock.spll;
 560                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 561                 union firmware_info *firmware_info =
 562                         (union firmware_info *)(mode_info->atom_context->bios +
 563                                                 data_offset);
 564                 /* pixel clocks */
 565                 ppll->reference_freq =
 566                     le16_to_cpu(firmware_info->info.usReferenceClock);
 567                 ppll->reference_div = 0;
 568
 569                 ppll->pll_out_min =
 570                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 571                 ppll->pll_out_max =
 572                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 573
 574                 ppll->lcd_pll_out_min =
 575                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 576                 if (ppll->lcd_pll_out_min == 0)
 577                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 578                 ppll->lcd_pll_out_max =
 579                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 580                 if (ppll->lcd_pll_out_max == 0)
 581                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 582
 583                 if (ppll->pll_out_min == 0)
 584                         ppll->pll_out_min = 64800;
 585
 586                 ppll->pll_in_min =
 587                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 588                 ppll->pll_in_max =
 589                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 590
 591                 ppll->min_post_div = 2;
 592                 ppll->max_post_div = 0x7f;
 593                 ppll->min_frac_feedback_div = 0;
 594                 ppll->max_frac_feedback_div = 9;
 595                 ppll->min_ref_div = 2;
 596                 ppll->max_ref_div = 0x3ff;
 597                 ppll->min_feedback_div = 4;
 598                 ppll->max_feedback_div = 0xfff;
 599                 ppll->best_vco = 0;
 600
 601                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 602                         adev->clock.ppll[i] = *ppll;
 603
 604                 /* system clock */
 605                 spll->reference_freq =
 606                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 607                 spll->reference_div = 0;
 608
 609                 spll->pll_out_min =
 610                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 611                 spll->pll_out_max =
 612                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 613
 614                 /* ??? */
 615                 if (spll->pll_out_min == 0)
 616                         spll->pll_out_min = 64800;
 617
 618                 spll->pll_in_min =
 619                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 620                 spll->pll_in_max =
 621                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 622
 623                 spll->min_post_div = 1;
 624                 spll->max_post_div = 1;
 625                 spll->min_ref_div = 2;
 626                 spll->max_ref_div = 0xff;
 627                 spll->min_feedback_div = 4;
 628                 spll->max_feedback_div = 0xff;
 629                 spll->best_vco = 0;
 630
 631                 /* memory clock */
 632                 mpll->reference_freq =
 633                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 634                 mpll->reference_div = 0;
 635
 636                 mpll->pll_out_min =
 637                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 638                 mpll->pll_out_max =
 639                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 640
 641                 /* ??? */
 642                 if (mpll->pll_out_min == 0)
 643                         mpll->pll_out_min = 64800;
 644
 645                 mpll->pll_in_min =
 646                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 647                 mpll->pll_in_max =
 648                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 649
 650                 adev->clock.default_sclk =
 651                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 652                 adev->clock.default_mclk =
 653                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 654
 655                 mpll->min_post_div = 1;
 656                 mpll->max_post_div = 1;
 657                 mpll->min_ref_div = 2;
 658                 mpll->max_ref_div = 0xff;
 659                 mpll->min_feedback_div = 4;
 660                 mpll->max_feedback_div = 0xff;
 661                 mpll->best_vco = 0;
 662
 663                 /* disp clock */
 664                 adev->clock.default_dispclk =
 665                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 666                 /* set a reasonable default for DP */
 667                 if (adev->clock.default_dispclk < 53900) {
 668                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 669                                  adev->clock.default_dispclk / 100);
 670                         adev->clock.default_dispclk = 60000;
 671                 }
 672                 adev->clock.dp_extclk =
 673                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 674                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 675
 676                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 677                 if (adev->clock.max_pixel_clock == 0)
 678                         adev->clock.max_pixel_clock = 40000;
 679
 680                 /* not technically a clock, but... */
 681                 adev->mode_info.firmware_flags =
 682                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 683
 684                 ret = 0;
 685         }
 686
 687         adev->pm.current_sclk = adev->clock.default_sclk;
 688         adev->pm.current_mclk = adev->clock.default_mclk;
 689
 690         return ret;
 691 }
 692
 693 union igp_info {
 694         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 695         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 696         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 697         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 698         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 699         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 700 };
 701
 702 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 703                                                  struct amdgpu_atom_ss *ss,
 704                                                  int id)
 705 {
 706         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 707         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 708         u16 data_offset, size;
 709         union igp_info *igp_info;
 710         u8 frev, crev;
 711         u16 percentage = 0, rate = 0;
 712
 713         /* get any igp specific overrides */
 714         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 715                                    &frev, &crev, &data_offset)) {
 716                 igp_info = (union igp_info *)
 717                         (mode_info->atom_context->bios + data_offset);
 718                 switch (crev) {
 719                 case 6:
 720                         switch (id) {
 721                         case ASIC_INTERNAL_SS_ON_TMDS:
 722                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 723                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 724                                 break;
 725                         case ASIC_INTERNAL_SS_ON_HDMI:
 726                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 727                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 728                                 break;
 729                         case ASIC_INTERNAL_SS_ON_LVDS:
 730                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 731                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 732                                 break;
 733                         }
 734                         break;
 735                 case 7:
 736                         switch (id) {
 737                         case ASIC_INTERNAL_SS_ON_TMDS:
 738                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 739                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 740                                 break;
 741                         case ASIC_INTERNAL_SS_ON_HDMI:
 742                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 743                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 744                                 break;
 745                         case ASIC_INTERNAL_SS_ON_LVDS:
 746                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 747                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 748                                 break;
 749                         }
 750                         break;
 751                 case 8:
 752                         switch (id) {
 753                         case ASIC_INTERNAL_SS_ON_TMDS:
 754                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 755                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 756                                 break;
 757                         case ASIC_INTERNAL_SS_ON_HDMI:
 758                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 759                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 760                                 break;
 761                         case ASIC_INTERNAL_SS_ON_LVDS:
 762                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 763                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 764                                 break;
 765                         }
 766                         break;
 767                 case 9:
 768                         switch (id) {
 769                         case ASIC_INTERNAL_SS_ON_TMDS:
 770                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 771                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 772                                 break;
 773                         case ASIC_INTERNAL_SS_ON_HDMI:
 774                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 775                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 776                                 break;
 777                         case ASIC_INTERNAL_SS_ON_LVDS:
 778                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 779                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 780                                 break;
 781                         }
 782                         break;
 783                 default:
 784                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 785                         break;
 786                 }
 787                 if (percentage)
 788                         ss->percentage = percentage;
 789                 if (rate)
 790                         ss->rate = rate;
 791         }
 792 }
 793
 794 union asic_ss_info {
 795         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 796         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 797         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 798 };
 799
 800 union asic_ss_assignment {
 801         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 802         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 803         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 804 };
 805
 806 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 807                                       struct amdgpu_atom_ss *ss,
 808                                       int id, u32 clock)
 809 {
 810         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 811         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 812         uint16_t data_offset, size;
 813         union asic_ss_info *ss_info;
 814         union asic_ss_assignment *ss_assign;
 815         uint8_t frev, crev;
 816         int i, num_indices;
 817
 818         if (id == ASIC_INTERNAL_MEMORY_SS) {
 819                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 820                         return false;
 821         }
 822         if (id == ASIC_INTERNAL_ENGINE_SS) {
 823                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 824                         return false;
 825         }
 826
 827         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 828         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 829                                    &frev, &crev, &data_offset)) {
 830
 831                 ss_info =
 832                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 833
 834                 switch (frev) {
 835                 case 1:
 836                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 837                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 838
 839                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 840                         for (i = 0; i < num_indices; i++) {
 841                                 if ((ss_assign->v1.ucClockIndication == id) &&
 842                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 843                                         ss->percentage =
 844                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 845                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 846                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 847                                         ss->percentage_divider = 100;
 848                                         return true;
 849                                 }
 850                                 ss_assign = (union asic_ss_assignment *)
 851                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 852                         }
 853                         break;
 854                 case 2:
 855                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 856                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 857                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 858                         for (i = 0; i < num_indices; i++) {
 859                                 if ((ss_assign->v2.ucClockIndication == id) &&
 860                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 861                                         ss->percentage =
 862                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 863                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 864                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 865                                         ss->percentage_divider = 100;
 866                                         if ((crev == 2) &&
 867                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 868                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 869                                                 ss->rate /= 100;
 870                                         return true;
 871                                 }
 872                                 ss_assign = (union asic_ss_assignment *)
 873                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 874                         }
 875                         break;
 876                 case 3:
 877                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 878                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 879                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 880                         for (i = 0; i < num_indices; i++) {
 881                                 if ((ss_assign->v3.ucClockIndication == id) &&
 882                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 883                                         ss->percentage =
 884                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 885                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 886                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 887                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 888                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 889                                                 ss->percentage_divider = 1000;
 890                                         else
 891                                                 ss->percentage_divider = 100;
 892                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 893                                             (id == ASIC_INTERNAL_MEMORY_SS))
 894                                                 ss->rate /= 100;
 895                                         if (adev->flags & AMD_IS_APU)
 896                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 897                                         return true;
 898                                 }
 899                                 ss_assign = (union asic_ss_assignment *)
 900                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 901                         }
 902                         break;
 903                 default:
 904                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 905                         break;
 906                 }
 907
 908         }
 909         return false;
 910 }
 911
 912 union get_clock_dividers {
 913         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 914         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 915         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 916         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 917         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 918         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 919         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 920 };
 921
 922 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 923                                        u8 clock_type,
 924                                        u32 clock,
 925                                        bool strobe_mode,
 926                                        struct atom_clock_dividers *dividers)
 927 {
 928         union get_clock_dividers args;
 929         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 930         u8 frev, crev;
 931
 932         memset(&args, 0, sizeof(args));
 933         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 934
 935         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 936                 return -EINVAL;
 937
 938         switch (crev) {
 939         case 4:
 940                 /* fusion */
 941                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
 942
 943                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 944
 945                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
 946                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
 947                 break;
 948         case 6:
 949                 /* CI */
 950                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
 951                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
 952                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
 953
 954                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 955
 956                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
 957                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
 958                 dividers->ref_div = args.v6_out.ucPllRefDiv;
 959                 dividers->post_div = args.v6_out.ucPllPostDiv;
 960                 dividers->flags = args.v6_out.ucPllCntlFlag;
 961                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
 962                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
 963                 break;
 964         default:
 965                 return -EINVAL;
 966         }
 967         return 0;
 968 }
 969
 970 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
 971                                             u32 clock,
 972                                             bool strobe_mode,
 973                                             struct atom_mpll_param *mpll_param)
 974 {
 975         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
 976         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
 977         u8 frev, crev;
 978
 979         memset(&args, 0, sizeof(args));
 980         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
 981
 982         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 983                 return -EINVAL;
 984
 985         switch (frev) {
 986         case 2:
 987                 switch (crev) {
 988                 case 1:
 989                         /* SI */
 990                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
 991                         args.ucInputFlag = 0;
 992                         if (strobe_mode)
 993                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
 994
 995                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 996
 997                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
 998                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
 999                         mpll_param->post_div = args.ucPostDiv;
1000                         mpll_param->dll_speed = args.ucDllSpeed;
1001                         mpll_param->bwcntl = args.ucBWCntl;
1002                         mpll_param->vco_mode =
1003                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1004                         mpll_param->yclk_sel =
1005                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1006                         mpll_param->qdr =
1007                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1008                         mpll_param->half_rate =
1009                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1010                         break;
1011                 default:
1012                         return -EINVAL;
1013                 }
1014                 break;
1015         default:
1016                 return -EINVAL;
1017         }
1018         return 0;
1019 }
1020
1021 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1022 {
1023         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1024         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1025
1026         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1027         return le32_to_cpu(args.ulReturnEngineClock);
1028 }
1029
1030 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1031 {
1032         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1033         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1034
1035         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1036         return le32_to_cpu(args.ulReturnMemoryClock);
1037 }
1038
1039 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1040                                       uint32_t eng_clock)
1041 {
1042         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1043         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1044
1045         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1046
1047         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1048 }
1049
1050 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1051                                       uint32_t mem_clock)
1052 {
1053         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1054         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1055
1056         if (adev->flags & AMD_IS_APU)
1057                 return;
1058
1059         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1060
1061         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1062 }
1063
1064 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1065                                              u32 eng_clock, u32 mem_clock)
1066 {
1067         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1068         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1069         u32 tmp;
1070
1071         memset(&args, 0, sizeof(args));
1072
1073         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1074         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1075
1076         args.ulTargetEngineClock = cpu_to_le32(tmp);
1077         if (mem_clock)
1078                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1079
1080         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1081 }
1082
1083 union set_voltage {
1084         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1085         struct _SET_VOLTAGE_PARAMETERS v1;
1086         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1087         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1088 };
1089
1090 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1091                                  u16 voltage_level,
1092                                  u8 voltage_type)
1093 {
1094         union set_voltage args;
1095         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1096         u8 frev, crev, volt_index = voltage_level;
1097
1098         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1099                 return;
1100
1101         /* 0xff01 is a flag rather then an actual voltage */
1102         if (voltage_level == 0xff01)
1103                 return;
1104
1105         switch (crev) {
1106         case 1:
1107                 args.v1.ucVoltageType = voltage_type;
1108                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1109                 args.v1.ucVoltageIndex = volt_index;
1110                 break;
1111         case 2:
1112                 args.v2.ucVoltageType = voltage_type;
1113                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1114                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1115                 break;
1116         case 3:
1117                 args.v3.ucVoltageType = voltage_type;
1118                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1119                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1120                 break;
1121         default:
1122                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1123                 return;
1124         }
1125
1126         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1127 }
1128
1129 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1130                                               u16 *leakage_id)
1131 {
1132         union set_voltage args;
1133         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1134         u8 frev, crev;
1135
1136         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1137                 return -EINVAL;
1138
1139         switch (crev) {
1140         case 3:
1141         case 4:
1142                 args.v3.ucVoltageType = 0;
1143                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1144                 args.v3.usVoltageLevel = 0;
1145
1146                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1147
1148                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1149                 break;
1150         default:
1151                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1152                 return -EINVAL;
1153         }
1154
1155         return 0;
1156 }
1157
1158 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1159                                                              u16 *vddc, u16 *vddci,
1160                                                              u16 virtual_voltage_id,
1161                                                              u16 vbios_voltage_id)
1162 {
1163         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1164         u8 frev, crev;
1165         u16 data_offset, size;
1166         int i, j;
1167         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1168         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1169
1170         *vddc = 0;
1171         *vddci = 0;
1172
1173         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1174                                     &frev, &crev, &data_offset))
1175                 return -EINVAL;
1176
1177         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1178                 (adev->mode_info.atom_context->bios + data_offset);
1179
1180         switch (frev) {
1181         case 1:
1182                 return -EINVAL;
1183         case 2:
1184                 switch (crev) {
1185                 case 1:
1186                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1187                                 return -EINVAL;
1188                         leakage_bin = (u16 *)
1189                                 (adev->mode_info.atom_context->bios + data_offset +
1190                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1191                         vddc_id_buf = (u16 *)
1192                                 (adev->mode_info.atom_context->bios + data_offset +
1193                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1194                         vddc_buf = (u16 *)
1195                                 (adev->mode_info.atom_context->bios + data_offset +
1196                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1197                         vddci_id_buf = (u16 *)
1198                                 (adev->mode_info.atom_context->bios + data_offset +
1199                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1200                         vddci_buf = (u16 *)
1201                                 (adev->mode_info.atom_context->bios + data_offset +
1202                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1203
1204                         if (profile->ucElbVDDC_Num > 0) {
1205                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1206                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1207                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1208                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1209                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1210                                                                 break;
1211                                                         }
1212                                                 }
1213                                                 break;
1214                                         }
1215                                 }
1216                         }
1217                         if (profile->ucElbVDDCI_Num > 0) {
1218                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1219                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1220                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1221                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1222                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1223                                                                 break;
1224                                                         }
1225                                                 }
1226                                                 break;
1227                                         }
1228                                 }
1229                         }
1230                         break;
1231                 default:
1232                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1233                         return -EINVAL;
1234                 }
1235                 break;
1236         default:
1237                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1238                 return -EINVAL;
1239         }
1240
1241         return 0;
1242 }
1243
1244 union get_voltage_info {
1245         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1246         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1247 };
1248
1249 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1250                                     u16 virtual_voltage_id,
1251                                     u16 *voltage)
1252 {
1253         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1254         u32 entry_id;
1255         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1256         union get_voltage_info args;
1257
1258         for (entry_id = 0; entry_id < count; entry_id++) {
1259                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1260                     virtual_voltage_id)
1261                         break;
1262         }
1263
1264         if (entry_id >= count)
1265                 return -EINVAL;
1266
1267         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1268         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1269         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1270         args.in.ulSCLKFreq =
1271                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1272
1273         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1274
1275         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1276
1277         return 0;
1278 }
1279
1280 union voltage_object_info {
1281         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1282         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1283         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1284 };
1285
1286 union voltage_object {
1287         struct _ATOM_VOLTAGE_OBJECT v1;
1288         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1289         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1290 };
1291
1292
1293 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1294                                                                         u8 voltage_type, u8 voltage_mode)
1295 {
1296         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1297         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1298         u8 *start = (u8*)v3;
1299
1300         while (offset < size) {
1301                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1302                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1303                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1304                         return vo;
1305                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1306         }
1307         return NULL;
1308 }
1309
1310 bool
1311 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1312                                 u8 voltage_type, u8 voltage_mode)
1313 {
1314         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1315         u8 frev, crev;
1316         u16 data_offset, size;
1317         union voltage_object_info *voltage_info;
1318
1319         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1320                                    &frev, &crev, &data_offset)) {
1321                 voltage_info = (union voltage_object_info *)
1322                         (adev->mode_info.atom_context->bios + data_offset);
1323
1324                 switch (frev) {
1325                 case 3:
1326                         switch (crev) {
1327                         case 1:
1328                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1329                                                                   voltage_type, voltage_mode))
1330                                         return true;
1331                                 break;
1332                         default:
1333                                 DRM_ERROR("unknown voltage object table\n");
1334                                 return false;
1335                         }
1336                         break;
1337                 default:
1338                         DRM_ERROR("unknown voltage object table\n");
1339                         return false;
1340                 }
1341
1342         }
1343         return false;
1344 }
1345
1346 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1347                                       u8 voltage_type, u8 voltage_mode,
1348                                       struct atom_voltage_table *voltage_table)
1349 {
1350         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1351         u8 frev, crev;
1352         u16 data_offset, size;
1353         int i;
1354         union voltage_object_info *voltage_info;
1355         union voltage_object *voltage_object = NULL;
1356
1357         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1358                                    &frev, &crev, &data_offset)) {
1359                 voltage_info = (union voltage_object_info *)
1360                         (adev->mode_info.atom_context->bios + data_offset);
1361
1362                 switch (frev) {
1363                 case 3:
1364                         switch (crev) {
1365                         case 1:
1366                                 voltage_object = (union voltage_object *)
1367                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1368                                                                       voltage_type, voltage_mode);
1369                                 if (voltage_object) {
1370                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1371                                                 &voltage_object->v3.asGpioVoltageObj;
1372                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1373                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1374                                                 return -EINVAL;
1375                                         lut = &gpio->asVolGpioLut[0];
1376                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1377                                                 voltage_table->entries[i].value =
1378                                                         le16_to_cpu(lut->usVoltageValue);
1379                                                 voltage_table->entries[i].smio_low =
1380                                                         le32_to_cpu(lut->ulVoltageId);
1381                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1382                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1383                                         }
1384                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1385                                         voltage_table->count = gpio->ucGpioEntryNum;
1386                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1387                                         return 0;
1388                                 }
1389                                 break;
1390                         default:
1391                                 DRM_ERROR("unknown voltage object table\n");
1392                                 return -EINVAL;
1393                         }
1394                         break;
1395                 default:
1396                         DRM_ERROR("unknown voltage object table\n");
1397                         return -EINVAL;
1398                 }
1399         }
1400         return -EINVAL;
1401 }
1402
1403 union vram_info {
1404         struct _ATOM_VRAM_INFO_V3 v1_3;
1405         struct _ATOM_VRAM_INFO_V4 v1_4;
1406         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1407 };
1408
1409 #define MEM_ID_MASK           0xff000000
1410 #define MEM_ID_SHIFT          24
1411 #define CLOCK_RANGE_MASK      0x00ffffff
1412 #define CLOCK_RANGE_SHIFT     0
1413 #define LOW_NIBBLE_MASK       0xf
1414 #define DATA_EQU_PREV         0
1415 #define DATA_FROM_TABLE       4
1416
1417 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1418                                       u8 module_index,
1419                                       struct atom_mc_reg_table *reg_table)
1420 {
1421         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1422         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1423         u32 i = 0, j;
1424         u16 data_offset, size;
1425         union vram_info *vram_info;
1426
1427         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1428
1429         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1430                                    &frev, &crev, &data_offset)) {
1431                 vram_info = (union vram_info *)
1432                         (adev->mode_info.atom_context->bios + data_offset);
1433                 switch (frev) {
1434                 case 1:
1435                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1436                         return -EINVAL;
1437                 case 2:
1438                         switch (crev) {
1439                         case 1:
1440                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1441                                         ATOM_INIT_REG_BLOCK *reg_block =
1442                                                 (ATOM_INIT_REG_BLOCK *)
1443                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1444                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1445                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1446                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1447                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1448                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1449                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1450                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1451                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1452                                                 return -EINVAL;
1453                                         while (i < num_entries) {
1454                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1455                                                         break;
1456                                                 reg_table->mc_reg_address[i].s1 =
1457                                                         (u16)(le16_to_cpu(format->usRegIndex));
1458                                                 reg_table->mc_reg_address[i].pre_reg_data =
1459                                                         (u8)(format->ucPreRegDataLength);
1460                                                 i++;
1461                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1462                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1463                                         }
1464                                         reg_table->last = i;
1465                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1466                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1467                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1468                                                                 >> MEM_ID_SHIFT);
1469                                                 if (module_index == t_mem_id) {
1470                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1471                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1472                                                                       >> CLOCK_RANGE_SHIFT);
1473                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1474                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1475                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1476                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1477                                                                         j++;
1478                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1479                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1480                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1481                                                                 }
1482                                                         }
1483                                                         num_ranges++;
1484                                                 }
1485                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1486                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1487                                         }
1488                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1489                                                 return -EINVAL;
1490                                         reg_table->num_entries = num_ranges;
1491                                 } else
1492                                         return -EINVAL;
1493                                 break;
1494                         default:
1495                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1496                                 return -EINVAL;
1497                         }
1498                         break;
1499                 default:
1500                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1501                         return -EINVAL;
1502                 }
1503                 return 0;
1504         }
1505         return -EINVAL;
1506 }
1507
1508 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1509 {
1510         uint32_t bios_6_scratch;
1511
1512         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1513
1514         if (lock) {
1515                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1516                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1517         } else {
1518                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1519                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1520         }
1521
1522         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1523 }
1524
1525 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1526 {
1527         uint32_t bios_2_scratch, bios_6_scratch;
1528
1529         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1530         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1531
1532         /* let the bios control the backlight */
1533         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1534
1535         /* tell the bios not to handle mode switching */
1536         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1537
1538         /* clear the vbios dpms state */
1539         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1540
1541         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1542         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1543 }
1544
1545 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1546 {
1547         int i;
1548
1549         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1550                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1551 }
1552
1553 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1554 {
1555         int i;
1556
1557         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1558                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1559 }
1560
1561 /* Atom needs data in little endian format
1562  * so swap as appropriate when copying data to
1563  * or from atom. Note that atom operates on
1564  * dw units.
1565  */
1566 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1567 {
1568 #ifdef __BIG_ENDIAN
1569         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1570         u32 *dst32, *src32;
1571         int i;
1572
1573         memcpy(src_tmp, src, num_bytes);
1574         src32 = (u32 *)src_tmp;
1575         dst32 = (u32 *)dst_tmp;
1576         if (to_le) {
1577                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1578                         dst32[i] = cpu_to_le32(src32[i]);
1579                 memcpy(dst, dst_tmp, num_bytes);
1580         } else {
1581                 u8 dws = num_bytes & ~3;
1582                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1583                         dst32[i] = le32_to_cpu(src32[i]);
1584                 memcpy(dst, dst_tmp, dws);
1585                 if (num_bytes % 4) {
1586                         for (i = 0; i < (num_bytes % 4); i++)
1587                                 dst[dws+i] = dst_tmp[dws+i];
1588                 }
1589         }
1590 #else
1591         memcpy(dst, src, num_bytes);
1592 #endif
1593 }