1 /*----------------------------------------------------------------------------
3 * The confidential and proprietary information contained in this file may
4 * only be used by a person authorised under and to the extent permitted
5 * by a subsisting licensing agreement from ARM Limited.
7 * (C) COPYRIGHT 2008-2009,2011-2013 ARM Limited.
10 * This entire notice must be reproduced on all copies of this file
11 * and copies of this file may only be made by a person if such person is
12 * permitted to do so under the terms of a subsisting license agreement
15 * Modified : $Date: 2013-08-01 18:15:13 +0100 (Thu, 01 Aug 2013) $
16 * Revision : $Revision: 66689 $
18 *-----------------------------------------------------------------------------*/
22 BRIEF DESCRIPTION, PURPOSE AND STRATEGY
23 =======================================
25 This test checks that the GPU's different power domains can be turned on and off.
27 It makes sure the power on or off status corresponds to the relevant domain's READY status.
30 DEBUG HINTS IN CASE OF FAILURE
31 ===========================
32 a) Check the APB bus connections as this is the bus that is used to communicate with the Job manager.
33 b) Check that the GPU's reset signal is not asserted.
34 c) Check that the GPU input clock is toggling as expected.
35 d) Check that the DFT signals are disabled.
36 e) Check that MBIST is disabled.
41 #include "MaliDefines-t760.h"
43 int RunMaliTest_sim4_t760_part0 (void);
46 static int Mali_test_reg(int unit, int core, int regnum, int read_mask, int write_mask, int reset_value, int access);
48 int RunMaliTest_sim4_t760 (int *base) {
51 RunMaliTest_sim4_t760_part0();
55 int RunMaliTest_sim4_t760_part0 (void) {
58 int gpuid, num_cores, l2_size, axi_width, i, as_present, js_present, core_bitmap;
60 printf("RUNNING TEST: sim4\n");
61 printf(" Purpose: Check APB register accesses\n");
62 printf(" Will check register read/write and reset value\n");
64 // Get current configuration to allow testing all registers
65 gpuid = Mali_RdReg(0x20, 0, 0x0000);
66 core_bitmap = Mali_RdReg(0x20, 0, 0x0100);
67 l2_size = ((Mali_RdReg(0x20, 0, 0x0004) >> 16) & 0xFF);
68 axi_width = (1 <<((Mali_RdReg(0x20, 0, 0x0004) >> 24) & 0xFF));
69 as_present = Mali_RdReg(0x20, 0, 0x0018);
70 js_present = Mali_RdReg(0x20, 0, 0x001c);
78 printf("Selected configuration:\n");
79 printf(" Bus width: %d\n", axi_width);
80 printf(" Number of shader cores: %d\n", num_cores);
81 printf(" L2 cache size: %d kB\n", ((1<<l2_size)/1024));
83 res |= Mali_test_reg(0, 0, 0x000, 0xffff0000, 0xffff0000, GPU_ID_VALUE, 1); /* GPU_ID */
84 res |= Mali_test_reg(0, 0, 0x100, 0xffffffff, 0xffffffff, core_bitmap, 1); /* SHADER_PRESENT_LO */
85 res |= Mali_test_reg(0, 0, 0x110, 0xffffffff, 0xffffffff, 0x00000001, 1); /* TILER_PRESENT_LO */
88 /* T760 has only one logical L2C */
89 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000001, 1); /* L2_PRESENT_LO */
92 { /* T608 MP6 and T608 MP8 have two L2Cs*/
93 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000011, 1); /* L2_PRESENT_LO */
97 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000001, 1); /* L2_PRESENT_LO */
101 res |= Mali_test_reg(0, 0, 0x140, 0xffffffff, 0xffffffff, 0x00000000, 1); /* SHADER_READY_LO */
102 res |= Mali_test_reg(0, 0, 0x150, 0xffffffff, 0xffffffff, 0x00000000, 1); /* TILER_READY_LO */
103 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 0x00000000, 1); /* L2_READY_LO */
104 for(i=0; i<num_cores; i++) {
105 printf("Power on/off shader core #%d\n", i);
106 Mali_WrReg(0, 0, 0x180, (1<<i)); /* SHADER_PWRON_LO */
107 while( Mali_RdReg(0, 0, 0x200) ) {}
108 res |= Mali_test_reg(0, 0, 0x140, 0xffffffff, 0xffffffff, (1<<i), 1); /* SHADER_READY_LO */
109 Mali_WrReg(0, 0, 0x1c0, (1<<i)); /* SHADER_PWROFF_LO */
110 while( Mali_RdReg(0, 0, 0x200) ) {}
111 res |= Mali_test_reg(0, 0, 0x140, 0xffffffff, 0xffffffff, 0, 1); /* SHADER_READY_LO */
114 printf("Power on/off tiler\n", i);
115 Mali_WrReg(0, 0, 0x190, 1); /* TILER_PWRON_LO */
116 while( Mali_RdReg(0, 0, 0x210) ) {}
117 res |= Mali_test_reg(0, 0, 0x150, 0xffffffff, 0xffffffff, 1, 1); /* TILER_READY_LO */
118 Mali_WrReg(0, 0, 0x1d0, 1); /* TILER_PWROFF_LO */
119 while( Mali_RdReg(0, 0, 0x210) ) {}
120 res |= Mali_test_reg(0, 0, 0x150, 0xffffffff, 0xffffffff, 0, 1); /* TILER_READY_LO */
122 printf("Power on/off L2\n", i);
124 /* T760 has only one logical L2C */
125 Mali_WrReg(0, 0, 0x1a0, 1); /* L2_PWRON_LO */
126 while( Mali_RdReg(0, 0, 0x220) ) {}
127 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 1, 1); /* L2_READY_LO */
128 Mali_WrReg(0, 0, 0x1e0, 1); /* L2_PWROFF_LO */
129 while( Mali_RdReg(0, 0, 0x220) ) {}
130 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 0, 1); /* L2_READY_LO */
133 { /* T608 MP6 and T608 MP8 have two L2Cs*/
134 Mali_WrReg(0, 0, 0x1a0, 17); /* L2_PWRON_LO */
135 while( Mali_RdReg(0, 0, 0x220) ) {}
136 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 17, 1); /* L2_READY_LO */
137 Mali_WrReg(0, 0, 0x1e0, 17); /* L2_PWROFF_LO */
138 while( Mali_RdReg(0, 0, 0x220) ) {}
139 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 0, 1); /* L2_READY_LO */
143 Mali_WrReg(0, 0, 0x1a0, 1); /* L2_PWRON_LO */
144 while( Mali_RdReg(0, 0, 0x220) ) {}
145 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 1, 1); /* L2_READY_LO */
146 Mali_WrReg(0, 0, 0x1e0, 1); /* L2_PWROFF_LO */
147 while( Mali_RdReg(0, 0, 0x220) ) {}
148 res |= Mali_test_reg(0, 0, 0x160, 0xffffffff, 0xffffffff, 0, 1); /* L2_READY_LO */
162 static int Mali_test_reg(int unit, int core, int regnum, int read_mask, int write_mask, int reset_value, int access) {
163 int value = Mali_RdReg(unit, core, regnum);
164 if( value != reset_value ) {
165 printf("FAILURE: Wrong reset value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x\n",
166 (unit<<28)+(core<<16)+regnum, value, reset_value);
170 Mali_WrReg(unit, core, regnum, (0xffffffff & write_mask));
171 value = Mali_RdReg(unit, core, regnum) & read_mask;
172 if( value != (0xffffffff & write_mask & read_mask) ) {
173 printf("FAILURE: Wrong value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x\n",
174 (unit<<28)+(core<<16)+regnum, value, (0xffffffff & write_mask & read_mask));
177 Mali_WrReg(unit, core, regnum, (0x12345678 & write_mask));
178 value = Mali_RdReg(unit, core, regnum) & read_mask;
179 if( value != (0x12345678 & write_mask & read_mask) ) {
180 printf("FAILURE: Wrong value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x\n",
181 (unit<<28)+(core<<16)+regnum, value, (0x12345678 & write_mask & read_mask));
185 printf("Register %08x: Success!\n", (unit<<28)+(core<<16)+regnum);