1 /*----------------------------------------------------------------------------
3 * The confidential and proprietary information contained in this file may
4 * only be used by a person authorised under and to the extent permitted
5 * by a subsisting licensing agreement from ARM Limited.
7 * (C) COPYRIGHT 2008-2009,2011-2013 ARM Limited.
10 * This entire notice must be reproduced on all copies of this file
11 * and copies of this file may only be made by a person if such person is
12 * permitted to do so under the terms of a subsisting license agreement
15 * Modified : $Date: 2013-08-01 18:15:13 +0100 (Thu, 01 Aug 2013) $
16 * Revision : $Revision: 66689 $
18 *-----------------------------------------------------------------------------*/
22 BRIEF DESCRIPTION, PURPOSE AND STRATEGY
23 =======================================
25 This test performs a basic check on the GPU's ability to access external memory on its ACE-Lite port.
27 A Null job descriptor is placed in memory which is then run by the GPU. The status of the job is written back to memory (each job descriptor has a status field).
29 On successful completion of the job, a job interrupt is triggered and the test is allowed to complete.
33 DEBUG HINTS IN CASE OF FAILURE
34 ===========================
35 a) Check the APB bus connections as this is the bus that is used to communicate with the Job manager.
36 b) Check that the GPU's reset signal is not asserted.
37 c) Check that the GPU input clock is toggling as expected.
38 d) Check that the DFT signals are disabled.
39 e) Check that MBIST is disabled.
40 f) Check every memory accesses from the GPU completes correctly.
41 g) Check the GPU interrupt signal IRQGPU is correctly connected (sim2 should pass if this is okay).
42 h) Check the GPU interrupt signal IRQMMU is correctly connected (sim2 should pass if this is okay).
43 i) Check the GPU interrupt signal IRQJOB is correctly connected (sim2 should pass if this is okay).
48 #include "MaliDefines-t760.h"
50 #include "sim3_t760_check_0_a.h"
51 #include "sim3_t760_mem_0.h"
53 int Check_sim3_t760_check_0_a (struct t_sim3_t760_mem_0 *p);
55 int RunMaliTest_sim3_t760_part0 (void);
56 int RunMaliTest_sim3_t760_part1 (void);
58 static volatile struct t_sim3_t760_mem_0 *malidata_0;
61 int RunMaliTest_sim3_t760 (int *base) {
65 RunMaliTest_sim3_t760_part0();
66 RunMaliTest_sim3_t760_part1();
71 int RunMaliTest_sim3_t760_part0 (void) {
74 int gpuid, num_cores, l2_size, axi_width, i, as_present, js_present, core_bitmap;
76 printf("RUNNING TEST: sim3\n");
77 printf(" Purpose: Check AXI connectivity\n");
78 printf(" Will run a simple NULL job which reads and writes data to memory.\n");
80 // Get current configuration to allow testing all registers
81 gpuid = Mali_RdReg(0x20, 0, 0x0000);
82 core_bitmap = Mali_RdReg(0x20, 0, 0x0100);
83 l2_size = ((Mali_RdReg(0x20, 0, 0x0004) >> 16) & 0xFF);
84 axi_width = (1 <<((Mali_RdReg(0x20, 0, 0x0004) >> 24) & 0xFF));
85 as_present = Mali_RdReg(0x20, 0, 0x0018);
86 js_present = Mali_RdReg(0x20, 0, 0x001c);
94 printf("Selected configuration:\n");
95 printf(" Bus width: %d\n", axi_width);
96 printf(" Number of shader cores: %d\n", num_cores);
97 printf(" L2 cache size: %d kB\n", ((1<<l2_size)/1024));
100 printk("JOB_IRQ_CLEAR is %x\n", JOB_IRQ_CLEAR);
101 Mali_WrReg(0x20,0x0,JOB_IRQ_CLEAR,0xFFFFFFFF);
102 Mali_WrReg(0x20,0x0,JOB_IRQ_MASK,0xFFFFFFFF);
103 Mali_WrReg(0x20,0x0,JS1_HEAD_NEXT_LO,0xFFFFFFFF);
104 Mali_WrReg(0x20,0x0,TILER_PWRON_LO,0xFFFFFFFF);
105 Mali_WrReg(0x20,0x0,JS1_CONFIG_NEXT,0x00001000);
106 Mali_WrReg(0x20,0x0,JS1_HEAD_NEXT_LO,0x00001000);
109 Mali_WrReg(0x20,0x0,JS1_AFFINITY_NEXT_LO,0x0000000F);
113 Mali_WrReg(0x20,0x0,JS1_AFFINITY_NEXT_LO,0xFFFFFFFF);
115 //(struct t_sim3_t760_mem_0 *)malidata_0 = Mali_LdMem(&sim3_t760_mem_0,sizeof(struct t_sim3_t760_mem_0),(int)sim3_t760_mem_0.ttb);
117 malidata_0 = (struct t_sim3_t760_mem_0 *)Mali_LdMem(&sim3_t760_mem_0,sizeof(struct t_sim3_t760_mem_0),(int)sim3_t760_mem_0.ttb);
118 /* Enable optional performance counting */
119 Mali_InitPerfCounters();
120 Mali_WrReg(0x20,0x0,GPU_IRQ_CLEAR,0xFFFFFFFF);
121 Mali_WrReg(0x20,0x0,GPU_IRQ_MASK,0x00000000);
122 Mali_WrReg(0x20,0x0,JS1_COMMAND_NEXT,0x00000001);
130 int RunMaliTest_sim3_t760_part1 (void) {
132 int have_interrupts = 0;
133 /* Check for any interrupt */
134 have_interrupts = Mali_InterruptCheck(0xFFFFFFFF,0xFFFFFFFF);
135 if (!have_interrupts) {
139 Mali_ReadPerfCounters();
140 //Mali_JobPartDone();
141 Mali_CheckReg(32, 0, 0x100c, 0x00000002);
142 res |= Check_sim3_t760_check_0_a(malidata_0);
144 Mali_MaskAllInterrupts();
149 int Check_sim3_t760_check_0_a (struct t_sim3_t760_mem_0 *p) {
150 struct t_CheckData_sim3_t760_check_0_a *r = &CheckData_sim3_t760_check_0_a;
152 printk("Performing data check of 32 bytes\n");
154 res |= Mali_MemCmp(p->data_00001000, 0x00001000, r->data_00001000, 0, 0x008);
155 /* Return -1 if a compare fail */
156 if (res) { return -1; };
157 printk("Check okay \n");