1 /*----------------------------------------------------------------------------
3 * The confidential and proprietary information contained in this file may
4 * only be used by a person authorised under and to the extent permitted
5 * by a subsisting licensing agreement from ARM Limited.
7 * (C) COPYRIGHT 2008-2009,2011-2013 ARM Limited.
10 * This entire notice must be reproduced on all copies of this file
11 * and copies of this file may only be made by a person if such person is
12 * permitted to do so under the terms of a subsisting license agreement
15 * Modified : $Date: 2013-08-01 18:15:13 +0100 (Thu, 01 Aug 2013) $
16 * Revision : $Revision: 66689 $
18 *-----------------------------------------------------------------------------*/
22 BRIEF DESCRIPTION, PURPOSE AND STRATEGY
23 =======================================
25 This test checks that the interrupts are correctly connected by directly writing to their RAW status registers.
28 DEBUG HINTS IN CASE OF FAILURE
29 ===========================
30 a) Check the APB bus connections as this is the bus that is used to communicate with the Job manager.
31 b) Check that the GPU's reset signal is not asserted.
32 c) Check that the GPU input clock is toggling as expected.
33 d) Check that the DFT signals are disabled.
34 e) Check that MBIST is disabled.
35 f) Check the GPU interrupt signals are connected correctly i.e. IRQGPU, IRQMMU and IRQJOB.
40 #include "MaliDefines-t760.h"
43 int RunMaliTest_sim2_t760_part0 (void);
44 int RunMaliTest_sim2_t760_part1 (void);
45 int RunMaliTest_sim2_t760_part2 (void);
46 int RunMaliTest_sim2_t760_part3 (void);
50 int RunMaliTest_sim2_t760 (int *base) {
53 RunMaliTest_sim2_t760_part0();
54 RunMaliTest_sim2_t760_part1();
55 RunMaliTest_sim2_t760_part2();
56 RunMaliTest_sim2_t760_part3();
62 int RunMaliTest_sim2_t760_part0 (void) {
65 int gpuid, num_cores, l2_size, axi_width, i, as_present, js_present, core_bitmap;
67 printf("RUNNING TEST: sim2\n");
68 printf(" Purpose: Check interrupt line connectivity\n");
69 printf(" Will assert all three interrupt signals sequentially.\n");
71 // Get current configuration to allow testing all registers
72 gpuid = Mali_RdReg(0x20, 0, 0x0000);
73 core_bitmap = Mali_RdReg(0x20, 0, 0x0100);
74 l2_size = ((Mali_RdReg(0x20, 0, 0x0004) >> 16) & 0xFF);
75 axi_width = (1 <<((Mali_RdReg(0x20, 0, 0x0004) >> 24) & 0xFF));
76 as_present = Mali_RdReg(0x20, 0, 0x0018);
77 js_present = Mali_RdReg(0x20, 0, 0x001c);
85 printf("Selected configuration:\n");
86 printf(" Bus width: %d\n", axi_width);
87 printf(" Number of shader cores: %d\n", num_cores);
88 printf(" L2 cache size: %d kB\n", ((1<<l2_size)/1024));
90 // Clear all interrupt registers
91 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
92 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
93 Mali_WrReg(0x20,0x0,0x2004,0xFFFFFFFF); // MMU_IRQ_CLEAR
95 // Enable GPU interrupt source, disable all other interrupt sources
96 Mali_WrReg(0x20,0x0,0x0028,0x00000001); // GPU_IRQ_MASK
97 Mali_WrReg(0x20,0x0,0x1008,0x00000000); // JOB_IRQ_MASK
98 Mali_WrReg(0x20,0x0,0x2008,0x00000000); // MMU_IRQ_MASK
100 // Trigger GPU interrupt
101 Mali_WrReg(0x20,0x0,0x0020,0x00000001); // GPU_IRQ_RAWSTAT
110 int RunMaliTest_sim2_t760_part1 (void) {
112 int gpu_irq_status, job_irq_status, mmu_irq_status;
113 gpu_irq_status = Mali_RdReg(0x20,0x0,0x002c);
114 job_irq_status = Mali_RdReg(0x20,0x0,0x100c);
115 mmu_irq_status = Mali_RdReg(0x20,0x0,0x200c);
116 if( (gpu_irq_status == 1) && (job_irq_status == 0) && (mmu_irq_status == 0) ) {
117 printf("GPU Interrupt asserted\n");
118 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
119 Mali_WrReg(0x20,0x0,0x0028,0x00000000); // GPU_IRQ_MASK
120 Mali_WrReg(0x20,0x0,0x1008,0x00000001); // JOB_IRQ_MASK
121 Mali_WrReg(0x20,0x0,0x1000,0x00000001); // JOB_IRQ_RAWSTAT
122 Mali_WrReg(0x20,0x0,0x0020,0x00000000); // GPU_IRQ_RAWSTAT
126 printf("FAILURE: Expected GPU interrupt. Got the following interrupts: GPU: %x JOB: %x MMU: %x\n",
127 gpu_irq_status, job_irq_status, mmu_irq_status);
128 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
129 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
130 Mali_WrReg(0x20,0x0,0x2004,0xFFFFFFFF); // MMU_IRQ_CLEAR
131 Mali_WrReg(0x20,0x0,0x0028,0x00000000); // GPU_IRQ_MASK
132 Mali_WrReg(0x20,0x0,0x1008,0x00000000); // JOB_IRQ_MASK
133 Mali_WrReg(0x20,0x0,0x2008,0x00000000); // MMU_IRQ_MASK
137 int RunMaliTest_sim2_t760_part2 (void) {
139 int gpu_irq_status, job_irq_status, mmu_irq_status;
140 gpu_irq_status = Mali_RdReg(0x20,0x0,0x002c);
141 job_irq_status = Mali_RdReg(0x20,0x0,0x100c);
142 mmu_irq_status = Mali_RdReg(0x20,0x0,0x200c);
143 if( (gpu_irq_status == 0) && (job_irq_status == 1) && (mmu_irq_status == 0) ) {
144 printf("JOB Interrupt asserted\n");
145 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
146 Mali_WrReg(0x20,0x0,0x1008,0x00000000); // JOB_IRQ_MASK
147 Mali_WrReg(0x20,0x0,0x2008,0x00000001); // MMU_IRQ_MASK
148 Mali_WrReg(0x20,0x0,0x2000,0x00000001); // MMU_IRQ_RAWSTAT
149 Mali_WrReg(0x20,0x0,0x1000,0x00000000); // JOB_IRQ_RAWSTAT
153 printf("FAILURE: Expected JOB interrupt. Got the following interrupts: GPU: %x JOB: %x MMU: %x\n",
154 gpu_irq_status, job_irq_status, mmu_irq_status);
155 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
156 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
157 Mali_WrReg(0x20,0x0,0x2004,0xFFFFFFFF); // MMU_IRQ_CLEAR
158 Mali_WrReg(0x20,0x0,0x0028,0x00000000); // GPU_IRQ_MASK
159 Mali_WrReg(0x20,0x0,0x1008,0x00000000); // JOB_IRQ_MASK
160 Mali_WrReg(0x20,0x0,0x2008,0x00000000); // MMU_IRQ_MASK
164 int RunMaliTest_sim2_t760_part3 (void) {
166 int gpu_irq_status, job_irq_status, mmu_irq_status;
167 gpu_irq_status = Mali_RdReg(0x20,0x0,0x002c);
168 job_irq_status = Mali_RdReg(0x20,0x0,0x100c);
169 mmu_irq_status = Mali_RdReg(0x20,0x0,0x200c);
170 if( (gpu_irq_status == 0) && (job_irq_status == 0) && (mmu_irq_status == 1) ) {
171 printf("MMU Interrupt asserted\n");
172 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
173 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
174 Mali_WrReg(0x20,0x0,0x2004,0xFFFFFFFF); // MMU_IRQ_CLEAR
175 Mali_WrReg(0x20,0x0,0x0028,0xFFFFFFFF); // GPU_IRQ_MASK
176 Mali_WrReg(0x20,0x0,0x1008,0xFFFFFFFF); // JOB_IRQ_MASK
177 Mali_WrReg(0x20,0x0,0x2008,0xFFFFFFFF); // MMU_IRQ_MASK
178 Mali_WrReg(0x20,0x0,0x2000,0x00000000); // MMU_IRQ_RAWSTAT
182 printf("FAILURE: Expected MMU interrupt. Got the following interrupts: GPU: %x JOB: %x MMU: %x\n",
183 gpu_irq_status, job_irq_status, mmu_irq_status);
184 Mali_WrReg(0x20,0x0,0x0024,0xFFFFFFFF); // GPU_IRQ_CLEAR
185 Mali_WrReg(0x20,0x0,0x1004,0xFFFFFFFF); // JOB_IRQ_CLEAR
186 Mali_WrReg(0x20,0x0,0x2004,0xFFFFFFFF); // MMU_IRQ_CLEAR
187 Mali_WrReg(0x20,0x0,0x0028,0x00000000); // GPU_IRQ_MASK
188 Mali_WrReg(0x20,0x0,0x1008,0x00000000); // JOB_IRQ_MASK
189 Mali_WrReg(0x20,0x0,0x2008,0x00000000); // MMU_IRQ_MASK