1 /*----------------------------------------------------------------------------
3 * The confidential and proprietary information contained in this file may
4 * only be used by a person authorised under and to the extent permitted
5 * by a subsisting licensing agreement from ARM Limited.
7 * (C) COPYRIGHT 2008-2009,2011-2013 ARM Limited.
10 * This entire notice must be reproduced on all copies of this file
11 * and copies of this file may only be made by a person if such person is
12 * permitted to do so under the terms of a subsisting license agreement
15 * Modified : $Date: 2013-08-01 18:15:13 +0100 (Thu, 01 Aug 2013) $
16 * Revision : $Revision: 66689 $
18 *-----------------------------------------------------------------------------*/
22 BRIEF DESCRIPTION, PURPOSE AND STRATEGY
23 =======================================
25 This test tests that most GPU registers can be read and written via the APB interface.
29 DEBUG HINTS IN CASE OF FAILURE
30 ===========================
31 a) Check the APB bus connections as this is the bus that is used to communicate with the Job manager.
32 b) Check that the GPU's reset signal is not asserted.
33 c) Check that the GPU input clock is toggling as expected.
34 d) Check that the DFT signals are disabled.
35 e) Check that MBIST is disabled.
40 #include "MaliDefines-t760.h"
44 int RunMaliTest_sim1_t760_part0 ();
45 static int Mali_test_reg(int unit, int core, int regnum, int read_mask, int write_mask, int reset_value, int access, char * reg_str);
47 int log2_of_x (int myval);
52 int RunMaliTest_sim1_t760 (int *base) {
55 RunMaliTest_sim1_t760_part0();
61 int RunMaliTest_sim1_t760_part0 () {
63 int gpuid, num_cores, l2_size, axi_width, i, as_present, js_present, core_bitmap, vTEXTURE_FEATURES_0;
66 printf("RUNNING TEST: sim1\n");
67 printf(" Purpose: Check APB register accesses\n");
68 printf(" Will check register read/write and reset value\n");
70 // Get current configuration to allow testing all registers
71 gpuid = Mali_RdReg(0x20, 0, 0x0000);
72 core_bitmap = Mali_RdReg(0x20, 0, 0x0100);
73 l2_size = ((Mali_RdReg(0x20, 0, 0x0004) >> 16) & 0xFF);
74 axi_width = (1 <<((Mali_RdReg(0x20, 0, 0x0004) >> 24) & 0xFF));
75 as_present = Mali_RdReg(0x20, 0, 0x0018);
76 js_present = Mali_RdReg(0x20, 0, 0x001c);
77 vTEXTURE_FEATURES_0 = Mali_RdReg(0x20, 0, 0x00b0);
85 printf("Selected configuration:\n");
86 printf(" Bus width: %d\n", axi_width);
87 printf(" Number of shader cores: %d\n", num_cores);
88 printf(" L2 cache size: %d kB\n", ((1<<l2_size)/1024));
90 printf("Reading/Writing GPU Configuration and Control registers:\n");
91 res |= Mali_test_reg (0, 0, 0x000, 0xffff0000, 0xffff0000, GPU_ID_VALUE, 1, "GPU_ID");
92 res |= Mali_test_reg (0, 0, 0x004, 0xffffffff, 0xffffffff, (0x00000206 + (l2_size << 16) | (log2_of_x(axi_width) << 24)), 1, "L2_FEATURES");
93 res |= Mali_test_reg (0, 0, 0x008, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_FEATURES");
94 res |= Mali_test_reg (0, 0, 0x00c, 0xffffffff, 0xffffffff, 0x00000809, 1, "TILER_FEATURES");
97 Skrymir has a new field
98 MEM_FEATURES[11:8] = L2_SLICES
100 res |= Mali_test_reg (0, 0, 0x010, 0xffffffff, 0xffffffff, 0x00000101, 1, "MEM_FEATURES");
102 res |= Mali_test_reg (0, 0, 0x010, 0xffffffff, 0xffffffff, 0x00000001, 1, "MEM_FEATURES");
105 res |= Mali_test_reg (0, 0, 0x014, 0xffffffff, 0xffffffff, 0x00002830, 1, "MMU_FEATURES");
106 res |= Mali_test_reg (0, 0, 0x018, 0xffffffff, 0xffffffff, as_present, 1, "AS_PRESENT");
107 res |= Mali_test_reg (0, 0, 0x01c, 0xffffffff, 0xffffffff, js_present, 1, "JS_PRESENT");
108 /* GPU config regs */
110 res |= Mali_test_reg(0, 0, 0x020, 0xffffffff, 0xffffffff, 0x00000100, 1, "GPU_IRQ_RAWSTAT");
111 res |= Mali_test_reg(0, 0, 0x028, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_IRQ_MASK");
112 res |= Mali_test_reg(0, 0, 0x02c, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_IRQ_STATUS");
116 res |= Mali_test_reg(0, 0, 0x1000, 0xffffffff, 0xffffffff, 0x00000000, 1, "JOB_IRQ_RAWSTAT");
117 res |= Mali_test_reg(0, 0, 0x1008, 0xffffffff, 0xffffffff, 0x00000000, 1, "JOB_IRQ_MASK");
118 res |= Mali_test_reg(0, 0, 0x100c, 0xffffffff, 0xffffffff, 0x00000000, 1, "JOB_IRQ_STATUS");
122 res |= Mali_test_reg(0, 0, 0x2000, 0xffffffff, 0xffffffff, 0x00000000, 1, "MMU_IRQ_RAWSTAT");
123 res |= Mali_test_reg(0, 0, 0x2008, 0xffffffff, 0xffffffff, 0x00000000, 1, "MMU_IRQ_MASK");
124 res |= Mali_test_reg(0, 0, 0x200c, 0xffffffff, 0xffffffff, 0x00000000, 1, "MMU_IRQ_STATUS");
126 /* res |= Mali_test_reg(0, 0, 0x030, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* GPU_COMMAND */ /* Write only */
127 res |= Mali_test_reg (0, 0, 0x034, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_STATUS");
128 /* res |= Mali_test_reg(0, 0, 0x038, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
129 res |= Mali_test_reg (0, 0, 0x03c, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_FAULTSTATUS");
130 res |= Mali_test_reg (0, 0, 0x040, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_FAULTADDRESS_LO");
131 res |= Mali_test_reg (0, 0, 0x044, 0xffffffff, 0xffffffff, 0x00000000, 1, "GPU_FAULTADDRESS_HI");
132 /* res |= Mali_test_reg(0, 0, 0x048, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
133 /* res |= Mali_test_reg(0, 0, 0x04c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
134 /* res |= Mali_test_reg(0, 0, 0x050, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* PWR_KEY */ /* Write only */
135 /* res |= Mali_test_reg(0, 0, 0x054, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* PWR_OVERRIDE0 */ /* Need PWR_KEY to work */
136 /* res |= Mali_test_reg(0, 0, 0x058, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* PWR_OVERRIDE1 */ /* Need PWR_KEY to work */
137 /* res |= Mali_test_reg(0, 0, 0x05c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
138 res |= Mali_test_reg (0, 0, 0x060, 0xffffffff, 0xfffff800, 0x00000000, 0, "PRFCNT_BASE_LO");
139 res |= Mali_test_reg (0, 0, 0x064, 0xffffffff, 0x0000ffff, 0x00000000, 0, "PRFCNT_BASE_HI");
140 res |= Mali_test_reg (0, 0, 0x068, 0xffffffff, 0x000000ff, 0x00000000, 0, "PRFCNT_CONFIG");
141 res |= Mali_test_reg (0, 0, 0x06c, 0xffffffff, 0x000000ff, 0x00000000, 0, "PRFCNT_JM_EN");
142 res |= Mali_test_reg (0, 0, 0x070, 0xffffffff, 0x0000ffff, 0x00000000, 0, "PRFCNT_SHADER_EN");
143 res |= Mali_test_reg (0, 0, 0x074, 0xffffffff, 0x0000ffff, 0x00000000, 0, "PRFCNT_TILER_EN");
144 res |= Mali_test_reg (0, 0, 0x078, 0xffffffff, 0xffffffff, 0x00000000, 1, "PRFCNT_L3_CACHE_EN");
145 res |= Mali_test_reg (0, 0, 0x07c, 0xffffffff, 0x0000ffff, 0x00000000, 0, "PRFCNT_MMU_L2_EN");
146 /* res |= Mali_test_reg(0, 0, 0x080, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
147 /* res |= Mali_test_reg(0, 0, 0x084, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
148 /* res |= Mali_test_reg(0, 0, 0x088, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
149 /* res |= Mali_test_reg(0, 0, 0x08c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
150 res |= Mali_test_reg (0, 0, 0x090, 0xffffffff, 0xffffffff, 0x00000000, 1, "CYCLE_COUNT_LO");
151 res |= Mali_test_reg (0, 0, 0x094, 0xffffffff, 0xffffffff, 0x00000000, 1, "CYCLE_COUNT_HI");
152 res |= Mali_test_reg (0, 0, 0x098, 0xffffffff, 0xffffffff, 0x00000000, 1, "TIMESTAMP_LO");
153 res |= Mali_test_reg (0, 0, 0x09c, 0xffffffff, 0xffffffff, 0x00000000, 1, "TIMESTAMP_HI");
154 /* res |= Mali_test_reg(0, 0, 0x0a0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
155 /* res |= Mali_test_reg(0, 0, 0x0a4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
156 /* res |= Mali_test_reg(0, 0, 0x0a8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
157 /* res |= Mali_test_reg(0, 0, 0x0ac, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
159 /* printf ("TEXTURE_FEATURES_0 is set to 0x%08x", Mali_RdReg(0x20, 0, 0x00b0)); */
161 printf (" Texture Compression Formats::\n");
162 printf (" TEXTURE_FEATURES_0 = 0x%08x\n" , vTEXTURE_FEATURES_0);
164 printf (" ETC2=%d\n" , ((vTEXTURE_FEATURES_0>> 1)&0x00000001) );
165 printf (" ETC2+EAC=%d\n" , ((vTEXTURE_FEATURES_0>> 3)&0x00000001) );
166 printf (" EAC_1_COMPONENT=%d\n" , ((vTEXTURE_FEATURES_0>> 2)&0x00000001) );
167 printf (" EAC_2_COMPONENTS=%d\n" , ((vTEXTURE_FEATURES_0>> 4)&0x00000001) );
168 printf (" EAC_SNORM_1_COMPONENT=%d\n" , ((vTEXTURE_FEATURES_0>>17)&0x00000001) );
169 printf (" EAC_SNORM_2_COMPONENTS=%d\n" , ((vTEXTURE_FEATURES_0>>18)&0x00000001) );
170 printf (" ETC2+Punch-Through Alpha=%d\n" , ((vTEXTURE_FEATURES_0>>19)&0x00000001) );
172 printf (" NXR=%d\n" , ((vTEXTURE_FEATURES_0>> 6)&0x00000001) );
174 printf (" BC1_UNORM=%d\n" , ((vTEXTURE_FEATURES_0>> 7)&0x00000001) );
175 printf (" BC2_UNORM=%d\n" , ((vTEXTURE_FEATURES_0>> 8)&0x00000001) );
176 printf (" BC3_UNORM=%d\n" , ((vTEXTURE_FEATURES_0>> 9)&0x00000001) );
177 printf (" BC4_UNORM=%d BC4_SNORM=%d\n" , ((vTEXTURE_FEATURES_0>>10)&0x00000001), ((vTEXTURE_FEATURES_0>>11)&0x00000001));
178 printf (" BC5_UNORM=%d BC5_SNORM=%d\n" , ((vTEXTURE_FEATURES_0>>12)&0x00000001), ((vTEXTURE_FEATURES_0>>13)&0x00000001));
179 printf (" BC6H_UF16=%d BC6H_SF16=%d\n" , ((vTEXTURE_FEATURES_0>>14)&0x00000001), ((vTEXTURE_FEATURES_0>>15)&0x00000001));
180 printf (" BC7_UNORM=%d\n" , ((vTEXTURE_FEATURES_0>>16)&0x00000001) );
182 printf (" ASTC_3D_LDR=%d ASTC_3D_HDR=%d\n" , ((vTEXTURE_FEATURES_0>>20)&0x00000001), ((vTEXTURE_FEATURES_0>>21)&0x00000001));
183 printf (" ASTC_2D_LDR=%d ASTC_2D_HDR=%d\n" , ((vTEXTURE_FEATURES_0>>22)&0x00000001), ((vTEXTURE_FEATURES_0>>23)&0x00000001));
185 res |= Mali_test_reg (0, 0, 0x0b4, 0xffffffff, 0xffffffff, 0x0000ffff, 1, "TEXTURE_FEATURES_1");
186 res |= Mali_test_reg (0, 0, 0x0b8, 0xffffffff, 0xffffffff, 0x9f81ffff, 1, "TEXTURE_FEATURES_2");
187 /* res |= Mali_test_reg(0, 0, 0x0bc, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
188 res |= Mali_test_reg (0, 0, 0x0c0, 0xffffffff, 0xffffffff, 0x0000020e, 1, "JS0_FEATURES");
189 res |= Mali_test_reg (0, 0, 0x0c4, 0xffffffff, 0xffffffff, 0x000001fe, 1, "JS1_FEATURES");
190 res |= Mali_test_reg (0, 0, 0x0c8, 0xffffffff, 0xffffffff, 0x0000007e, 1, "JS2_FEATURES");
191 res |= Mali_test_reg (0, 0, 0x0cc, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS3_FEATURES");
192 res |= Mali_test_reg (0, 0, 0x0d0, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS4_FEATURES");
193 res |= Mali_test_reg (0, 0, 0x0d4, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS5_FEATURES");
194 res |= Mali_test_reg (0, 0, 0x0d8, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS6_FEATURES");
195 res |= Mali_test_reg (0, 0, 0x0dc, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS7_FEATURES");
196 res |= Mali_test_reg (0, 0, 0x0e0, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS8_FEATURES");
197 res |= Mali_test_reg (0, 0, 0x0e4, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS9_FEATURES");
198 res |= Mali_test_reg (0, 0, 0x0e8, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS10_FEATURES");
199 res |= Mali_test_reg (0, 0, 0x0ec, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS11_FEATURES");
200 res |= Mali_test_reg (0, 0, 0x0f0, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS12_FEATURES");
201 res |= Mali_test_reg (0, 0, 0x0f4, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS13_FEATURES");
202 res |= Mali_test_reg (0, 0, 0x0f8, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS14_FEATURES");
203 res |= Mali_test_reg (0, 0, 0x0fc, 0xffffffff, 0xffffffff, 0x00000000, 1, "JS15_FEATURES");
204 res |= Mali_test_reg (0, 0, 0x100, 0xffffffff, 0xffffffff, core_bitmap, 1, "SHADER_PRESENT_LO");
205 res |= Mali_test_reg (0, 0, 0x104, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_PRESENT_HI");
206 /* res |= Mali_test_reg(0, 0, 0x108, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
207 /* res |= Mali_test_reg(0, 0, 0x10c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
208 res |= Mali_test_reg (0, 0, 0x110, 0xffffffff, 0xffffffff, 0x00000001, 1, "TILER_PRESENT_LO");
209 res |= Mali_test_reg (0, 0, 0x114, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_PRESENT_HI");
210 /* res |= Mali_test_reg(0, 0, 0x118, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
211 /* res |= Mali_test_reg(0, 0, 0x11c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
214 /* T760 has only one logical L2C */
215 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000001, 1, "L2_PRESENT_LO");
218 { /* T608 MP6 and T608 MP8 have two L2Cs*/
219 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000011, 1, "L2_PRESENT_LO");
223 res |= Mali_test_reg (0, 0, 0x120, 0xffffffff, 0xffffffff, 0x00000001, 1, "L2_PRESENT_LO");
226 res |= Mali_test_reg (0, 0, 0x124, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_PRESENT_HI");
227 /* res |= Mali_test_reg(0, 0, 0x128, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
228 /* res |= Mali_test_reg(0, 0, 0x12c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
229 res |= Mali_test_reg (0, 0, 0x130, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PRESENT_LO");
230 res |= Mali_test_reg (0, 0, 0x134, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PRESENT_HI");
231 /* res |= Mali_test_reg(0, 0, 0x138, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
232 /* res |= Mali_test_reg(0, 0, 0x13c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
233 res |= Mali_test_reg (0, 0, 0x140, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_READY_LO");
234 res |= Mali_test_reg (0, 0, 0x144, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_READY_HI");
235 /* res |= Mali_test_reg(0, 0, 0x148, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
236 /* res |= Mali_test_reg(0, 0, 0x14c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
237 res |= Mali_test_reg (0, 0, 0x150, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_READY_LO");
238 res |= Mali_test_reg (0, 0, 0x154, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_READY_HI");
239 /* res |= Mali_test_reg(0, 0, 0x158, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
240 /* res |= Mali_test_reg(0, 0, 0x15c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
241 res |= Mali_test_reg (0, 0, 0x160, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_READY_LO");
242 res |= Mali_test_reg (0, 0, 0x164, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_READY_HI");
243 /* res |= Mali_test_reg(0, 0, 0x168, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
244 /* res |= Mali_test_reg(0, 0, 0x16c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
245 res |= Mali_test_reg (0, 0, 0x170, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_READY_LO");
246 res |= Mali_test_reg (0, 0, 0x174, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_READY_HI");
247 /* res |= Mali_test_reg(0, 0, 0x178, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
248 /* res |= Mali_test_reg(0, 0, 0x17c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
249 /* res |= Mali_test_reg(0, 0, 0x180, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* SHADER_PWRON_LO */ /* Write Only */
250 /* res |= Mali_test_reg(0, 0, 0x184, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* SHADER_PWRON_HI */ /* Write Only */
251 /* res |= Mali_test_reg(0, 0, 0x188, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
252 /* res |= Mali_test_reg(0, 0, 0x18c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
253 /* res |= Mali_test_reg(0, 0, 0x190, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* TILER_PWRON_LO */ /* Write Only */
254 /* res |= Mali_test_reg(0, 0, 0x194, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* TILER_PWRON_HI */ /* Write Only */
255 /* res |= Mali_test_reg(0, 0, 0x198, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
256 /* res |= Mali_test_reg(0, 0, 0x19c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
257 /* res |= Mali_test_reg(0, 0, 0x1a0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L2_PWRON_LO */ /* Write Only */
258 /* res |= Mali_test_reg(0, 0, 0x1a4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L2_PWRON_HI */ /* Write Only */
259 /* res |= Mali_test_reg(0, 0, 0x1a8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
260 /* res |= Mali_test_reg(0, 0, 0x1ac, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
261 /* res |= Mali_test_reg(0, 0, 0x1b0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L3_PWRON_LO */ /* Write Only */
262 /* res |= Mali_test_reg(0, 0, 0x1b4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L3_PWRON_HI */ /* Write Only */
263 /* res |= Mali_test_reg(0, 0, 0x1b8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
264 /* res |= Mali_test_reg(0, 0, 0x1bc, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
265 /* res |= Mali_test_reg(0, 0, 0x1c0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* SHADER_PWROFF_LO */ /* Write Only */
266 /* res |= Mali_test_reg(0, 0, 0x1c4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* SHADER_PWROFF_HI */ /* Write Only */
267 /* res |= Mali_test_reg(0, 0, 0x1c8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
268 /* res |= Mali_test_reg(0, 0, 0x1cc, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
269 /* res |= Mali_test_reg(0, 0, 0x1d0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* TILER_PWROFF_LO */ /* Write Only */
270 /* res |= Mali_test_reg(0, 0, 0x1d4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* TILER_PWROFF_HI */ /* Write Only */
271 /* res |= Mali_test_reg(0, 0, 0x1d8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
272 /* res |= Mali_test_reg(0, 0, 0x1dc, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
273 /* res |= Mali_test_reg(0, 0, 0x1e0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L2_PWROFF_LO */ /* Write Only */
274 /* res |= Mali_test_reg(0, 0, 0x1e4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L2_PWROFF_HI */ /* Write Only */
275 /* res |= Mali_test_reg(0, 0, 0x1e8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
276 /* res |= Mali_test_reg(0, 0, 0x1ec, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
277 /* res |= Mali_test_reg(0, 0, 0x1f0, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L3_PWROFF_LO */ /* Write Only */
278 /* res |= Mali_test_reg(0, 0, 0x1f4, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* L3_PWROFF_HI */ /* Write Only */
279 /* res |= Mali_test_reg(0, 0, 0x1f8, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
280 /* res |= Mali_test_reg(0, 0, 0x1fc, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
281 res |= Mali_test_reg (0, 0, 0x200, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_PWRTRANS_LO");
282 res |= Mali_test_reg (0, 0, 0x204, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_PWRTRANS_HI");
283 /* res |= Mali_test_reg(0, 0, 0x208, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
284 /* res |= Mali_test_reg(0, 0, 0x20c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
285 res |= Mali_test_reg (0, 0, 0x210, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_PWRTRANS_LO");
286 res |= Mali_test_reg (0, 0, 0x214, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_PWRTRANS_HI");
287 /* res |= Mali_test_reg(0, 0, 0x218, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
288 /* res |= Mali_test_reg(0, 0, 0x21c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
289 res |= Mali_test_reg (0, 0, 0x220, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_PWRTRANS_LO");
290 res |= Mali_test_reg (0, 0, 0x224, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_PWRTRANS_HI");
291 /* res |= Mali_test_reg(0, 0, 0x228, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
292 /* res |= Mali_test_reg(0, 0, 0x22c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
293 res |= Mali_test_reg (0, 0, 0x230, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PWRTRANS_LO");
294 res |= Mali_test_reg (0, 0, 0x234, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PWRTRANS_HI");
295 /* res |= Mali_test_reg(0, 0, 0x238, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
296 /* res |= Mali_test_reg(0, 0, 0x23c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
297 res |= Mali_test_reg (0, 0, 0x240, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_PWRACTIVE_LO");
298 res |= Mali_test_reg (0, 0, 0x244, 0xffffffff, 0xffffffff, 0x00000000, 1, "SHADER_PWRACTIVE_HI");
299 /* res |= Mali_test_reg(0, 0, 0x248, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
300 /* res |= Mali_test_reg(0, 0, 0x24c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
301 res |= Mali_test_reg (0, 0, 0x250, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_PWRACTIVE_LO");
302 res |= Mali_test_reg (0, 0, 0x254, 0xffffffff, 0xffffffff, 0x00000000, 1, "TILER_PWRACTIVE_HI");
303 /* res |= Mali_test_reg(0, 0, 0x258, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
304 /* res |= Mali_test_reg(0, 0, 0x25c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
305 res |= Mali_test_reg (0, 0, 0x260, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_PWRACTIVE_LO");
306 res |= Mali_test_reg (0, 0, 0x264, 0xffffffff, 0xffffffff, 0x00000000, 1, "L2_PWRACTIVE_HI");
307 /* res |= Mali_test_reg(0, 0, 0x268, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
308 /* res |= Mali_test_reg(0, 0, 0x26c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
309 res |= Mali_test_reg (0, 0, 0x270, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PWRACTIVE_LO");
310 res |= Mali_test_reg (0, 0, 0x274, 0xffffffff, 0xffffffff, 0x00000000, 1, "L3_PWRACTIVE_HI");
311 /* res |= Mali_test_reg(0, 0, 0x278, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
312 /* res |= Mali_test_reg(0, 0, 0x27c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
314 printf("Reading/Writing JOB Configuration and Control registers:\n");
315 /* res |= Mali_test_reg(0, 0, 0x1000, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* JOB_IRQ_RAWSTAT */
316 /* res |= Mali_test_reg(0, 0, 0x1004, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* JOB_IRQ_CLEAR */ /* Write Only */
317 /* res |= Mali_test_reg(0, 0, 0x1008, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* JOB_IRQ_MASK */
318 /* res |= Mali_test_reg(0, 0, 0x100c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* JOB_IRQ_STATUS */
320 if( ((js_present >> i) & 1) ) {
321 res |= Mali_test_reg (0, 0, 0x1800 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_HEAD_LO");
322 res |= Mali_test_reg (0, 0, 0x1804 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_HEAD_HI");
323 res |= Mali_test_reg (0, 0, 0x1808 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_TAIL_LO");
324 res |= Mali_test_reg (0, 0, 0x180c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_TAIL_HI");
325 res |= Mali_test_reg (0, 0, 0x1810 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_AFFINITY_LO");
326 res |= Mali_test_reg (0, 0, 0x1814 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_AFFINITY_HI");
327 res |= Mali_test_reg (0, 0, 0x1818 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_CONFIG");
328 /* res |= Mali_test_reg(0, 0, 0x181c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
329 /* res |= Mali_test_reg(0, 0, 0x1820 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* JSx_COMMAND */ /* Write Only */
330 res |= Mali_test_reg (0, 0, 0x1824 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1, "JSx_STATUS");
331 /* res |= Mali_test_reg(0, 0, 0x1828 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
332 /* res |= Mali_test_reg(0, 0, 0x182c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
333 /* res |= Mali_test_reg(0, 0, 0x1830 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
334 /* res |= Mali_test_reg(0, 0, 0x1834 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
335 /* res |= Mali_test_reg(0, 0, 0x1838 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
336 /* res |= Mali_test_reg(0, 0, 0x183c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
337 res |= Mali_test_reg (0, 0, 0x1840 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 0, "JSx_HEAD_NEXT_LO");
338 res |= Mali_test_reg (0, 0, 0x1844 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 0, "JSx_HEAD_NEXT_HI");
339 /* res |= Mali_test_reg(0, 0, 0x1848 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
340 /* res |= Mali_test_reg(0, 0, 0x184c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
341 res |= Mali_test_reg (0, 0, 0x1850 + i*0x80, 0xffffffff, 0x00000001, 0x00000000, 0, "JSx_AFFINITY_NEXT_LO");
342 res |= Mali_test_reg (0, 0, 0x1854 + i*0x80, 0xffffffff, 0x00000000, 0x00000000, 0, "JSx_AFFINITY_NEXT_HI");
343 res |= Mali_test_reg (0, 0, 0x1858 + i*0x80, 0xffffffff, 0x0000370f, 0x00000000, 0, "JSx_CONFIG_NEXT");
344 /* res |= Mali_test_reg(0, 0, 0x185c + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* Reserved */
345 /* res |= Mali_test_reg(0, 0, 0x1860 + i*0x80, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* JSx_COMMAND_NEXT */ /* Write Only? */
349 printf("Reading/Writing MMU Configuration and Control registers:\n");
350 /* res |= Mali_test_reg(0, 0, 0x2000, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* MMU_IRQ_RAWSTAT */
351 /* res |= Mali_test_reg(0, 0, 0x2004, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* MMU_IRQ_CLEAR */ /* Write Only */
352 /* res |= Mali_test_reg(0, 0, 0x2008, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* MMU_IRQ_MASK */
353 /* res |= Mali_test_reg(0, 0, 0x200c, 0xffffffff, 0xffffffff, 0x00000000, 1); */ /* MMU_IRQ_STATUS */
355 if( ((as_present >> i) & 1) ) {
356 res |= Mali_test_reg (0, 0, 0x2400 + i*0x40, 0xffffffff, 0xfffff01f, 0x00000000, 0, "ASx_TRANSTAB_LO");
357 res |= Mali_test_reg (0, 0, 0x2404 + i*0x40, 0xffffffff, 0x000000ff, 0x00000000, 0, "ASx_TRANSTAB_HI");
358 res |= Mali_test_reg (0, 0, 0x2408 + i*0x40, 0xffffffff, 0xcfcfcfcf, 0x00000000, 0, "ASx_MEMATTR_LO");
359 res |= Mali_test_reg (0, 0, 0x240c + i*0x40, 0xffffffff, 0xcfcfcfcf, 0x00000000, 0, "ASx_MEMATTR_HI");
360 res |= Mali_test_reg (0, 0, 0x2410 + i*0x40, 0xffffffff, 0xfffff03f, 0x00000000, 0, "ASx_LOCKADDR_LO");
361 res |= Mali_test_reg (0, 0, 0x2414 + i*0x40, 0xffffffff, 0x0000ffff, 0x00000000, 0, "ASx_LOCKADDR_HI");
362 /* res |= Mali_test_reg(0, 0, 0x2418 + i*0x40, 0xffffffff, 0xffffffff, 0x00000000, 0); */ /* ASx_COMMAND */ /* Write Only */
363 res |= Mali_test_reg (0, 0, 0x241c + i*0x40, 0xffffffff, 0xffffffff, 0x00000000, 1, "ASx_FAULTSTATUS");
364 res |= Mali_test_reg (0, 0, 0x2420 + i*0x40, 0xffffffff, 0xffffffff, 0x00000000, 1, "ASx_FAULTADDRESS_LO");
365 res |= Mali_test_reg (0, 0, 0x2424 + i*0x40, 0xffffffff, 0xffffffff, 0x00000000, 1, "ASx_FAULTADDRESS_HI");
366 res |= Mali_test_reg (0, 0, 0x2428 + i*0x40, 0xffffffff, 0xffffffff, 0x00000000, 1, "ASx_STATUS");
378 static int Mali_test_reg(int unit, int core, int regnum, int read_mask, int write_mask, int reset_value, int access, char * reg_str) {
379 int value = Mali_RdReg(unit, core, regnum);
380 if( value != reset_value ) {
381 printf("FAILURE: Wrong reset value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x for %s\n",
382 (unit<<28)+(core<<16)+regnum, value, reset_value, reg_str);
386 Mali_WrReg(unit, core, regnum, (0xffffffff & write_mask));
387 value = Mali_RdReg(unit, core, regnum) & read_mask;
388 if( value != (0xffffffff & write_mask & read_mask) ) {
389 printf("FAILURE: Wrong value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x for %s\n",
390 (unit<<28)+(core<<16)+regnum, value, (0xffffffff & write_mask & read_mask), reg_str);
393 Mali_WrReg(unit, core, regnum, (0x12345678 & write_mask));
394 value = Mali_RdReg(unit, core, regnum) & read_mask;
395 if( value != (0x12345678 & write_mask & read_mask) ) {
396 printf("FAILURE: Wrong value. Addr: 0x%08x Value: 0x%08x Expected: 0x%08x for %s\n",
397 (unit<<28)+(core<<16)+regnum, value, (0x12345678 & write_mask & read_mask), reg_str);
401 printf("Register %08x: for %s Success!\n", (unit<<28)+(core<<16)+regnum, reg_str);
408 int log2_of_x (int myval) {