3 * (C) COPYRIGHT ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
22 * Base structures shared with the kernel.
25 #ifndef _BASE_KERNEL_H_
26 #define _BASE_KERNEL_H_
28 /* For now we support the legacy API as well as the new API */
29 #define BASE_LEGACY_JD_API 1
31 typedef mali_addr64 base_mem_handle;
33 #include <kbase/src/mali_base_mem_priv.h>
34 #include <kbase/src/mali_kbase_profiling_gator_api.h>
37 * Dependency stuff, keep it private for now. May want to expose it if
38 * we decide to make the number of semaphores a configurable
41 #define BASE_JD_ATOM_COUNT 256
43 #define BASEP_JD_SEM_PER_WORD_LOG2 5
44 #define BASEP_JD_SEM_PER_WORD (1 << BASEP_JD_SEM_PER_WORD_LOG2)
45 #define BASEP_JD_SEM_WORD_NR(x) ((x) >> BASEP_JD_SEM_PER_WORD_LOG2)
46 #define BASEP_JD_SEM_MASK_IN_WORD(x) (1 << ((x) & (BASEP_JD_SEM_PER_WORD - 1)))
47 #define BASEP_JD_SEM_ARRAY_SIZE BASEP_JD_SEM_WORD_NR(BASE_JD_ATOM_COUNT)
49 #if BASE_LEGACY_JD_API
50 /* Size of the ring buffer */
51 #define BASEP_JCTX_RB_NRPAGES 4
52 #endif /* BASE_LEGACY_JD_API */
54 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
56 #define BASE_MAX_COHERENT_GROUPS 16
58 #if defined CDBG_ASSERT
59 #define LOCAL_ASSERT CDBG_ASSERT
60 #elif defined KBASE_DEBUG_ASSERT
61 #define LOCAL_ASSERT KBASE_DEBUG_ASSERT
63 #error assert macro not defined!
67 #define LOCAL_PAGE_LSB ~PAGE_MASK
69 #include <osu/mali_osu.h>
71 #if defined OSU_CONFIG_CPU_PAGE_SIZE_LOG2
72 #define LOCAL_PAGE_LSB ((1ul << OSU_CONFIG_CPU_PAGE_SIZE_LOG2) - 1)
74 #error Failed to find page size
78 /** 32/64-bit neutral way to represent pointers */
79 typedef union kbase_pointer {
80 void *value; /**< client should store their pointers here */
81 u32 compat_value; /**< 64-bit kernels should fetch value here when handling 32-bit clients */
82 u64 sizer; /**< Force 64-bit storage for all clients regardless */
86 * @addtogroup base_user_api User-side Base APIs
91 * @addtogroup base_user_api_memory User-side Base Memory APIs
96 * @brief Memory allocation, access/hint flags
98 * A combination of MEM_PROT/MEM_HINT flags must be passed to each allocator
99 * in order to determine the best cache policy. Some combinations are
100 * of course invalid (eg @c MEM_PROT_CPU_WR | @c MEM_HINT_CPU_RD),
101 * which defines a @a write-only region on the CPU side, which is
102 * heavily read by the CPU...
103 * Other flags are only meaningful to a particular allocator.
104 * More flags can be added to this list, as long as they don't clash
105 * (see ::BASE_MEM_FLAGS_NR_BITS for the number of the first free bit).
107 typedef u32 base_mem_alloc_flags;
110 * @brief Memory allocation, access/hint flags
112 * See ::base_mem_alloc_flags.
116 BASE_MEM_PROT_CPU_RD = (1U << 0), /**< Read access CPU side */
117 BASE_MEM_PROT_CPU_WR = (1U << 1), /**< Write access CPU side */
118 BASE_MEM_PROT_GPU_RD = (1U << 2), /**< Read access GPU side */
119 BASE_MEM_PROT_GPU_WR = (1U << 3), /**< Write access GPU side */
120 BASE_MEM_PROT_GPU_EX = (1U << 4), /**< Execute allowed on the GPU side */
122 /* Note that the HINT flags are obsolete now. If you want the memory
123 * to be cached on the CPU please use the BASE_MEM_CACHED_CPU flag
125 BASE_MEM_HINT_CPU_RD = (1U << 5), /**< Heavily read CPU side - OBSOLETE */
126 BASE_MEM_HINT_CPU_WR = (1U << 6), /**< Heavily written CPU side - OBSOLETE */
127 BASE_MEM_HINT_GPU_RD = (1U << 7), /**< Heavily read GPU side - OBSOLETE */
128 BASE_MEM_HINT_GPU_WR = (1U << 8), /**< Heavily written GPU side - OBSOLETE */
130 BASE_MEM_GROW_ON_GPF = (1U << 9), /**< Grow backing store on GPU Page Fault */
132 BASE_MEM_COHERENT_SYSTEM = (1U << 10), /**< Page coherence Outer shareable */
133 BASE_MEM_COHERENT_LOCAL = (1U << 11), /**< Page coherence Inner shareable */
134 BASE_MEM_CACHED_CPU = (1U << 12), /**< Should be cached on the CPU */
136 BASE_MEM_SAME_VA = (1U << 13) /**< Must have same VA on both the GPU and the CPU */
140 * @brief Memory types supported by @a base_mem_import
142 * Each type defines what the supported handle type is.
144 * If any new type is added here ARM must be contacted
145 * to allocate a numeric value for it.
146 * Do not just add a new type without synchronizing with ARM
147 * as future releases from ARM might include other new types
148 * which could clash with your custom types.
150 typedef enum base_mem_import_type {
151 BASE_MEM_IMPORT_TYPE_INVALID = 0,
152 /** UMP import. Handle type is ump_secure_id. */
153 BASE_MEM_IMPORT_TYPE_UMP = 1,
154 /** UMM import. Handle type is a file descriptor (int) */
155 BASE_MEM_IMPORT_TYPE_UMM = 2
156 } base_mem_import_type;
158 /* legacy API wrappers */
159 #define base_tmem_import_type base_mem_import_type
160 #define BASE_TMEM_IMPORT_TYPE_INVALID BASE_MEM_IMPORT_TYPE_INVALID
161 #define BASE_TMEM_IMPORT_TYPE_UMP BASE_MEM_IMPORT_TYPE_UMP
162 #define BASE_TMEM_IMPORT_TYPE_UMM BASE_MEM_IMPORT_TYPE_UMM
165 * @brief Number of bits used as flags for base memory management
167 * Must be kept in sync with the ::base_mem_alloc_flags flags
169 #define BASE_MEM_FLAGS_NR_BITS 14
172 * @brief Result codes of changing the size of the backing store allocated to a tmem region
174 typedef enum base_backing_threshold_status {
175 BASE_BACKING_THRESHOLD_OK = 0, /**< Resize successful */
176 BASE_BACKING_THRESHOLD_ERROR_NOT_GROWABLE = -1, /**< Not a growable tmem object */
177 BASE_BACKING_THRESHOLD_ERROR_OOM = -2, /**< Increase failed due to an out-of-memory condition */
178 BASE_BACKING_THRESHOLD_ERROR_MAPPED = -3, /**< Resize attempted on buffer while it was mapped, which is not permitted */
179 BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS = -4 /**< Invalid arguments (not tmem, illegal size request, etc.) */
180 } base_backing_threshold_status;
183 * @addtogroup base_user_api_memory_defered User-side Base Defered Memory Coherency APIs
188 * @brief a basic memory operation (sync-set).
190 * The content of this structure is private, and should only be used
193 typedef struct base_syncset {
194 basep_syncset basep_sset;
197 /** @} end group base_user_api_memory_defered */
200 * Handle to represent imported memory object.
201 * Simple opague handle to imported memory, can't be used
202 * with anything but base_external_resource_init to bind to an atom.
204 typedef struct base_import_handle {
208 } base_import_handle;
210 /** @} end group base_user_api_memory */
213 * @addtogroup base_user_api_job_dispatch User-side Base Job Dispatcher APIs
217 typedef int platform_fence_type;
218 #define INVALID_PLATFORM_FENCE ((platform_fence_type)-1)
221 * Base stream handle.
223 * References an underlying base stream object.
225 typedef struct base_stream {
234 * References an underlying base fence object.
236 typedef struct base_fence {
243 #if BASE_LEGACY_JD_API
245 * @brief A pre- or post- dual dependency.
247 * This structure is used to express either
248 * @li a single or dual pre-dependency (a job depending on one or two
250 * @li a single or dual post-dependency (a job resolving a dependency
251 * for one or two other jobs).
253 * The dependency itself is specified as a u8, where 0 indicates no
254 * dependency. A single dependency is expressed by having one of the
255 * dependencies set to 0.
257 typedef struct base_jd_dep {
258 u8 dep[2]; /**< pre/post dependencies */
260 #endif /* BASE_LEGACY_JD_API */
263 * @brief Per-job data
265 * This structure is used to store per-job data, and is completly unused
266 * by the Base driver. It can be used to store things such as callback
267 * function pointer, data to handle job completion. It is guaranteed to be
268 * untouched by the Base driver.
270 typedef struct base_jd_udata {
271 u64 blob[2]; /**< per-job data array */
275 * @brief Job chain hardware requirements.
277 * A job chain must specify what GPU features it needs to allow the
278 * driver to schedule the job correctly. By not specifying the
279 * correct settings can/will cause an early job termination. Multiple
280 * values can be ORed together to specify multiple requirements.
281 * Special case is ::BASE_JD_REQ_DEP, which is used to express complex
282 * dependencies, and that doesn't execute anything on the hardware.
284 typedef u16 base_jd_core_req;
286 /* Requirements that come from the HW */
287 #define BASE_JD_REQ_DEP 0 /**< No requirement, dependency only */
288 #define BASE_JD_REQ_FS (1U << 0) /**< Requires fragment shaders */
290 * Requires compute shaders
291 * This covers any of the following Midgard Job types:
292 * - Vertex Shader Job
293 * - Geometry Shader Job
294 * - An actual Compute Shader Job
296 * Compare this with @ref BASE_JD_REQ_ONLY_COMPUTE, which specifies that the
297 * job is specifically just the "Compute Shader" job type, and not the "Vertex
298 * Shader" nor the "Geometry Shader" job type.
300 #define BASE_JD_REQ_CS (1U << 1)
301 #define BASE_JD_REQ_T (1U << 2) /**< Requires tiling */
302 #define BASE_JD_REQ_CF (1U << 3) /**< Requires cache flushes */
303 #define BASE_JD_REQ_V (1U << 4) /**< Requires value writeback */
305 /* SW-only requirements - the HW does not expose these as part of the job slot capabilities */
307 * SW Only requirement: the job chain requires a coherent core group. We don't
308 * mind which coherent core group is used.
310 #define BASE_JD_REQ_COHERENT_GROUP (1U << 6)
313 * SW Only requirement: The performance counters should be enabled only when
314 * they are needed, to reduce power consumption.
317 #define BASE_JD_REQ_PERMON (1U << 7)
320 * SW Only requirement: External resources are referenced by this atom.
321 * When external resources are referenced no syncsets can be bundled with the atom
322 * but should instead be part of a NULL jobs inserted into the dependency tree.
323 * The first pre_dep object must be configured for the external resouces to use,
324 * the second pre_dep object can be used to create other dependencies.
326 #define BASE_JD_REQ_EXTERNAL_RESOURCES (1U << 8)
329 * SW Only requirement: Software defined job. Jobs with this bit set will not be submitted
330 * to the hardware but will cause some action to happen within the driver
332 #define BASE_JD_REQ_SOFT_JOB (1U << 9)
334 #define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
335 #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
336 #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
339 * HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders)
341 * This indicates that the Job Chain contains Midgard Jobs of the 'Compute Shaders' type.
343 * In contrast to @ref BASE_JD_REQ_CS, this does \b not indicate that the Job
344 * Chain contains 'Geometry Shader' or 'Vertex Shader' jobs.
346 * @note This is a more flexible variant of the @ref BASE_CONTEXT_HINT_ONLY_COMPUTE flag,
347 * allowing specific jobs to be marked as 'Only Compute' instead of the entire context
349 #define BASE_JD_REQ_ONLY_COMPUTE (1U << 10)
352 * HW Requirement: Use the base_jd_atom::device_nr field to specify a
353 * particular core group
355 * If both BASE_JD_REQ_COHERENT_GROUP and this flag are set, this flag takes priority
357 * This is only guaranteed to work for BASE_JD_REQ_ONLY_COMPUTE atoms.
359 * If the core availability policy is keeping the required core group turned off, then
360 * the job will fail with a BASE_JD_EVENT_PM_EVENT error code.
362 #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP (1U << 11)
365 * SW Flag: If this bit is set then the successful completion of this atom
366 * will not cause an event to be sent to userspace
368 #define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE (1U << 12)
371 * These requirement bits are currently unused in base_jd_core_req (currently a u16)
374 #define BASEP_JD_REQ_RESERVED_BIT5 (1U << 5)
375 #define BASEP_JD_REQ_RESERVED_BIT13 (1U << 13)
376 #define BASEP_JD_REQ_RESERVED_BIT14 (1U << 14)
377 #define BASEP_JD_REQ_RESERVED_BIT15 (1U << 15)
380 * Mask of all the currently unused requirement bits in base_jd_core_req.
383 #define BASEP_JD_REQ_RESERVED (BASEP_JD_REQ_RESERVED_BIT5 | BASEP_JD_REQ_RESERVED_BIT13 |\
384 BASEP_JD_REQ_RESERVED_BIT14 | BASEP_JD_REQ_RESERVED_BIT15)
387 * Mask of all bits in base_jd_core_req that control the type of the atom.
389 * This allows dependency only atoms to have flags set
391 #define BASEP_JD_REQ_ATOM_TYPE (~(BASEP_JD_REQ_RESERVED | BASE_JD_REQ_EVENT_ONLY_ON_FAILURE |\
392 BASE_JD_REQ_EXTERNAL_RESOURCES))
394 #if BASE_LEGACY_JD_API
396 * @brief A single job chain, with pre/post dependendencies and mem ops
398 * This structure is used to describe a single job-chain to be submitted
400 * It contains all the necessary information for Base to take care of this
401 * job-chain, including core requirements, priority, syncsets and
404 typedef struct base_jd_atom {
405 mali_addr64 jc; /**< job-chain GPU address */
406 base_jd_udata udata; /**< user data */
407 base_jd_dep pre_dep; /**< pre-dependencies */
408 base_jd_dep post_dep; /**< post-dependencies */
409 base_jd_core_req core_req; /**< core requirements */
410 u16 nr_syncsets; /**< nr of syncsets following the atom */
411 u16 nr_extres; /**< nr of external resources following the atom */
413 /** @brief Relative priority.
415 * A positive value requests a lower priority, whilst a negative value
416 * requests a higher priority. Only privileged processes may request a
417 * higher priority. For unprivileged processes, a negative priority will
418 * be interpreted as zero.
423 * @brief Device number to use, depending on @ref base_jd_core_req flags set.
425 * When BASE_JD_REQ_SPECIFIC_COHERENT_GROUP is set, a 'device' is one of
426 * the coherent core groups, and so this targets a particular coherent
427 * core-group. They are numbered from 0 to (mali_base_gpu_coherent_group_info::num_groups - 1),
428 * and the cores targeted by this device_nr will usually be those specified by
429 * (mali_base_gpu_coherent_group_info::group[device_nr].core_mask).
430 * Further, two atoms from different processes using the same \a device_nr
431 * at the same time will always target the same coherent core-group.
433 * There are exceptions to when the device_nr is ignored:
434 * - when any process in the system uses a BASE_JD_REQ_CS or
435 * BASE_JD_REQ_ONLY_COMPUTE atom that can run on all cores across all
436 * coherency groups (i.e. also does \b not have the
437 * BASE_JD_REQ_COHERENT_GROUP or BASE_JD_REQ_SPECIFIC_COHERENT_GROUP flags
438 * set). In this case, such atoms would block device_nr==1 being used due
439 * to restrictions on affinity, perhaps indefinitely. To ensure progress is
440 * made, the atoms targeted for device_nr 1 will instead be redirected to
442 * - During certain HW workarounds, such as BASE_HW_ISSUE_8987, where
443 * BASE_JD_REQ_ONLY_COMPUTE atoms must not use the same cores as other
444 * atoms. In this case, all atoms are targeted to device_nr == min( num_groups, 1 )
446 * Note that the 'device' number for a coherent coregroup cannot exceed
447 * (BASE_MAX_COHERENT_GROUPS - 1).
451 #endif /* BASE_LEGACY_JD_API */
453 typedef u8 base_atom_id; /**< Type big enough to store an atom number in */
455 typedef struct base_jd_atom_v2 {
456 mali_addr64 jc; /**< job-chain GPU address */
457 base_jd_udata udata; /**< user data */
458 kbase_pointer extres_list; /**< list of external resources */
459 u16 nr_extres; /**< nr of external resources */
460 base_jd_core_req core_req; /**< core requirements */
461 base_atom_id pre_dep[2]; /**< pre-dependencies */
462 base_atom_id atom_number; /**< unique number to identify the atom */
463 s8 prio; /**< priority - smaller is higher priority */
464 u8 device_nr; /**< coregroup when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP specified */
468 #if BASE_LEGACY_JD_API
469 /* Structure definition works around the fact that C89 doesn't allow arrays of size 0 */
470 typedef struct basep_jd_atom_ss {
472 base_syncset syncsets[1];
474 #endif /* BASE_LEGACY_JD_API */
476 typedef enum base_external_resource_access {
477 BASE_EXT_RES_ACCESS_SHARED,
478 BASE_EXT_RES_ACCESS_EXCLUSIVE
479 } base_external_resource_access;
481 typedef struct base_external_resource {
483 } base_external_resource;
485 #if BASE_LEGACY_JD_API
486 /* Structure definition works around the fact that C89 doesn't allow arrays of size 0 */
487 typedef struct basep_jd_atom_ext_res {
489 base_external_resource resources[1];
490 } basep_jd_atom_ext_res;
492 static INLINE size_t base_jd_atom_size_ex(u32 syncset_count, u32 external_res_count)
496 LOCAL_ASSERT(0 == syncset_count || 0 == external_res_count);
498 size = syncset_count ? offsetof(basep_jd_atom_ss, syncsets[0]) + (sizeof(base_syncset) * syncset_count) : external_res_count ? offsetof(basep_jd_atom_ext_res, resources[0]) + (sizeof(base_external_resource) * external_res_count) : sizeof(base_jd_atom);
500 /* Atom minimum size set to 64 bytes to ensure that the maximum
501 * number of atoms in the ring buffer is limited to 256 */
502 return MAX(64, size);
506 * @brief Atom size evaluator
508 * This function returns the size in bytes of a ::base_jd_atom
509 * containing @a n syncsets. It must be used to compute the size of a
510 * bag before allocation.
512 * @param nr the number of syncsets for this atom
513 * @return the atom size in bytes
515 static INLINE size_t base_jd_atom_size(u32 nr)
517 return base_jd_atom_size_ex(nr, 0);
521 * @brief Atom syncset accessor
523 * This function returns a pointer to the nth syncset allocated
524 * together with an atom.
526 * @param[in] atom The allocated atom
527 * @param n The number of the syncset to be returned
528 * @return a pointer to the nth syncset.
530 static INLINE base_syncset *base_jd_get_atom_syncset(base_jd_atom *atom, u16 n)
532 LOCAL_ASSERT(atom != NULL);
533 LOCAL_ASSERT(0 == (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES));
534 LOCAL_ASSERT(n <= atom->nr_syncsets);
535 return &((basep_jd_atom_ss *) atom)->syncsets[n];
537 #endif /* BASE_LEGACY_JD_API */
540 * @brief Soft-atom fence trigger setup.
542 * Sets up an atom to be a SW-only atom signaling a fence
543 * when it reaches the run state.
545 * Using the existing base dependency system the fence can
546 * be set to trigger when a GPU job has finished.
548 * The base fence object must not be terminated until the atom
549 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
551 * @a fence must be a valid fence set up with @a base_fence_init.
552 * Calling this function with a uninitialized fence results in undefined behavior.
554 * @param[out] atom A pre-allocated atom to configure as a fence trigger SW atom
555 * @param[in] fence The base fence object to trigger.
557 static INLINE void base_jd_fence_trigger_setup(base_jd_atom * const atom, base_fence *fence)
561 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
562 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
563 atom->jc = (uintptr_t) fence;
564 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
567 static INLINE void base_jd_fence_trigger_setup_v2(base_jd_atom_v2 *atom, base_fence *fence)
571 LOCAL_ASSERT(fence->basep.fd == INVALID_PLATFORM_FENCE);
572 LOCAL_ASSERT(fence->basep.stream_fd >= 0);
573 atom->jc = (uintptr_t) fence;
574 atom->core_req = BASE_JD_REQ_SOFT_FENCE_TRIGGER;
578 * @brief Soft-atom fence wait setup.
580 * Sets up an atom to be a SW-only atom waiting on a fence.
581 * When the fence becomes triggered the atom becomes runnable
582 * and completes immediately.
584 * Using the existing base dependency system the fence can
585 * be set to block a GPU job until it has been triggered.
587 * The base fence object must not be terminated until the atom
588 * has been submitted to @a base_jd_submit_bag and @a base_jd_submit_bag has returned.
590 * @a fence must be a valid fence set up with @a base_fence_init or @a base_fence_import.
591 * Calling this function with a uninitialized fence results in undefined behavior.
593 * @param[out] atom A pre-allocated atom to configure as a fence wait SW atom
594 * @param[in] fence The base fence object to wait on
596 static INLINE void base_jd_fence_wait_setup(base_jd_atom * const atom, base_fence *fence)
600 LOCAL_ASSERT(fence->basep.fd >= 0);
601 atom->jc = (uintptr_t) fence;
602 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
605 static INLINE void base_jd_fence_wait_setup_v2(base_jd_atom_v2 *atom, base_fence *fence)
609 LOCAL_ASSERT(fence->basep.fd >= 0);
610 atom->jc = (uintptr_t) fence;
611 atom->core_req = BASE_JD_REQ_SOFT_FENCE_WAIT;
614 #if BASE_LEGACY_JD_API
616 * @brief Atom external resource accessor
618 * This functions returns a pointer to the nth external resource tracked by the atom.
620 * @param[in] atom The allocated atom
621 * @param n The number of the external resource to return a pointer to
622 * @return a pointer to the nth external resource
624 static INLINE base_external_resource * base_jd_get_external_resource(base_jd_atom *atom, u16 n)
626 LOCAL_ASSERT(atom != NULL);
627 LOCAL_ASSERT(BASE_JD_REQ_EXTERNAL_RESOURCES == (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES));
628 LOCAL_ASSERT(n <= atom->nr_extres);
629 return &((basep_jd_atom_ext_res *) atom)->resources[n];
631 #endif /* BASE_LEGACY_JD_API */
634 * @brief External resource info initialization.
636 * Sets up a external resource object to reference
637 * a memory allocation and the type of access requested.
639 * @param[in] res The resource object to initialize
640 * @param handle The handle to the imported memory object
641 * @param access The type of access requested
643 static INLINE void base_external_resource_init(base_external_resource * res, base_import_handle handle, base_external_resource_access access)
646 address = handle.basep.handle;
648 LOCAL_ASSERT(res != NULL);
649 LOCAL_ASSERT(0 == (address & LOCAL_PAGE_LSB));
650 LOCAL_ASSERT(access == BASE_EXT_RES_ACCESS_SHARED || access == BASE_EXT_RES_ACCESS_EXCLUSIVE);
652 res->ext_resource = address | (access & LOCAL_PAGE_LSB);
655 #if BASE_LEGACY_JD_API
657 * @brief Next atom accessor
659 * This function returns a pointer to the next allocated atom. It
660 * relies on the fact that the current atom has been correctly
661 * initialized (relies on the base_jd_atom::nr_syncsets field).
663 * @param[in] atom The allocated atom
664 * @return a pointer to the next atom.
666 static INLINE base_jd_atom *base_jd_get_next_atom(base_jd_atom *atom)
668 LOCAL_ASSERT(atom != NULL);
669 return (atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES) ? (base_jd_atom *) base_jd_get_external_resource(atom, atom->nr_extres) : (base_jd_atom *) base_jd_get_atom_syncset(atom, atom->nr_syncsets);
671 #endif /* BASE_LEGACY_JD_API */
674 * @brief Job chain event code bits
675 * Defines the bits used to create ::base_jd_event_code
678 BASE_JD_SW_EVENT_KERNEL = (1u << 15), /**< Kernel side event */
679 BASE_JD_SW_EVENT = (1u << 14), /**< SW defined event */
680 BASE_JD_SW_EVENT_SUCCESS = (1u << 13), /**< Event idicates success (SW events only) */
681 BASE_JD_SW_EVENT_JOB = (0u << 11), /**< Job related event */
682 BASE_JD_SW_EVENT_BAG = (1u << 11), /**< Bag related event */
683 BASE_JD_SW_EVENT_INFO = (2u << 11), /**< Misc/info event */
684 BASE_JD_SW_EVENT_RESERVED = (3u << 11), /**< Reserved event type */
685 BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11) /**< Mask to extract the type from an event code */
689 * @brief Job chain event codes
691 * HW and low-level SW events are represented by event codes.
692 * The status of jobs which succeeded are also represented by
693 * an event code (see ::BASE_JD_EVENT_DONE).
694 * Events are usually reported as part of a ::base_jd_event.
696 * The event codes are encoded in the following way:
699 * @li 13 - SW success (only valid if the SW bit is set)
700 * @li 14 - SW event (HW event if not set)
701 * @li 15 - Kernel event (should never be seen in userspace)
703 * Events are split up into ranges as follows:
704 * - BASE_JD_EVENT_RANGE_\<description\>_START
705 * - BASE_JD_EVENT_RANGE_\<description\>_END
707 * \a code is in \<description\>'s range when:
708 * - <tt>BASE_JD_EVENT_RANGE_\<description\>_START <= code < BASE_JD_EVENT_RANGE_\<description\>_END </tt>
710 * Ranges can be asserted for adjacency by testing that the END of the previous
711 * is equal to the START of the next. This is useful for optimizing some tests
714 * A limitation is that the last member of this enum must explicitly be handled
715 * (with an assert-unreachable statement) in switch statements that use
716 * variables of this type. Otherwise, the compiler warns that we have not
717 * handled that enum value.
719 typedef enum base_jd_event_code {
720 /* HW defined exceptions */
722 /** Start of HW Non-fault status codes
724 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
725 * because the job was hard-stopped
727 BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0,
729 /* non-fatal exceptions */
730 BASE_JD_EVENT_NOT_STARTED = 0x00, /**< Can't be seen by userspace, treated as 'previous job done' */
731 BASE_JD_EVENT_DONE = 0x01,
732 BASE_JD_EVENT_STOPPED = 0x03, /**< Can't be seen by userspace, becomes TERMINATED, DONE or JOB_CANCELLED */
733 BASE_JD_EVENT_TERMINATED = 0x04, /**< This is actually a fault status code - the job was hard stopped */
734 BASE_JD_EVENT_ACTIVE = 0x08, /**< Can't be seen by userspace, jobs only returned on complete/fail/cancel */
736 /** End of HW Non-fault status codes
738 * @note Obscurely, BASE_JD_EVENT_TERMINATED indicates a real fault,
739 * because the job was hard-stopped
741 BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40,
743 /** Start of HW fault and SW Error status codes */
744 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40,
747 BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40,
748 BASE_JD_EVENT_JOB_POWER_FAULT = 0x41,
749 BASE_JD_EVENT_JOB_READ_FAULT = 0x42,
750 BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43,
751 BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44,
752 BASE_JD_EVENT_JOB_BUS_FAULT = 0x48,
753 BASE_JD_EVENT_INSTR_INVALID_PC = 0x50,
754 BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51,
755 BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52,
756 BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53,
757 BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54,
758 BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55,
759 BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56,
760 BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58,
761 BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59,
762 BASE_JD_EVENT_STATE_FAULT = 0x5A,
763 BASE_JD_EVENT_OUT_OF_MEMORY = 0x60,
764 BASE_JD_EVENT_UNKNOWN = 0x7F,
767 BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80,
768 BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88,
771 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1,
772 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2,
773 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3,
774 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4,
775 BASE_JD_EVENT_PERMISSION_FAULT = 0xC8,
776 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1,
777 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2,
778 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3,
779 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4,
780 BASE_JD_EVENT_ACCESS_FLAG = 0xD8,
782 /* SW defined exceptions */
783 BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
784 BASE_JD_EVENT_TIMED_OUT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001,
785 BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
786 BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
787 BASE_JD_EVENT_PM_EVENT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004,
789 BASE_JD_EVENT_BAG_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003,
791 /** End of HW fault and SW Error status codes */
792 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
794 /** Start of SW Success status codes */
795 BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,
797 BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000,
798 BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_BAG | 0x000,
799 BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,
801 /** End of SW Success status codes */
802 BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
804 /** Start of Kernel-only status codes. Such codes are never returned to user-space */
805 BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
806 BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,
808 /** End of Kernel-only status codes. */
809 BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
810 } base_jd_event_code;
813 * @brief Event reporting structure
815 * This structure is used by the kernel driver to report information
816 * about GPU events. The can either be HW-specific events or low-level
817 * SW events, such as job-chain completion.
819 * The event code contains an event type field which can be extracted
820 * by ANDing with ::BASE_JD_SW_EVENT_TYPE_MASK.
822 * Based on the event type base_jd_event::data holds:
823 * @li ::BASE_JD_SW_EVENT_JOB : the offset in the ring-buffer for the completed
825 * @li ::BASE_JD_SW_EVENT_BAG : The address of the ::base_jd_bag that has
826 * been completed (ie all contained job-chains have been completed).
827 * @li ::BASE_JD_SW_EVENT_INFO : base_jd_event::data not used
829 #if BASE_LEGACY_JD_API
830 typedef struct base_jd_event {
831 base_jd_event_code event_code; /**< event code */
832 void *data; /**< event specific data */
836 typedef struct base_jd_event_v2 {
837 base_jd_event_code event_code; /**< event code */
838 base_atom_id atom_number; /**< the atom number that has completed */
839 base_jd_udata udata; /**< user data */
843 * Padding required to ensure that the @ref basep_dump_cpu_gpu_counters structure fills
847 #define BASE_CPU_GPU_CACHE_LINE_PADDING (36)
851 * @brief Structure for BASE_JD_REQ_SOFT_DUMP_CPU_GPU_COUNTERS jobs.
853 * This structure is stored into the memory pointed to by the @c jc field of @ref base_jd_atom.
855 * This structure must be padded to ensure that it will occupy whole cache lines. This is to avoid
856 * cases where access to pages containing the structure is shared between cached and un-cached
857 * memory regions, which would cause memory corruption. Here we set the structure size to be 64 bytes
858 * which is the cache line for ARM A15 processors.
861 typedef struct base_dump_cpu_gpu_counters {
866 u8 padding[BASE_CPU_GPU_CACHE_LINE_PADDING];
867 } base_dump_cpu_gpu_counters;
871 /** @} end group base_user_api_job_dispatch */
875 * The following typedefs should be removed when a midg types header is added.
876 * See MIDCOM-1657 for details.
878 typedef u32 midg_product_id;
879 typedef u32 midg_cache_features;
880 typedef u32 midg_tiler_features;
881 typedef u32 midg_mem_features;
882 typedef u32 midg_mmu_features;
883 typedef u32 midg_js_features;
884 typedef u32 midg_as_present;
885 typedef u32 midg_js_present;
887 #define MIDG_MAX_JOB_SLOTS 16
890 #include <midg/mali_midg.h>
894 * @page page_base_user_api_gpuprops User-side Base GPU Property Query API
896 * The User-side Base GPU Property Query API encapsulates two
899 * - @ref base_user_api_gpuprops_dyn "Dynamic GPU Properties"
900 * - @ref base_plat_config_gpuprops "Base Platform Config GPU Properties"
902 * There is a related third module outside of Base, which is owned by the MIDG
904 * - @ref midg_gpuprops_static "Midgard Compile-time GPU Properties"
906 * Base only deals with properties that vary between different Midgard
907 * implementations - the Dynamic GPU properties and the Platform Config
910 * For properties that are constant for the Midgard Architecture, refer to the
911 * MIDG module. However, we will discuss their relevance here <b>just to
912 * provide background information.</b>
914 * @section sec_base_user_api_gpuprops_about About the GPU Properties in Base and MIDG modules
916 * The compile-time properties (Platform Config, Midgard Compile-time
917 * properties) are exposed as pre-processor macros.
919 * Complementing the compile-time properties are the Dynamic GPU
920 * Properties, which act as a conduit for the Midgard Configuration
923 * In general, the dynamic properties are present to verify that the platform
924 * has been configured correctly with the right set of Platform Config
925 * Compile-time Properties.
927 * As a consistant guide across the entire DDK, the choice for dynamic or
928 * compile-time should consider the following, in order:
929 * -# Can the code be written so that it doesn't need to know the
930 * implementation limits at all?
931 * -# If you need the limits, get the information from the Dynamic Property
932 * lookup. This should be done once as you fetch the context, and then cached
933 * as part of the context data structure, so it's cheap to access.
934 * -# If there's a clear and arguable inefficiency in using Dynamic Properties,
935 * then use a Compile-Time Property (Platform Config, or Midgard Compile-time
936 * property). Examples of where this might be sensible follow:
937 * - Part of a critical inner-loop
938 * - Frequent re-use throughout the driver, causing significant extra load
939 * instructions or control flow that would be worthwhile optimizing out.
941 * We cannot provide an exhaustive set of examples, neither can we provide a
942 * rule for every possible situation. Use common sense, and think about: what
943 * the rest of the driver will be doing; how the compiler might represent the
944 * value if it is a compile-time constant; whether an OEM shipping multiple
945 * devices would benefit much more from a single DDK binary, instead of
946 * insignificant micro-optimizations.
948 * @section sec_base_user_api_gpuprops_dyn Dynamic GPU Properties
950 * Dynamic GPU properties are presented in two sets:
951 * -# the commonly used properties in @ref base_gpu_props, which have been
952 * unpacked from GPU register bitfields.
953 * -# The full set of raw, unprocessed properties in @ref midg_raw_gpu_props
954 * (also a member of @ref base_gpu_props). All of these are presented in
955 * the packed form, as presented by the GPU registers themselves.
957 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
958 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
959 * behaving differently?". In this case, all information about the
960 * configuration is potentially useful, but it <b>does not need to be processed
961 * by the driver</b>. Instead, the raw registers can be processed by the Mali
962 * Tools software on the host PC.
964 * The properties returned extend the Midgard Configuration Discovery
965 * registers. For example, GPU clock speed is not specified in the Midgard
966 * Architecture, but is <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
968 * The GPU properties are obtained by a call to
969 * _mali_base_get_gpu_props(). This simply returns a pointer to a const
970 * base_gpu_props structure. It is constant for the life of a base
971 * context. Multiple calls to _mali_base_get_gpu_props() to a base context
972 * return the same pointer to a constant structure. This avoids cache pollution
973 * of the common data.
975 * This pointer must not be freed, because it does not point to the start of a
976 * region allocated by the memory allocator; instead, just close the @ref
980 * @section sec_base_user_api_gpuprops_config Platform Config Compile-time Properties
982 * The Platform Config File sets up gpu properties that are specific to a
983 * certain platform. Properties that are 'Implementation Defined' in the
984 * Midgard Architecture spec are placed here.
986 * @note Reference configurations are provided for Midgard Implementations, such as
987 * the Mali-T600 family. The customer need not repeat this information, and can select one of
988 * these reference configurations. For example, VA_BITS, PA_BITS and the
989 * maximum number of samples per pixel might vary between Midgard Implementations, but
990 * \b not for platforms using the Mali-T604. This information is placed in
991 * the reference configuration files.
993 * The System Integrator creates the following structure:
995 * - platform_XYZ/plat
996 * - platform_XYZ/plat/plat_config.h
998 * They then edit plat_config.h, using the example plat_config.h files as a
1001 * At the very least, the customer must set @ref CONFIG_GPU_CORE_TYPE, and will
1002 * receive a helpful \#error message if they do not do this correctly. This
1003 * selects the Reference Configuration for the Midgard Implementation. The rationale
1004 * behind this decision (against asking the customer to write \#include
1005 * <gpus/mali_t600.h> in their plat_config.h) is as follows:
1006 * - This mechanism 'looks' like a regular config file (such as Linux's
1008 * - It is difficult to get wrong in a way that will produce strange build
1010 * - They need not know where the mali_t600.h, other_midg_gpu.h etc. files are stored - and
1011 * so they won't accidentally pick another file with 'mali_t600' in its name
1012 * - When the build doesn't work, the System Integrator may think the DDK is
1013 * doesn't work, and attempt to fix it themselves:
1014 * - For the @ref CONFIG_GPU_CORE_TYPE mechanism, the only way to get past the
1015 * error is to set @ref CONFIG_GPU_CORE_TYPE, and this is what the \#error tells
1017 * - For a \#include mechanism, checks must still be made elsewhere, which the
1018 * System Integrator may try working around by setting \#defines (such as
1019 * VA_BITS) themselves in their plat_config.h. In the worst case, they may
1020 * set the prevention-mechanism \#define of
1021 * "A_CORRECT_MIDGARD_CORE_WAS_CHOSEN".
1022 * - In this case, they would believe they are on the right track, because
1023 * the build progresses with their fix, but with errors elsewhere.
1025 * However, there is nothing to prevent the customer using \#include to organize
1026 * their own configurations files hierarchically.
1028 * The mechanism for the header file processing is as follows:
1031 digraph plat_config_mechanism {
1040 rank = same; ordering = out;
1042 "midg/midg_gpu_props.h";
1043 "base/midg_gpus/mali_t600.h";
1044 "base/midg_gpus/other_midg_gpu.h";
1046 { rank = same; "plat/plat_config.h"; }
1049 "midg/midg.h" [ shape=box ];
1050 gpu_chooser [ label="" style="invisible" width=0 height=0 fixedsize=true ];
1051 select_gpu [ label="Mali-T600 | Other\n(select_gpu.h)" shape=polygon,sides=4,distortion=0.25 width=3.3 height=0.99 fixedsize=true ] ;
1054 { rank = same; "plat/plat_config.h"; }
1055 { rank = same; "mali_base.h"; }
1057 "mali_base.h" -> "midg/midg.h" -> "midg/midg_gpu_props.h";
1058 "mali_base.h" -> "plat/plat_config.h" ;
1059 "mali_base.h" -> select_gpu ;
1061 "plat/plat_config.h" -> gpu_chooser [style="dotted,bold" dir=none weight=4] ;
1062 gpu_chooser -> select_gpu [style="dotted,bold"] ;
1064 select_gpu -> "base/midg_gpus/mali_t600.h" ;
1065 select_gpu -> "base/midg_gpus/other_midg_gpu.h" ;
1070 * @section sec_base_user_api_gpuprops_kernel Kernel Operation
1072 * During Base Context Create time, user-side makes a single kernel call:
1073 * - A call to fill user memory with GPU information structures
1075 * The kernel-side will fill the provided the entire processed @ref base_gpu_props
1076 * structure, because this information is required in both
1077 * user and kernel side; it does not make sense to decode it twice.
1079 * Coherency groups must be derived from the bitmasks, but this can be done
1080 * kernel side, and just once at kernel startup: Coherency groups must already
1081 * be known kernel-side, to support chains that specify a 'Only Coherent Group'
1082 * SW requirement, or 'Only Coherent Group with Tiler' SW requirement.
1084 * @section sec_base_user_api_gpuprops_cocalc Coherency Group calculation
1085 * Creation of the coherent group data is done at device-driver startup, and so
1086 * is one-time. This will most likely involve a loop with CLZ, shifting, and
1087 * bit clearing on the L2_PRESENT or L3_PRESENT masks, depending on whether the
1088 * system is L2 or L2+L3 Coherent. The number of shader cores is done by a
1089 * population count, since faulty cores may be disabled during production,
1090 * producing a non-contiguous mask.
1092 * The memory requirements for this algoirthm can be determined either by a u64
1093 * population count on the L2/L3_PRESENT masks (a LUT helper already is
1094 * requried for the above), or simple assumption that there can be no more than
1095 * 16 coherent groups, since core groups are typically 4 cores.
1099 * @addtogroup base_user_api_gpuprops User-side Base GPU Property Query APIs
1104 * @addtogroup base_user_api_gpuprops_dyn Dynamic HW Properties
1108 #define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
1110 #define BASE_MAX_COHERENT_GROUPS 16
1112 struct mali_base_gpu_core_props {
1114 * Product specific value.
1116 midg_product_id product_id;
1119 * Status of the GPU release.
1120 * No defined values, but starts at 0 and increases by one for each release
1121 * status (alpha, beta, EAC, etc.).
1122 * 4 bit values (0-15).
1127 * Minor release number of the GPU. "P" part of an "RnPn" release number.
1128 * 8 bit values (0-255).
1133 * Major release number of the GPU. "R" part of an "RnPn" release number.
1134 * 4 bit values (0-15).
1141 * @usecase GPU clock speed is not specified in the Midgard Architecture, but is
1142 * <b>necessary for OpenCL's clGetDeviceInfo() function</b>.
1147 * @usecase GPU clock max/min speed is required for computing best/worst case
1148 * in tasks as job scheduling ant irq_throttling. (It is not specified in the
1149 * Midgard Architecture).
1151 u32 gpu_freq_khz_max;
1152 u32 gpu_freq_khz_min;
1155 * Size of the shader program counter, in bits.
1157 u32 log2_program_counter_size;
1160 * TEXTURE_FEATURES_x registers, as exposed by the GPU. This is a
1161 * bitpattern where a set bit indicates that the format is supported.
1163 * Before using a texture format, it is recommended that the corresponding
1166 u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
1169 * Theoretical maximum memory available to the GPU. It is unlikely that a
1170 * client will be able to allocate all of this memory for their own
1171 * purposes, but this at least provides an upper bound on the memory
1172 * available to the GPU.
1174 * This is required for OpenCL's clGetDeviceInfo() call when
1175 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
1176 * client will not be expecting to allocate anywhere near this value.
1178 u64 gpu_available_memory_size;
1183 * More information is possible - but associativity and bus width are not
1184 * required by upper-level apis.
1186 struct mali_base_gpu_l2_cache_props {
1189 u8 num_l2_slices; /* Number of L2C slices. 1 or higher */
1193 struct mali_base_gpu_l3_cache_props {
1199 struct mali_base_gpu_tiler_props {
1200 u32 bin_size_bytes; /* Max is 4*2^15 */
1201 u32 max_active_levels; /* Max is 2^15 */
1205 * GPU threading system details.
1207 struct mali_base_gpu_thread_props {
1208 u32 max_threads; /* Max. number of threads per core */
1209 u32 max_workgroup_size; /* Max. number of threads per workgroup */
1210 u32 max_barrier_size; /* Max. number of threads that can synchronize on a simple barrier */
1211 u16 max_registers; /* Total size [1..65535] of the register file available per core. */
1212 u8 max_task_queue; /* Max. tasks [1..255] which may be sent to a core before it becomes blocked. */
1213 u8 max_thread_group_split; /* Max. allowed value [1..15] of the Thread Group Split field. */
1214 u8 impl_tech; /* 0 = Not specified, 1 = Silicon, 2 = FPGA, 3 = SW Model/Emulation */
1219 * @brief descriptor for a coherent group
1221 * \c core_mask exposes all cores in that coherent group, and \c num_cores
1222 * provides a cached population-count for that mask.
1224 * @note Whilst all cores are exposed in the mask, not all may be available to
1225 * the application, depending on the Kernel Job Scheduler policy. Therefore,
1226 * the application should not further restrict the core mask itself, as it may
1227 * result in an empty core mask. However, it can guarentee that there will be
1228 * at least one core available for each core group exposed .
1230 * @usecase Chains marked at certain user-side priorities (e.g. the Long-running
1231 * (batch) priority ) can be prevented from running on entire core groups by the
1232 * Kernel Chain Scheduler policy.
1234 * @note if u64s must be 8-byte aligned, then this structure has 32-bits of wastage.
1236 struct mali_base_gpu_coherent_group {
1237 u64 core_mask; /**< Core restriction mask required for the group */
1238 u16 num_cores; /**< Number of cores in the group */
1243 * @brief Coherency group information
1245 * Note that the sizes of the members could be reduced. However, the \c group
1246 * member might be 8-byte aligned to ensure the u64 core_mask is 8-byte
1247 * aligned, thus leading to wastage if the other members sizes were reduced.
1249 * The groups are sorted by core mask. The core masks are non-repeating and do
1252 struct mali_base_gpu_coherent_group_info {
1256 * Number of core groups (coherent or not) in the GPU. Equivalent to the number of L2 Caches.
1258 * The GPU Counter dumping writes 2048 bytes per core group, regardless of
1259 * whether the core groups are coherent or not. Hence this member is needed
1260 * to calculate how much memory is required for dumping.
1262 * @note Do not use it to work out how many valid elements are in the
1263 * group[] member. Use num_groups instead.
1265 u32 num_core_groups;
1268 * Coherency features of the memory, accessed by @ref midg_mem_features
1271 midg_mem_features coherency;
1276 * Descriptors of coherent groups
1278 struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
1282 * A complete description of the GPU's Hardware Configuration Discovery
1285 * The information is presented inefficiently for access. For frequent access,
1286 * the values should be better expressed in an unpacked form in the
1287 * base_gpu_props structure.
1289 * @usecase The raw properties in @ref midg_raw_gpu_props are necessary to
1290 * allow a user of the Mali Tools (e.g. PAT) to determine "Why is this device
1291 * behaving differently?". In this case, all information about the
1292 * configuration is potentially useful, but it <b>does not need to be processed
1293 * by the driver</b>. Instead, the raw registers can be processed by the Mali
1294 * Tools software on the host PC.
1297 struct midg_raw_gpu_props {
1303 midg_cache_features l2_features;
1304 midg_cache_features l3_features;
1305 midg_mem_features mem_features;
1306 midg_mmu_features mmu_features;
1308 midg_as_present as_present;
1311 midg_js_features js_features[MIDG_MAX_JOB_SLOTS];
1312 midg_tiler_features tiler_features;
1313 u32 texture_features[3];
1317 u32 thread_max_threads;
1318 u32 thread_max_workgroup_size;
1319 u32 thread_max_barrier_size;
1320 u32 thread_features;
1326 * Return structure for _mali_base_get_gpu_props().
1328 * NOTE: the raw_props member in this datastructure contains the register
1329 * values from which the value of the other members are derived. The derived
1330 * members exist to allow for efficient access and/or shielding the details
1331 * of the layout of the registers.
1334 typedef struct mali_base_gpu_props {
1335 struct mali_base_gpu_core_props core_props;
1336 struct mali_base_gpu_l2_cache_props l2_props;
1337 struct mali_base_gpu_l3_cache_props l3_props;
1338 struct mali_base_gpu_tiler_props tiler_props;
1339 struct mali_base_gpu_thread_props thread_props;
1341 /** This member is large, likely to be 128 bytes */
1342 struct midg_raw_gpu_props raw_props;
1344 /** This must be last member of the structure */
1345 struct mali_base_gpu_coherent_group_info coherency_info;
1348 /** @} end group base_user_api_gpuprops_dyn */
1350 /** @} end group base_user_api_gpuprops */
1353 * @addtogroup base_user_api_core User-side Base core APIs
1358 * \enum base_context_create_flags
1360 * Flags to pass to ::base_context_init.
1361 * Flags can be ORed together to enable multiple things.
1363 * These share the same space as @ref basep_context_private_flags, and so must
1364 * not collide with them.
1366 enum base_context_create_flags {
1368 BASE_CONTEXT_CREATE_FLAG_NONE = 0,
1370 /** Base context is embedded in a cctx object (flag used for CINSTR software counter macros) */
1371 BASE_CONTEXT_CCTX_EMBEDDED = (1u << 0),
1373 /** Base context is a 'System Monitor' context for Hardware counters.
1375 * One important side effect of this is that job submission is disabled. */
1376 BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED = (1u << 1),
1378 /** Base context flag indicating a 'hint' that this context uses Compute
1381 * Specifially, this means that it only sends atoms that <b>do not</b>
1382 * contain the following @ref base_jd_core_req :
1386 * Violation of these requirements will cause the Job-Chains to be rejected.
1388 * In addition, it is inadvisable for the atom's Job-Chains to contain Jobs
1389 * of the following @ref midg_job_type (whilst it may work now, it may not
1391 * - @ref MIDG_JOB_VERTEX
1392 * - @ref MIDG_JOB_GEOMETRY
1394 * @note An alternative to using this is to specify the BASE_JD_REQ_ONLY_COMPUTE
1395 * requirement in atoms.
1397 BASE_CONTEXT_HINT_ONLY_COMPUTE = (1u << 2)
1401 * Bitpattern describing the ::base_context_create_flags that can be passed to base_context_init()
1403 #define BASE_CONTEXT_CREATE_ALLOWED_FLAGS \
1404 (((u32)BASE_CONTEXT_CCTX_EMBEDDED) | \
1405 ((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1406 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1409 * Bitpattern describing the ::base_context_create_flags that can be passed to the kernel
1411 #define BASE_CONTEXT_CREATE_KERNEL_FLAGS \
1412 (((u32)BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED) | \
1413 ((u32)BASE_CONTEXT_HINT_ONLY_COMPUTE))
1416 * Private flags used on the base context
1418 * These start at bit 31, and run down to zero.
1420 * They share the same space as @ref base_context_create_flags, and so must
1421 * not collide with them.
1423 enum basep_context_private_flags {
1424 /** Private flag tracking whether job descriptor dumping is disabled */
1425 BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED = (1 << 31)
1428 /** @} end group base_user_api_core */
1430 /** @} end group base_user_api */
1433 * @addtogroup base_plat_config_gpuprops Base Platform Config GPU Properties
1436 * C Pre-processor macros are exposed here to do with Platform
1440 * - GPU Properties that are constant on a particular Midgard Family
1441 * Implementation e.g. Maximum samples per pixel on Mali-T600.
1442 * - General platform config for the GPU, such as the GPU major and minor
1446 /** @} end group base_plat_config_gpuprops */
1449 * @addtogroup base_api Base APIs
1453 * @addtogroup basecpuprops Base CPU Properties
1458 * @brief CPU Property Flag for base_cpu_props::cpu_flags, indicating a
1459 * Little Endian System. If not set in base_cpu_props::cpu_flags, then the
1460 * system is Big Endian.
1462 * The compile-time equivalent is @ref OSU_CONFIG_CPU_LITTLE_ENDIAN.
1464 #define BASE_CPU_PROPERTY_FLAG_LITTLE_ENDIAN F_BIT_0
1468 * @brief Platform dynamic CPU ID properties structure
1470 typedef struct base_cpu_id_props
1483 * ASCII code of implementer trademark
1503 Validity of CPU id where 0-invalid and
1504 1-valid only if ALL the cpu_id props are valid
1512 /** @brief Platform Dynamic CPU properties structure */
1513 typedef struct base_cpu_props {
1514 u32 nr_cores; /**< Number of CPU cores */
1517 * CPU page size as a Logarithm to Base 2. The compile-time
1518 * equivalent is @ref OSU_CONFIG_CPU_PAGE_SIZE_LOG2
1520 u32 cpu_page_size_log2;
1523 * CPU L1 Data cache line size as a Logarithm to Base 2. The compile-time
1524 * equivalent is @ref OSU_CONFIG_CPU_L1_DCACHE_LINE_SIZE_LOG2.
1526 u32 cpu_l1_dcache_line_size_log2;
1529 * CPU L1 Data cache size, in bytes. The compile-time equivalient is
1530 * @ref OSU_CONFIG_CPU_L1_DCACHE_SIZE.
1532 * This CPU Property is mainly provided to implement OpenCL's
1533 * clGetDeviceInfo(), which allows the CL_DEVICE_GLOBAL_MEM_CACHE_SIZE
1534 * hint to be queried.
1536 u32 cpu_l1_dcache_size;
1539 * CPU Property Flags bitpattern.
1541 * This is a combination of bits as specified by the macros prefixed with
1542 * 'BASE_CPU_PROPERTY_FLAG_'.
1547 * Maximum clock speed in MHz.
1548 * @usecase 'Maximum' CPU Clock Speed information is required by OpenCL's
1549 * clGetDeviceInfo() function for the CL_DEVICE_MAX_CLOCK_FREQUENCY hint.
1551 u32 max_cpu_clock_speed_mhz;
1554 * @brief Total memory, in bytes.
1556 * This is the theoretical maximum memory available to the CPU. It is
1557 * unlikely that a client will be able to allocate all of this memory for
1558 * their own purposes, but this at least provides an upper bound on the
1559 * memory available to the CPU.
1561 * This is required for OpenCL's clGetDeviceInfo() call when
1562 * CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL CPU devices.
1564 u64 available_memory_size;
1567 * CPU ID detailed info
1569 base_cpu_id_props cpu_id;
1573 /** @} end group basecpuprops */
1575 /** @} end group base_api */
1577 typedef struct base_profiling_controls {
1578 u32 profiling_controls[FBDUMP_CONTROL_MAX];
1579 } base_profiling_controls;
1581 #endif /* _BASE_KERNEL_H_ */