drivers/gpu/arm/t6xx/kbase/mali_base_hwconfig.h

   1 /*
   2  *
   3  * (C) COPYRIGHT ARM Limited. All rights reserved.
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * A copy of the licence is included with the program, and can also be obtained
  11  * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  12  * Boston, MA  02110-1301, USA.
  13  *
  14  */
  15
  16
  17
  18
  19
  20 /**
  21  * @file
  22  * Software workarounds configuration for Hardware issues.
  23  */
  24
  25 #ifndef _BASE_HWCONFIG_H_
  26 #define _BASE_HWCONFIG_H_
  27
  28 #include <malisw/mali_malisw.h>
  29
  30 /**
  31  * List of all hw features.
  32  *
  33  */
  34 typedef enum base_hw_feature {
  35         /* Allow soft/hard stopping of job depending on job chain flag */
  36         BASE_HW_FEATURE_JOBCHAIN_DISAMBIGUATION,
  37
  38         /* Allow writes to SHADER_PWRON and TILER_PWRON registers while these cores are currently transitioning to OFF power state */
  39         BASE_HW_FEATURE_PWRON_DURING_PWROFF_TRANS,
  40
  41         /* The BASE_HW_FEATURE_END value must be the last feature listed in this enumeration
  42          * and must be the last value in each array that contains the list of features
  43          * for a particular HW version.
  44          */
  45         BASE_HW_FEATURE_END
  46 } base_hw_feature;
  47
  48 static const base_hw_feature base_hw_features_generic[] = {
  49         BASE_HW_FEATURE_END
  50 };
  51
  52 static const base_hw_feature base_hw_features_t76x[] = {
  53         BASE_HW_FEATURE_JOBCHAIN_DISAMBIGUATION,
  54         BASE_HW_FEATURE_PWRON_DURING_PWROFF_TRANS,
  55         BASE_HW_FEATURE_END
  56 };
  57
  58
  59 /**
  60  * List of all workarounds.
  61  *
  62  */
  63
  64 typedef enum base_hw_issue {
  65
  66         /* The current version of the model doesn't support Soft-Stop */
  67         BASE_HW_ISSUE_5736,
  68
  69         /* Need way to guarantee that all previously-translated memory accesses are commited */
  70         BASE_HW_ISSUE_6367,
  71
  72         /* Result swizzling doesn't work for GRDESC/GRDESC_DER */
  73         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
  74         BASE_HW_ISSUE_6398,
  75
  76         /* Unaligned load stores crossing 128 bit boundaries will fail */
  77         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
  78         BASE_HW_ISSUE_6402,
  79
  80         /* On job complete with non-done the cache is not flushed */
  81         BASE_HW_ISSUE_6787,
  82
  83         /* WLS allocation does not respect the Instances field in the Thread Storage Descriptor */
  84         BASE_HW_ISSUE_7027,
  85
  86         /* The clamp integer coordinate flag bit of the sampler descriptor is reserved */
  87         BASE_HW_ISSUE_7144,
  88
  89         /* TEX_INDEX LOD is always use converted */
  90         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
  91         BASE_HW_ISSUE_8073,
  92
  93         /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a instrumentation dump if
  94            PRFCNT_TILER_EN is enabled */
  95         BASE_HW_ISSUE_8186,
  96
  97         /* Do not set .skip flag on the GRDESC, GRDESC_DER, DELTA, MOV, and NOP texturing instructions */
  98         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
  99         BASE_HW_ISSUE_8215,
 100
 101         /* TIB: Reports faults from a vtile which has not yet been allocated */
 102         BASE_HW_ISSUE_8245,
 103
 104         /* WLMA memory goes wrong when run on shader cores other than core 0. */
 105         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 106         BASE_HW_ISSUE_8250,
 107
 108         /* Hierz doesn't work when stenciling is enabled */
 109         BASE_HW_ISSUE_8260,
 110
 111         /* Livelock in L0 icache */
 112         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 113         BASE_HW_ISSUE_8280,
 114
 115         /* uTLB deadlock could occur when writing to an invalid page at the same time as
 116          * access to a valid page in the same uTLB cache line ( == 4 PTEs == 16K block of mapping) */
 117         BASE_HW_ISSUE_8316,
 118
 119         /* TLS base address mismatch, must stay below 1MB TLS */
 120         BASE_HW_ISSUE_8381,
 121
 122         /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is still executing */
 123         BASE_HW_ISSUE_8394,
 124
 125         /* CSE : Sends a TERMINATED response for a task that should not be terminated */
 126         /* (Note that PRLAM-8379 also uses this workaround) */
 127         BASE_HW_ISSUE_8401,
 128
 129         /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader, Cache Flush, Tiler)
 130          * jobs causes 0x58 error on tiler job. */
 131         BASE_HW_ISSUE_8408,
 132
 133         /* Disable the Pause Buffer in the LS pipe. */
 134         BASE_HW_ISSUE_8443,
 135
 136         /* Stencil test enable 1->0 sticks */
 137         BASE_HW_ISSUE_8456,
 138
 139         /* Tiler heap issue using FBOs or multiple processes using the tiler simultaneously */
 140         /* (Note that PRLAM-9049 also uses this work-around) */
 141         BASE_HW_ISSUE_8564,
 142
 143         /* Livelock issue using atomic instructions (particularly when using atomic_cmpxchg as a spinlock) */
 144         BASE_HW_ISSUE_8791,
 145
 146         /* Fused jobs are not supported (for various reasons) */
 147         /* Jobs with relaxed dependencies do not support soft-stop */
 148         /* (Note that PRLAM-8803, PRLAM-8393, PRLAM-8559, PRLAM-8601 & PRLAM-8607 all use this work-around) */
 149         BASE_HW_ISSUE_8803,
 150
 151         /* Blend shader output is wrong for certain formats */
 152         BASE_HW_ISSUE_8833,
 153
 154         /* Occlusion queries can create false 0 result in boolean and counter modes */
 155         BASE_HW_ISSUE_8879,
 156
 157         /* Output has half intensity with blend shaders enabled on 8xMSAA. */
 158         BASE_HW_ISSUE_8896,
 159
 160         /* 8xMSAA does not work with CRC */
 161         BASE_HW_ISSUE_8975,
 162
 163         /* Boolean occlusion queries don't work properly due to sdc issue. */
 164         BASE_HW_ISSUE_8986,
 165
 166         /* Change in RMUs in use causes problems related with the core's SDC */
 167         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 168         BASE_HW_ISSUE_8987,
 169
 170         /* Occlusion query result is not updated if color writes are disabled. */
 171         BASE_HW_ISSUE_9010,
 172
 173         /* Problem with number of work registers in the RSD if set to 0 */
 174         BASE_HW_ISSUE_9275,
 175
 176         /* Translate load/store moves into decode instruction */
 177         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 178         BASE_HW_ISSUE_9418,
 179
 180         /* Incorrect coverage mask for 8xMSAA */
 181         BASE_HW_ISSUE_9423,
 182
 183         /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop won't complete until all 4 tasks have completed */
 184         BASE_HW_ISSUE_9435,
 185
 186         /* HT: Tiler returns TERMINATED for command that hasn't been terminated */
 187         BASE_HW_ISSUE_9510,
 188
 189         /* Livelock issue using atomic_cmpxchg */
 190         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 191         BASE_HW_ISSUE_9566,
 192
 193         /* Occasionally the GPU will issue multiple page faults for the same address before the MMU page table has been read by the GPU */
 194         BASE_HW_ISSUE_9630,
 195
 196         /* Must clear the 64 byte private state of the tiler information */
 197         BASE_HW_ISSUE_10127,
 198
 199         /* RA DCD load request to SDC returns invalid load ignore causing colour buffer mismatch */
 200         BASE_HW_ISSUE_10327,
 201
 202         /* Occlusion query result may be updated prematurely when fragment shader alters coverage */
 203         BASE_HW_ISSUE_10410,
 204
 205         /* TEXGRD doesn't honor Sampler Descriptor LOD clamps nor bias */
 206         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 207         BASE_HW_ISSUE_10471,
 208
 209         /* MAG / MIN filter selection happens after image descriptor clamps were applied */
 210         BASE_HW_ISSUE_10472,
 211
 212         /* GPU interprets sampler and image descriptor pointer array sizes as one bigger than they are defined in midg structures */
 213         BASE_HW_ISSUE_10487,
 214
 215         /* ld_special 0x1n applies SRGB conversion */
 216         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 217         BASE_HW_ISSUE_10607,
 218
 219         /* LD_SPECIAL instruction reads incorrect RAW tile buffer value when internal tib format is R10G10B10A2 */
 220         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 221         BASE_HW_ISSUE_10632,
 222
 223         /* MMU TLB invalidation hazards */
 224         BASE_HW_ISSUE_10649,
 225
 226         /* Missing cache flush in multi core-group configuration */
 227         BASE_HW_ISSUE_10676,
 228
 229         /* Indexed format 95 cannot be used with a component swizzle of "set to 1" when sampled as integer texture */
 230         BASE_HW_ISSUE_10682,
 231
 232         /* sometimes HW doesn't invalidate cached VPDs when it has to */
 233         BASE_HW_ISSUE_10684,
 234
 235         /* Chicken bit on (t67x_r1p0 and t72x) to work for a HW workaround in compiler */
 236
 237         BASE_HW_ISSUE_10797,
 238
 239         /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
 240         BASE_HW_ISSUE_10817,
 241
 242         /* Fragment frontend heuristic bias to force early-z required */
 243         BASE_HW_ISSUE_10821,
 244
 245         /* Intermittent missing interrupt on job completion */
 246         BASE_HW_ISSUE_10883,
 247
 248         /* Depth bounds incorrectly normalized in hierz depth bounds test */
 249         BASE_HW_ISSUE_10931,
 250
 251         /* Incorrect cubemap sampling */
 252         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 253         BASE_HW_ISSUE_10946,
 254
 255         /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR (similar to issue 10817) and can use BASE_HW_ISSUE_10817 workaround  */
 256         BASE_HW_ISSUE_10959,
 257
 258         /* Soft-stopped fragment shader job can restart with out-of-bound restart index  */
 259         BASE_HW_ISSUE_10969,
 260
 261         /* TEX_INDEX lod selection (immediate , register) not working with 8.8 encoding for levels > 1 */
 262         /* NOTE: compiler workaround: keep in sync with _essl_hwrev_needs_workaround() */
 263         BASE_HW_ISSUE_10995,
 264
 265         /* T76X hw issues */
 266
 267         /* 16xMSAA implementation wasn't finished */
 268         BASE_HW_ISSUE_T76X_26,
 269
 270         /* Forward pixel kill doesn't work with MRT */
 271         BASE_HW_ISSUE_T76X_2121,
 272
 273     /* CRC not working with MFBD and more than one render target */
 274         BASE_HW_ISSUE_T76X_2315,
 275
 276     /* Some indexed formats not supported for MFBD preload. */
 277         BASE_HW_ISSUE_T76X_2686,
 278
 279         /* Must disable CRC if the tile output size is 8 bytes or less. */
 280         BASE_HW_ISSUE_T76X_2712,
 281
 282         /* DBD clean pixel enable bit is reserved */
 283         BASE_HW_ISSUE_T76X_2772,
 284
 285         /* AFBC is not supported for T76X beta. */
 286         BASE_HW_ISSUE_T76X_2906,
 287
 288         /* Prevent MMU deadlock for T76X beta. */
 289         BASE_HW_ISSUE_T76X_3285,
 290
 291         /* The BASE_HW_ISSUE_END value must be the last issue listed in this enumeration
 292          * and must be the last value in each array that contains the list of workarounds
 293          * for a particular HW version.
 294          */
 295         BASE_HW_ISSUE_END
 296 } base_hw_issue;
 297
 298 /**
 299  * Workarounds configuration for each HW revision
 300  */
 301 /* Mali T60x r0p0-15dev0 - 2011-W39-stable-9 */
 302 static const base_hw_issue base_hw_issues_t60x_r0p0_15dev0[] = {
 303         BASE_HW_ISSUE_6367,
 304         BASE_HW_ISSUE_6398,
 305         BASE_HW_ISSUE_6402,
 306         BASE_HW_ISSUE_6787,
 307         BASE_HW_ISSUE_7027,
 308         BASE_HW_ISSUE_7144,
 309         BASE_HW_ISSUE_8073,
 310         BASE_HW_ISSUE_8186,
 311         BASE_HW_ISSUE_8215,
 312         BASE_HW_ISSUE_8245,
 313         BASE_HW_ISSUE_8250,
 314         BASE_HW_ISSUE_8260,
 315         BASE_HW_ISSUE_8280,
 316         BASE_HW_ISSUE_8316,
 317         BASE_HW_ISSUE_8381,
 318         BASE_HW_ISSUE_8394,
 319         BASE_HW_ISSUE_8401,
 320         BASE_HW_ISSUE_8408,
 321         BASE_HW_ISSUE_8443,
 322         BASE_HW_ISSUE_8456,
 323         BASE_HW_ISSUE_8564,
 324         BASE_HW_ISSUE_8791,
 325         BASE_HW_ISSUE_8803,
 326         BASE_HW_ISSUE_8833,
 327         BASE_HW_ISSUE_8896,
 328         BASE_HW_ISSUE_8975,
 329         BASE_HW_ISSUE_8986,
 330         BASE_HW_ISSUE_8987,
 331         BASE_HW_ISSUE_9010,
 332         BASE_HW_ISSUE_9275,
 333         BASE_HW_ISSUE_9418,
 334         BASE_HW_ISSUE_9423,
 335         BASE_HW_ISSUE_9435,
 336         BASE_HW_ISSUE_9510,
 337         BASE_HW_ISSUE_9566,
 338         BASE_HW_ISSUE_9630,
 339         BASE_HW_ISSUE_10410,
 340         BASE_HW_ISSUE_10471,
 341         BASE_HW_ISSUE_10472,
 342         BASE_HW_ISSUE_10487,
 343         BASE_HW_ISSUE_10607,
 344         BASE_HW_ISSUE_10632,
 345         BASE_HW_ISSUE_10649,
 346         BASE_HW_ISSUE_10676,
 347         BASE_HW_ISSUE_10682,
 348         BASE_HW_ISSUE_10684,
 349         BASE_HW_ISSUE_10883,
 350         BASE_HW_ISSUE_10931,
 351         BASE_HW_ISSUE_10946,
 352         BASE_HW_ISSUE_10969,
 353         BASE_HW_ISSUE_10995,
 354         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 355         BASE_HW_ISSUE_END
 356 };
 357
 358 /* Mali T60x r0p0-00rel0 - 2011-W46-stable-13c */
 359 static const base_hw_issue base_hw_issues_t60x_r0p0_eac[] = {
 360         BASE_HW_ISSUE_6367,
 361         BASE_HW_ISSUE_6402,
 362         BASE_HW_ISSUE_6787,
 363         BASE_HW_ISSUE_7027,
 364         BASE_HW_ISSUE_8408,
 365         BASE_HW_ISSUE_8564,
 366         BASE_HW_ISSUE_8803,
 367         BASE_HW_ISSUE_8975,
 368         BASE_HW_ISSUE_9010,
 369         BASE_HW_ISSUE_9275,
 370         BASE_HW_ISSUE_9418,
 371         BASE_HW_ISSUE_9423,
 372         BASE_HW_ISSUE_9435,
 373         BASE_HW_ISSUE_9510,
 374         BASE_HW_ISSUE_10410,
 375         BASE_HW_ISSUE_10471,
 376         BASE_HW_ISSUE_10472,
 377         BASE_HW_ISSUE_10487,
 378         BASE_HW_ISSUE_10607,
 379         BASE_HW_ISSUE_10632,
 380         BASE_HW_ISSUE_10649,
 381         BASE_HW_ISSUE_10676,
 382         BASE_HW_ISSUE_10682,
 383         BASE_HW_ISSUE_10684,
 384         BASE_HW_ISSUE_10883,
 385         BASE_HW_ISSUE_10931,
 386         BASE_HW_ISSUE_10946,
 387         BASE_HW_ISSUE_10969,
 388         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 389         BASE_HW_ISSUE_END
 390 };
 391
 392 /* Mali T60x r0p1 */
 393 static const base_hw_issue base_hw_issues_t60x_r0p1[] = {
 394         BASE_HW_ISSUE_6367,
 395         BASE_HW_ISSUE_6402,
 396         BASE_HW_ISSUE_6787,
 397         BASE_HW_ISSUE_7027,
 398         BASE_HW_ISSUE_8408,
 399         BASE_HW_ISSUE_8564,
 400         BASE_HW_ISSUE_8803,
 401         BASE_HW_ISSUE_8975,
 402         BASE_HW_ISSUE_9010,
 403         BASE_HW_ISSUE_9275,
 404         BASE_HW_ISSUE_9435,
 405         BASE_HW_ISSUE_9510,
 406         BASE_HW_ISSUE_10410,
 407         BASE_HW_ISSUE_10471,
 408         BASE_HW_ISSUE_10472,
 409         BASE_HW_ISSUE_10487,
 410         BASE_HW_ISSUE_10607,
 411         BASE_HW_ISSUE_10632,
 412         BASE_HW_ISSUE_10649,
 413         BASE_HW_ISSUE_10676,
 414         BASE_HW_ISSUE_10682,
 415         BASE_HW_ISSUE_10684,
 416         BASE_HW_ISSUE_10883,
 417         BASE_HW_ISSUE_10931,
 418         BASE_HW_ISSUE_10946,
 419         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 420         BASE_HW_ISSUE_END
 421 };
 422
 423 /* Mali T65x r0p1 */
 424 static const base_hw_issue base_hw_issues_t65x_r0p1[] = {
 425         BASE_HW_ISSUE_6367,
 426         BASE_HW_ISSUE_6402,
 427         BASE_HW_ISSUE_6787,
 428         BASE_HW_ISSUE_7027,
 429         BASE_HW_ISSUE_8408,
 430         BASE_HW_ISSUE_8564,
 431         BASE_HW_ISSUE_8803,
 432         BASE_HW_ISSUE_9010,
 433         BASE_HW_ISSUE_9275,
 434         BASE_HW_ISSUE_9435,
 435         BASE_HW_ISSUE_9510,
 436         BASE_HW_ISSUE_10410,
 437         BASE_HW_ISSUE_10471,
 438         BASE_HW_ISSUE_10472,
 439         BASE_HW_ISSUE_10487,
 440         BASE_HW_ISSUE_10607,
 441         BASE_HW_ISSUE_10632,
 442         BASE_HW_ISSUE_10649,
 443         BASE_HW_ISSUE_10676,
 444         BASE_HW_ISSUE_10682,
 445         BASE_HW_ISSUE_10684,
 446         BASE_HW_ISSUE_10883,
 447         BASE_HW_ISSUE_10931,
 448         BASE_HW_ISSUE_10946,
 449         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 450         BASE_HW_ISSUE_END
 451 };
 452
 453 /* Mali T62x r0p0 */
 454 static const base_hw_issue base_hw_issues_t62x_r0p0[] = {
 455         BASE_HW_ISSUE_6402,
 456         BASE_HW_ISSUE_8803,
 457         BASE_HW_ISSUE_9435,
 458         BASE_HW_ISSUE_10127,
 459         BASE_HW_ISSUE_10327,
 460         BASE_HW_ISSUE_10410,
 461         BASE_HW_ISSUE_10471,
 462         BASE_HW_ISSUE_10472,
 463         BASE_HW_ISSUE_10487,
 464         BASE_HW_ISSUE_10607,
 465         BASE_HW_ISSUE_10632,
 466         BASE_HW_ISSUE_10649,
 467         BASE_HW_ISSUE_10676,
 468         BASE_HW_ISSUE_10682,
 469         BASE_HW_ISSUE_10684,
 470         BASE_HW_ISSUE_10817,
 471         BASE_HW_ISSUE_10821,
 472         BASE_HW_ISSUE_10883,
 473         BASE_HW_ISSUE_10931,
 474         BASE_HW_ISSUE_10946,
 475         BASE_HW_ISSUE_10959,
 476         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 477         BASE_HW_ISSUE_END
 478 };
 479
 480 /* Mali T67x r0p0 */
 481 static const base_hw_issue base_hw_issues_t67x_r0p0[] = {
 482         BASE_HW_ISSUE_6402,
 483         BASE_HW_ISSUE_8803,
 484         BASE_HW_ISSUE_9435,
 485         BASE_HW_ISSUE_10127,
 486         BASE_HW_ISSUE_10327,
 487         BASE_HW_ISSUE_10410,
 488         BASE_HW_ISSUE_10471,
 489         BASE_HW_ISSUE_10472,
 490         BASE_HW_ISSUE_10487,
 491         BASE_HW_ISSUE_10607,
 492         BASE_HW_ISSUE_10632,
 493         BASE_HW_ISSUE_10649,
 494         BASE_HW_ISSUE_10676,
 495         BASE_HW_ISSUE_10682,
 496         BASE_HW_ISSUE_10684,
 497         BASE_HW_ISSUE_10817,
 498         BASE_HW_ISSUE_10821,
 499         BASE_HW_ISSUE_10883,
 500         BASE_HW_ISSUE_10931,
 501         BASE_HW_ISSUE_10946,
 502         BASE_HW_ISSUE_10959,
 503         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 504         BASE_HW_ISSUE_END
 505 };
 506
 507 /* Mali T62x r0p1 */
 508 static const base_hw_issue base_hw_issues_t62x_r0p1[] = {
 509         BASE_HW_ISSUE_6402,
 510         BASE_HW_ISSUE_8803,
 511         BASE_HW_ISSUE_9435,
 512         BASE_HW_ISSUE_10127,
 513         BASE_HW_ISSUE_10327,
 514         BASE_HW_ISSUE_10410,
 515         BASE_HW_ISSUE_10471,
 516         BASE_HW_ISSUE_10472,
 517         BASE_HW_ISSUE_10487,
 518         BASE_HW_ISSUE_10607,
 519         BASE_HW_ISSUE_10632,
 520         BASE_HW_ISSUE_10649,
 521         BASE_HW_ISSUE_10676,
 522         BASE_HW_ISSUE_10682,
 523         BASE_HW_ISSUE_10684,
 524         BASE_HW_ISSUE_10817,
 525         BASE_HW_ISSUE_10821,
 526         BASE_HW_ISSUE_10883,
 527         BASE_HW_ISSUE_10931,
 528         BASE_HW_ISSUE_10946,
 529         BASE_HW_ISSUE_10959,
 530         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 531         BASE_HW_ISSUE_END
 532 };
 533
 534 /* Mali T67x r0p1 */
 535 static const base_hw_issue base_hw_issues_t67x_r0p1[] = {
 536         BASE_HW_ISSUE_6402,
 537         BASE_HW_ISSUE_8803,
 538         BASE_HW_ISSUE_9435,
 539         BASE_HW_ISSUE_10127,
 540         BASE_HW_ISSUE_10327,
 541         BASE_HW_ISSUE_10410,
 542         BASE_HW_ISSUE_10471,
 543         BASE_HW_ISSUE_10472,
 544         BASE_HW_ISSUE_10487,
 545         BASE_HW_ISSUE_10607,
 546         BASE_HW_ISSUE_10632,
 547         BASE_HW_ISSUE_10649,
 548         BASE_HW_ISSUE_10676,
 549         BASE_HW_ISSUE_10682,
 550         BASE_HW_ISSUE_10684,
 551         BASE_HW_ISSUE_10817,
 552         BASE_HW_ISSUE_10821,
 553         BASE_HW_ISSUE_10883,
 554         BASE_HW_ISSUE_10931,
 555         BASE_HW_ISSUE_10946,
 556         BASE_HW_ISSUE_10959,
 557         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 558         BASE_HW_ISSUE_END
 559 };
 560
 561 /* Mali T62x r1p0 */
 562 static const base_hw_issue base_hw_issues_t62x_r1p0[] = {
 563         BASE_HW_ISSUE_6402,
 564         BASE_HW_ISSUE_8803,
 565         BASE_HW_ISSUE_9435,
 566         BASE_HW_ISSUE_10471,
 567         BASE_HW_ISSUE_10472,
 568         BASE_HW_ISSUE_10649,
 569         BASE_HW_ISSUE_10684,
 570         BASE_HW_ISSUE_10821,
 571         BASE_HW_ISSUE_10883,
 572         BASE_HW_ISSUE_10931,
 573         BASE_HW_ISSUE_10946,
 574         BASE_HW_ISSUE_10959,
 575         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 576         BASE_HW_ISSUE_END
 577 };
 578
 579 /* Mali T67x r1p0 */
 580 static const base_hw_issue base_hw_issues_t67x_r1p0[] = {
 581         BASE_HW_ISSUE_6402,
 582         BASE_HW_ISSUE_8803,
 583         BASE_HW_ISSUE_9435,
 584         BASE_HW_ISSUE_10471,
 585         BASE_HW_ISSUE_10472,
 586         BASE_HW_ISSUE_10649,
 587         BASE_HW_ISSUE_10684,
 588         BASE_HW_ISSUE_10797,
 589         BASE_HW_ISSUE_10821,
 590         BASE_HW_ISSUE_10883,
 591         BASE_HW_ISSUE_10931,
 592         BASE_HW_ISSUE_10946,
 593         BASE_HW_ISSUE_10959,
 594         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 595         BASE_HW_ISSUE_END
 596 };
 597
 598 /* Mali T76x r0p0 beta */
 599 static const base_hw_issue base_hw_issues_t76x_r0p0_beta[] = {
 600         BASE_HW_ISSUE_8803,
 601         BASE_HW_ISSUE_9435,
 602         BASE_HW_ISSUE_10649,
 603         BASE_HW_ISSUE_10821,
 604         BASE_HW_ISSUE_10883,
 605         BASE_HW_ISSUE_10946,
 606         BASE_HW_ISSUE_10959,
 607         BASE_HW_ISSUE_T76X_26,
 608         BASE_HW_ISSUE_T76X_2121,
 609         BASE_HW_ISSUE_T76X_2315,
 610         BASE_HW_ISSUE_T76X_2686,
 611         BASE_HW_ISSUE_T76X_2712,
 612         BASE_HW_ISSUE_T76X_2772,
 613         BASE_HW_ISSUE_T76X_2906,
 614         BASE_HW_ISSUE_T76X_3285,
 615     /* List of hardware issues must end with BASE_HW_ISSUE_END */
 616         BASE_HW_ISSUE_END
 617 };
 618
 619 /* Mali T76x r0p0 */
 620 static const base_hw_issue base_hw_issues_t76x_r0p0[] = {
 621         BASE_HW_ISSUE_8803,
 622         BASE_HW_ISSUE_9435,
 623         BASE_HW_ISSUE_10649,
 624         BASE_HW_ISSUE_10821,
 625         BASE_HW_ISSUE_10883,
 626         BASE_HW_ISSUE_10946,
 627         BASE_HW_ISSUE_10959,
 628         BASE_HW_ISSUE_T76X_26,
 629         BASE_HW_ISSUE_T76X_2712,
 630         BASE_HW_ISSUE_T76X_3285,
 631         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 632         BASE_HW_ISSUE_END
 633 };
 634
 635 /* Mali T72x r0p0 */
 636 static const base_hw_issue base_hw_issues_t72x_r0p0[] = {
 637         BASE_HW_ISSUE_6402,
 638         BASE_HW_ISSUE_8803,
 639         BASE_HW_ISSUE_8975,
 640         BASE_HW_ISSUE_9435,
 641         BASE_HW_ISSUE_10472,
 642         BASE_HW_ISSUE_10649,
 643         BASE_HW_ISSUE_10684,
 644         BASE_HW_ISSUE_10797,
 645         BASE_HW_ISSUE_10821,
 646         BASE_HW_ISSUE_10883,
 647         BASE_HW_ISSUE_10931,
 648         BASE_HW_ISSUE_10946,
 649         BASE_HW_ISSUE_10959,
 650         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 651         BASE_HW_ISSUE_END
 652 };
 653
 654 /* Model configuration
 655  */
 656 static const base_hw_issue base_hw_issues_model_t72x[] =
 657 {
 658         BASE_HW_ISSUE_5736,
 659         BASE_HW_ISSUE_6402, /* NOTE: Fix is present in model r125162 but is not enabled until RTL is fixed */
 660         BASE_HW_ISSUE_9275,
 661         BASE_HW_ISSUE_9435,
 662         BASE_HW_ISSUE_10472,
 663         BASE_HW_ISSUE_10632,
 664         BASE_HW_ISSUE_10797,
 665         BASE_HW_ISSUE_10931,
 666         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 667         BASE_HW_ISSUE_END
 668 };
 669
 670 static const base_hw_issue base_hw_issues_model_t7xx[] =
 671 {
 672         BASE_HW_ISSUE_5736,
 673         BASE_HW_ISSUE_9275,
 674         BASE_HW_ISSUE_9435,
 675         BASE_HW_ISSUE_10931,
 676         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 677         BASE_HW_ISSUE_END
 678 };
 679
 680 static const base_hw_issue base_hw_issues_model_t6xx[] =
 681 {
 682         BASE_HW_ISSUE_5736,
 683         BASE_HW_ISSUE_6402, /* NOTE: Fix is present in model r125162 but is not enabled until RTL is fixed */
 684         BASE_HW_ISSUE_9275,
 685         BASE_HW_ISSUE_9435,
 686         BASE_HW_ISSUE_10472,
 687         BASE_HW_ISSUE_10632,
 688         BASE_HW_ISSUE_10931,
 689         /* List of hardware issues must end with BASE_HW_ISSUE_END */
 690         BASE_HW_ISSUE_END
 691 };
 692
 693 #endif                          /* _BASE_HWCONFIG_H_ */