drivers/gpu/arm/midgard_for_linux/backend/gpu/mali_kbase_time.c

   1 /*
   2  *
   3  * (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * A copy of the licence is included with the program, and can also be obtained
  11  * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  12  * Boston, MA  02110-1301, USA.
  13  *
  14  */
  15
  16
  17
  18 #include <mali_kbase.h>
  19 #include <mali_kbase_hwaccess_time.h>
  20 #include <backend/gpu/mali_kbase_device_internal.h>
  21 #include <backend/gpu/mali_kbase_pm_internal.h>
  22
  23 void kbase_backend_get_gpu_time(struct kbase_device *kbdev, u64 *cycle_counter,
  24                                 u64 *system_time, struct timespec *ts)
  25 {
  26         u32 hi1, hi2;
  27
  28         kbase_pm_request_gpu_cycle_counter(kbdev);
  29
  30         /* Read hi, lo, hi to ensure that overflow from lo to hi is handled
  31          * correctly */
  32         do {
  33                 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
  34                                                                         NULL);
  35                 *cycle_counter = kbase_reg_read(kbdev,
  36                                         GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
  37                 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
  38                                                                         NULL);
  39                 *cycle_counter |= (((u64) hi1) << 32);
  40         } while (hi1 != hi2);
  41
  42         /* Read hi, lo, hi to ensure that overflow from lo to hi is handled
  43          * correctly */
  44         do {
  45                 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
  46                                                                         NULL);
  47                 *system_time = kbase_reg_read(kbdev,
  48                                         GPU_CONTROL_REG(TIMESTAMP_LO), NULL);
  49                 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
  50                                                                         NULL);
  51                 *system_time |= (((u64) hi1) << 32);
  52         } while (hi1 != hi2);
  53
  54         /* Record the CPU's idea of current time */
  55         getrawmonotonic(ts);
  56
  57         kbase_pm_release_gpu_cycle_counter(kbdev);
  58 }
  59
  60 /**
  61  * kbase_wait_write_flush -  Wait for GPU write flush
  62  * @kctx: Context pointer
  63  *
  64  * Wait 1000 GPU clock cycles. This delay is known to give the GPU time to flush
  65  * its write buffer.
  66  *
  67  * Only in use for BASE_HW_ISSUE_6367
  68  *
  69  * Note : If GPU resets occur then the counters are reset to zero, the delay may
  70  * not be as expected.
  71  */
  72 #ifndef CONFIG_MALI_NO_MALI
  73 void kbase_wait_write_flush(struct kbase_context *kctx)
  74 {
  75         u32 base_count = 0;
  76
  77         /*
  78          * The caller must be holding onto the kctx or the call is from
  79          * userspace.
  80          */
  81         kbase_pm_context_active(kctx->kbdev);
  82         kbase_pm_request_gpu_cycle_counter(kctx->kbdev);
  83
  84         while (true) {
  85                 u32 new_count;
  86
  87                 new_count = kbase_reg_read(kctx->kbdev,
  88                                         GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
  89                 /* First time around, just store the count. */
  90                 if (base_count == 0) {
  91                         base_count = new_count;
  92                         continue;
  93                 }
  94
  95                 /* No need to handle wrapping, unsigned maths works for this. */
  96                 if ((new_count - base_count) > 1000)
  97                         break;
  98         }
  99
 100         kbase_pm_release_gpu_cycle_counter(kctx->kbdev);
 101         kbase_pm_context_idle(kctx->kbdev);
 102 }
 103 #endif                          /* CONFIG_MALI_NO_MALI */