3 * (C) COPYRIGHT 2014-2015 ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
22 #include <mali_kbase.h>
23 #include <backend/gpu/mali_kbase_instr_internal.h>
24 #include <backend/gpu/mali_kbase_pm_internal.h>
26 #include <backend/gpu/mali_kbase_device_internal.h>
28 #if !defined(CONFIG_MALI_NO_MALI)
29 void kbase_reg_write(struct kbase_device *kbdev, u16 offset, u32 value,
30 struct kbase_context *kctx)
32 KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
33 KBASE_DEBUG_ASSERT(kctx == NULL || kctx->as_nr != KBASEP_AS_NR_INVALID);
34 KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
35 dev_dbg(kbdev->dev, "w: reg %04x val %08x", offset, value);
36 writel(value, kbdev->reg + offset);
37 if (kctx && kctx->jctx.tb)
38 kbase_device_trace_register_access(kctx, REG_WRITE, offset,
42 KBASE_EXPORT_TEST_API(kbase_reg_write);
44 u32 kbase_reg_read(struct kbase_device *kbdev, u16 offset,
45 struct kbase_context *kctx)
48 KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
49 KBASE_DEBUG_ASSERT(kctx == NULL || kctx->as_nr != KBASEP_AS_NR_INVALID);
50 KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
51 val = readl(kbdev->reg + offset);
52 dev_dbg(kbdev->dev, "r: reg %04x val %08x", offset, val);
53 if (kctx && kctx->jctx.tb)
54 kbase_device_trace_register_access(kctx, REG_READ, offset, val);
58 KBASE_EXPORT_TEST_API(kbase_reg_read);
59 #endif /* !defined(CONFIG_MALI_NO_MALI) */
62 * kbase_report_gpu_fault - Report a GPU fault.
63 * @kbdev: Kbase device pointer
64 * @multiple: Zero if only GPU_FAULT was raised, non-zero if MULTIPLE_GPU_FAULTS
67 * This function is called from the interrupt handler when a GPU fault occurs.
68 * It reports the details of the fault using dev_warn().
70 static void kbase_report_gpu_fault(struct kbase_device *kbdev, int multiple)
75 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS), NULL);
76 address = (u64) kbase_reg_read(kbdev,
77 GPU_CONTROL_REG(GPU_FAULTADDRESS_HI), NULL) << 32;
78 address |= kbase_reg_read(kbdev,
79 GPU_CONTROL_REG(GPU_FAULTADDRESS_LO), NULL);
81 dev_warn(kbdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx",
83 kbase_exception_name(kbdev, status),
86 dev_warn(kbdev->dev, "There were multiple GPU faults - some have not been reported\n");
89 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
91 KBASE_TRACE_ADD(kbdev, CORE_GPU_IRQ, NULL, NULL, 0u, val);
93 kbase_report_gpu_fault(kbdev, val & MULTIPLE_GPU_FAULTS);
95 if (val & RESET_COMPLETED)
96 kbase_pm_reset_done(kbdev);
98 if (val & PRFCNT_SAMPLE_COMPLETED)
99 kbase_instr_hwcnt_sample_done(kbdev);
101 if (val & CLEAN_CACHES_COMPLETED)
102 kbase_clean_caches_done(kbdev);
104 KBASE_TRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, NULL, 0u, val);
105 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val, NULL);
107 /* kbase_pm_check_transitions must be called after the IRQ has been
108 * cleared. This is because it might trigger further power transitions
109 * and we don't want to miss the interrupt raised to notify us that
110 * these further transitions have finished.
112 if (val & POWER_CHANGED_ALL)
113 kbase_pm_power_changed(kbdev);
115 KBASE_TRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, NULL, 0u, val);