drivers/gpu/arm/midgard/platform/rk/mali_kbase_config_rk.c

   1 /*
   2  *
   3  * (C) COPYRIGHT ARM Limited. All rights reserved.
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * A copy of the licence is included with the program, and can also be obtained
  11  * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  12  * Boston, MA  02110-1301, USA.
  13  *
  14  */
  15
  16
  17
  18
  19
  20 #include <linux/ioport.h>
  21 #include <mali_kbase.h>
  22 #include <mali_kbase_defs.h>
  23 #include <mali_kbase_config.h>
  24 #ifdef CONFIG_UMP
  25 #include <linux/ump-common.h>
  26 #endif                          /* CONFIG_UMP */
  27 #include <platform/rk/mali_kbase_platform.h>
  28 #include <platform/rk/mali_kbase_dvfs.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/suspend.h>
  31
  32 int get_cpu_clock_speed(u32 *cpu_clock);
  33
  34 #define HZ_IN_MHZ                           (1000000)
  35 #ifdef CONFIG_MALI_MIDGARD_RT_PM
  36 #define RUNTIME_PM_DELAY_TIME 100
  37 #endif
  38
  39 /* Versatile Express (VE) configuration defaults shared between config_attributes[]
  40  * and config_attributes_hw_issue_8408[]. Settings are not shared for
  41  * JS_HARD_STOP_TICKS_SS and JS_RESET_TICKS_SS.
  42  */
  43 #define KBASE_VE_MEMORY_PER_PROCESS_LIMIT       (512 * 1024 * 1024UL)   /* 512MB */
  44 #define KBASE_VE_MEMORY_OS_SHARED_MAX           (2048 * 1024 * 1024UL)  /* 768MB */
  45 #define KBASE_VE_MEMORY_OS_SHARED_PERF_GPU      KBASE_MEM_PERF_FAST/*KBASE_MEM_PERF_SLOW*/
  46 #define KBASE_VE_GPU_FREQ_KHZ_MAX               500000
  47 #define KBASE_VE_GPU_FREQ_KHZ_MIN               100000
  48 #ifdef CONFIG_UMP
  49 #define KBASE_VE_UMP_DEVICE                     UMP_DEVICE_Z_SHIFT
  50 #endif                          /* CONFIG_UMP */
  51
  52 #define KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG    15000000u      /* 15ms, an agressive tick for testing purposes. This will reduce performance significantly */
  53 #define KBASE_VE_JS_SOFT_STOP_TICKS_DEBUG       1       /* between 15ms and 30ms before soft-stop a job */
  54 #define KBASE_VE_JS_HARD_STOP_TICKS_SS_DEBUG    333     /* 5s before hard-stop */
  55 #define KBASE_VE_JS_HARD_STOP_TICKS_SS_8401_DEBUG 2000  /* 30s before hard-stop, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */
  56 #define KBASE_VE_JS_HARD_STOP_TICKS_NSS_DEBUG   100000  /* 1500s (25mins) before NSS hard-stop */
  57 #define KBASE_VE_JS_RESET_TICKS_SS_DEBUG        500     /* 45s before resetting GPU, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) */
  58 #define KBASE_VE_JS_RESET_TICKS_SS_8401_DEBUG   3000    /* 7.5s before resetting GPU - for issue 8401 */
  59 #define KBASE_VE_JS_RESET_TICKS_NSS_DEBUG       100166  /* 1502s before resetting GPU */
  60
  61 #define KBASE_VE_JS_SCHEDULING_TICK_NS          2500000000u     /* 2.5s */
  62 #define KBASE_VE_JS_SOFT_STOP_TICKS             1       /* 2.5s before soft-stop a job */
  63 #define KBASE_VE_JS_HARD_STOP_TICKS_SS          2       /* 5s before hard-stop */
  64 #define KBASE_VE_JS_HARD_STOP_TICKS_SS_8401     12      /* 30s before hard-stop, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */
  65 #define KBASE_VE_JS_HARD_STOP_TICKS_NSS         600     /* 1500s before NSS hard-stop */
  66 #define KBASE_VE_JS_RESET_TICKS_SS              3       /* 7.5s before resetting GPU */
  67 #define KBASE_VE_JS_RESET_TICKS_SS_8401         18      /* 45s before resetting GPU, for a certain GLES2 test at 128x128 (bound by combined vertex+tiler job) - for issue 8401 */
  68 #define KBASE_VE_JS_RESET_TICKS_NSS             601     /* 1502s before resetting GPU */
  69
  70 #define KBASE_VE_JS_RESET_TIMEOUT_MS            500     /* 3s before cancelling stuck jobs */
  71 #define KBASE_VE_JS_CTX_TIMESLICE_NS            1000000 /* 1ms - an agressive timeslice for testing purposes (causes lots of scheduling out for >4 ctxs) */
  72 #define KBASE_VE_SECURE_BUT_LOSS_OF_PERFORMANCE ((uintptr_t)MALI_FALSE) /* By default we prefer performance over security on r0p0-15dev0 and KBASE_CONFIG_ATTR_ earlier */
  73 //#define KBASE_VE_POWER_MANAGEMENT_CALLBACKS     ((uintptr_t)&pm_callbacks)
  74 #define KBASE_VE_CPU_SPEED_FUNC                 ((uintptr_t)&get_cpu_clock_speed)
  75
  76 static int mali_pm_notifier(struct notifier_block *nb,unsigned long event,void* cmd);
  77 static struct notifier_block mali_pm_nb = {
  78         .notifier_call = mali_pm_notifier
  79 };
  80
  81 #ifndef CONFIG_OF
  82 static kbase_io_resources io_resources = {
  83         .job_irq_number = 68,
  84         .mmu_irq_number = 69,
  85         .gpu_irq_number = 70,
  86         .io_memory_region = {
  87                              .start = 0xFC010000,
  88                              .end = 0xFC010000 + (4096 * 5) - 1}
  89 };
  90 #endif
  91 int get_cpu_clock_speed(u32 *cpu_clock)
  92 {
  93 #if 0
  94         struct clk *cpu_clk;
  95         u32 freq = 0;
  96         cpu_clk = clk_get(NULL, "armclk");
  97         if (IS_ERR(cpu_clk))
  98                 return 1;
  99         freq = clk_get_rate(cpu_clk);
 100         *cpu_clock = (freq / HZ_IN_MHZ);
 101 #endif
 102         return 0;
 103 }
 104
 105 static int mali_pm_notifier(struct notifier_block *nb,unsigned long event,void* cmd)
 106 {
 107         int err = NOTIFY_OK;
 108         switch (event) {
 109                 case PM_SUSPEND_PREPARE:
 110 #ifdef CONFIG_MALI_MIDGARD_DVFS
 111                         //if (kbase_platform_dvfs_enable(false, MALI_DVFS_BL_CONFIG_FREQ)!= MALI_TRUE)
 112                         if (kbase_platform_dvfs_enable(false, p_mali_dvfs_infotbl[MALI_DVFS_STEP-1].clock)!= MALI_TRUE)
 113                                 err = NOTIFY_BAD;
 114 #endif
 115                         break;
 116                 case PM_POST_SUSPEND:
 117 #ifdef CONFIG_MALI_MIDGARD_DVFS
 118                         //if (kbase_platform_dvfs_enable(true, MALI_DVFS_START_FREQ)!= MALI_TRUE)
 119                         if (kbase_platform_dvfs_enable(true, p_mali_dvfs_infotbl[0].clock)!= MALI_TRUE)
 120                                 err = NOTIFY_BAD;
 121 #endif
 122                         break;
 123                 default:
 124                         break;
 125         }
 126         return err;
 127 }
 128
 129 /*
 130   rk3288 hardware specific initialization
 131  */
 132 mali_bool kbase_platform_rk_init(kbase_device *kbdev)
 133 {
 134         if(MALI_ERROR_NONE == kbase_platform_init(kbdev))
 135         {
 136                 if (register_pm_notifier(&mali_pm_nb)) {
 137                         return MALI_FALSE;
 138                 }
 139                 return MALI_TRUE;
 140         }
 141         return MALI_FALSE;
 142 }
 143
 144 /*
 145  rk3288  hardware specific termination
 146 */
 147 void kbase_platform_rk_term(kbase_device *kbdev)
 148 {
 149         unregister_pm_notifier(&mali_pm_nb);
 150 #ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS
 151         kbase_platform_remove_sysfs_file(kbdev->dev);
 152 #endif                          /* CONFIG_MALI_MIDGARD_DEBUG_SYS */
 153         kbase_platform_term(kbdev);
 154 }
 155
 156 kbase_platform_funcs_conf platform_funcs = {
 157         .platform_init_func = &kbase_platform_rk_init,
 158         .platform_term_func = &kbase_platform_rk_term,
 159 };
 160
 161 #ifdef CONFIG_MALI_MIDGARD_RT_PM
 162 static int pm_callback_power_on(kbase_device *kbdev)
 163 {
 164         int result;
 165         int ret_val;
 166         struct device *dev = kbdev->dev;
 167         struct rk_context *platform;
 168
 169         platform = (struct rk_context *)kbdev->platform_context;
 170
 171         if (pm_runtime_status_suspended(dev))
 172                 ret_val = 1;
 173         else
 174                 ret_val = 0;
 175
 176         if(dev->power.disable_depth > 0) {
 177                 if(platform->cmu_pmu_status == 0)
 178                         kbase_platform_cmu_pmu_control(kbdev, 1);
 179                 return ret_val;
 180         }
 181         result = pm_runtime_resume(dev);
 182
 183         if (result < 0 && result == -EAGAIN)
 184                 kbase_platform_cmu_pmu_control(kbdev, 1);
 185         else if (result < 0)
 186                 printk(KERN_ERR "pm_runtime_get_sync failed (%d)\n", result);
 187
 188         return ret_val;
 189 }
 190
 191 static void pm_callback_power_off(kbase_device *kbdev)
 192 {
 193         struct device *dev = kbdev->dev;
 194         pm_schedule_suspend(dev, RUNTIME_PM_DELAY_TIME);
 195 }
 196
 197 mali_error kbase_device_runtime_init(struct kbase_device *kbdev)
 198 {
 199         pm_suspend_ignore_children(kbdev->dev, true);
 200         pm_runtime_enable(kbdev->dev);
 201 #ifdef CONFIG_MALI_MIDGARD_DEBUG_SYS
 202         if (kbase_platform_create_sysfs_file(kbdev->dev))
 203                 return MALI_ERROR_FUNCTION_FAILED;
 204 #endif                          /* CONFIG_MALI_MIDGARD_DEBUG_SYS */
 205         return MALI_ERROR_NONE;
 206 }
 207
 208 void kbase_device_runtime_disable(struct kbase_device *kbdev)
 209 {
 210         pm_runtime_disable(kbdev->dev);
 211 }
 212
 213 static int pm_callback_runtime_on(kbase_device *kbdev)
 214 {
 215 #ifdef CONFIG_MALI_MIDGARD_DVFS
 216         struct rk_context *platform = (struct rk_context *)kbdev->platform_context;
 217 #endif
 218         kbase_platform_clock_on(kbdev);
 219 #ifdef CONFIG_MALI_MIDGARD_DVFS
 220         if (platform->dvfs_enabled) {
 221                 //if (kbase_platform_dvfs_enable(true, MALI_DVFS_START_FREQ)!= MALI_TRUE)
 222                 if (kbase_platform_dvfs_enable(true, p_mali_dvfs_infotbl[0].clock)!= MALI_TRUE)
 223                         return -EPERM;
 224         } else {
 225                 if (kbase_platform_dvfs_enable(false, MALI_DVFS_CURRENT_FREQ)!= MALI_TRUE)
 226                         return -EPERM;
 227         }
 228 #endif
 229         return 0;
 230 }
 231
 232 static void pm_callback_runtime_off(kbase_device *kbdev)
 233 {
 234         kbase_platform_clock_off(kbdev);
 235 #ifdef CONFIG_MALI_MIDGARD_DVFS
 236         if (kbase_platform_dvfs_enable(false, MALI_DVFS_CURRENT_FREQ)!= MALI_TRUE)
 237                 printk("[err] disabling dvfs is faled\n");
 238 #endif
 239 }
 240
 241 static kbase_pm_callback_conf pm_callbacks = {
 242         .power_on_callback = pm_callback_power_on,
 243         .power_off_callback = pm_callback_power_off,
 244 #ifdef CONFIG_PM_RUNTIME
 245         .power_runtime_init_callback = kbase_device_runtime_init,
 246         .power_runtime_term_callback = kbase_device_runtime_disable,
 247         .power_runtime_on_callback = pm_callback_runtime_on,
 248         .power_runtime_off_callback = pm_callback_runtime_off,
 249
 250 #else                           /* CONFIG_PM_RUNTIME */
 251         .power_runtime_init_callback = NULL,
 252         .power_runtime_term_callback = NULL,
 253         .power_runtime_on_callback = NULL,
 254         .power_runtime_off_callback = NULL,
 255
 256 #endif                          /* CONFIG_PM_RUNTIME */
 257 };
 258 #endif
 259
 260
 261 /* Please keep table config_attributes in sync with config_attributes_hw_issue_8408 */
 262 static kbase_attribute config_attributes[] = {
 263 #if 0
 264         {
 265          KBASE_CONFIG_ATTR_MEMORY_PER_PROCESS_LIMIT,
 266          KBASE_VE_MEMORY_PER_PROCESS_LIMIT},
 267 #endif
 268 #ifdef CONFIG_UMP
 269         {
 270          KBASE_CONFIG_ATTR_UMP_DEVICE,
 271          KBASE_VE_UMP_DEVICE},
 272 #endif                          /* CONFIG_UMP */
 273 #ifdef CONFIG_MALI_MIDGARD_RT_PM
 274         {
 275          KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS,
 276          (uintptr_t)&pm_callbacks},
 277 #endif
 278 #if 0
 279         {
 280          KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_MAX,
 281          KBASE_VE_MEMORY_OS_SHARED_MAX},
 282 #endif
 283 #if 0
 284         {
 285          KBASE_CONFIG_ATTR_MEMORY_OS_SHARED_PERF_GPU,
 286          KBASE_VE_MEMORY_OS_SHARED_PERF_GPU},
 287 #endif
 288         {
 289          KBASE_CONFIG_ATTR_PLATFORM_FUNCS,
 290          (uintptr_t) &platform_funcs},
 291
 292         {
 293          KBASE_CONFIG_ATTR_GPU_FREQ_KHZ_MAX,
 294          KBASE_VE_GPU_FREQ_KHZ_MAX},
 295
 296         {
 297          KBASE_CONFIG_ATTR_GPU_FREQ_KHZ_MIN,
 298          KBASE_VE_GPU_FREQ_KHZ_MIN},
 299
 300 #ifdef CONFIG_MALI_DEBUG
 301 /* Use more aggressive scheduling timeouts in debug builds for testing purposes */
 302         {
 303          KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS,
 304          KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG},
 305
 306         {
 307          KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS,
 308          KBASE_VE_JS_SOFT_STOP_TICKS_DEBUG},
 309
 310         {
 311          KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS,
 312          KBASE_VE_JS_HARD_STOP_TICKS_SS_DEBUG},
 313
 314         {
 315          KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS,
 316          KBASE_VE_JS_HARD_STOP_TICKS_NSS_DEBUG},
 317
 318         {
 319          KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS,
 320          KBASE_VE_JS_RESET_TICKS_SS_DEBUG},
 321
 322         {
 323          KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS,
 324          KBASE_VE_JS_RESET_TICKS_NSS_DEBUG},
 325 #else                           /* CONFIG_MALI_DEBUG */
 326 /* In release builds same as the defaults but scaled for 5MHz FPGA */
 327 #if 0
 328         {
 329          KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS,
 330          KBASE_VE_JS_SCHEDULING_TICK_NS},
 331 #endif
 332 #if 0
 333         {
 334          KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS,
 335          KBASE_VE_JS_SOFT_STOP_TICKS},
 336 #endif
 337 #if 0
 338         {
 339          KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS,
 340          KBASE_VE_JS_HARD_STOP_TICKS_SS},
 341 #endif
 342 #if 0
 343         {
 344          KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS,
 345          KBASE_VE_JS_HARD_STOP_TICKS_NSS},
 346 #endif
 347 #if 0
 348         {
 349          KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS,
 350          KBASE_VE_JS_RESET_TICKS_SS},
 351 #endif
 352 #if 0
 353         {
 354          KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS,
 355          KBASE_VE_JS_RESET_TICKS_NSS},
 356 #endif
 357 #endif                          /* CONFIG_MALI_DEBUG */
 358 #if 1
 359         {
 360          KBASE_CONFIG_ATTR_JS_RESET_TIMEOUT_MS,
 361          KBASE_VE_JS_RESET_TIMEOUT_MS},
 362 #endif
 363 #if 0
 364         {
 365          KBASE_CONFIG_ATTR_JS_CTX_TIMESLICE_NS,
 366          KBASE_VE_JS_CTX_TIMESLICE_NS},
 367 #endif
 368 #if 0
 369         {
 370          KBASE_CONFIG_ATTR_CPU_SPEED_FUNC,
 371          KBASE_VE_CPU_SPEED_FUNC},
 372 #endif
 373 #if 0
 374         {
 375          KBASE_CONFIG_ATTR_SECURE_BUT_LOSS_OF_PERFORMANCE,
 376          KBASE_VE_SECURE_BUT_LOSS_OF_PERFORMANCE},
 377 #endif
 378 #if 0
 379         {
 380          KBASE_CONFIG_ATTR_GPU_IRQ_THROTTLE_TIME_US,
 381          20},
 382 #endif
 383         {
 384          KBASE_CONFIG_ATTR_END,
 385          0}
 386 };
 387
 388 static kbase_platform_config rk_platform_config = {
 389         .attributes = config_attributes,
 390 #ifndef CONFIG_OF
 391         .io_resources = &io_resources
 392 #endif
 393 };
 394 #if 1
 395 kbase_platform_config *kbase_get_platform_config(void)
 396 {
 397         return &rk_platform_config;
 398 }
 399 #endif
 400 int kbase_platform_early_init(void)
 401 {
 402         /* Nothing needed at this stage */
 403         return 0;
 404 }