3 * (C) COPYRIGHT 2010-2015 ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
20 #ifndef _MIDGARD_REGMAP_H_
21 #define _MIDGARD_REGMAP_H_
24 * Begin Register Offsets
27 #define GPU_CONTROL_BASE 0x0000
28 #define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
29 #define GPU_ID 0x000 /* (RO) GPU and revision identifier */
30 #define L2_FEATURES 0x004 /* (RO) Level 2 cache features */
31 #define SUSPEND_SIZE 0x008 /* (RO) Fixed-function suspend buffer
33 #define TILER_FEATURES 0x00C /* (RO) Tiler Features */
34 #define MEM_FEATURES 0x010 /* (RO) Memory system features */
35 #define MMU_FEATURES 0x014 /* (RO) MMU features */
36 #define AS_PRESENT 0x018 /* (RO) Address space slots present */
37 #define JS_PRESENT 0x01C /* (RO) Job slots present */
38 #define GPU_IRQ_RAWSTAT 0x020 /* (RW) */
39 #define GPU_IRQ_CLEAR 0x024 /* (WO) */
40 #define GPU_IRQ_MASK 0x028 /* (RW) */
41 #define GPU_IRQ_STATUS 0x02C /* (RO) */
44 #define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
45 #define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */
46 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. Intended to use with SOFT_RESET
47 commands which may take time. */
48 #define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
49 #define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down
50 and the power manager is idle. */
52 #define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */
53 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
55 #define GPU_IRQ_REG_ALL (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \
56 | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED)
58 #define GPU_COMMAND 0x030 /* (WO) */
59 #define GPU_STATUS 0x034 /* (RO) */
62 #define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */
64 #define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */
65 #define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */
66 #define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */
68 #define PWR_KEY 0x050 /* (WO) Power manager key register */
69 #define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */
70 #define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */
72 #define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory region base address, low word */
73 #define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory region base address, high word */
74 #define PRFCNT_CONFIG 0x068 /* (RW) Performance counter configuration */
75 #define PRFCNT_JM_EN 0x06C /* (RW) Performance counter enable flags for Job Manager */
76 #define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable flags for shader cores */
77 #define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable flags for tiler */
78 #define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable flags for MMU/L2 cache */
80 #define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */
81 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */
82 #define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */
83 #define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */
85 #define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */
86 #define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
87 #define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */
88 #define THREAD_FEATURES 0x0AC /* (RO) Thread features */
90 #define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */
91 #define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */
92 #define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */
94 #define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2))
96 #define JS0_FEATURES 0x0C0 /* (RO) Features of job slot 0 */
97 #define JS1_FEATURES 0x0C4 /* (RO) Features of job slot 1 */
98 #define JS2_FEATURES 0x0C8 /* (RO) Features of job slot 2 */
99 #define JS3_FEATURES 0x0CC /* (RO) Features of job slot 3 */
100 #define JS4_FEATURES 0x0D0 /* (RO) Features of job slot 4 */
101 #define JS5_FEATURES 0x0D4 /* (RO) Features of job slot 5 */
102 #define JS6_FEATURES 0x0D8 /* (RO) Features of job slot 6 */
103 #define JS7_FEATURES 0x0DC /* (RO) Features of job slot 7 */
104 #define JS8_FEATURES 0x0E0 /* (RO) Features of job slot 8 */
105 #define JS9_FEATURES 0x0E4 /* (RO) Features of job slot 9 */
106 #define JS10_FEATURES 0x0E8 /* (RO) Features of job slot 10 */
107 #define JS11_FEATURES 0x0EC /* (RO) Features of job slot 11 */
108 #define JS12_FEATURES 0x0F0 /* (RO) Features of job slot 12 */
109 #define JS13_FEATURES 0x0F4 /* (RO) Features of job slot 13 */
110 #define JS14_FEATURES 0x0F8 /* (RO) Features of job slot 14 */
111 #define JS15_FEATURES 0x0FC /* (RO) Features of job slot 15 */
113 #define JS_FEATURES_REG(n) GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2))
115 #define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
116 #define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
118 #define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
119 #define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
121 #define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
122 #define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
125 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
126 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
128 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
129 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
131 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
132 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
135 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
136 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
138 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
139 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
141 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
142 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
144 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
145 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
147 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
148 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
150 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
151 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
153 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
154 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
156 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
157 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
159 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
160 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
162 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
163 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
165 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
166 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
168 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
169 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
172 #define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */
173 #define TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */
174 #define L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */
176 #define JOB_CONTROL_BASE 0x1000
178 #define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
180 #define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */
181 #define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
182 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
183 #define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
184 #define JOB_IRQ_JS_STATE 0x010 /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */
185 #define JOB_IRQ_THROTTLE 0x014 /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt. */
187 #define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */
188 #define JOB_SLOT1 0x880 /* Configuration registers for job slot 1 */
189 #define JOB_SLOT2 0x900 /* Configuration registers for job slot 2 */
190 #define JOB_SLOT3 0x980 /* Configuration registers for job slot 3 */
191 #define JOB_SLOT4 0xA00 /* Configuration registers for job slot 4 */
192 #define JOB_SLOT5 0xA80 /* Configuration registers for job slot 5 */
193 #define JOB_SLOT6 0xB00 /* Configuration registers for job slot 6 */
194 #define JOB_SLOT7 0xB80 /* Configuration registers for job slot 7 */
195 #define JOB_SLOT8 0xC00 /* Configuration registers for job slot 8 */
196 #define JOB_SLOT9 0xC80 /* Configuration registers for job slot 9 */
197 #define JOB_SLOT10 0xD00 /* Configuration registers for job slot 10 */
198 #define JOB_SLOT11 0xD80 /* Configuration registers for job slot 11 */
199 #define JOB_SLOT12 0xE00 /* Configuration registers for job slot 12 */
200 #define JOB_SLOT13 0xE80 /* Configuration registers for job slot 13 */
201 #define JOB_SLOT14 0xF00 /* Configuration registers for job slot 14 */
202 #define JOB_SLOT15 0xF80 /* Configuration registers for job slot 15 */
204 #define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
206 #define JS_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */
207 #define JS_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */
208 #define JS_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */
209 #define JS_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */
210 #define JS_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */
211 #define JS_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */
212 #define JS_CONFIG 0x18 /* (RO) Configuration settings for job slot n */
214 #define JS_COMMAND 0x20 /* (WO) Command register for job slot n */
215 #define JS_STATUS 0x24 /* (RO) Status register for job slot n */
217 #define JS_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */
218 #define JS_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */
220 #define JS_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */
221 #define JS_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */
222 #define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */
224 #define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */
227 #define MEMORY_MANAGEMENT_BASE 0x2000
228 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
230 #define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
231 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
232 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
233 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
235 #define MMU_AS0 0x400 /* Configuration registers for address space 0 */
236 #define MMU_AS1 0x440 /* Configuration registers for address space 1 */
237 #define MMU_AS2 0x480 /* Configuration registers for address space 2 */
238 #define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */
239 #define MMU_AS4 0x500 /* Configuration registers for address space 4 */
240 #define MMU_AS5 0x540 /* Configuration registers for address space 5 */
241 #define MMU_AS6 0x580 /* Configuration registers for address space 6 */
242 #define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */
243 #define MMU_AS8 0x600 /* Configuration registers for address space 8 */
244 #define MMU_AS9 0x640 /* Configuration registers for address space 9 */
245 #define MMU_AS10 0x680 /* Configuration registers for address space 10 */
246 #define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */
247 #define MMU_AS12 0x700 /* Configuration registers for address space 12 */
248 #define MMU_AS13 0x740 /* Configuration registers for address space 13 */
249 #define MMU_AS14 0x780 /* Configuration registers for address space 14 */
250 #define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */
252 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
254 #define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
255 #define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
256 #define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
257 #define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
258 #define AS_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */
259 #define AS_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */
260 #define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
261 #define AS_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */
262 #define AS_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */
263 #define AS_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */
264 #define AS_STATUS 0x28 /* (RO) Status flags for address space n */
268 /* End Register Offsets */
271 * MMU_IRQ_RAWSTAT register values. Values are valid also for
272 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
275 #define MMU_PAGE_FAULT_FLAGS 16
277 /* Macros returning a bitmask to retrieve page fault or bus error flags from
279 #define MMU_PAGE_FAULT(n) (1UL << (n))
280 #define MMU_BUS_ERROR(n) (1UL << ((n) + MMU_PAGE_FAULT_FLAGS))
283 * Begin LPAE MMU TRANSTAB register values
285 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffff000
286 #define AS_TRANSTAB_LPAE_ADRMODE_UNMAPPED (0u << 0)
287 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY (1u << 1)
288 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE (3u << 0)
289 #define AS_TRANSTAB_LPAE_READ_INNER (1u << 2)
290 #define AS_TRANSTAB_LPAE_SHARE_OUTER (1u << 4)
292 #define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x00000003
296 * Begin MMU STATUS register values
298 #define AS_STATUS_AS_ACTIVE 0x01
300 #define AS_FAULTSTATUS_EXCEPTION_CODE_MASK (0x7<<3)
301 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT (0x0<<3)
302 #define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT (0x1<<3)
303 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT (0x2<<3)
304 #define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG (0x3<<3)
307 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3<<8)
308 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1<<8)
309 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2<<8)
310 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3<<8)
314 * Begin Command Values
317 /* JS_COMMAND register commands */
318 #define JS_COMMAND_NOP 0x00 /* NOP Operation. Writing this value is ignored */
319 #define JS_COMMAND_START 0x01 /* Start processing a job chain. Writing this value is ignored */
320 #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */
321 #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */
322 #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
323 #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
324 #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
325 #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
327 #define JS_COMMAND_MASK 0x07 /* Mask of bits currently in use by the HW */
329 /* AS_COMMAND register commands */
330 #define AS_COMMAND_NOP 0x00 /* NOP Operation */
331 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
332 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
333 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
334 #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs
335 (deprecated - only for use with T60x) */
336 #define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */
337 #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then
338 flush all L2 caches then issue a flush region command to all MMUs */
340 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
341 #define JS_CONFIG_START_FLUSH_NO_ACTION (0u << 0)
342 #define JS_CONFIG_START_FLUSH_CLEAN (1u << 8)
343 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8)
344 #define JS_CONFIG_START_MMU (1u << 10)
345 #define JS_CONFIG_JOB_CHAIN_FLAG (1u << 11)
346 #define JS_CONFIG_END_FLUSH_NO_ACTION JS_CONFIG_START_FLUSH_NO_ACTION
347 #define JS_CONFIG_END_FLUSH_CLEAN (1u << 12)
348 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12)
349 #define JS_CONFIG_THREAD_PRI(n) ((n) << 16)
351 /* JS_STATUS register values */
353 /* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h.
354 * The values are separated to avoid dependency of userspace and kernel code.
357 /* Group of values representing the job status insead a particular fault */
358 #define JS_STATUS_NO_EXCEPTION_BASE 0x00
359 #define JS_STATUS_INTERRUPTED (JS_STATUS_NO_EXCEPTION_BASE + 0x02) /* 0x02 means INTERRUPTED */
360 #define JS_STATUS_STOPPED (JS_STATUS_NO_EXCEPTION_BASE + 0x03) /* 0x03 means STOPPED */
361 #define JS_STATUS_TERMINATED (JS_STATUS_NO_EXCEPTION_BASE + 0x04) /* 0x04 means TERMINATED */
363 /* General fault values */
364 #define JS_STATUS_FAULT_BASE 0x40
365 #define JS_STATUS_CONFIG_FAULT (JS_STATUS_FAULT_BASE) /* 0x40 means CONFIG FAULT */
366 #define JS_STATUS_POWER_FAULT (JS_STATUS_FAULT_BASE + 0x01) /* 0x41 means POWER FAULT */
367 #define JS_STATUS_READ_FAULT (JS_STATUS_FAULT_BASE + 0x02) /* 0x42 means READ FAULT */
368 #define JS_STATUS_WRITE_FAULT (JS_STATUS_FAULT_BASE + 0x03) /* 0x43 means WRITE FAULT */
369 #define JS_STATUS_AFFINITY_FAULT (JS_STATUS_FAULT_BASE + 0x04) /* 0x44 means AFFINITY FAULT */
370 #define JS_STATUS_BUS_FAULT (JS_STATUS_FAULT_BASE + 0x08) /* 0x48 means BUS FAULT */
372 /* Instruction or data faults */
373 #define JS_STATUS_INSTRUCTION_FAULT_BASE 0x50
374 #define JS_STATUS_INSTR_INVALID_PC (JS_STATUS_INSTRUCTION_FAULT_BASE) /* 0x50 means INSTR INVALID PC */
375 #define JS_STATUS_INSTR_INVALID_ENC (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x01) /* 0x51 means INSTR INVALID ENC */
376 #define JS_STATUS_INSTR_TYPE_MISMATCH (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x02) /* 0x52 means INSTR TYPE MISMATCH */
377 #define JS_STATUS_INSTR_OPERAND_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x03) /* 0x53 means INSTR OPERAND FAULT */
378 #define JS_STATUS_INSTR_TLS_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x04) /* 0x54 means INSTR TLS FAULT */
379 #define JS_STATUS_INSTR_BARRIER_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x05) /* 0x55 means INSTR BARRIER FAULT */
380 #define JS_STATUS_INSTR_ALIGN_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x06) /* 0x56 means INSTR ALIGN FAULT */
381 /* NOTE: No fault with 0x57 code defined in spec. */
382 #define JS_STATUS_DATA_INVALID_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x08) /* 0x58 means DATA INVALID FAULT */
383 #define JS_STATUS_TILE_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x09) /* 0x59 means TILE RANGE FAULT */
384 #define JS_STATUS_ADDRESS_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x0A) /* 0x5A means ADDRESS RANGE FAULT */
387 #define JS_STATUS_MEMORY_FAULT_BASE 0x60
388 #define JS_STATUS_OUT_OF_MEMORY (JS_STATUS_MEMORY_FAULT_BASE) /* 0x60 means OUT OF MEMORY */
389 #define JS_STATUS_UNKNOWN 0x7F /* 0x7F means UNKNOWN */
391 /* GPU_COMMAND values */
392 #define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */
393 #define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */
394 #define GPU_COMMAND_HARD_RESET 0x02 /* Immediately reset the entire GPU. */
395 #define GPU_COMMAND_PRFCNT_CLEAR 0x03 /* Clear all performance counters, setting them all to zero. */
396 #define GPU_COMMAND_PRFCNT_SAMPLE 0x04 /* Sample all performance counters, writing them out to memory */
397 #define GPU_COMMAND_CYCLE_COUNT_START 0x05 /* Starts the cycle counter, and system timestamp propagation */
398 #define GPU_COMMAND_CYCLE_COUNT_STOP 0x06 /* Stops the cycle counter, and system timestamp propagation */
399 #define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */
400 #define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */
402 /* End Command Values */
404 /* GPU_STATUS values */
405 #define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */
407 /* PRFCNT_CONFIG register values */
408 #define PRFCNT_CONFIG_AS_SHIFT 4 /* address space bitmap starts from bit 4 of the register */
409 #define PRFCNT_CONFIG_MODE_OFF 0 /* The performance counters are disabled. */
410 #define PRFCNT_CONFIG_MODE_MANUAL 1 /* The performance counters are enabled, but are only written out when a PRFCNT_SAMPLE command is issued using the GPU_COMMAND register. */
411 #define PRFCNT_CONFIG_MODE_TILE 2 /* The performance counters are enabled, and are written out each time a tile finishes rendering. */
413 /* AS<n>_MEMATTR values: */
415 /* Use GPU implementation-defined caching policy. */
416 #define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull
417 /* The attribute set to force all resources to be cached. */
418 #define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL 0x4Full
419 /* Inner write-alloc cache setup, no outer caching */
420 #define AS_MEMATTR_LPAE_WRITE_ALLOC 0x4Dull
421 /* Set to implementation defined, outer caching */
422 #define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull
423 /* Set to write back memory, outer caching */
424 #define AS_MEMATTR_LPAE_OUTER_WA 0x8Dull
426 /* Symbol for default MEMATTR to use */
427 #define AS_MEMATTR_INDEX_DEFAULT 0
429 /* HW implementation defined caching */
430 #define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
432 #define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1
434 #define AS_MEMATTR_INDEX_WRITE_ALLOC 2
435 /* Outer coherent, inner implementation defined policy */
436 #define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3
437 /* Outer coherent, write alloc inner */
438 #define AS_MEMATTR_INDEX_OUTER_WA 4
440 /* GPU_ID register */
441 #define GPU_ID_VERSION_STATUS_SHIFT 0
442 #define GPU_ID_VERSION_MINOR_SHIFT 4
443 #define GPU_ID_VERSION_MAJOR_SHIFT 12
444 #define GPU_ID_VERSION_PRODUCT_ID_SHIFT 16
445 #define GPU_ID_VERSION_STATUS (0xF << GPU_ID_VERSION_STATUS_SHIFT)
446 #define GPU_ID_VERSION_MINOR (0xFF << GPU_ID_VERSION_MINOR_SHIFT)
447 #define GPU_ID_VERSION_MAJOR (0xF << GPU_ID_VERSION_MAJOR_SHIFT)
448 #define GPU_ID_VERSION_PRODUCT_ID (0xFFFF << GPU_ID_VERSION_PRODUCT_ID_SHIFT)
450 /* Values for GPU_ID_VERSION_PRODUCT_ID bitfield */
451 #define GPU_ID_PI_T60X 0x6956
452 #define GPU_ID_PI_T62X 0x0620
453 #define GPU_ID_PI_T76X 0x0750
454 #define GPU_ID_PI_T72X 0x0720
455 #define GPU_ID_PI_TFRX 0x0880
456 #define GPU_ID_PI_T86X 0x0860
457 #define GPU_ID_PI_T82X 0x0820
458 #define GPU_ID_PI_T83X 0x0830
460 /* Values for GPU_ID_VERSION_STATUS field for PRODUCT_ID GPU_ID_PI_T60X */
461 #define GPU_ID_S_15DEV0 0x1
462 #define GPU_ID_S_EAC 0x2
464 /* Helper macro to create a GPU_ID assuming valid values for id, major, minor, status */
465 #define GPU_ID_MAKE(id, major, minor, status) \
466 (((id) << GPU_ID_VERSION_PRODUCT_ID_SHIFT) | \
467 ((major) << GPU_ID_VERSION_MAJOR_SHIFT) | \
468 ((minor) << GPU_ID_VERSION_MINOR_SHIFT) | \
469 ((status) << GPU_ID_VERSION_STATUS_SHIFT))
471 /* End GPU_ID register */
473 /* JS<n>_FEATURES register */
475 #define JS_FEATURE_NULL_JOB (1u << 1)
476 #define JS_FEATURE_SET_VALUE_JOB (1u << 2)
477 #define JS_FEATURE_CACHE_FLUSH_JOB (1u << 3)
478 #define JS_FEATURE_COMPUTE_JOB (1u << 4)
479 #define JS_FEATURE_VERTEX_JOB (1u << 5)
480 #define JS_FEATURE_GEOMETRY_JOB (1u << 6)
481 #define JS_FEATURE_TILER_JOB (1u << 7)
482 #define JS_FEATURE_FUSED_JOB (1u << 8)
483 #define JS_FEATURE_FRAGMENT_JOB (1u << 9)
485 /* End JS<n>_FEATURES register */
487 /* L2_MMU_CONFIG register */
488 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT (24)
489 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
490 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
491 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
492 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
494 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT (26)
495 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
496 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
497 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
498 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
499 /* End L2_MMU_CONFIG register */
501 /* THREAD_* registers */
503 /* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */
504 #define IMPLEMENTATION_UNSPECIFIED 0
505 #define IMPLEMENTATION_SILICON 1
506 #define IMPLEMENTATION_FPGA 2
507 #define IMPLEMENTATION_MODEL 3
509 /* Default values when registers are not supported by the implemented hardware */
510 #define THREAD_MT_DEFAULT 256
511 #define THREAD_MWS_DEFAULT 256
512 #define THREAD_MBS_DEFAULT 256
513 #define THREAD_MR_DEFAULT 1024
514 #define THREAD_MTQ_DEFAULT 4
515 #define THREAD_MTGS_DEFAULT 10
517 /* End THREAD_* registers */
519 /* COHERENCY_* values*/
520 #define COHERENCY_ACE_LITE 0
521 #define COHERENCY_ACE 1
522 #define COHERENCY_NONE 0xFFFF
523 #define COHERENCY_FEATURE_BIT(x) (1 << (x))
524 /* End COHERENCY_* values */
526 /* SHADER_CONFIG register */
528 #define SC_ALT_COUNTERS (1ul << 3)
529 #define SC_OVERRIDE_FWD_PIXEL_KILL (1ul << 4)
530 #define SC_SDC_DISABLE_OQ_DISCARD (1ul << 6)
531 #define SC_LS_PAUSEBUFFER_DISABLE (1ul << 16)
532 #define SC_ENABLE_TEXGRD_FLAGS (1ul << 25)
533 /* End SHADER_CONFIG register */
535 /* TILER_CONFIG register */
537 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
539 /* End TILER_CONFIG register */
542 #endif /* _MIDGARD_REGMAP_H_ */