3 * (C) COPYRIGHT 2010-2016 ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
20 #include "mali_kbase_mmu_mode.h"
22 #include "mali_kbase.h"
23 #include "mali_midg_regmap.h"
25 #define ENTRY_TYPE_MASK 3ULL
26 #define ENTRY_IS_ATE 1ULL
27 #define ENTRY_IS_INVAL 2ULL
28 #define ENTRY_IS_PTE 3ULL
30 #define ENTRY_ATTR_BITS (7ULL << 2) /* bits 4:2 */
31 #define ENTRY_RD_BIT (1ULL << 6)
32 #define ENTRY_WR_BIT (1ULL << 7)
33 #define ENTRY_SHARE_BITS (3ULL << 8) /* bits 9:8 */
34 #define ENTRY_ACCESS_BIT (1ULL << 10)
35 #define ENTRY_NX_BIT (1ULL << 54)
37 #define ENTRY_FLAGS_MASK (ENTRY_ATTR_BITS | ENTRY_RD_BIT | ENTRY_WR_BIT | \
38 ENTRY_SHARE_BITS | ENTRY_ACCESS_BIT | ENTRY_NX_BIT)
40 /* Helper Function to perform assignment of page table entries, to
41 * ensure the use of strd, which is required on LPAE systems.
43 static inline void page_table_entry_set(u64 *pte, u64 phy)
47 #elif defined(CONFIG_ARM)
49 * In order to prevent the compiler keeping cached copies of
50 * memory, we have to explicitly say that we have updated
53 * Note: We could manually move the data ourselves into R0 and
54 * R1 by specifying register variables that are explicitly
55 * given registers assignments, the down side of this is that
56 * we have to assume cpu endianness. To avoid this we can use
57 * the ldrd to read the data from memory into R0 and R1 which
58 * will respect the cpu endianness, we then use strd to make
59 * the 64 bit assignment to the page table entry.
61 asm volatile("ldrd r0, r1, [%[ptemp]]\n\t"
62 "strd r0, r1, [%[pte]]\n\t"
64 : [ptemp] "r" (&phy), [pte] "r" (pte), "m" (phy)
67 #error "64-bit atomic write must be implemented for your architecture"
71 static void mmu_get_as_setup(struct kbase_context *kctx,
72 struct kbase_mmu_setup * const setup)
74 /* Set up the required caching policies at the correct indices
75 * in the memattr register. */
77 (AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY <<
78 (AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY * 8)) |
79 (AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL <<
80 (AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL * 8)) |
81 (AS_MEMATTR_LPAE_WRITE_ALLOC <<
82 (AS_MEMATTR_INDEX_WRITE_ALLOC * 8)) |
83 (AS_MEMATTR_LPAE_OUTER_IMPL_DEF <<
84 (AS_MEMATTR_INDEX_OUTER_IMPL_DEF * 8)) |
85 (AS_MEMATTR_LPAE_OUTER_WA <<
86 (AS_MEMATTR_INDEX_OUTER_WA * 8)) |
87 0; /* The other indices are unused for now */
89 setup->transtab = ((u64)kctx->pgd &
90 ((0xFFFFFFFFULL << 32) | AS_TRANSTAB_LPAE_ADDR_SPACE_MASK)) |
91 AS_TRANSTAB_LPAE_ADRMODE_TABLE |
92 AS_TRANSTAB_LPAE_READ_INNER;
94 #ifdef CONFIG_MALI_GPU_MMU_AARCH64
95 setup->transcfg = AS_TRANSCFG_ADRMODE_LEGACY;
101 static void mmu_update(struct kbase_context *kctx)
103 struct kbase_device * const kbdev = kctx->kbdev;
104 struct kbase_as * const as = &kbdev->as[kctx->as_nr];
105 struct kbase_mmu_setup * const current_setup = &as->current_setup;
107 mmu_get_as_setup(kctx, current_setup);
109 /* Apply the address space setting */
110 kbase_mmu_hw_configure(kbdev, as, kctx);
113 static void mmu_disable_as(struct kbase_device *kbdev, int as_nr)
115 struct kbase_as * const as = &kbdev->as[as_nr];
116 struct kbase_mmu_setup * const current_setup = &as->current_setup;
118 current_setup->transtab = AS_TRANSTAB_LPAE_ADRMODE_UNMAPPED;
120 #ifdef CONFIG_MALI_GPU_MMU_AARCH64
121 current_setup->transcfg = AS_TRANSCFG_ADRMODE_LEGACY;
124 /* Apply the address space setting */
125 kbase_mmu_hw_configure(kbdev, as, NULL);
128 static phys_addr_t pte_to_phy_addr(u64 entry)
133 return entry & ~0xFFF;
136 static int ate_is_valid(u64 ate)
138 return ((ate & ENTRY_TYPE_MASK) == ENTRY_IS_ATE);
141 static int pte_is_valid(u64 pte)
143 return ((pte & ENTRY_TYPE_MASK) == ENTRY_IS_PTE);
147 * Map KBASE_REG flags to MMU flags
149 static u64 get_mmu_flags(unsigned long flags)
153 /* store mem_attr index as 4:2 (macro called ensures 3 bits already) */
154 mmu_flags = KBASE_REG_MEMATTR_VALUE(flags) << 2;
156 /* write perm if requested */
157 mmu_flags |= (flags & KBASE_REG_GPU_WR) ? ENTRY_WR_BIT : 0;
158 /* read perm if requested */
159 mmu_flags |= (flags & KBASE_REG_GPU_RD) ? ENTRY_RD_BIT : 0;
160 /* nx if requested */
161 mmu_flags |= (flags & KBASE_REG_GPU_NX) ? ENTRY_NX_BIT : 0;
163 if (flags & KBASE_REG_SHARE_BOTH) {
164 /* inner and outer shareable */
165 mmu_flags |= SHARE_BOTH_BITS;
166 } else if (flags & KBASE_REG_SHARE_IN) {
167 /* inner shareable coherency */
168 mmu_flags |= SHARE_INNER_BITS;
174 static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags)
176 page_table_entry_set(entry, (phy & ~0xFFF) |
177 get_mmu_flags(flags) |
181 static void entry_set_pte(u64 *entry, phys_addr_t phy)
183 page_table_entry_set(entry, (phy & ~0xFFF) | ENTRY_IS_PTE);
186 static void entry_invalidate(u64 *entry)
188 page_table_entry_set(entry, ENTRY_IS_INVAL);
191 static struct kbase_mmu_mode const lpae_mode = {
192 .update = mmu_update,
193 .get_as_setup = mmu_get_as_setup,
194 .disable_as = mmu_disable_as,
195 .pte_to_phy_addr = pte_to_phy_addr,
196 .ate_is_valid = ate_is_valid,
197 .pte_is_valid = pte_is_valid,
198 .entry_set_ate = entry_set_ate,
199 .entry_set_pte = entry_set_pte,
200 .entry_invalidate = entry_invalidate
203 struct kbase_mmu_mode const *kbase_mmu_mode_get_lpae(void)