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19 * @file mali_kbase_config_defaults.h
21 * Default values for configuration settings
25 #ifndef _KBASE_CONFIG_DEFAULTS_H_
26 #define _KBASE_CONFIG_DEFAULTS_H_
28 /* Include mandatory definitions per platform */
29 #include <mali_kbase_config_platform.h>
32 * Irq throttle. It is the minimum desired time in between two
33 * consecutive gpu interrupts (given in 'us'). The irq throttle
34 * gpu register will be configured after this, taking into
35 * account the configured max frequency.
37 * Attached value: number in micro seconds
39 #define DEFAULT_IRQ_THROTTLE_TIME_US 20
41 /*** Begin Scheduling defaults ***/
44 * Default scheduling tick granuality, in nanoseconds
47 #define DEFAULT_JS_SCHEDULING_TICK_NS 50000000u
50 * Default minimum number of scheduling ticks before jobs are soft-stopped.
52 * This defines the time-slice for a job (which may be different from that of
55 /* Between 0.1 and 0.15s before soft-stop */
56 #define DEFAULT_JS_SOFT_STOP_TICKS 2
59 * Default minimum number of scheduling ticks before CL jobs are soft-stopped.
61 /* Between 0.05 and 0.1s before soft-stop */
62 #define DEFAULT_JS_SOFT_STOP_TICKS_CL 1
65 * Default minimum number of scheduling ticks before jobs are hard-stopped
67 /* 1.2s before hard-stop, for a certain GLES2 test at 128x128 (bound by
68 * combined vertex+tiler job)
70 #define DEFAULT_JS_HARD_STOP_TICKS_SS_HW_ISSUE_8408 24
71 /* Between 0.2 and 0.25s before hard-stop */
72 #define DEFAULT_JS_HARD_STOP_TICKS_SS 4
75 * Default minimum number of scheduling ticks before CL jobs are hard-stopped.
77 /* Between 0.1 and 0.15s before hard-stop */
78 #define DEFAULT_JS_HARD_STOP_TICKS_CL 2
81 * Default minimum number of scheduling ticks before jobs are hard-stopped
85 #define DEFAULT_JS_HARD_STOP_TICKS_NSS 1200
88 * Default minimum number of scheduling ticks before the GPU is reset
89 * to clear a "stuck" job
91 /* 1.8s before resetting GPU, for a certain GLES2 test at 128x128 (bound by
92 * combined vertex+tiler job)
94 #define DEFAULT_JS_RESET_TICKS_SS_HW_ISSUE_8408 36
95 /* 0.3-0.35s before GPU is reset */
96 #define DEFAULT_JS_RESET_TICKS_SS 6
99 * Default minimum number of scheduling ticks before the GPU is reset
100 * to clear a "stuck" CL job.
102 /* 0.2-0.25s before GPU is reset */
103 #define DEFAULT_JS_RESET_TICKS_CL 4
106 * Default minimum number of scheduling ticks before the GPU is reset
107 * to clear a "stuck" job during dumping.
109 /* 60.1s @ 100ms tick */
110 #define DEFAULT_JS_RESET_TICKS_NSS 1202
113 * Number of milliseconds given for other jobs on the GPU to be
114 * soft-stopped when the GPU needs to be reset.
116 #define DEFAULT_JS_RESET_TIMEOUT_MS 3000
119 * Default timeslice that a context is scheduled in for, in nanoseconds.
121 * When a context has used up this amount of time across its jobs, it is
122 * scheduled out to let another run.
124 * @note the resolution is nanoseconds (ns) here, because that's the format
125 * often used by the OS.
127 /* 0.05s - at 20fps a ctx does at least 1 frame before being scheduled out.
128 * At 40fps, 2 frames, etc
130 #define DEFAULT_JS_CTX_TIMESLICE_NS 50000000
133 * Default Job Scheduler initial runtime of a context for the CFS Policy,
136 * This value is relative to that of the least-run context, and defines
137 * where in the CFS queue a new context is added. A value of 1 means 'after
138 * the least-run context has used its timeslice'. Therefore, when all
139 * contexts consistently use the same amount of time, a value of 1 models a
140 * FIFO. A value of 0 would model a LIFO.
142 * The value is represented in "numbers of time slices". Multiply this
143 * value by that defined in @ref DEFAULT_JS_CTX_TIMESLICE_NS to get
144 * the time value for this in nanoseconds.
146 #define DEFAULT_JS_CFS_CTX_RUNTIME_INIT_SLICES 1
149 * Default Job Scheduler minimum runtime value of a context for CFS, in
150 * time_slices relative to that of the least-run context.
152 * This is a measure of how much preferrential treatment is given to a
153 * context that is not run very often.
155 * Specficially, this value defines how many timeslices such a context is
156 * (initially) allowed to use at once. Such contexts (e.g. 'interactive'
157 * processes) will appear near the front of the CFS queue, and can initially
158 * use more time than contexts that run continuously (e.g. 'batch'
161 * This limit \b prevents a "stored-up timeslices" DoS attack, where a ctx
162 * not run for a long time attacks the system by using a very large initial
163 * number of timeslices when it finally does run.
165 * @note A value of zero allows not-run-often contexts to get scheduled in
166 * quickly, but to only use a single timeslice when they get scheduled in.
168 #define DEFAULT_JS_CFS_CTX_RUNTIME_MIN_SLICES 2
171 * Boolean indicating whether the driver is configured to be secure at
172 * a potential loss of performance.
174 * This currently affects only r0p0-15dev0 HW and earlier.
176 * On r0p0-15dev0 HW and earlier, there are tradeoffs between security and
179 * - When this is set to MALI_TRUE, the driver remains fully secure,
180 * but potentially loses performance compared with setting this to
182 * - When set to MALI_FALSE, the driver is open to certain security
185 * From r0p0-00rel0 and onwards, there is no security loss by setting
186 * this to MALI_FALSE, and no performance loss by setting it to
189 #define DEFAULT_SECURE_BUT_LOSS_OF_PERFORMANCE MALI_FALSE
193 * Use unrestricted Address ID width on the AXI bus.
198 * Restrict GPU to a half of maximum Address ID count.
199 * This will reduce performance, but reduce bus load due to GPU.
204 * Restrict GPU to a quarter of maximum Address ID count.
205 * This will reduce performance, but reduce bus load due to GPU.
210 * Restrict GPU to an eighth of maximum Address ID count.
211 * This will reduce performance, but reduce bus load due to GPU.
217 * Default setting for read Address ID limiting on AXI bus.
219 * Attached value: u32 register value
220 * KBASE_AID_32 - use the full 32 IDs (5 ID bits)
221 * KBASE_AID_16 - use 16 IDs (4 ID bits)
222 * KBASE_AID_8 - use 8 IDs (3 ID bits)
223 * KBASE_AID_4 - use 4 IDs (2 ID bits)
224 * Default value: KBASE_AID_32 (no limit). Note hardware implementation
225 * may limit to a lower value.
227 #define DEFAULT_ARID_LIMIT KBASE_AID_32
230 * Default setting for write Address ID limiting on AXI.
232 * Attached value: u32 register value
233 * KBASE_AID_32 - use the full 32 IDs (5 ID bits)
234 * KBASE_AID_16 - use 16 IDs (4 ID bits)
235 * KBASE_AID_8 - use 8 IDs (3 ID bits)
236 * KBASE_AID_4 - use 4 IDs (2 ID bits)
237 * Default value: KBASE_AID_32 (no limit). Note hardware implementation
238 * may limit to a lower value.
240 #define DEFAULT_AWID_LIMIT KBASE_AID_32
243 * Default setting for using alternative hardware counters.
245 #define DEFAULT_ALTERNATIVE_HWC MALI_FALSE
247 /*** End Scheduling defaults ***/
249 /*** Begin Power Manager defaults */
252 #define DEFAULT_PM_DVFS_FREQ 500
255 * Default poweroff tick granuality, in nanoseconds
258 #define DEFAULT_PM_GPU_POWEROFF_TICK_NS 400000
261 * Default number of poweroff ticks before shader cores are powered off
264 #define DEFAULT_PM_POWEROFF_TICK_SHADER 2
267 * Default number of poweroff ticks before GPU is powered off
269 #define DEFAULT_PM_POWEROFF_TICK_GPU 2 /* 400-800us */
271 /*** End Power Manager defaults ***/
275 * Default UMP device mapping. A UMP_DEVICE_<device>_SHIFT value which
276 * defines which UMP device this GPU should be mapped to.
278 #define DEFAULT_UMP_GPU_DEVICE_SHIFT UMP_DEVICE_Z_SHIFT
281 * Default value for KBASE_CONFIG_ATTR_CPU_SPEED_FUNC.
282 * Points to @ref kbase_cpuprops_get_default_clock_speed.
284 #define DEFAULT_CPU_SPEED_FUNC \
285 ((uintptr_t)kbase_cpuprops_get_default_clock_speed)
287 #endif /* _KBASE_CONFIG_DEFAULTS_H_ */