drivers/gpu/arm/midgard/backend/gpu/mali_kbase_time.c

   1 /*
   2  *
   3  * (C) COPYRIGHT 2014-2015 ARM Limited. All rights reserved.
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * A copy of the licence is included with the program, and can also be obtained
  11  * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  12  * Boston, MA  02110-1301, USA.
  13  *
  14  */
  15
  16
  17
  18
  19 /**
  20  *
  21  */
  22
  23 #include <mali_kbase.h>
  24 #include <mali_kbase_hwaccess_time.h>
  25 #include <backend/gpu/mali_kbase_device_internal.h>
  26 #include <backend/gpu/mali_kbase_pm_internal.h>
  27
  28 void kbase_backend_get_gpu_time(struct kbase_device *kbdev, u64 *cycle_counter,
  29                                 u64 *system_time, struct timespec *ts)
  30 {
  31         u32 hi1, hi2;
  32
  33         kbase_pm_request_gpu_cycle_counter(kbdev);
  34
  35         /* Read hi, lo, hi to ensure that overflow from lo to hi is handled
  36          * correctly */
  37         do {
  38                 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
  39                                                                         NULL);
  40                 *cycle_counter = kbase_reg_read(kbdev,
  41                                         GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
  42                 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI),
  43                                                                         NULL);
  44                 *cycle_counter |= (((u64) hi1) << 32);
  45         } while (hi1 != hi2);
  46
  47         /* Read hi, lo, hi to ensure that overflow from lo to hi is handled
  48          * correctly */
  49         do {
  50                 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
  51                                                                         NULL);
  52                 *system_time = kbase_reg_read(kbdev,
  53                                         GPU_CONTROL_REG(TIMESTAMP_LO), NULL);
  54                 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI),
  55                                                                         NULL);
  56                 *system_time |= (((u64) hi1) << 32);
  57         } while (hi1 != hi2);
  58
  59         /* Record the CPU's idea of current time */
  60         getrawmonotonic(ts);
  61
  62         kbase_pm_release_gpu_cycle_counter(kbdev);
  63 }
  64
  65 /**
  66  * kbase_wait_write_flush -  Wait for GPU write flush
  67  * @kctx: Context pointer
  68  *
  69  * Wait 1000 GPU clock cycles. This delay is known to give the GPU time to flush
  70  * its write buffer.
  71  *
  72  * Only in use for BASE_HW_ISSUE_6367
  73  *
  74  * Note : If GPU resets occur then the counters are reset to zero, the delay may
  75  * not be as expected.
  76  */
  77 #ifndef CONFIG_MALI_NO_MALI
  78 void kbase_wait_write_flush(struct kbase_context *kctx)
  79 {
  80         u32 base_count = 0;
  81
  82         /* A suspend won't happen here, because we're in a syscall from a
  83          * userspace thread */
  84
  85         kbase_pm_context_active(kctx->kbdev);
  86         kbase_pm_request_gpu_cycle_counter(kctx->kbdev);
  87
  88         while (true) {
  89                 u32 new_count;
  90
  91                 new_count = kbase_reg_read(kctx->kbdev,
  92                                         GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL);
  93                 /* First time around, just store the count. */
  94                 if (base_count == 0) {
  95                         base_count = new_count;
  96                         continue;
  97                 }
  98
  99                 /* No need to handle wrapping, unsigned maths works for this. */
 100                 if ((new_count - base_count) > 1000)
 101                         break;
 102         }
 103
 104         kbase_pm_release_gpu_cycle_counter(kctx->kbdev);
 105         kbase_pm_context_idle(kctx->kbdev);
 106 }
 107 #endif                          /* CONFIG_MALI_NO_MALI */