1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/syscore_ops.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
31 #include <mach/iomux.h>
33 #include <asm/mach/irq.h>
35 #ifdef CONFIG_ARCH_RK30
36 #define MAX_PIN RK30_PIN6_PB7
37 #elif defined(CONFIG_ARCH_RK31)
38 #define MAX_PIN RK30_PIN3_PD7
39 #elif defined(CONFIG_ARCH_RK2928)
40 #define MAX_PIN RK2928_PIN3_PD7
41 #define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS
42 #define RK30_GPIO0_BASE RK2928_GPIO0_BASE
43 #define RK30_GPIO0_SIZE RK2928_GPIO0_SIZE
44 #define RK30_GPIO1_PHYS RK2928_GPIO1_PHYS
45 #define RK30_GPIO1_BASE RK2928_GPIO1_BASE
46 #define RK30_GPIO1_SIZE RK2928_GPIO1_SIZE
47 #define RK30_GPIO2_PHYS RK2928_GPIO2_PHYS
48 #define RK30_GPIO2_BASE RK2928_GPIO2_BASE
49 #define RK30_GPIO2_SIZE RK2928_GPIO2_SIZE
50 #define RK30_GPIO3_PHYS RK2928_GPIO3_PHYS
51 #define RK30_GPIO3_BASE RK2928_GPIO3_BASE
52 #define RK30_GPIO3_SIZE RK2928_GPIO3_SIZE
53 #define RK30_GRF_BASE RK2928_GRF_BASE
56 #define to_rk30_gpio_bank(c) container_of(c, struct rk30_gpio_bank, chip)
58 struct rk30_gpio_bank {
59 struct gpio_chip chip;
62 void __iomem *regbase; /* Base of register bank */
69 static struct lock_class_key gpio_lock_class;
71 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
72 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
73 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset);
74 static int rk30_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
75 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
76 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable);
77 static int rk30_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
79 #define RK30_GPIO_BANK(ID) \
82 .label = "gpio" #ID, \
83 .direction_input = rk30_gpiolib_direction_input, \
84 .direction_output = rk30_gpiolib_direction_output, \
85 .get = rk30_gpiolib_get, \
86 .set = rk30_gpiolib_set, \
87 .pull_updown = rk30_gpiolib_pull_updown, \
88 .dbg_show = rk30_gpiolib_dbg_show, \
89 .to_irq = rk30_gpiolib_to_irq, \
90 .base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
91 .ngpio = ID < 6 ? NUM_GROUP : 16, \
94 .irq = IRQ_GPIO##ID, \
95 .regbase = (unsigned char __iomem *) RK30_GPIO##ID##_BASE, \
98 static struct rk30_gpio_bank rk30_gpio_banks[] = {
103 #ifdef CONFIG_ARCH_RK30
109 static inline void rk30_gpio_bit_op(void __iomem *regbase, unsigned int offset, u32 bit, unsigned char flag)
111 u32 val = __raw_readl(regbase + offset);
116 __raw_writel(val, regbase + offset);
119 static inline struct gpio_chip *pin_to_gpio_chip(unsigned pin)
121 if (pin < PIN_BASE || pin > MAX_PIN)
126 if (likely(pin < ARRAY_SIZE(rk30_gpio_banks)))
127 return &(rk30_gpio_banks[pin].chip);
131 static inline unsigned gpio_to_bit(unsigned gpio)
134 return 1u << (gpio % NUM_GROUP);
137 static inline unsigned offset_to_bit(unsigned offset)
142 static void GPIOSetPinLevel(void __iomem *regbase, unsigned int bit, eGPIOPinLevel_t level)
144 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, 1);
145 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DR, bit, level);
148 static int GPIOGetPinLevel(void __iomem *regbase, unsigned int bit)
150 return ((__raw_readl(regbase + GPIO_EXT_PORT) & bit) != 0);
153 static void GPIOSetPinDirection(void __iomem *regbase, unsigned int bit, eGPIOPinDirection_t direction)
155 rk30_gpio_bit_op(regbase, GPIO_SWPORT_DDR, bit, direction);
156 /* Enable debounce may halt cpu on wfi, disable it by default */
157 //rk30_gpio_bit_op(regbase, GPIO_DEBOUNCE, bit, 1);
160 static void GPIOEnableIntr(void __iomem *regbase, unsigned int bit)
162 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 1);
165 static void GPIODisableIntr(void __iomem *regbase, unsigned int bit)
167 rk30_gpio_bit_op(regbase, GPIO_INTEN, bit, 0);
170 static void GPIOAckIntr(void __iomem *regbase, unsigned int bit)
172 rk30_gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);
175 static void GPIOSetIntrType(void __iomem *regbase, unsigned int bit, eGPIOIntType_t type)
179 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
180 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
183 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);
184 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
186 case GPIOEdgelFalling:
187 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
188 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);
190 case GPIOEdgelRising:
191 rk30_gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);
192 rk30_gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);
197 static int rk30_gpio_irq_set_type(struct irq_data *d, unsigned int type)
199 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
200 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
201 eGPIOIntType_t int_type;
205 case IRQ_TYPE_EDGE_RISING:
206 int_type = GPIOEdgelRising;
208 case IRQ_TYPE_EDGE_FALLING:
209 int_type = GPIOEdgelFalling;
211 case IRQ_TYPE_LEVEL_HIGH:
212 int_type = GPIOLevelHigh;
214 case IRQ_TYPE_LEVEL_LOW:
215 int_type = GPIOLevelLow;
221 spin_lock_irqsave(&bank->lock, flags);
222 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
223 GPIOSetPinDirection(bank->regbase, bit, GPIO_IN);
224 GPIOSetIntrType(bank->regbase, bit, int_type);
225 spin_unlock_irqrestore(&bank->lock, flags);
227 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
228 __irq_set_handler_locked(d->irq, handle_level_irq);
229 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
230 __irq_set_handler_locked(d->irq, handle_edge_irq);
235 static int rk30_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
237 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
238 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
241 spin_lock_irqsave(&bank->lock, flags);
243 bank->suspend_wakeup |= bit;
245 bank->suspend_wakeup &= ~bit;
246 spin_unlock_irqrestore(&bank->lock, flags);
251 static void rk30_gpio_irq_unmask(struct irq_data *d)
253 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
254 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
257 spin_lock_irqsave(&bank->lock, flags);
258 GPIOEnableIntr(bank->regbase, bit);
259 spin_unlock_irqrestore(&bank->lock, flags);
262 static void rk30_gpio_irq_mask(struct irq_data *d)
264 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
265 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
268 spin_lock_irqsave(&bank->lock, flags);
269 GPIODisableIntr(bank->regbase, bit);
270 spin_unlock_irqrestore(&bank->lock, flags);
273 static void rk30_gpio_irq_ack(struct irq_data *d)
275 struct rk30_gpio_bank *bank = irq_data_get_irq_chip_data(d);
276 u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
278 GPIOAckIntr(bank->regbase, bit);
281 static int rk30_gpiolib_direction_output(struct gpio_chip *chip, unsigned offset, int val)
283 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
284 u32 bit = offset_to_bit(offset);
287 spin_lock_irqsave(&bank->lock, flags);
288 GPIOSetPinDirection(bank->regbase, bit, GPIO_OUT);
289 GPIOSetPinLevel(bank->regbase, bit, val);
290 spin_unlock_irqrestore(&bank->lock, flags);
294 static int rk30_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
296 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
299 spin_lock_irqsave(&bank->lock, flags);
300 GPIOSetPinDirection(bank->regbase, offset_to_bit(offset), GPIO_IN);
301 spin_unlock_irqrestore(&bank->lock, flags);
306 static int rk30_gpiolib_get(struct gpio_chip *chip, unsigned offset)
308 return GPIOGetPinLevel(to_rk30_gpio_bank(chip)->regbase, offset_to_bit(offset));
311 static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
313 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
316 spin_lock_irqsave(&bank->lock, flags);
317 GPIOSetPinLevel(bank->regbase, offset_to_bit(offset), val);
318 spin_unlock_irqrestore(&bank->lock, flags);
321 static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable)
323 #if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK2928)
324 struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip);
327 spin_lock_irqsave(&bank->lock, flags);
329 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0H_PULL + bank->id * 8, (1<<offset) | offset_to_bit(offset-16), !enable);
331 rk30_gpio_bit_op((void *__iomem) RK30_GRF_BASE, GRF_GPIO0L_PULL + bank->id * 8, (1<<(offset+16)) | offset_to_bit(offset), !enable);
332 spin_unlock_irqrestore(&bank->lock, flags);
337 static int rk30_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
339 return chip->base + offset;
342 static void rk30_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
347 for (i = 0; i < chip->ngpio; i++) {
348 unsigned pin = chip->base + i;
349 struct gpio_chip *chip = pin_to_gpioChip(pin);
350 u32 bit = pin_to_bit(pin);
351 const char *gpio_label;
356 gpio_label = gpiochip_is_requested(chip, i);
358 seq_printf(s, "[%s] GPIO%s%d: ",
359 gpio_label, chip->label, i);
363 seq_printf(s, "!chip || !bit\t");
367 GPIOSetPinDirection(chip,bit,GPIO_IN);
368 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,bit));
375 static void rk30_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
377 struct rk30_gpio_bank *bank = irq_get_handler_data(irq);
378 struct irq_chip *chip = irq_desc_get_chip(desc);
382 unsigned unmasked = 0;
384 chained_irq_enter(chip, desc);
386 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
387 ilr = __raw_readl(bank->regbase + GPIO_INTTYPE_LEVEL);
389 gpio_irq = gpio_to_irq(bank->chip.base);
393 /* if gpio is edge triggered, clear condition
394 * before executing the hander so that we don't
397 if (ilr & (1 << pin)) {
399 chained_irq_exit(chip, desc);
402 generic_handle_irq(gpio_irq + pin);
407 chained_irq_exit(chip, desc);
410 static struct irq_chip rk30_gpio_irq_chip = {
412 .irq_ack = rk30_gpio_irq_ack,
413 .irq_disable = rk30_gpio_irq_mask,
414 .irq_mask = rk30_gpio_irq_mask,
415 .irq_unmask = rk30_gpio_irq_unmask,
416 .irq_set_type = rk30_gpio_irq_set_type,
417 .irq_set_wake = rk30_gpio_irq_set_wake,
420 void __init rk30_gpio_init(void)
422 unsigned int i, j, pin;
423 struct rk30_gpio_bank *bank;
425 bank = rk30_gpio_banks;
428 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
429 spin_lock_init(&bank->lock);
430 bank->clk = clk_get(NULL, bank->chip.label);
431 clk_enable(bank->clk);
432 gpiochip_add(&bank->chip);
434 __raw_writel(0, bank->regbase + GPIO_INTEN);
435 for (j = 0; j < 32; j++) {
436 unsigned int irq = gpio_to_irq(pin);
439 irq_set_lockdep_class(irq, &gpio_lock_class);
440 irq_set_chip_data(irq, bank);
441 irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
442 set_irq_flags(irq, IRQF_VALID);
446 irq_set_handler_data(bank->irq, bank);
447 irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
449 printk("%s: %d gpio irqs in %d banks\n", __func__, pin - PIN_BASE, ARRAY_SIZE(rk30_gpio_banks));
453 __weak void rk30_setgpio_suspend_board(void)
457 __weak void rk30_setgpio_resume_board(void)
461 static int rk30_gpio_suspend(void)
465 rk30_setgpio_suspend_board();
467 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
468 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
470 bank->saved_wakeup = __raw_readl(bank->regbase + GPIO_INTEN);
471 __raw_writel(bank->suspend_wakeup, bank->regbase + GPIO_INTEN);
473 if (!bank->suspend_wakeup)
474 clk_disable(bank->clk);
480 static void rk30_gpio_resume(void)
484 for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++) {
485 struct rk30_gpio_bank *bank = &rk30_gpio_banks[i];
488 if (!bank->suspend_wakeup)
489 clk_enable(bank->clk);
491 /* keep enable for resume irq */
492 isr = __raw_readl(bank->regbase + GPIO_INT_STATUS);
493 __raw_writel(bank->saved_wakeup | (bank->suspend_wakeup & isr), bank->regbase + GPIO_INTEN);
496 rk30_setgpio_resume_board();
499 static struct syscore_ops rk30_gpio_syscore_ops = {
500 .suspend = rk30_gpio_suspend,
501 .resume = rk30_gpio_resume,
504 static int __init rk30_gpio_sysinit(void)
506 register_syscore_ops(&rk30_gpio_syscore_ops);
510 arch_initcall(rk30_gpio_sysinit);