2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
33 static LIST_HEAD(omap_gpio_list);
51 struct list_head node;
55 u32 enabled_non_wakeup_gpios;
56 struct gpio_regs context;
61 struct gpio_chip chip;
74 int context_loss_count;
76 bool workaround_enabled;
78 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
79 int (*get_context_loss_count)(struct device *dev);
81 struct omap_gpio_reg_offs *regs;
84 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85 #define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio)))
86 #define GPIO_MOD_CTRL_BIT BIT(0)
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
89 #define LINE_USED(line, offset) (line & (BIT(offset)))
91 static void omap_gpio_unmask_irq(struct irq_data *d);
93 static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
95 return bank->chip.base + gpio_irq;
98 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
101 return container_of(chip, struct gpio_bank, chip);
104 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
107 void __iomem *reg = bank->base;
110 reg += bank->regs->direction;
111 l = readl_relaxed(reg);
116 writel_relaxed(l, reg);
117 bank->context.oe = l;
121 /* set data out value using dedicate set/clear register */
122 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio,
125 void __iomem *reg = bank->base;
126 u32 l = GPIO_BIT(bank, gpio);
129 reg += bank->regs->set_dataout;
130 bank->context.dataout |= l;
132 reg += bank->regs->clr_dataout;
133 bank->context.dataout &= ~l;
136 writel_relaxed(l, reg);
139 /* set data out value using mask register */
140 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, int gpio,
143 void __iomem *reg = bank->base + bank->regs->dataout;
144 u32 gpio_bit = GPIO_BIT(bank, gpio);
147 l = readl_relaxed(reg);
152 writel_relaxed(l, reg);
153 bank->context.dataout = l;
156 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
158 void __iomem *reg = bank->base + bank->regs->datain;
160 return (readl_relaxed(reg) & (BIT(offset))) != 0;
163 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
165 void __iomem *reg = bank->base + bank->regs->dataout;
167 return (readl_relaxed(reg) & (BIT(offset))) != 0;
170 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
172 int l = readl_relaxed(base + reg);
179 writel_relaxed(l, base + reg);
182 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
184 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
185 clk_prepare_enable(bank->dbck);
186 bank->dbck_enabled = true;
188 writel_relaxed(bank->dbck_enable_mask,
189 bank->base + bank->regs->debounce_en);
193 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
195 if (bank->dbck_enable_mask && bank->dbck_enabled) {
197 * Disable debounce before cutting it's clock. If debounce is
198 * enabled but the clock is not, GPIO module seems to be unable
199 * to detect events and generate interrupts at least on OMAP3.
201 writel_relaxed(0, bank->base + bank->regs->debounce_en);
203 clk_disable_unprepare(bank->dbck);
204 bank->dbck_enabled = false;
209 * omap2_set_gpio_debounce - low level gpio debounce time
210 * @bank: the gpio bank we're acting upon
211 * @gpio: the gpio number on this @gpio
212 * @debounce: debounce time to use
214 * OMAP's debounce time is in 31us steps so we need
215 * to convert and round up to the closest unit.
217 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
224 if (!bank->dbck_flag)
229 else if (debounce > 7936)
232 debounce = (debounce / 0x1f) - 1;
234 l = GPIO_BIT(bank, gpio);
236 clk_prepare_enable(bank->dbck);
237 reg = bank->base + bank->regs->debounce;
238 writel_relaxed(debounce, reg);
240 reg = bank->base + bank->regs->debounce_en;
241 val = readl_relaxed(reg);
247 bank->dbck_enable_mask = val;
249 writel_relaxed(val, reg);
250 clk_disable_unprepare(bank->dbck);
252 * Enable debounce clock per module.
253 * This call is mandatory because in omap_gpio_request() when
254 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
255 * runtime callbck fails to turn on dbck because dbck_enable_mask
256 * used within _gpio_dbck_enable() is still not initialized at
257 * that point. Therefore we have to enable dbck here.
259 omap_gpio_dbck_enable(bank);
260 if (bank->dbck_enable_mask) {
261 bank->context.debounce = debounce;
262 bank->context.debounce_en = val;
267 * omap_clear_gpio_debounce - clear debounce settings for a gpio
268 * @bank: the gpio bank we're acting upon
269 * @gpio: the gpio number on this @gpio
271 * If a gpio is using debounce, then clear the debounce enable bit and if
272 * this is the only gpio in this bank using debounce, then clear the debounce
273 * time too. The debounce clock will also be disabled when calling this function
274 * if this is the only gpio in the bank using debounce.
276 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
278 u32 gpio_bit = GPIO_BIT(bank, gpio);
280 if (!bank->dbck_flag)
283 if (!(bank->dbck_enable_mask & gpio_bit))
286 bank->dbck_enable_mask &= ~gpio_bit;
287 bank->context.debounce_en &= ~gpio_bit;
288 writel_relaxed(bank->context.debounce_en,
289 bank->base + bank->regs->debounce_en);
291 if (!bank->dbck_enable_mask) {
292 bank->context.debounce = 0;
293 writel_relaxed(bank->context.debounce, bank->base +
294 bank->regs->debounce);
295 clk_disable_unprepare(bank->dbck);
296 bank->dbck_enabled = false;
300 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
303 void __iomem *base = bank->base;
304 u32 gpio_bit = BIT(gpio);
306 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
307 trigger & IRQ_TYPE_LEVEL_LOW);
308 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
309 trigger & IRQ_TYPE_LEVEL_HIGH);
310 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
311 trigger & IRQ_TYPE_EDGE_RISING);
312 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
313 trigger & IRQ_TYPE_EDGE_FALLING);
315 bank->context.leveldetect0 =
316 readl_relaxed(bank->base + bank->regs->leveldetect0);
317 bank->context.leveldetect1 =
318 readl_relaxed(bank->base + bank->regs->leveldetect1);
319 bank->context.risingdetect =
320 readl_relaxed(bank->base + bank->regs->risingdetect);
321 bank->context.fallingdetect =
322 readl_relaxed(bank->base + bank->regs->fallingdetect);
324 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
325 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
326 bank->context.wake_en =
327 readl_relaxed(bank->base + bank->regs->wkup_en);
330 /* This part needs to be executed always for OMAP{34xx, 44xx} */
331 if (!bank->regs->irqctrl) {
332 /* On omap24xx proceed only when valid GPIO bit is set */
333 if (bank->non_wakeup_gpios) {
334 if (!(bank->non_wakeup_gpios & gpio_bit))
339 * Log the edge gpio and manually trigger the IRQ
340 * after resume if the input level changes
341 * to avoid irq lost during PER RET/OFF mode
342 * Applies for omap2 non-wakeup gpio and all omap3 gpios
344 if (trigger & IRQ_TYPE_EDGE_BOTH)
345 bank->enabled_non_wakeup_gpios |= gpio_bit;
347 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
352 readl_relaxed(bank->base + bank->regs->leveldetect0) |
353 readl_relaxed(bank->base + bank->regs->leveldetect1);
356 #ifdef CONFIG_ARCH_OMAP1
358 * This only applies to chips that can't do both rising and falling edge
359 * detection at once. For all other chips, this function is a noop.
361 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
363 void __iomem *reg = bank->base;
366 if (!bank->regs->irqctrl)
369 reg += bank->regs->irqctrl;
371 l = readl_relaxed(reg);
377 writel_relaxed(l, reg);
380 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
383 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
386 void __iomem *reg = bank->base;
387 void __iomem *base = bank->base;
390 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
391 omap_set_gpio_trigger(bank, gpio, trigger);
392 } else if (bank->regs->irqctrl) {
393 reg += bank->regs->irqctrl;
395 l = readl_relaxed(reg);
396 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
397 bank->toggle_mask |= BIT(gpio);
398 if (trigger & IRQ_TYPE_EDGE_RISING)
400 else if (trigger & IRQ_TYPE_EDGE_FALLING)
405 writel_relaxed(l, reg);
406 } else if (bank->regs->edgectrl1) {
408 reg += bank->regs->edgectrl2;
410 reg += bank->regs->edgectrl1;
413 l = readl_relaxed(reg);
414 l &= ~(3 << (gpio << 1));
415 if (trigger & IRQ_TYPE_EDGE_RISING)
416 l |= 2 << (gpio << 1);
417 if (trigger & IRQ_TYPE_EDGE_FALLING)
420 /* Enable wake-up during idle for dynamic tick */
421 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
422 bank->context.wake_en =
423 readl_relaxed(bank->base + bank->regs->wkup_en);
424 writel_relaxed(l, reg);
429 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
431 if (bank->regs->pinctrl) {
432 void __iomem *reg = bank->base + bank->regs->pinctrl;
434 /* Claim the pin for MPU */
435 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
438 if (bank->regs->ctrl && !BANK_USED(bank)) {
439 void __iomem *reg = bank->base + bank->regs->ctrl;
442 ctrl = readl_relaxed(reg);
443 /* Module is enabled, clocks are not gated */
444 ctrl &= ~GPIO_MOD_CTRL_BIT;
445 writel_relaxed(ctrl, reg);
446 bank->context.ctrl = ctrl;
450 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
452 void __iomem *base = bank->base;
454 if (bank->regs->wkup_en &&
455 !LINE_USED(bank->mod_usage, offset) &&
456 !LINE_USED(bank->irq_usage, offset)) {
457 /* Disable wake-up during idle for dynamic tick */
458 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
459 bank->context.wake_en =
460 readl_relaxed(bank->base + bank->regs->wkup_en);
463 if (bank->regs->ctrl && !BANK_USED(bank)) {
464 void __iomem *reg = bank->base + bank->regs->ctrl;
467 ctrl = readl_relaxed(reg);
468 /* Module is disabled, clocks are gated */
469 ctrl |= GPIO_MOD_CTRL_BIT;
470 writel_relaxed(ctrl, reg);
471 bank->context.ctrl = ctrl;
475 static int omap_gpio_is_input(struct gpio_bank *bank, int mask)
477 void __iomem *reg = bank->base + bank->regs->direction;
479 return readl_relaxed(reg) & mask;
482 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned gpio,
485 if (!LINE_USED(bank->mod_usage, offset)) {
486 omap_enable_gpio_module(bank, offset);
487 omap_set_gpio_direction(bank, offset, 1);
489 bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio));
492 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
494 struct gpio_bank *bank = omap_irq_data_get_bank(d);
500 if (!BANK_USED(bank))
501 pm_runtime_get_sync(bank->dev);
503 #ifdef CONFIG_ARCH_OMAP1
504 if (d->irq > IH_MPUIO_BASE)
505 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
509 gpio = omap_irq_to_gpio(bank, d->hwirq);
511 if (type & ~IRQ_TYPE_SENSE_MASK)
514 if (!bank->regs->leveldetect0 &&
515 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
518 spin_lock_irqsave(&bank->lock, flags);
519 offset = GPIO_INDEX(bank, gpio);
520 retval = omap_set_gpio_triggering(bank, offset, type);
521 omap_gpio_init_irq(bank, gpio, offset);
522 if (!omap_gpio_is_input(bank, BIT(offset))) {
523 spin_unlock_irqrestore(&bank->lock, flags);
526 spin_unlock_irqrestore(&bank->lock, flags);
528 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
529 __irq_set_handler_locked(d->irq, handle_level_irq);
530 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
531 __irq_set_handler_locked(d->irq, handle_edge_irq);
536 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
538 void __iomem *reg = bank->base;
540 reg += bank->regs->irqstatus;
541 writel_relaxed(gpio_mask, reg);
543 /* Workaround for clearing DSP GPIO interrupts to allow retention */
544 if (bank->regs->irqstatus2) {
545 reg = bank->base + bank->regs->irqstatus2;
546 writel_relaxed(gpio_mask, reg);
549 /* Flush posted write for the irq status to avoid spurious interrupts */
553 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
555 omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
558 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
560 void __iomem *reg = bank->base;
562 u32 mask = (BIT(bank->width)) - 1;
564 reg += bank->regs->irqenable;
565 l = readl_relaxed(reg);
566 if (bank->regs->irqenable_inv)
572 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
574 void __iomem *reg = bank->base;
577 if (bank->regs->set_irqenable) {
578 reg += bank->regs->set_irqenable;
580 bank->context.irqenable1 |= gpio_mask;
582 reg += bank->regs->irqenable;
583 l = readl_relaxed(reg);
584 if (bank->regs->irqenable_inv)
588 bank->context.irqenable1 = l;
591 writel_relaxed(l, reg);
594 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
596 void __iomem *reg = bank->base;
599 if (bank->regs->clr_irqenable) {
600 reg += bank->regs->clr_irqenable;
602 bank->context.irqenable1 &= ~gpio_mask;
604 reg += bank->regs->irqenable;
605 l = readl_relaxed(reg);
606 if (bank->regs->irqenable_inv)
610 bank->context.irqenable1 = l;
613 writel_relaxed(l, reg);
616 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio,
620 omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
622 omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
626 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
627 * 1510 does not seem to have a wake-up register. If JTAG is connected
628 * to the target, system will wake up always on GPIO events. While
629 * system is running all registered GPIO interrupts need to have wake-up
630 * enabled. When system is suspended, only selected GPIO interrupts need
631 * to have wake-up enabled.
633 static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
635 u32 gpio_bit = GPIO_BIT(bank, gpio);
638 if (bank->non_wakeup_gpios & gpio_bit) {
640 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
644 spin_lock_irqsave(&bank->lock, flags);
646 bank->context.wake_en |= gpio_bit;
648 bank->context.wake_en &= ~gpio_bit;
650 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
651 spin_unlock_irqrestore(&bank->lock, flags);
656 static void omap_reset_gpio(struct gpio_bank *bank, int gpio)
658 omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
659 omap_set_gpio_irqenable(bank, gpio, 0);
660 omap_clear_gpio_irqstatus(bank, gpio);
661 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
662 omap_clear_gpio_debounce(bank, gpio);
665 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
666 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
668 struct gpio_bank *bank = omap_irq_data_get_bank(d);
669 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
671 return omap_set_gpio_wakeup(bank, gpio, enable);
674 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
676 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
680 * If this is the first gpio_request for the bank,
681 * enable the bank module.
683 if (!BANK_USED(bank))
684 pm_runtime_get_sync(bank->dev);
686 spin_lock_irqsave(&bank->lock, flags);
687 /* Set trigger to none. You need to enable the desired trigger with
688 * request_irq() or set_irq_type(). Only do this if the IRQ line has
689 * not already been requested.
691 if (!LINE_USED(bank->irq_usage, offset)) {
692 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
693 omap_enable_gpio_module(bank, offset);
695 bank->mod_usage |= BIT(offset);
696 spin_unlock_irqrestore(&bank->lock, flags);
701 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
703 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
706 spin_lock_irqsave(&bank->lock, flags);
707 bank->mod_usage &= ~(BIT(offset));
708 omap_disable_gpio_module(bank, offset);
709 omap_reset_gpio(bank, bank->chip.base + offset);
710 spin_unlock_irqrestore(&bank->lock, flags);
713 * If this is the last gpio to be freed in the bank,
714 * disable the bank module.
716 if (!BANK_USED(bank))
717 pm_runtime_put(bank->dev);
721 * We need to unmask the GPIO bank interrupt as soon as possible to
722 * avoid missing GPIO interrupts for other lines in the bank.
723 * Then we need to mask-read-clear-unmask the triggered GPIO lines
724 * in the bank to avoid missing nested interrupts for a GPIO line.
725 * If we wait to unmask individual GPIO lines in the bank after the
726 * line's interrupt handler has been run, we may miss some nested
729 static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
731 void __iomem *isr_reg = NULL;
734 struct gpio_bank *bank;
736 struct irq_chip *irqchip = irq_desc_get_chip(desc);
737 struct gpio_chip *chip = irq_get_handler_data(irq);
739 chained_irq_enter(irqchip, desc);
741 bank = container_of(chip, struct gpio_bank, chip);
742 isr_reg = bank->base + bank->regs->irqstatus;
743 pm_runtime_get_sync(bank->dev);
745 if (WARN_ON(!isr_reg))
749 u32 isr_saved, level_mask = 0;
752 enabled = omap_get_gpio_irqbank_mask(bank);
753 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
755 if (bank->level_mask)
756 level_mask = bank->level_mask & enabled;
758 /* clear edge sensitive interrupts before handler(s) are
759 called so that we don't miss any interrupt occurred while
761 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
762 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
763 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
765 /* if there is only edge sensitive GPIO pin interrupts
766 configured, we could unmask GPIO bank interrupt immediately */
767 if (!level_mask && !unmasked) {
769 chained_irq_exit(irqchip, desc);
780 * Some chips can't respond to both rising and falling
781 * at the same time. If this irq was requested with
782 * both flags, we need to flip the ICR data for the IRQ
783 * to respond to the IRQ for the opposite direction.
784 * This will be indicated in the bank toggle_mask.
786 if (bank->toggle_mask & (BIT(bit)))
787 omap_toggle_gpio_edge_triggering(bank, bit);
789 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
793 /* if bank has any level sensitive GPIO pin interrupt
794 configured, we must unmask the bank interrupt only after
795 handler(s) are executed in order to avoid spurious bank
799 chained_irq_exit(irqchip, desc);
800 pm_runtime_put(bank->dev);
803 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
805 struct gpio_bank *bank = omap_irq_data_get_bank(d);
806 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
808 unsigned offset = GPIO_INDEX(bank, gpio);
810 if (!BANK_USED(bank))
811 pm_runtime_get_sync(bank->dev);
813 spin_lock_irqsave(&bank->lock, flags);
814 omap_gpio_init_irq(bank, gpio, offset);
815 spin_unlock_irqrestore(&bank->lock, flags);
816 omap_gpio_unmask_irq(d);
821 static void omap_gpio_irq_shutdown(struct irq_data *d)
823 struct gpio_bank *bank = omap_irq_data_get_bank(d);
824 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
826 unsigned offset = GPIO_INDEX(bank, gpio);
828 spin_lock_irqsave(&bank->lock, flags);
829 bank->irq_usage &= ~(BIT(offset));
830 omap_disable_gpio_module(bank, offset);
831 omap_reset_gpio(bank, gpio);
832 spin_unlock_irqrestore(&bank->lock, flags);
835 * If this is the last IRQ to be freed in the bank,
836 * disable the bank module.
838 if (!BANK_USED(bank))
839 pm_runtime_put(bank->dev);
842 static void omap_gpio_ack_irq(struct irq_data *d)
844 struct gpio_bank *bank = omap_irq_data_get_bank(d);
845 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
847 omap_clear_gpio_irqstatus(bank, gpio);
850 static void omap_gpio_mask_irq(struct irq_data *d)
852 struct gpio_bank *bank = omap_irq_data_get_bank(d);
853 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
856 spin_lock_irqsave(&bank->lock, flags);
857 omap_set_gpio_irqenable(bank, gpio, 0);
858 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
859 spin_unlock_irqrestore(&bank->lock, flags);
862 static void omap_gpio_unmask_irq(struct irq_data *d)
864 struct gpio_bank *bank = omap_irq_data_get_bank(d);
865 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
866 unsigned int irq_mask = GPIO_BIT(bank, gpio);
867 u32 trigger = irqd_get_trigger_type(d);
870 spin_lock_irqsave(&bank->lock, flags);
872 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
874 /* For level-triggered GPIOs, the clearing must be done after
875 * the HW source is cleared, thus after the handler has run */
876 if (bank->level_mask & irq_mask) {
877 omap_set_gpio_irqenable(bank, gpio, 0);
878 omap_clear_gpio_irqstatus(bank, gpio);
881 omap_set_gpio_irqenable(bank, gpio, 1);
882 spin_unlock_irqrestore(&bank->lock, flags);
885 /*---------------------------------------------------------------------*/
887 static int omap_mpuio_suspend_noirq(struct device *dev)
889 struct platform_device *pdev = to_platform_device(dev);
890 struct gpio_bank *bank = platform_get_drvdata(pdev);
891 void __iomem *mask_reg = bank->base +
892 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
895 spin_lock_irqsave(&bank->lock, flags);
896 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
897 spin_unlock_irqrestore(&bank->lock, flags);
902 static int omap_mpuio_resume_noirq(struct device *dev)
904 struct platform_device *pdev = to_platform_device(dev);
905 struct gpio_bank *bank = platform_get_drvdata(pdev);
906 void __iomem *mask_reg = bank->base +
907 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
910 spin_lock_irqsave(&bank->lock, flags);
911 writel_relaxed(bank->context.wake_en, mask_reg);
912 spin_unlock_irqrestore(&bank->lock, flags);
917 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
918 .suspend_noirq = omap_mpuio_suspend_noirq,
919 .resume_noirq = omap_mpuio_resume_noirq,
922 /* use platform_driver for this. */
923 static struct platform_driver omap_mpuio_driver = {
926 .pm = &omap_mpuio_dev_pm_ops,
930 static struct platform_device omap_mpuio_device = {
934 .driver = &omap_mpuio_driver.driver,
936 /* could list the /proc/iomem resources */
939 static inline void omap_mpuio_init(struct gpio_bank *bank)
941 platform_set_drvdata(&omap_mpuio_device, bank);
943 if (platform_driver_register(&omap_mpuio_driver) == 0)
944 (void) platform_device_register(&omap_mpuio_device);
947 /*---------------------------------------------------------------------*/
949 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
951 struct gpio_bank *bank;
956 bank = container_of(chip, struct gpio_bank, chip);
957 reg = bank->base + bank->regs->direction;
958 spin_lock_irqsave(&bank->lock, flags);
959 dir = !!(readl_relaxed(reg) & BIT(offset));
960 spin_unlock_irqrestore(&bank->lock, flags);
964 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
966 struct gpio_bank *bank;
969 bank = container_of(chip, struct gpio_bank, chip);
970 spin_lock_irqsave(&bank->lock, flags);
971 omap_set_gpio_direction(bank, offset, 1);
972 spin_unlock_irqrestore(&bank->lock, flags);
976 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
978 struct gpio_bank *bank;
981 bank = container_of(chip, struct gpio_bank, chip);
982 mask = (BIT(offset));
984 if (omap_gpio_is_input(bank, mask))
985 return omap_get_gpio_datain(bank, offset);
987 return omap_get_gpio_dataout(bank, offset);
990 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
992 struct gpio_bank *bank;
995 bank = container_of(chip, struct gpio_bank, chip);
996 spin_lock_irqsave(&bank->lock, flags);
997 bank->set_dataout(bank, offset, value);
998 omap_set_gpio_direction(bank, offset, 0);
999 spin_unlock_irqrestore(&bank->lock, flags);
1003 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1006 struct gpio_bank *bank;
1007 unsigned long flags;
1009 bank = container_of(chip, struct gpio_bank, chip);
1011 spin_lock_irqsave(&bank->lock, flags);
1012 omap2_set_gpio_debounce(bank, offset, debounce);
1013 spin_unlock_irqrestore(&bank->lock, flags);
1018 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1020 struct gpio_bank *bank;
1021 unsigned long flags;
1023 bank = container_of(chip, struct gpio_bank, chip);
1024 spin_lock_irqsave(&bank->lock, flags);
1025 bank->set_dataout(bank, offset, value);
1026 spin_unlock_irqrestore(&bank->lock, flags);
1029 /*---------------------------------------------------------------------*/
1031 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1036 if (called || bank->regs->revision == USHRT_MAX)
1039 rev = readw_relaxed(bank->base + bank->regs->revision);
1040 pr_info("OMAP GPIO hardware version %d.%d\n",
1041 (rev >> 4) & 0x0f, rev & 0x0f);
1046 static void omap_gpio_mod_init(struct gpio_bank *bank)
1048 void __iomem *base = bank->base;
1051 if (bank->width == 16)
1054 if (bank->is_mpuio) {
1055 writel_relaxed(l, bank->base + bank->regs->irqenable);
1059 omap_gpio_rmw(base, bank->regs->irqenable, l,
1060 bank->regs->irqenable_inv);
1061 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1062 !bank->regs->irqenable_inv);
1063 if (bank->regs->debounce_en)
1064 writel_relaxed(0, base + bank->regs->debounce_en);
1066 /* Save OE default value (0xffffffff) in the context */
1067 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1068 /* Initialize interface clk ungated, module enabled */
1069 if (bank->regs->ctrl)
1070 writel_relaxed(0, base + bank->regs->ctrl);
1072 bank->dbck = clk_get(bank->dev, "dbclk");
1073 if (IS_ERR(bank->dbck))
1074 dev_err(bank->dev, "Could not get gpio dbck\n");
1078 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1081 struct irq_chip_generic *gc;
1082 struct irq_chip_type *ct;
1084 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1087 dev_err(bank->dev, "Memory alloc failed for gc\n");
1091 ct = gc->chip_types;
1093 /* NOTE: No ack required, reading IRQ status clears it. */
1094 ct->chip.irq_mask = irq_gc_mask_set_bit;
1095 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1096 ct->chip.irq_set_type = omap_gpio_irq_type;
1098 if (bank->regs->wkup_en)
1099 ct->chip.irq_set_wake = omap_gpio_wake_enable;
1101 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1102 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1103 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1106 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1114 * REVISIT eventually switch from OMAP-specific gpio structs
1115 * over to the generic ones
1117 bank->chip.request = omap_gpio_request;
1118 bank->chip.free = omap_gpio_free;
1119 bank->chip.get_direction = omap_gpio_get_direction;
1120 bank->chip.direction_input = omap_gpio_input;
1121 bank->chip.get = omap_gpio_get;
1122 bank->chip.direction_output = omap_gpio_output;
1123 bank->chip.set_debounce = omap_gpio_debounce;
1124 bank->chip.set = omap_gpio_set;
1125 if (bank->is_mpuio) {
1126 bank->chip.label = "mpuio";
1127 if (bank->regs->wkup_en)
1128 bank->chip.dev = &omap_mpuio_device.dev;
1129 bank->chip.base = OMAP_MPUIO(0);
1131 bank->chip.label = "gpio";
1132 bank->chip.base = gpio;
1133 gpio += bank->width;
1135 bank->chip.ngpio = bank->width;
1137 ret = gpiochip_add(&bank->chip);
1139 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1143 #ifdef CONFIG_ARCH_OMAP1
1145 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1146 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1148 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1150 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1155 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1156 irq_base, omap_gpio_irq_handler,
1160 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1161 gpiochip_remove(&bank->chip);
1165 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1166 bank->irq, omap_gpio_irq_handler);
1168 for (j = 0; j < bank->width; j++) {
1169 int irq = irq_find_mapping(bank->chip.irqdomain, j);
1170 if (bank->is_mpuio) {
1171 omap_mpuio_alloc_gc(bank, irq, bank->width);
1172 irq_set_chip_and_handler(irq, NULL, NULL);
1173 set_irq_flags(irq, 0);
1180 static const struct of_device_id omap_gpio_match[];
1182 static int omap_gpio_probe(struct platform_device *pdev)
1184 struct device *dev = &pdev->dev;
1185 struct device_node *node = dev->of_node;
1186 const struct of_device_id *match;
1187 const struct omap_gpio_platform_data *pdata;
1188 struct resource *res;
1189 struct gpio_bank *bank;
1190 struct irq_chip *irqc;
1193 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1195 pdata = match ? match->data : dev_get_platdata(dev);
1199 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1201 dev_err(dev, "Memory alloc failed\n");
1205 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1209 irqc->irq_startup = omap_gpio_irq_startup,
1210 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1211 irqc->irq_ack = omap_gpio_ack_irq,
1212 irqc->irq_mask = omap_gpio_mask_irq,
1213 irqc->irq_unmask = omap_gpio_unmask_irq,
1214 irqc->irq_set_type = omap_gpio_irq_type,
1215 irqc->irq_set_wake = omap_gpio_wake_enable,
1216 irqc->name = dev_name(&pdev->dev);
1218 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1219 if (unlikely(!res)) {
1220 dev_err(dev, "Invalid IRQ resource\n");
1224 bank->irq = res->start;
1226 bank->chip.dev = dev;
1227 bank->dbck_flag = pdata->dbck_flag;
1228 bank->stride = pdata->bank_stride;
1229 bank->width = pdata->bank_width;
1230 bank->is_mpuio = pdata->is_mpuio;
1231 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1232 bank->regs = pdata->regs;
1233 #ifdef CONFIG_OF_GPIO
1234 bank->chip.of_node = of_node_get(node);
1237 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1238 bank->loses_context = true;
1240 bank->loses_context = pdata->loses_context;
1242 if (bank->loses_context)
1243 bank->get_context_loss_count =
1244 pdata->get_context_loss_count;
1247 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1248 bank->set_dataout = omap_set_gpio_dataout_reg;
1250 bank->set_dataout = omap_set_gpio_dataout_mask;
1252 spin_lock_init(&bank->lock);
1254 /* Static mapping, never released */
1255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256 bank->base = devm_ioremap_resource(dev, res);
1257 if (IS_ERR(bank->base)) {
1258 irq_domain_remove(bank->chip.irqdomain);
1259 return PTR_ERR(bank->base);
1262 platform_set_drvdata(pdev, bank);
1264 pm_runtime_enable(bank->dev);
1265 pm_runtime_irq_safe(bank->dev);
1266 pm_runtime_get_sync(bank->dev);
1269 omap_mpuio_init(bank);
1271 omap_gpio_mod_init(bank);
1273 ret = omap_gpio_chip_init(bank, irqc);
1277 omap_gpio_show_rev(bank);
1279 pm_runtime_put(bank->dev);
1281 list_add_tail(&bank->node, &omap_gpio_list);
1286 #ifdef CONFIG_ARCH_OMAP2PLUS
1288 #if defined(CONFIG_PM)
1289 static void omap_gpio_restore_context(struct gpio_bank *bank);
1291 static int omap_gpio_runtime_suspend(struct device *dev)
1293 struct platform_device *pdev = to_platform_device(dev);
1294 struct gpio_bank *bank = platform_get_drvdata(pdev);
1296 unsigned long flags;
1297 u32 wake_low, wake_hi;
1299 spin_lock_irqsave(&bank->lock, flags);
1302 * Only edges can generate a wakeup event to the PRCM.
1304 * Therefore, ensure any wake-up capable GPIOs have
1305 * edge-detection enabled before going idle to ensure a wakeup
1306 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1309 * The normal values will be restored upon ->runtime_resume()
1310 * by writing back the values saved in bank->context.
1312 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1314 writel_relaxed(wake_low | bank->context.fallingdetect,
1315 bank->base + bank->regs->fallingdetect);
1316 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1318 writel_relaxed(wake_hi | bank->context.risingdetect,
1319 bank->base + bank->regs->risingdetect);
1321 if (!bank->enabled_non_wakeup_gpios)
1322 goto update_gpio_context_count;
1324 if (bank->power_mode != OFF_MODE) {
1325 bank->power_mode = 0;
1326 goto update_gpio_context_count;
1329 * If going to OFF, remove triggering for all
1330 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1331 * generated. See OMAP2420 Errata item 1.101.
1333 bank->saved_datain = readl_relaxed(bank->base +
1334 bank->regs->datain);
1335 l1 = bank->context.fallingdetect;
1336 l2 = bank->context.risingdetect;
1338 l1 &= ~bank->enabled_non_wakeup_gpios;
1339 l2 &= ~bank->enabled_non_wakeup_gpios;
1341 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1342 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1344 bank->workaround_enabled = true;
1346 update_gpio_context_count:
1347 if (bank->get_context_loss_count)
1348 bank->context_loss_count =
1349 bank->get_context_loss_count(bank->dev);
1351 omap_gpio_dbck_disable(bank);
1352 spin_unlock_irqrestore(&bank->lock, flags);
1357 static void omap_gpio_init_context(struct gpio_bank *p);
1359 static int omap_gpio_runtime_resume(struct device *dev)
1361 struct platform_device *pdev = to_platform_device(dev);
1362 struct gpio_bank *bank = platform_get_drvdata(pdev);
1363 u32 l = 0, gen, gen0, gen1;
1364 unsigned long flags;
1367 spin_lock_irqsave(&bank->lock, flags);
1370 * On the first resume during the probe, the context has not
1371 * been initialised and so initialise it now. Also initialise
1372 * the context loss count.
1374 if (bank->loses_context && !bank->context_valid) {
1375 omap_gpio_init_context(bank);
1377 if (bank->get_context_loss_count)
1378 bank->context_loss_count =
1379 bank->get_context_loss_count(bank->dev);
1382 omap_gpio_dbck_enable(bank);
1385 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1386 * GPIOs were set to edge trigger also in order to be able to
1387 * generate a PRCM wakeup. Here we restore the
1388 * pre-runtime_suspend() values for edge triggering.
1390 writel_relaxed(bank->context.fallingdetect,
1391 bank->base + bank->regs->fallingdetect);
1392 writel_relaxed(bank->context.risingdetect,
1393 bank->base + bank->regs->risingdetect);
1395 if (bank->loses_context) {
1396 if (!bank->get_context_loss_count) {
1397 omap_gpio_restore_context(bank);
1399 c = bank->get_context_loss_count(bank->dev);
1400 if (c != bank->context_loss_count) {
1401 omap_gpio_restore_context(bank);
1403 spin_unlock_irqrestore(&bank->lock, flags);
1409 if (!bank->workaround_enabled) {
1410 spin_unlock_irqrestore(&bank->lock, flags);
1414 l = readl_relaxed(bank->base + bank->regs->datain);
1417 * Check if any of the non-wakeup interrupt GPIOs have changed
1418 * state. If so, generate an IRQ by software. This is
1419 * horribly racy, but it's the best we can do to work around
1422 l ^= bank->saved_datain;
1423 l &= bank->enabled_non_wakeup_gpios;
1426 * No need to generate IRQs for the rising edge for gpio IRQs
1427 * configured with falling edge only; and vice versa.
1429 gen0 = l & bank->context.fallingdetect;
1430 gen0 &= bank->saved_datain;
1432 gen1 = l & bank->context.risingdetect;
1433 gen1 &= ~(bank->saved_datain);
1435 /* FIXME: Consider GPIO IRQs with level detections properly! */
1436 gen = l & (~(bank->context.fallingdetect) &
1437 ~(bank->context.risingdetect));
1438 /* Consider all GPIO IRQs needed to be updated */
1444 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1445 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1447 if (!bank->regs->irqstatus_raw0) {
1448 writel_relaxed(old0 | gen, bank->base +
1449 bank->regs->leveldetect0);
1450 writel_relaxed(old1 | gen, bank->base +
1451 bank->regs->leveldetect1);
1454 if (bank->regs->irqstatus_raw0) {
1455 writel_relaxed(old0 | l, bank->base +
1456 bank->regs->leveldetect0);
1457 writel_relaxed(old1 | l, bank->base +
1458 bank->regs->leveldetect1);
1460 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1461 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1464 bank->workaround_enabled = false;
1465 spin_unlock_irqrestore(&bank->lock, flags);
1469 #endif /* CONFIG_PM */
1471 void omap2_gpio_prepare_for_idle(int pwr_mode)
1473 struct gpio_bank *bank;
1475 list_for_each_entry(bank, &omap_gpio_list, node) {
1476 if (!BANK_USED(bank) || !bank->loses_context)
1479 bank->power_mode = pwr_mode;
1481 pm_runtime_put_sync_suspend(bank->dev);
1485 void omap2_gpio_resume_after_idle(void)
1487 struct gpio_bank *bank;
1489 list_for_each_entry(bank, &omap_gpio_list, node) {
1490 if (!BANK_USED(bank) || !bank->loses_context)
1493 pm_runtime_get_sync(bank->dev);
1497 #if defined(CONFIG_PM)
1498 static void omap_gpio_init_context(struct gpio_bank *p)
1500 struct omap_gpio_reg_offs *regs = p->regs;
1501 void __iomem *base = p->base;
1503 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1504 p->context.oe = readl_relaxed(base + regs->direction);
1505 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1506 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1507 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1508 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1509 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1510 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1511 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1513 if (regs->set_dataout && p->regs->clr_dataout)
1514 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1516 p->context.dataout = readl_relaxed(base + regs->dataout);
1518 p->context_valid = true;
1521 static void omap_gpio_restore_context(struct gpio_bank *bank)
1523 writel_relaxed(bank->context.wake_en,
1524 bank->base + bank->regs->wkup_en);
1525 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1526 writel_relaxed(bank->context.leveldetect0,
1527 bank->base + bank->regs->leveldetect0);
1528 writel_relaxed(bank->context.leveldetect1,
1529 bank->base + bank->regs->leveldetect1);
1530 writel_relaxed(bank->context.risingdetect,
1531 bank->base + bank->regs->risingdetect);
1532 writel_relaxed(bank->context.fallingdetect,
1533 bank->base + bank->regs->fallingdetect);
1534 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1535 writel_relaxed(bank->context.dataout,
1536 bank->base + bank->regs->set_dataout);
1538 writel_relaxed(bank->context.dataout,
1539 bank->base + bank->regs->dataout);
1540 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1542 if (bank->dbck_enable_mask) {
1543 writel_relaxed(bank->context.debounce, bank->base +
1544 bank->regs->debounce);
1545 writel_relaxed(bank->context.debounce_en,
1546 bank->base + bank->regs->debounce_en);
1549 writel_relaxed(bank->context.irqenable1,
1550 bank->base + bank->regs->irqenable);
1551 writel_relaxed(bank->context.irqenable2,
1552 bank->base + bank->regs->irqenable2);
1554 #endif /* CONFIG_PM */
1556 #define omap_gpio_runtime_suspend NULL
1557 #define omap_gpio_runtime_resume NULL
1558 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1561 static const struct dev_pm_ops gpio_pm_ops = {
1562 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1566 #if defined(CONFIG_OF)
1567 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1568 .revision = OMAP24XX_GPIO_REVISION,
1569 .direction = OMAP24XX_GPIO_OE,
1570 .datain = OMAP24XX_GPIO_DATAIN,
1571 .dataout = OMAP24XX_GPIO_DATAOUT,
1572 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1573 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1574 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1575 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1576 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1577 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1578 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1579 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1580 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1581 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1582 .ctrl = OMAP24XX_GPIO_CTRL,
1583 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1584 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1585 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1586 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1587 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1590 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1591 .revision = OMAP4_GPIO_REVISION,
1592 .direction = OMAP4_GPIO_OE,
1593 .datain = OMAP4_GPIO_DATAIN,
1594 .dataout = OMAP4_GPIO_DATAOUT,
1595 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1596 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1597 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1598 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1599 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1600 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1601 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1602 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1603 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1604 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1605 .ctrl = OMAP4_GPIO_CTRL,
1606 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1607 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1608 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1609 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1610 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1613 static const struct omap_gpio_platform_data omap2_pdata = {
1614 .regs = &omap2_gpio_regs,
1619 static const struct omap_gpio_platform_data omap3_pdata = {
1620 .regs = &omap2_gpio_regs,
1625 static const struct omap_gpio_platform_data omap4_pdata = {
1626 .regs = &omap4_gpio_regs,
1631 static const struct of_device_id omap_gpio_match[] = {
1633 .compatible = "ti,omap4-gpio",
1634 .data = &omap4_pdata,
1637 .compatible = "ti,omap3-gpio",
1638 .data = &omap3_pdata,
1641 .compatible = "ti,omap2-gpio",
1642 .data = &omap2_pdata,
1646 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1649 static struct platform_driver omap_gpio_driver = {
1650 .probe = omap_gpio_probe,
1652 .name = "omap_gpio",
1654 .of_match_table = of_match_ptr(omap_gpio_match),
1659 * gpio driver register needs to be done before
1660 * machine_init functions access gpio APIs.
1661 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1663 static int __init omap_gpio_drv_reg(void)
1665 return platform_driver_register(&omap_gpio_driver);
1667 postcore_initcall(omap_gpio_drv_reg);