2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/gpio.h>
18 #include <linux/slab.h>
19 #include <linux/irq.h>
21 #define MPC8XXX_GPIO_PINS 32
29 #define GPIO_ICR2 0x18
31 struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
44 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
49 static inline struct mpc8xxx_gpio_chip *
50 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
55 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
62 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
67 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
78 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
85 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
103 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
118 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
124 mpc8xxx_gpio_set(gc, gpio, val);
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
135 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
137 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
138 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
140 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
141 return irq_create_mapping(mpc8xxx_gc->irq, offset);
146 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
149 struct irq_chip *chip = irq_desc_get_chip(desc);
150 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
153 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
155 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
157 chip->irq_eoi(&desc->irq_data);
160 static void mpc8xxx_irq_unmask(struct irq_data *d)
162 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
163 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
166 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
168 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
170 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
173 static void mpc8xxx_irq_mask(struct irq_data *d)
175 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
176 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
179 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
183 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
186 static void mpc8xxx_irq_ack(struct irq_data *d)
188 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
189 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
191 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
194 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
201 case IRQ_TYPE_EDGE_FALLING:
202 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
203 setbits32(mm->regs + GPIO_ICR,
204 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
205 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
208 case IRQ_TYPE_EDGE_BOTH:
209 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
210 clrbits32(mm->regs + GPIO_ICR,
211 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
212 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
222 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
224 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
225 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
226 unsigned long gpio = irqd_to_hwirq(d);
232 reg = mm->regs + GPIO_ICR;
233 shift = (15 - gpio) * 2;
235 reg = mm->regs + GPIO_ICR2;
236 shift = (15 - (gpio % 16)) * 2;
240 case IRQ_TYPE_EDGE_FALLING:
241 case IRQ_TYPE_LEVEL_LOW:
242 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
243 clrsetbits_be32(reg, 3 << shift, 2 << shift);
244 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
247 case IRQ_TYPE_EDGE_RISING:
248 case IRQ_TYPE_LEVEL_HIGH:
249 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
250 clrsetbits_be32(reg, 3 << shift, 1 << shift);
251 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 case IRQ_TYPE_EDGE_BOTH:
255 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
256 clrbits32(reg, 3 << shift);
257 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
267 static struct irq_chip mpc8xxx_irq_chip = {
268 .name = "mpc8xxx-gpio",
269 .irq_unmask = mpc8xxx_irq_unmask,
270 .irq_mask = mpc8xxx_irq_mask,
271 .irq_ack = mpc8xxx_irq_ack,
272 .irq_set_type = mpc8xxx_irq_set_type,
275 static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
278 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
280 if (mpc8xxx_gc->of_dev_id_data)
281 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
283 irq_set_chip_data(virq, h->host_data);
284 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
285 irq_set_irq_type(virq, IRQ_TYPE_NONE);
290 static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
291 const u32 *intspec, unsigned int intsize,
292 irq_hw_number_t *out_hwirq,
293 unsigned int *out_flags)
296 /* interrupt sense values coming from the device tree equal either
297 * EDGE_FALLING or EDGE_BOTH
299 *out_hwirq = intspec[0];
300 *out_flags = intspec[1];
305 static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
306 .map = mpc8xxx_gpio_irq_map,
307 .xlate = mpc8xxx_gpio_irq_xlate,
310 static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
311 { .compatible = "fsl,mpc8349-gpio", },
312 { .compatible = "fsl,mpc8572-gpio", },
313 { .compatible = "fsl,mpc8610-gpio", },
314 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
315 { .compatible = "fsl,pq3-gpio", },
316 { .compatible = "fsl,qoriq-gpio", },
320 static void __init mpc8xxx_add_controller(struct device_node *np)
322 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
323 struct of_mm_gpio_chip *mm_gc;
324 struct gpio_chip *gc;
325 const struct of_device_id *id;
329 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
335 spin_lock_init(&mpc8xxx_gc->lock);
337 mm_gc = &mpc8xxx_gc->mm_gc;
340 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
341 gc->ngpio = MPC8XXX_GPIO_PINS;
342 gc->direction_input = mpc8xxx_gpio_dir_in;
343 gc->direction_output = mpc8xxx_gpio_dir_out;
344 if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
345 gc->get = mpc8572_gpio_get;
347 gc->get = mpc8xxx_gpio_get;
348 gc->set = mpc8xxx_gpio_set;
349 gc->to_irq = mpc8xxx_gpio_to_irq;
351 ret = of_mm_gpiochip_add(np, mm_gc);
355 hwirq = irq_of_parse_and_map(np, 0);
360 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
361 &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
362 if (!mpc8xxx_gc->irq)
365 id = of_match_node(mpc8xxx_gpio_ids, np);
367 mpc8xxx_gc->of_dev_id_data = id->data;
369 mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
371 /* ack and mask all irqs */
372 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
373 out_be32(mm_gc->regs + GPIO_IMR, 0);
375 irq_set_handler_data(hwirq, mpc8xxx_gc);
376 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
382 pr_err("%s: registration failed with status %d\n",
389 static int __init mpc8xxx_add_gpiochips(void)
391 struct device_node *np;
393 for_each_matching_node(np, mpc8xxx_gpio_ids)
394 mpc8xxx_add_controller(np);
398 arch_initcall(mpc8xxx_add_gpiochips);