drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define ohci_info(ohci, f, args...)     dev_info(ohci->card.device, f, ##args)
  58 #define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  59 #define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  60
  61 #define DESCRIPTOR_OUTPUT_MORE          0
  62 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  63 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  64 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  65 #define DESCRIPTOR_STATUS               (1 << 11)
  66 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  67 #define DESCRIPTOR_PING                 (1 << 7)
  68 #define DESCRIPTOR_YY                   (1 << 6)
  69 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  70 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  71 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  72 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  73 #define DESCRIPTOR_WAIT                 (3 << 0)
  74
  75 #define DESCRIPTOR_CMD                  (0xf << 12)
  76
  77 struct descriptor {
  78         __le16 req_count;
  79         __le16 control;
  80         __le32 data_address;
  81         __le32 branch_address;
  82         __le16 res_count;
  83         __le16 transfer_status;
  84 } __attribute__((aligned(16)));
  85
  86 #define CONTROL_SET(regs)       (regs)
  87 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  88 #define COMMAND_PTR(regs)       ((regs) + 12)
  89 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  90
  91 #define AR_BUFFER_SIZE  (32*1024)
  92 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  93 /* we need at least two pages for proper list management */
  94 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  95
  96 #define MAX_ASYNC_PAYLOAD       4096
  97 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  98 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  99
 100 struct ar_context {
 101         struct fw_ohci *ohci;
 102         struct page *pages[AR_BUFFERS];
 103         void *buffer;
 104         struct descriptor *descriptors;
 105         dma_addr_t descriptors_bus;
 106         void *pointer;
 107         unsigned int last_buffer_index;
 108         u32 regs;
 109         struct tasklet_struct tasklet;
 110 };
 111
 112 struct context;
 113
 114 typedef int (*descriptor_callback_t)(struct context *ctx,
 115                                      struct descriptor *d,
 116                                      struct descriptor *last);
 117
 118 /*
 119  * A buffer that contains a block of DMA-able coherent memory used for
 120  * storing a portion of a DMA descriptor program.
 121  */
 122 struct descriptor_buffer {
 123         struct list_head list;
 124         dma_addr_t buffer_bus;
 125         size_t buffer_size;
 126         size_t used;
 127         struct descriptor buffer[0];
 128 };
 129
 130 struct context {
 131         struct fw_ohci *ohci;
 132         u32 regs;
 133         int total_allocation;
 134         u32 current_bus;
 135         bool running;
 136         bool flushing;
 137
 138         /*
 139          * List of page-sized buffers for storing DMA descriptors.
 140          * Head of list contains buffers in use and tail of list contains
 141          * free buffers.
 142          */
 143         struct list_head buffer_list;
 144
 145         /*
 146          * Pointer to a buffer inside buffer_list that contains the tail
 147          * end of the current DMA program.
 148          */
 149         struct descriptor_buffer *buffer_tail;
 150
 151         /*
 152          * The descriptor containing the branch address of the first
 153          * descriptor that has not yet been filled by the device.
 154          */
 155         struct descriptor *last;
 156
 157         /*
 158          * The last descriptor block in the DMA program. It contains the branch
 159          * address that must be updated upon appending a new descriptor.
 160          */
 161         struct descriptor *prev;
 162         int prev_z;
 163
 164         descriptor_callback_t callback;
 165
 166         struct tasklet_struct tasklet;
 167 };
 168
 169 #define IT_HEADER_SY(v)          ((v) <<  0)
 170 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 171 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 172 #define IT_HEADER_TAG(v)         ((v) << 14)
 173 #define IT_HEADER_SPEED(v)       ((v) << 16)
 174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 175
 176 struct iso_context {
 177         struct fw_iso_context base;
 178         struct context context;
 179         void *header;
 180         size_t header_length;
 181         unsigned long flushing_completions;
 182         u32 mc_buffer_bus;
 183         u16 mc_completed;
 184         u16 last_timestamp;
 185         u8 sync;
 186         u8 tags;
 187 };
 188
 189 #define CONFIG_ROM_SIZE 1024
 190
 191 struct fw_ohci {
 192         struct fw_card card;
 193
 194         __iomem char *registers;
 195         int node_id;
 196         int generation;
 197         int request_generation; /* for timestamping incoming requests */
 198         unsigned quirks;
 199         unsigned int pri_req_max;
 200         u32 bus_time;
 201         bool bus_time_running;
 202         bool is_root;
 203         bool csr_state_setclear_abdicate;
 204         int n_ir;
 205         int n_it;
 206         /*
 207          * Spinlock for accessing fw_ohci data.  Never call out of
 208          * this driver with this lock held.
 209          */
 210         spinlock_t lock;
 211
 212         struct mutex phy_reg_mutex;
 213
 214         void *misc_buffer;
 215         dma_addr_t misc_buffer_bus;
 216
 217         struct ar_context ar_request_ctx;
 218         struct ar_context ar_response_ctx;
 219         struct context at_request_ctx;
 220         struct context at_response_ctx;
 221
 222         u32 it_context_support;
 223         u32 it_context_mask;     /* unoccupied IT contexts */
 224         struct iso_context *it_context_list;
 225         u64 ir_context_channels; /* unoccupied channels */
 226         u32 ir_context_support;
 227         u32 ir_context_mask;     /* unoccupied IR contexts */
 228         struct iso_context *ir_context_list;
 229         u64 mc_channels; /* channels in use by the multichannel IR context */
 230         bool mc_allocated;
 231
 232         __be32    *config_rom;
 233         dma_addr_t config_rom_bus;
 234         __be32    *next_config_rom;
 235         dma_addr_t next_config_rom_bus;
 236         __be32     next_header;
 237
 238         __le32    *self_id_cpu;
 239         dma_addr_t self_id_bus;
 240         struct work_struct bus_reset_work;
 241
 242         u32 self_id_buffer[512];
 243 };
 244
 245 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 246 {
 247         return container_of(card, struct fw_ohci, card);
 248 }
 249
 250 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 251 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 252 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 253 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 254 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 255 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 256
 257 #define CONTEXT_RUN     0x8000
 258 #define CONTEXT_WAKE    0x1000
 259 #define CONTEXT_DEAD    0x0800
 260 #define CONTEXT_ACTIVE  0x0400
 261
 262 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 263 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 264 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 265
 266 #define OHCI1394_REGISTER_SIZE          0x800
 267 #define OHCI1394_PCI_HCI_Control        0x40
 268 #define SELF_ID_BUF_SIZE                0x800
 269 #define OHCI_TCODE_PHY_PACKET           0x0e
 270 #define OHCI_VERSION_1_1                0x010010
 271
 272 static char ohci_driver_name[] = KBUILD_MODNAME;
 273
 274 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 275 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 276 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 277 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 278 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 279 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 280 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 281 #define PCI_DEVICE_ID_VIA_VT630X        0x3044
 282 #define PCI_REV_ID_VIA_VT6306           0x46
 283
 284 #define QUIRK_CYCLE_TIMER               0x1
 285 #define QUIRK_RESET_PACKET              0x2
 286 #define QUIRK_BE_HEADERS                0x4
 287 #define QUIRK_NO_1394A                  0x8
 288 #define QUIRK_NO_MSI                    0x10
 289 #define QUIRK_TI_SLLZ059                0x20
 290 #define QUIRK_IR_WAKE                   0x40
 291
 292 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 293 static const struct {
 294         unsigned short vendor, device, revision, flags;
 295 } ohci_quirks[] = {
 296         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 297                 QUIRK_CYCLE_TIMER},
 298
 299         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 300                 QUIRK_BE_HEADERS},
 301
 302         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 303                 QUIRK_NO_MSI},
 304
 305         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 306                 QUIRK_RESET_PACKET},
 307
 308         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 309                 QUIRK_NO_MSI},
 310
 311         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 312                 QUIRK_CYCLE_TIMER},
 313
 314         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 315                 QUIRK_NO_MSI},
 316
 317         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 318                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 319
 320         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 321                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 322
 323         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 324                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 325
 326         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 327                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 328
 329         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 330                 QUIRK_RESET_PACKET},
 331
 332         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 333                 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 334
 335         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 336                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 337 };
 338
 339 /* This overrides anything that was found in ohci_quirks[]. */
 340 static int param_quirks;
 341 module_param_named(quirks, param_quirks, int, 0644);
 342 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 343         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 344         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 345         ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 346         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 347         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 348         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 349         ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 350         ")");
 351
 352 #define OHCI_PARAM_DEBUG_AT_AR          1
 353 #define OHCI_PARAM_DEBUG_SELFIDS        2
 354 #define OHCI_PARAM_DEBUG_IRQS           4
 355 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 356
 357 static int param_debug;
 358 module_param_named(debug, param_debug, int, 0644);
 359 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 360         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 361         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 362         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 363         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 364         ", or a combination, or all = -1)");
 365
 366 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 367 {
 368         if (likely(!(param_debug &
 369                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 370                 return;
 371
 372         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 373             !(evt & OHCI1394_busReset))
 374                 return;
 375
 376         ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 377             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 378             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 379             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 380             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 381             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 382             evt & OHCI1394_isochRx              ? " IR"                 : "",
 383             evt & OHCI1394_isochTx              ? " IT"                 : "",
 384             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 385             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 386             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 387             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 388             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 389             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 390             evt & OHCI1394_busReset             ? " busReset"           : "",
 391             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 392                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 393                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 394                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 395                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 396                     OHCI1394_cycleInconsistent |
 397                     OHCI1394_regAccessFail | OHCI1394_busReset)
 398                                                 ? " ?"                  : "");
 399 }
 400
 401 static const char *speed[] = {
 402         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 403 };
 404 static const char *power[] = {
 405         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 406         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 407 };
 408 static const char port[] = { '.', '-', 'p', 'c', };
 409
 410 static char _p(u32 *s, int shift)
 411 {
 412         return port[*s >> shift & 3];
 413 }
 414
 415 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 416 {
 417         u32 *s;
 418
 419         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 420                 return;
 421
 422         ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 423                     self_id_count, generation, ohci->node_id);
 424
 425         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 426                 if ((*s & 1 << 23) == 0)
 427                         ohci_notice(ohci,
 428                             "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 429                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 430                             speed[*s >> 14 & 3], *s >> 16 & 63,
 431                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 432                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 433                 else
 434                         ohci_notice(ohci,
 435                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 436                             *s, *s >> 24 & 63,
 437                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 438                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 439 }
 440
 441 static const char *evts[] = {
 442         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 443         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 444         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 445         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 446         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 447         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 448         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 449         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 450         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 451         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 452         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 453         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 454         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 455         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 456         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 457         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 458         [0x20] = "pending/cancelled",
 459 };
 460 static const char *tcodes[] = {
 461         [0x0] = "QW req",               [0x1] = "BW req",
 462         [0x2] = "W resp",               [0x3] = "-reserved-",
 463         [0x4] = "QR req",               [0x5] = "BR req",
 464         [0x6] = "QR resp",              [0x7] = "BR resp",
 465         [0x8] = "cycle start",          [0x9] = "Lk req",
 466         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 467         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 468         [0xe] = "link internal",        [0xf] = "-reserved-",
 469 };
 470
 471 static void log_ar_at_event(struct fw_ohci *ohci,
 472                             char dir, int speed, u32 *header, int evt)
 473 {
 474         int tcode = header[0] >> 4 & 0xf;
 475         char specific[12];
 476
 477         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 478                 return;
 479
 480         if (unlikely(evt >= ARRAY_SIZE(evts)))
 481                         evt = 0x1f;
 482
 483         if (evt == OHCI1394_evt_bus_reset) {
 484                 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 485                             dir, (header[2] >> 16) & 0xff);
 486                 return;
 487         }
 488
 489         switch (tcode) {
 490         case 0x0: case 0x6: case 0x8:
 491                 snprintf(specific, sizeof(specific), " = %08x",
 492                          be32_to_cpu((__force __be32)header[3]));
 493                 break;
 494         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 495                 snprintf(specific, sizeof(specific), " %x,%x",
 496                          header[3] >> 16, header[3] & 0xffff);
 497                 break;
 498         default:
 499                 specific[0] = '\0';
 500         }
 501
 502         switch (tcode) {
 503         case 0xa:
 504                 ohci_notice(ohci, "A%c %s, %s\n",
 505                             dir, evts[evt], tcodes[tcode]);
 506                 break;
 507         case 0xe:
 508                 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 509                             dir, evts[evt], header[1], header[2]);
 510                 break;
 511         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 512                 ohci_notice(ohci,
 513                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
 514                             dir, speed, header[0] >> 10 & 0x3f,
 515                             header[1] >> 16, header[0] >> 16, evts[evt],
 516                             tcodes[tcode], header[1] & 0xffff, header[2], specific);
 517                 break;
 518         default:
 519                 ohci_notice(ohci,
 520                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 521                             dir, speed, header[0] >> 10 & 0x3f,
 522                             header[1] >> 16, header[0] >> 16, evts[evt],
 523                             tcodes[tcode], specific);
 524         }
 525 }
 526
 527 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 528 {
 529         writel(data, ohci->registers + offset);
 530 }
 531
 532 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 533 {
 534         return readl(ohci->registers + offset);
 535 }
 536
 537 static inline void flush_writes(const struct fw_ohci *ohci)
 538 {
 539         /* Do a dummy read to flush writes. */
 540         reg_read(ohci, OHCI1394_Version);
 541 }
 542
 543 /*
 544  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 545  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 546  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 547  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 548  */
 549 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 550 {
 551         u32 val;
 552         int i;
 553
 554         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 555         for (i = 0; i < 3 + 100; i++) {
 556                 val = reg_read(ohci, OHCI1394_PhyControl);
 557                 if (!~val)
 558                         return -ENODEV; /* Card was ejected. */
 559
 560                 if (val & OHCI1394_PhyControl_ReadDone)
 561                         return OHCI1394_PhyControl_ReadData(val);
 562
 563                 /*
 564                  * Try a few times without waiting.  Sleeping is necessary
 565                  * only when the link/PHY interface is busy.
 566                  */
 567                 if (i >= 3)
 568                         msleep(1);
 569         }
 570         ohci_err(ohci, "failed to read phy reg %d\n", addr);
 571         dump_stack();
 572
 573         return -EBUSY;
 574 }
 575
 576 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 577 {
 578         int i;
 579
 580         reg_write(ohci, OHCI1394_PhyControl,
 581                   OHCI1394_PhyControl_Write(addr, val));
 582         for (i = 0; i < 3 + 100; i++) {
 583                 val = reg_read(ohci, OHCI1394_PhyControl);
 584                 if (!~val)
 585                         return -ENODEV; /* Card was ejected. */
 586
 587                 if (!(val & OHCI1394_PhyControl_WritePending))
 588                         return 0;
 589
 590                 if (i >= 3)
 591                         msleep(1);
 592         }
 593         ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
 594         dump_stack();
 595
 596         return -EBUSY;
 597 }
 598
 599 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 600                           int clear_bits, int set_bits)
 601 {
 602         int ret = read_phy_reg(ohci, addr);
 603         if (ret < 0)
 604                 return ret;
 605
 606         /*
 607          * The interrupt status bits are cleared by writing a one bit.
 608          * Avoid clearing them unless explicitly requested in set_bits.
 609          */
 610         if (addr == 5)
 611                 clear_bits |= PHY_INT_STATUS_BITS;
 612
 613         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 614 }
 615
 616 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 617 {
 618         int ret;
 619
 620         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 621         if (ret < 0)
 622                 return ret;
 623
 624         return read_phy_reg(ohci, addr);
 625 }
 626
 627 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 628 {
 629         struct fw_ohci *ohci = fw_ohci(card);
 630         int ret;
 631
 632         mutex_lock(&ohci->phy_reg_mutex);
 633         ret = read_phy_reg(ohci, addr);
 634         mutex_unlock(&ohci->phy_reg_mutex);
 635
 636         return ret;
 637 }
 638
 639 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 640                                int clear_bits, int set_bits)
 641 {
 642         struct fw_ohci *ohci = fw_ohci(card);
 643         int ret;
 644
 645         mutex_lock(&ohci->phy_reg_mutex);
 646         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 647         mutex_unlock(&ohci->phy_reg_mutex);
 648
 649         return ret;
 650 }
 651
 652 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 653 {
 654         return page_private(ctx->pages[i]);
 655 }
 656
 657 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 658 {
 659         struct descriptor *d;
 660
 661         d = &ctx->descriptors[index];
 662         d->branch_address  &= cpu_to_le32(~0xf);
 663         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 664         d->transfer_status =  0;
 665
 666         wmb(); /* finish init of new descriptors before branch_address update */
 667         d = &ctx->descriptors[ctx->last_buffer_index];
 668         d->branch_address  |= cpu_to_le32(1);
 669
 670         ctx->last_buffer_index = index;
 671
 672         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 673 }
 674
 675 static void ar_context_release(struct ar_context *ctx)
 676 {
 677         unsigned int i;
 678
 679         if (ctx->buffer)
 680                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 681
 682         for (i = 0; i < AR_BUFFERS; i++)
 683                 if (ctx->pages[i]) {
 684                         dma_unmap_page(ctx->ohci->card.device,
 685                                        ar_buffer_bus(ctx, i),
 686                                        PAGE_SIZE, DMA_FROM_DEVICE);
 687                         __free_page(ctx->pages[i]);
 688                 }
 689 }
 690
 691 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 692 {
 693         struct fw_ohci *ohci = ctx->ohci;
 694
 695         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 696                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 697                 flush_writes(ohci);
 698
 699                 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 700         }
 701         /* FIXME: restart? */
 702 }
 703
 704 static inline unsigned int ar_next_buffer_index(unsigned int index)
 705 {
 706         return (index + 1) % AR_BUFFERS;
 707 }
 708
 709 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 710 {
 711         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 712 }
 713
 714 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 715 {
 716         return ar_next_buffer_index(ctx->last_buffer_index);
 717 }
 718
 719 /*
 720  * We search for the buffer that contains the last AR packet DMA data written
 721  * by the controller.
 722  */
 723 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 724                                                  unsigned int *buffer_offset)
 725 {
 726         unsigned int i, next_i, last = ctx->last_buffer_index;
 727         __le16 res_count, next_res_count;
 728
 729         i = ar_first_buffer_index(ctx);
 730         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 731
 732         /* A buffer that is not yet completely filled must be the last one. */
 733         while (i != last && res_count == 0) {
 734
 735                 /* Peek at the next descriptor. */
 736                 next_i = ar_next_buffer_index(i);
 737                 rmb(); /* read descriptors in order */
 738                 next_res_count = ACCESS_ONCE(
 739                                 ctx->descriptors[next_i].res_count);
 740                 /*
 741                  * If the next descriptor is still empty, we must stop at this
 742                  * descriptor.
 743                  */
 744                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 745                         /*
 746                          * The exception is when the DMA data for one packet is
 747                          * split over three buffers; in this case, the middle
 748                          * buffer's descriptor might be never updated by the
 749                          * controller and look still empty, and we have to peek
 750                          * at the third one.
 751                          */
 752                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 753                                 next_i = ar_next_buffer_index(next_i);
 754                                 rmb();
 755                                 next_res_count = ACCESS_ONCE(
 756                                         ctx->descriptors[next_i].res_count);
 757                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 758                                         goto next_buffer_is_active;
 759                         }
 760
 761                         break;
 762                 }
 763
 764 next_buffer_is_active:
 765                 i = next_i;
 766                 res_count = next_res_count;
 767         }
 768
 769         rmb(); /* read res_count before the DMA data */
 770
 771         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 772         if (*buffer_offset > PAGE_SIZE) {
 773                 *buffer_offset = 0;
 774                 ar_context_abort(ctx, "corrupted descriptor");
 775         }
 776
 777         return i;
 778 }
 779
 780 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 781                                     unsigned int end_buffer_index,
 782                                     unsigned int end_buffer_offset)
 783 {
 784         unsigned int i;
 785
 786         i = ar_first_buffer_index(ctx);
 787         while (i != end_buffer_index) {
 788                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 789                                         ar_buffer_bus(ctx, i),
 790                                         PAGE_SIZE, DMA_FROM_DEVICE);
 791                 i = ar_next_buffer_index(i);
 792         }
 793         if (end_buffer_offset > 0)
 794                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 795                                         ar_buffer_bus(ctx, i),
 796                                         end_buffer_offset, DMA_FROM_DEVICE);
 797 }
 798
 799 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 800 #define cond_le32_to_cpu(v) \
 801         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 802 #else
 803 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 804 #endif
 805
 806 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 807 {
 808         struct fw_ohci *ohci = ctx->ohci;
 809         struct fw_packet p;
 810         u32 status, length, tcode;
 811         int evt;
 812
 813         p.header[0] = cond_le32_to_cpu(buffer[0]);
 814         p.header[1] = cond_le32_to_cpu(buffer[1]);
 815         p.header[2] = cond_le32_to_cpu(buffer[2]);
 816
 817         tcode = (p.header[0] >> 4) & 0x0f;
 818         switch (tcode) {
 819         case TCODE_WRITE_QUADLET_REQUEST:
 820         case TCODE_READ_QUADLET_RESPONSE:
 821                 p.header[3] = (__force __u32) buffer[3];
 822                 p.header_length = 16;
 823                 p.payload_length = 0;
 824                 break;
 825
 826         case TCODE_READ_BLOCK_REQUEST :
 827                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 828                 p.header_length = 16;
 829                 p.payload_length = 0;
 830                 break;
 831
 832         case TCODE_WRITE_BLOCK_REQUEST:
 833         case TCODE_READ_BLOCK_RESPONSE:
 834         case TCODE_LOCK_REQUEST:
 835         case TCODE_LOCK_RESPONSE:
 836                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 837                 p.header_length = 16;
 838                 p.payload_length = p.header[3] >> 16;
 839                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 840                         ar_context_abort(ctx, "invalid packet length");
 841                         return NULL;
 842                 }
 843                 break;
 844
 845         case TCODE_WRITE_RESPONSE:
 846         case TCODE_READ_QUADLET_REQUEST:
 847         case OHCI_TCODE_PHY_PACKET:
 848                 p.header_length = 12;
 849                 p.payload_length = 0;
 850                 break;
 851
 852         default:
 853                 ar_context_abort(ctx, "invalid tcode");
 854                 return NULL;
 855         }
 856
 857         p.payload = (void *) buffer + p.header_length;
 858
 859         /* FIXME: What to do about evt_* errors? */
 860         length = (p.header_length + p.payload_length + 3) / 4;
 861         status = cond_le32_to_cpu(buffer[length]);
 862         evt    = (status >> 16) & 0x1f;
 863
 864         p.ack        = evt - 16;
 865         p.speed      = (status >> 21) & 0x7;
 866         p.timestamp  = status & 0xffff;
 867         p.generation = ohci->request_generation;
 868
 869         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 870
 871         /*
 872          * Several controllers, notably from NEC and VIA, forget to
 873          * write ack_complete status at PHY packet reception.
 874          */
 875         if (evt == OHCI1394_evt_no_status &&
 876             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 877                 p.ack = ACK_COMPLETE;
 878
 879         /*
 880          * The OHCI bus reset handler synthesizes a PHY packet with
 881          * the new generation number when a bus reset happens (see
 882          * section 8.4.2.3).  This helps us determine when a request
 883          * was received and make sure we send the response in the same
 884          * generation.  We only need this for requests; for responses
 885          * we use the unique tlabel for finding the matching
 886          * request.
 887          *
 888          * Alas some chips sometimes emit bus reset packets with a
 889          * wrong generation.  We set the correct generation for these
 890          * at a slightly incorrect time (in bus_reset_work).
 891          */
 892         if (evt == OHCI1394_evt_bus_reset) {
 893                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 894                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 895         } else if (ctx == &ohci->ar_request_ctx) {
 896                 fw_core_handle_request(&ohci->card, &p);
 897         } else {
 898                 fw_core_handle_response(&ohci->card, &p);
 899         }
 900
 901         return buffer + length + 1;
 902 }
 903
 904 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 905 {
 906         void *next;
 907
 908         while (p < end) {
 909                 next = handle_ar_packet(ctx, p);
 910                 if (!next)
 911                         return p;
 912                 p = next;
 913         }
 914
 915         return p;
 916 }
 917
 918 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 919 {
 920         unsigned int i;
 921
 922         i = ar_first_buffer_index(ctx);
 923         while (i != end_buffer) {
 924                 dma_sync_single_for_device(ctx->ohci->card.device,
 925                                            ar_buffer_bus(ctx, i),
 926                                            PAGE_SIZE, DMA_FROM_DEVICE);
 927                 ar_context_link_page(ctx, i);
 928                 i = ar_next_buffer_index(i);
 929         }
 930 }
 931
 932 static void ar_context_tasklet(unsigned long data)
 933 {
 934         struct ar_context *ctx = (struct ar_context *)data;
 935         unsigned int end_buffer_index, end_buffer_offset;
 936         void *p, *end;
 937
 938         p = ctx->pointer;
 939         if (!p)
 940                 return;
 941
 942         end_buffer_index = ar_search_last_active_buffer(ctx,
 943                                                         &end_buffer_offset);
 944         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 945         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 946
 947         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 948                 /*
 949                  * The filled part of the overall buffer wraps around; handle
 950                  * all packets up to the buffer end here.  If the last packet
 951                  * wraps around, its tail will be visible after the buffer end
 952                  * because the buffer start pages are mapped there again.
 953                  */
 954                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 955                 p = handle_ar_packets(ctx, p, buffer_end);
 956                 if (p < buffer_end)
 957                         goto error;
 958                 /* adjust p to point back into the actual buffer */
 959                 p -= AR_BUFFERS * PAGE_SIZE;
 960         }
 961
 962         p = handle_ar_packets(ctx, p, end);
 963         if (p != end) {
 964                 if (p > end)
 965                         ar_context_abort(ctx, "inconsistent descriptor");
 966                 goto error;
 967         }
 968
 969         ctx->pointer = p;
 970         ar_recycle_buffers(ctx, end_buffer_index);
 971
 972         return;
 973
 974 error:
 975         ctx->pointer = NULL;
 976 }
 977
 978 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 979                            unsigned int descriptors_offset, u32 regs)
 980 {
 981         unsigned int i;
 982         dma_addr_t dma_addr;
 983         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 984         struct descriptor *d;
 985
 986         ctx->regs        = regs;
 987         ctx->ohci        = ohci;
 988         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 989
 990         for (i = 0; i < AR_BUFFERS; i++) {
 991                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 992                 if (!ctx->pages[i])
 993                         goto out_of_memory;
 994                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 995                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 996                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 997                         __free_page(ctx->pages[i]);
 998                         ctx->pages[i] = NULL;
 999                         goto out_of_memory;
1000                 }
1001                 set_page_private(ctx->pages[i], dma_addr);
1002         }
1003
1004         for (i = 0; i < AR_BUFFERS; i++)
1005                 pages[i]              = ctx->pages[i];
1006         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1007                 pages[AR_BUFFERS + i] = ctx->pages[i];
1008         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1009                                  -1, PAGE_KERNEL);
1010         if (!ctx->buffer)
1011                 goto out_of_memory;
1012
1013         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1014         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1015
1016         for (i = 0; i < AR_BUFFERS; i++) {
1017                 d = &ctx->descriptors[i];
1018                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1019                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1020                                                 DESCRIPTOR_STATUS |
1021                                                 DESCRIPTOR_BRANCH_ALWAYS);
1022                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1023                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1024                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1025         }
1026
1027         return 0;
1028
1029 out_of_memory:
1030         ar_context_release(ctx);
1031
1032         return -ENOMEM;
1033 }
1034
1035 static void ar_context_run(struct ar_context *ctx)
1036 {
1037         unsigned int i;
1038
1039         for (i = 0; i < AR_BUFFERS; i++)
1040                 ar_context_link_page(ctx, i);
1041
1042         ctx->pointer = ctx->buffer;
1043
1044         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1045         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1046 }
1047
1048 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1049 {
1050         __le16 branch;
1051
1052         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1053
1054         /* figure out which descriptor the branch address goes in */
1055         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1056                 return d;
1057         else
1058                 return d + z - 1;
1059 }
1060
1061 static void context_tasklet(unsigned long data)
1062 {
1063         struct context *ctx = (struct context *) data;
1064         struct descriptor *d, *last;
1065         u32 address;
1066         int z;
1067         struct descriptor_buffer *desc;
1068
1069         desc = list_entry(ctx->buffer_list.next,
1070                         struct descriptor_buffer, list);
1071         last = ctx->last;
1072         while (last->branch_address != 0) {
1073                 struct descriptor_buffer *old_desc = desc;
1074                 address = le32_to_cpu(last->branch_address);
1075                 z = address & 0xf;
1076                 address &= ~0xf;
1077                 ctx->current_bus = address;
1078
1079                 /* If the branch address points to a buffer outside of the
1080                  * current buffer, advance to the next buffer. */
1081                 if (address < desc->buffer_bus ||
1082                                 address >= desc->buffer_bus + desc->used)
1083                         desc = list_entry(desc->list.next,
1084                                         struct descriptor_buffer, list);
1085                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1086                 last = find_branch_descriptor(d, z);
1087
1088                 if (!ctx->callback(ctx, d, last))
1089                         break;
1090
1091                 if (old_desc != desc) {
1092                         /* If we've advanced to the next buffer, move the
1093                          * previous buffer to the free list. */
1094                         unsigned long flags;
1095                         old_desc->used = 0;
1096                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1097                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1098                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1099                 }
1100                 ctx->last = last;
1101         }
1102 }
1103
1104 /*
1105  * Allocate a new buffer and add it to the list of free buffers for this
1106  * context.  Must be called with ohci->lock held.
1107  */
1108 static int context_add_buffer(struct context *ctx)
1109 {
1110         struct descriptor_buffer *desc;
1111         dma_addr_t uninitialized_var(bus_addr);
1112         int offset;
1113
1114         /*
1115          * 16MB of descriptors should be far more than enough for any DMA
1116          * program.  This will catch run-away userspace or DoS attacks.
1117          */
1118         if (ctx->total_allocation >= 16*1024*1024)
1119                 return -ENOMEM;
1120
1121         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1122                         &bus_addr, GFP_ATOMIC);
1123         if (!desc)
1124                 return -ENOMEM;
1125
1126         offset = (void *)&desc->buffer - (void *)desc;
1127         desc->buffer_size = PAGE_SIZE - offset;
1128         desc->buffer_bus = bus_addr + offset;
1129         desc->used = 0;
1130
1131         list_add_tail(&desc->list, &ctx->buffer_list);
1132         ctx->total_allocation += PAGE_SIZE;
1133
1134         return 0;
1135 }
1136
1137 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1138                         u32 regs, descriptor_callback_t callback)
1139 {
1140         ctx->ohci = ohci;
1141         ctx->regs = regs;
1142         ctx->total_allocation = 0;
1143
1144         INIT_LIST_HEAD(&ctx->buffer_list);
1145         if (context_add_buffer(ctx) < 0)
1146                 return -ENOMEM;
1147
1148         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1149                         struct descriptor_buffer, list);
1150
1151         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1152         ctx->callback = callback;
1153
1154         /*
1155          * We put a dummy descriptor in the buffer that has a NULL
1156          * branch address and looks like it's been sent.  That way we
1157          * have a descriptor to append DMA programs to.
1158          */
1159         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1160         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1161         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1162         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1163         ctx->last = ctx->buffer_tail->buffer;
1164         ctx->prev = ctx->buffer_tail->buffer;
1165         ctx->prev_z = 1;
1166
1167         return 0;
1168 }
1169
1170 static void context_release(struct context *ctx)
1171 {
1172         struct fw_card *card = &ctx->ohci->card;
1173         struct descriptor_buffer *desc, *tmp;
1174
1175         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1176                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1177                         desc->buffer_bus -
1178                         ((void *)&desc->buffer - (void *)desc));
1179 }
1180
1181 /* Must be called with ohci->lock held */
1182 static struct descriptor *context_get_descriptors(struct context *ctx,
1183                                                   int z, dma_addr_t *d_bus)
1184 {
1185         struct descriptor *d = NULL;
1186         struct descriptor_buffer *desc = ctx->buffer_tail;
1187
1188         if (z * sizeof(*d) > desc->buffer_size)
1189                 return NULL;
1190
1191         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1192                 /* No room for the descriptor in this buffer, so advance to the
1193                  * next one. */
1194
1195                 if (desc->list.next == &ctx->buffer_list) {
1196                         /* If there is no free buffer next in the list,
1197                          * allocate one. */
1198                         if (context_add_buffer(ctx) < 0)
1199                                 return NULL;
1200                 }
1201                 desc = list_entry(desc->list.next,
1202                                 struct descriptor_buffer, list);
1203                 ctx->buffer_tail = desc;
1204         }
1205
1206         d = desc->buffer + desc->used / sizeof(*d);
1207         memset(d, 0, z * sizeof(*d));
1208         *d_bus = desc->buffer_bus + desc->used;
1209
1210         return d;
1211 }
1212
1213 static void context_run(struct context *ctx, u32 extra)
1214 {
1215         struct fw_ohci *ohci = ctx->ohci;
1216
1217         reg_write(ohci, COMMAND_PTR(ctx->regs),
1218                   le32_to_cpu(ctx->last->branch_address));
1219         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1220         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1221         ctx->running = true;
1222         flush_writes(ohci);
1223 }
1224
1225 static void context_append(struct context *ctx,
1226                            struct descriptor *d, int z, int extra)
1227 {
1228         dma_addr_t d_bus;
1229         struct descriptor_buffer *desc = ctx->buffer_tail;
1230         struct descriptor *d_branch;
1231
1232         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1233
1234         desc->used += (z + extra) * sizeof(*d);
1235
1236         wmb(); /* finish init of new descriptors before branch_address update */
1237
1238         d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1239         d_branch->branch_address = cpu_to_le32(d_bus | z);
1240
1241         /*
1242          * VT6306 incorrectly checks only the single descriptor at the
1243          * CommandPtr when the wake bit is written, so if it's a
1244          * multi-descriptor block starting with an INPUT_MORE, put a copy of
1245          * the branch address in the first descriptor.
1246          *
1247          * Not doing this for transmit contexts since not sure how it interacts
1248          * with skip addresses.
1249          */
1250         if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1251             d_branch != ctx->prev &&
1252             (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1253              cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1254                 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1255         }
1256
1257         ctx->prev = d;
1258         ctx->prev_z = z;
1259 }
1260
1261 static void context_stop(struct context *ctx)
1262 {
1263         struct fw_ohci *ohci = ctx->ohci;
1264         u32 reg;
1265         int i;
1266
1267         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1268         ctx->running = false;
1269
1270         for (i = 0; i < 1000; i++) {
1271                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1272                 if ((reg & CONTEXT_ACTIVE) == 0)
1273                         return;
1274
1275                 if (i)
1276                         udelay(10);
1277         }
1278         ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1279 }
1280
1281 struct driver_data {
1282         u8 inline_data[8];
1283         struct fw_packet *packet;
1284 };
1285
1286 /*
1287  * This function apppends a packet to the DMA queue for transmission.
1288  * Must always be called with the ochi->lock held to ensure proper
1289  * generation handling and locking around packet queue manipulation.
1290  */
1291 static int at_context_queue_packet(struct context *ctx,
1292                                    struct fw_packet *packet)
1293 {
1294         struct fw_ohci *ohci = ctx->ohci;
1295         dma_addr_t d_bus, uninitialized_var(payload_bus);
1296         struct driver_data *driver_data;
1297         struct descriptor *d, *last;
1298         __le32 *header;
1299         int z, tcode;
1300
1301         d = context_get_descriptors(ctx, 4, &d_bus);
1302         if (d == NULL) {
1303                 packet->ack = RCODE_SEND_ERROR;
1304                 return -1;
1305         }
1306
1307         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1308         d[0].res_count = cpu_to_le16(packet->timestamp);
1309
1310         /*
1311          * The DMA format for asynchronous link packets is different
1312          * from the IEEE1394 layout, so shift the fields around
1313          * accordingly.
1314          */
1315
1316         tcode = (packet->header[0] >> 4) & 0x0f;
1317         header = (__le32 *) &d[1];
1318         switch (tcode) {
1319         case TCODE_WRITE_QUADLET_REQUEST:
1320         case TCODE_WRITE_BLOCK_REQUEST:
1321         case TCODE_WRITE_RESPONSE:
1322         case TCODE_READ_QUADLET_REQUEST:
1323         case TCODE_READ_BLOCK_REQUEST:
1324         case TCODE_READ_QUADLET_RESPONSE:
1325         case TCODE_READ_BLOCK_RESPONSE:
1326         case TCODE_LOCK_REQUEST:
1327         case TCODE_LOCK_RESPONSE:
1328                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1329                                         (packet->speed << 16));
1330                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1331                                         (packet->header[0] & 0xffff0000));
1332                 header[2] = cpu_to_le32(packet->header[2]);
1333
1334                 if (TCODE_IS_BLOCK_PACKET(tcode))
1335                         header[3] = cpu_to_le32(packet->header[3]);
1336                 else
1337                         header[3] = (__force __le32) packet->header[3];
1338
1339                 d[0].req_count = cpu_to_le16(packet->header_length);
1340                 break;
1341
1342         case TCODE_LINK_INTERNAL:
1343                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1344                                         (packet->speed << 16));
1345                 header[1] = cpu_to_le32(packet->header[1]);
1346                 header[2] = cpu_to_le32(packet->header[2]);
1347                 d[0].req_count = cpu_to_le16(12);
1348
1349                 if (is_ping_packet(&packet->header[1]))
1350                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1351                 break;
1352
1353         case TCODE_STREAM_DATA:
1354                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1355                                         (packet->speed << 16));
1356                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1357                 d[0].req_count = cpu_to_le16(8);
1358                 break;
1359
1360         default:
1361                 /* BUG(); */
1362                 packet->ack = RCODE_SEND_ERROR;
1363                 return -1;
1364         }
1365
1366         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1367         driver_data = (struct driver_data *) &d[3];
1368         driver_data->packet = packet;
1369         packet->driver_data = driver_data;
1370
1371         if (packet->payload_length > 0) {
1372                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1373                         payload_bus = dma_map_single(ohci->card.device,
1374                                                      packet->payload,
1375                                                      packet->payload_length,
1376                                                      DMA_TO_DEVICE);
1377                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1378                                 packet->ack = RCODE_SEND_ERROR;
1379                                 return -1;
1380                         }
1381                         packet->payload_bus     = payload_bus;
1382                         packet->payload_mapped  = true;
1383                 } else {
1384                         memcpy(driver_data->inline_data, packet->payload,
1385                                packet->payload_length);
1386                         payload_bus = d_bus + 3 * sizeof(*d);
1387                 }
1388
1389                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1390                 d[2].data_address = cpu_to_le32(payload_bus);
1391                 last = &d[2];
1392                 z = 3;
1393         } else {
1394                 last = &d[0];
1395                 z = 2;
1396         }
1397
1398         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1399                                      DESCRIPTOR_IRQ_ALWAYS |
1400                                      DESCRIPTOR_BRANCH_ALWAYS);
1401
1402         /* FIXME: Document how the locking works. */
1403         if (ohci->generation != packet->generation) {
1404                 if (packet->payload_mapped)
1405                         dma_unmap_single(ohci->card.device, payload_bus,
1406                                          packet->payload_length, DMA_TO_DEVICE);
1407                 packet->ack = RCODE_GENERATION;
1408                 return -1;
1409         }
1410
1411         context_append(ctx, d, z, 4 - z);
1412
1413         if (ctx->running)
1414                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1415         else
1416                 context_run(ctx, 0);
1417
1418         return 0;
1419 }
1420
1421 static void at_context_flush(struct context *ctx)
1422 {
1423         tasklet_disable(&ctx->tasklet);
1424
1425         ctx->flushing = true;
1426         context_tasklet((unsigned long)ctx);
1427         ctx->flushing = false;
1428
1429         tasklet_enable(&ctx->tasklet);
1430 }
1431
1432 static int handle_at_packet(struct context *context,
1433                             struct descriptor *d,
1434                             struct descriptor *last)
1435 {
1436         struct driver_data *driver_data;
1437         struct fw_packet *packet;
1438         struct fw_ohci *ohci = context->ohci;
1439         int evt;
1440
1441         if (last->transfer_status == 0 && !context->flushing)
1442                 /* This descriptor isn't done yet, stop iteration. */
1443                 return 0;
1444
1445         driver_data = (struct driver_data *) &d[3];
1446         packet = driver_data->packet;
1447         if (packet == NULL)
1448                 /* This packet was cancelled, just continue. */
1449                 return 1;
1450
1451         if (packet->payload_mapped)
1452                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1453                                  packet->payload_length, DMA_TO_DEVICE);
1454
1455         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1456         packet->timestamp = le16_to_cpu(last->res_count);
1457
1458         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1459
1460         switch (evt) {
1461         case OHCI1394_evt_timeout:
1462                 /* Async response transmit timed out. */
1463                 packet->ack = RCODE_CANCELLED;
1464                 break;
1465
1466         case OHCI1394_evt_flushed:
1467                 /*
1468                  * The packet was flushed should give same error as
1469                  * when we try to use a stale generation count.
1470                  */
1471                 packet->ack = RCODE_GENERATION;
1472                 break;
1473
1474         case OHCI1394_evt_missing_ack:
1475                 if (context->flushing)
1476                         packet->ack = RCODE_GENERATION;
1477                 else {
1478                         /*
1479                          * Using a valid (current) generation count, but the
1480                          * node is not on the bus or not sending acks.
1481                          */
1482                         packet->ack = RCODE_NO_ACK;
1483                 }
1484                 break;
1485
1486         case ACK_COMPLETE + 0x10:
1487         case ACK_PENDING + 0x10:
1488         case ACK_BUSY_X + 0x10:
1489         case ACK_BUSY_A + 0x10:
1490         case ACK_BUSY_B + 0x10:
1491         case ACK_DATA_ERROR + 0x10:
1492         case ACK_TYPE_ERROR + 0x10:
1493                 packet->ack = evt - 0x10;
1494                 break;
1495
1496         case OHCI1394_evt_no_status:
1497                 if (context->flushing) {
1498                         packet->ack = RCODE_GENERATION;
1499                         break;
1500                 }
1501                 /* fall through */
1502
1503         default:
1504                 packet->ack = RCODE_SEND_ERROR;
1505                 break;
1506         }
1507
1508         packet->callback(packet, &ohci->card, packet->ack);
1509
1510         return 1;
1511 }
1512
1513 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1514 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1515 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1516 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1517 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1518
1519 static void handle_local_rom(struct fw_ohci *ohci,
1520                              struct fw_packet *packet, u32 csr)
1521 {
1522         struct fw_packet response;
1523         int tcode, length, i;
1524
1525         tcode = HEADER_GET_TCODE(packet->header[0]);
1526         if (TCODE_IS_BLOCK_PACKET(tcode))
1527                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1528         else
1529                 length = 4;
1530
1531         i = csr - CSR_CONFIG_ROM;
1532         if (i + length > CONFIG_ROM_SIZE) {
1533                 fw_fill_response(&response, packet->header,
1534                                  RCODE_ADDRESS_ERROR, NULL, 0);
1535         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1536                 fw_fill_response(&response, packet->header,
1537                                  RCODE_TYPE_ERROR, NULL, 0);
1538         } else {
1539                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1540                                  (void *) ohci->config_rom + i, length);
1541         }
1542
1543         fw_core_handle_response(&ohci->card, &response);
1544 }
1545
1546 static void handle_local_lock(struct fw_ohci *ohci,
1547                               struct fw_packet *packet, u32 csr)
1548 {
1549         struct fw_packet response;
1550         int tcode, length, ext_tcode, sel, try;
1551         __be32 *payload, lock_old;
1552         u32 lock_arg, lock_data;
1553
1554         tcode = HEADER_GET_TCODE(packet->header[0]);
1555         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1556         payload = packet->payload;
1557         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1558
1559         if (tcode == TCODE_LOCK_REQUEST &&
1560             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1561                 lock_arg = be32_to_cpu(payload[0]);
1562                 lock_data = be32_to_cpu(payload[1]);
1563         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1564                 lock_arg = 0;
1565                 lock_data = 0;
1566         } else {
1567                 fw_fill_response(&response, packet->header,
1568                                  RCODE_TYPE_ERROR, NULL, 0);
1569                 goto out;
1570         }
1571
1572         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1573         reg_write(ohci, OHCI1394_CSRData, lock_data);
1574         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1575         reg_write(ohci, OHCI1394_CSRControl, sel);
1576
1577         for (try = 0; try < 20; try++)
1578                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1579                         lock_old = cpu_to_be32(reg_read(ohci,
1580                                                         OHCI1394_CSRData));
1581                         fw_fill_response(&response, packet->header,
1582                                          RCODE_COMPLETE,
1583                                          &lock_old, sizeof(lock_old));
1584                         goto out;
1585                 }
1586
1587         ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1588         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1589
1590  out:
1591         fw_core_handle_response(&ohci->card, &response);
1592 }
1593
1594 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1595 {
1596         u64 offset, csr;
1597
1598         if (ctx == &ctx->ohci->at_request_ctx) {
1599                 packet->ack = ACK_PENDING;
1600                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1601         }
1602
1603         offset =
1604                 ((unsigned long long)
1605                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1606                 packet->header[2];
1607         csr = offset - CSR_REGISTER_BASE;
1608
1609         /* Handle config rom reads. */
1610         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1611                 handle_local_rom(ctx->ohci, packet, csr);
1612         else switch (csr) {
1613         case CSR_BUS_MANAGER_ID:
1614         case CSR_BANDWIDTH_AVAILABLE:
1615         case CSR_CHANNELS_AVAILABLE_HI:
1616         case CSR_CHANNELS_AVAILABLE_LO:
1617                 handle_local_lock(ctx->ohci, packet, csr);
1618                 break;
1619         default:
1620                 if (ctx == &ctx->ohci->at_request_ctx)
1621                         fw_core_handle_request(&ctx->ohci->card, packet);
1622                 else
1623                         fw_core_handle_response(&ctx->ohci->card, packet);
1624                 break;
1625         }
1626
1627         if (ctx == &ctx->ohci->at_response_ctx) {
1628                 packet->ack = ACK_COMPLETE;
1629                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1630         }
1631 }
1632
1633 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1634 {
1635         unsigned long flags;
1636         int ret;
1637
1638         spin_lock_irqsave(&ctx->ohci->lock, flags);
1639
1640         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1641             ctx->ohci->generation == packet->generation) {
1642                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1643                 handle_local_request(ctx, packet);
1644                 return;
1645         }
1646
1647         ret = at_context_queue_packet(ctx, packet);
1648         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1649
1650         if (ret < 0)
1651                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1652
1653 }
1654
1655 static void detect_dead_context(struct fw_ohci *ohci,
1656                                 const char *name, unsigned int regs)
1657 {
1658         u32 ctl;
1659
1660         ctl = reg_read(ohci, CONTROL_SET(regs));
1661         if (ctl & CONTEXT_DEAD)
1662                 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1663                         name, evts[ctl & 0x1f]);
1664 }
1665
1666 static void handle_dead_contexts(struct fw_ohci *ohci)
1667 {
1668         unsigned int i;
1669         char name[8];
1670
1671         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1672         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1673         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1674         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1675         for (i = 0; i < 32; ++i) {
1676                 if (!(ohci->it_context_support & (1 << i)))
1677                         continue;
1678                 sprintf(name, "IT%u", i);
1679                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1680         }
1681         for (i = 0; i < 32; ++i) {
1682                 if (!(ohci->ir_context_support & (1 << i)))
1683                         continue;
1684                 sprintf(name, "IR%u", i);
1685                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1686         }
1687         /* TODO: maybe try to flush and restart the dead contexts */
1688 }
1689
1690 static u32 cycle_timer_ticks(u32 cycle_timer)
1691 {
1692         u32 ticks;
1693
1694         ticks = cycle_timer & 0xfff;
1695         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1696         ticks += (3072 * 8000) * (cycle_timer >> 25);
1697
1698         return ticks;
1699 }
1700
1701 /*
1702  * Some controllers exhibit one or more of the following bugs when updating the
1703  * iso cycle timer register:
1704  *  - When the lowest six bits are wrapping around to zero, a read that happens
1705  *    at the same time will return garbage in the lowest ten bits.
1706  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1707  *    not incremented for about 60 ns.
1708  *  - Occasionally, the entire register reads zero.
1709  *
1710  * To catch these, we read the register three times and ensure that the
1711  * difference between each two consecutive reads is approximately the same, i.e.
1712  * less than twice the other.  Furthermore, any negative difference indicates an
1713  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1714  * execute, so we have enough precision to compute the ratio of the differences.)
1715  */
1716 static u32 get_cycle_time(struct fw_ohci *ohci)
1717 {
1718         u32 c0, c1, c2;
1719         u32 t0, t1, t2;
1720         s32 diff01, diff12;
1721         int i;
1722
1723         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1724
1725         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1726                 i = 0;
1727                 c1 = c2;
1728                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1729                 do {
1730                         c0 = c1;
1731                         c1 = c2;
1732                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1733                         t0 = cycle_timer_ticks(c0);
1734                         t1 = cycle_timer_ticks(c1);
1735                         t2 = cycle_timer_ticks(c2);
1736                         diff01 = t1 - t0;
1737                         diff12 = t2 - t1;
1738                 } while ((diff01 <= 0 || diff12 <= 0 ||
1739                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1740                          && i++ < 20);
1741         }
1742
1743         return c2;
1744 }
1745
1746 /*
1747  * This function has to be called at least every 64 seconds.  The bus_time
1748  * field stores not only the upper 25 bits of the BUS_TIME register but also
1749  * the most significant bit of the cycle timer in bit 6 so that we can detect
1750  * changes in this bit.
1751  */
1752 static u32 update_bus_time(struct fw_ohci *ohci)
1753 {
1754         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1755
1756         if (unlikely(!ohci->bus_time_running)) {
1757                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1758                 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1759                                  (cycle_time_seconds & 0x40);
1760                 ohci->bus_time_running = true;
1761         }
1762
1763         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1764                 ohci->bus_time += 0x40;
1765
1766         return ohci->bus_time | cycle_time_seconds;
1767 }
1768
1769 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1770 {
1771         int reg;
1772
1773         mutex_lock(&ohci->phy_reg_mutex);
1774         reg = write_phy_reg(ohci, 7, port_index);
1775         if (reg >= 0)
1776                 reg = read_phy_reg(ohci, 8);
1777         mutex_unlock(&ohci->phy_reg_mutex);
1778         if (reg < 0)
1779                 return reg;
1780
1781         switch (reg & 0x0f) {
1782         case 0x06:
1783                 return 2;       /* is child node (connected to parent node) */
1784         case 0x0e:
1785                 return 3;       /* is parent node (connected to child node) */
1786         }
1787         return 1;               /* not connected */
1788 }
1789
1790 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1791         int self_id_count)
1792 {
1793         int i;
1794         u32 entry;
1795
1796         for (i = 0; i < self_id_count; i++) {
1797                 entry = ohci->self_id_buffer[i];
1798                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1799                         return -1;
1800                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1801                         return i;
1802         }
1803         return i;
1804 }
1805
1806 static int initiated_reset(struct fw_ohci *ohci)
1807 {
1808         int reg;
1809         int ret = 0;
1810
1811         mutex_lock(&ohci->phy_reg_mutex);
1812         reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1813         if (reg >= 0) {
1814                 reg = read_phy_reg(ohci, 8);
1815                 reg |= 0x40;
1816                 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1817                 if (reg >= 0) {
1818                         reg = read_phy_reg(ohci, 12); /* read register 12 */
1819                         if (reg >= 0) {
1820                                 if ((reg & 0x08) == 0x08) {
1821                                         /* bit 3 indicates "initiated reset" */
1822                                         ret = 0x2;
1823                                 }
1824                         }
1825                 }
1826         }
1827         mutex_unlock(&ohci->phy_reg_mutex);
1828         return ret;
1829 }
1830
1831 /*
1832  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1833  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1834  * Construct the selfID from phy register contents.
1835  */
1836 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1837 {
1838         int reg, i, pos, status;
1839         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1840         u32 self_id = 0x8040c800;
1841
1842         reg = reg_read(ohci, OHCI1394_NodeID);
1843         if (!(reg & OHCI1394_NodeID_idValid)) {
1844                 ohci_notice(ohci,
1845                             "node ID not valid, new bus reset in progress\n");
1846                 return -EBUSY;
1847         }
1848         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1849
1850         reg = ohci_read_phy_reg(&ohci->card, 4);
1851         if (reg < 0)
1852                 return reg;
1853         self_id |= ((reg & 0x07) << 8); /* power class */
1854
1855         reg = ohci_read_phy_reg(&ohci->card, 1);
1856         if (reg < 0)
1857                 return reg;
1858         self_id |= ((reg & 0x3f) << 16); /* gap count */
1859
1860         for (i = 0; i < 3; i++) {
1861                 status = get_status_for_port(ohci, i);
1862                 if (status < 0)
1863                         return status;
1864                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1865         }
1866
1867         self_id |= initiated_reset(ohci);
1868
1869         pos = get_self_id_pos(ohci, self_id, self_id_count);
1870         if (pos >= 0) {
1871                 memmove(&(ohci->self_id_buffer[pos+1]),
1872                         &(ohci->self_id_buffer[pos]),
1873                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1874                 ohci->self_id_buffer[pos] = self_id;
1875                 self_id_count++;
1876         }
1877         return self_id_count;
1878 }
1879
1880 static void bus_reset_work(struct work_struct *work)
1881 {
1882         struct fw_ohci *ohci =
1883                 container_of(work, struct fw_ohci, bus_reset_work);
1884         int self_id_count, generation, new_generation, i, j;
1885         u32 reg;
1886         void *free_rom = NULL;
1887         dma_addr_t free_rom_bus = 0;
1888         bool is_new_root;
1889
1890         reg = reg_read(ohci, OHCI1394_NodeID);
1891         if (!(reg & OHCI1394_NodeID_idValid)) {
1892                 ohci_notice(ohci,
1893                             "node ID not valid, new bus reset in progress\n");
1894                 return;
1895         }
1896         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1897                 ohci_notice(ohci, "malconfigured bus\n");
1898                 return;
1899         }
1900         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1901                                OHCI1394_NodeID_nodeNumber);
1902
1903         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1904         if (!(ohci->is_root && is_new_root))
1905                 reg_write(ohci, OHCI1394_LinkControlSet,
1906                           OHCI1394_LinkControl_cycleMaster);
1907         ohci->is_root = is_new_root;
1908
1909         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1910         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1911                 ohci_notice(ohci, "self ID receive error\n");
1912                 return;
1913         }
1914         /*
1915          * The count in the SelfIDCount register is the number of
1916          * bytes in the self ID receive buffer.  Since we also receive
1917          * the inverted quadlets and a header quadlet, we shift one
1918          * bit extra to get the actual number of self IDs.
1919          */
1920         self_id_count = (reg >> 3) & 0xff;
1921
1922         if (self_id_count > 252) {
1923                 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1924                 return;
1925         }
1926
1927         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1928         rmb();
1929
1930         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1931                 u32 id  = cond_le32_to_cpu(ohci->self_id_cpu[i]);
1932                 u32 id2 = cond_le32_to_cpu(ohci->self_id_cpu[i + 1]);
1933
1934                 if (id != ~id2) {
1935                         /*
1936                          * If the invalid data looks like a cycle start packet,
1937                          * it's likely to be the result of the cycle master
1938                          * having a wrong gap count.  In this case, the self IDs
1939                          * so far are valid and should be processed so that the
1940                          * bus manager can then correct the gap count.
1941                          */
1942                         if (id == 0xffff008f) {
1943                                 ohci_notice(ohci, "ignoring spurious self IDs\n");
1944                                 self_id_count = j;
1945                                 break;
1946                         }
1947
1948                         ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1949                                     j, self_id_count, id, id2);
1950                         return;
1951                 }
1952                 ohci->self_id_buffer[j] = id;
1953         }
1954
1955         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1956                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1957                 if (self_id_count < 0) {
1958                         ohci_notice(ohci,
1959                                     "could not construct local self ID\n");
1960                         return;
1961                 }
1962         }
1963
1964         if (self_id_count == 0) {
1965                 ohci_notice(ohci, "no self IDs\n");
1966                 return;
1967         }
1968         rmb();
1969
1970         /*
1971          * Check the consistency of the self IDs we just read.  The
1972          * problem we face is that a new bus reset can start while we
1973          * read out the self IDs from the DMA buffer. If this happens,
1974          * the DMA buffer will be overwritten with new self IDs and we
1975          * will read out inconsistent data.  The OHCI specification
1976          * (section 11.2) recommends a technique similar to
1977          * linux/seqlock.h, where we remember the generation of the
1978          * self IDs in the buffer before reading them out and compare
1979          * it to the current generation after reading them out.  If
1980          * the two generations match we know we have a consistent set
1981          * of self IDs.
1982          */
1983
1984         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1985         if (new_generation != generation) {
1986                 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1987                 return;
1988         }
1989
1990         /* FIXME: Document how the locking works. */
1991         spin_lock_irq(&ohci->lock);
1992
1993         ohci->generation = -1; /* prevent AT packet queueing */
1994         context_stop(&ohci->at_request_ctx);
1995         context_stop(&ohci->at_response_ctx);
1996
1997         spin_unlock_irq(&ohci->lock);
1998
1999         /*
2000          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2001          * packets in the AT queues and software needs to drain them.
2002          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2003          */
2004         at_context_flush(&ohci->at_request_ctx);
2005         at_context_flush(&ohci->at_response_ctx);
2006
2007         spin_lock_irq(&ohci->lock);
2008
2009         ohci->generation = generation;
2010         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2011
2012         if (ohci->quirks & QUIRK_RESET_PACKET)
2013                 ohci->request_generation = generation;
2014
2015         /*
2016          * This next bit is unrelated to the AT context stuff but we
2017          * have to do it under the spinlock also.  If a new config rom
2018          * was set up before this reset, the old one is now no longer
2019          * in use and we can free it. Update the config rom pointers
2020          * to point to the current config rom and clear the
2021          * next_config_rom pointer so a new update can take place.
2022          */
2023
2024         if (ohci->next_config_rom != NULL) {
2025                 if (ohci->next_config_rom != ohci->config_rom) {
2026                         free_rom      = ohci->config_rom;
2027                         free_rom_bus  = ohci->config_rom_bus;
2028                 }
2029                 ohci->config_rom      = ohci->next_config_rom;
2030                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
2031                 ohci->next_config_rom = NULL;
2032
2033                 /*
2034                  * Restore config_rom image and manually update
2035                  * config_rom registers.  Writing the header quadlet
2036                  * will indicate that the config rom is ready, so we
2037                  * do that last.
2038                  */
2039                 reg_write(ohci, OHCI1394_BusOptions,
2040                           be32_to_cpu(ohci->config_rom[2]));
2041                 ohci->config_rom[0] = ohci->next_header;
2042                 reg_write(ohci, OHCI1394_ConfigROMhdr,
2043                           be32_to_cpu(ohci->next_header));
2044         }
2045
2046 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2047         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2048         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2049 #endif
2050
2051         spin_unlock_irq(&ohci->lock);
2052
2053         if (free_rom)
2054                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2055                                   free_rom, free_rom_bus);
2056
2057         log_selfids(ohci, generation, self_id_count);
2058
2059         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2060                                  self_id_count, ohci->self_id_buffer,
2061                                  ohci->csr_state_setclear_abdicate);
2062         ohci->csr_state_setclear_abdicate = false;
2063 }
2064
2065 static irqreturn_t irq_handler(int irq, void *data)
2066 {
2067         struct fw_ohci *ohci = data;
2068         u32 event, iso_event;
2069         int i;
2070
2071         event = reg_read(ohci, OHCI1394_IntEventClear);
2072
2073         if (!event || !~event)
2074                 return IRQ_NONE;
2075
2076         /*
2077          * busReset and postedWriteErr must not be cleared yet
2078          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2079          */
2080         reg_write(ohci, OHCI1394_IntEventClear,
2081                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2082         log_irqs(ohci, event);
2083
2084         if (event & OHCI1394_selfIDComplete)
2085                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2086
2087         if (event & OHCI1394_RQPkt)
2088                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2089
2090         if (event & OHCI1394_RSPkt)
2091                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2092
2093         if (event & OHCI1394_reqTxComplete)
2094                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2095
2096         if (event & OHCI1394_respTxComplete)
2097                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2098
2099         if (event & OHCI1394_isochRx) {
2100                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2101                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2102
2103                 while (iso_event) {
2104                         i = ffs(iso_event) - 1;
2105                         tasklet_schedule(
2106                                 &ohci->ir_context_list[i].context.tasklet);
2107                         iso_event &= ~(1 << i);
2108                 }
2109         }
2110
2111         if (event & OHCI1394_isochTx) {
2112                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2113                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2114
2115                 while (iso_event) {
2116                         i = ffs(iso_event) - 1;
2117                         tasklet_schedule(
2118                                 &ohci->it_context_list[i].context.tasklet);
2119                         iso_event &= ~(1 << i);
2120                 }
2121         }
2122
2123         if (unlikely(event & OHCI1394_regAccessFail))
2124                 ohci_err(ohci, "register access failure\n");
2125
2126         if (unlikely(event & OHCI1394_postedWriteErr)) {
2127                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2128                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2129                 reg_write(ohci, OHCI1394_IntEventClear,
2130                           OHCI1394_postedWriteErr);
2131                 if (printk_ratelimit())
2132                         ohci_err(ohci, "PCI posted write error\n");
2133         }
2134
2135         if (unlikely(event & OHCI1394_cycleTooLong)) {
2136                 if (printk_ratelimit())
2137                         ohci_notice(ohci, "isochronous cycle too long\n");
2138                 reg_write(ohci, OHCI1394_LinkControlSet,
2139                           OHCI1394_LinkControl_cycleMaster);
2140         }
2141
2142         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2143                 /*
2144                  * We need to clear this event bit in order to make
2145                  * cycleMatch isochronous I/O work.  In theory we should
2146                  * stop active cycleMatch iso contexts now and restart
2147                  * them at least two cycles later.  (FIXME?)
2148                  */
2149                 if (printk_ratelimit())
2150                         ohci_notice(ohci, "isochronous cycle inconsistent\n");
2151         }
2152
2153         if (unlikely(event & OHCI1394_unrecoverableError))
2154                 handle_dead_contexts(ohci);
2155
2156         if (event & OHCI1394_cycle64Seconds) {
2157                 spin_lock(&ohci->lock);
2158                 update_bus_time(ohci);
2159                 spin_unlock(&ohci->lock);
2160         } else
2161                 flush_writes(ohci);
2162
2163         return IRQ_HANDLED;
2164 }
2165
2166 static int software_reset(struct fw_ohci *ohci)
2167 {
2168         u32 val;
2169         int i;
2170
2171         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2172         for (i = 0; i < 500; i++) {
2173                 val = reg_read(ohci, OHCI1394_HCControlSet);
2174                 if (!~val)
2175                         return -ENODEV; /* Card was ejected. */
2176
2177                 if (!(val & OHCI1394_HCControl_softReset))
2178                         return 0;
2179
2180                 msleep(1);
2181         }
2182
2183         return -EBUSY;
2184 }
2185
2186 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2187 {
2188         size_t size = length * 4;
2189
2190         memcpy(dest, src, size);
2191         if (size < CONFIG_ROM_SIZE)
2192                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2193 }
2194
2195 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2196 {
2197         bool enable_1394a;
2198         int ret, clear, set, offset;
2199
2200         /* Check if the driver should configure link and PHY. */
2201         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2202               OHCI1394_HCControl_programPhyEnable))
2203                 return 0;
2204
2205         /* Paranoia: check whether the PHY supports 1394a, too. */
2206         enable_1394a = false;
2207         ret = read_phy_reg(ohci, 2);
2208         if (ret < 0)
2209                 return ret;
2210         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2211                 ret = read_paged_phy_reg(ohci, 1, 8);
2212                 if (ret < 0)
2213                         return ret;
2214                 if (ret >= 1)
2215                         enable_1394a = true;
2216         }
2217
2218         if (ohci->quirks & QUIRK_NO_1394A)
2219                 enable_1394a = false;
2220
2221         /* Configure PHY and link consistently. */
2222         if (enable_1394a) {
2223                 clear = 0;
2224                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2225         } else {
2226                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2227                 set = 0;
2228         }
2229         ret = update_phy_reg(ohci, 5, clear, set);
2230         if (ret < 0)
2231                 return ret;
2232
2233         if (enable_1394a)
2234                 offset = OHCI1394_HCControlSet;
2235         else
2236                 offset = OHCI1394_HCControlClear;
2237         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2238
2239         /* Clean up: configuration has been taken care of. */
2240         reg_write(ohci, OHCI1394_HCControlClear,
2241                   OHCI1394_HCControl_programPhyEnable);
2242
2243         return 0;
2244 }
2245
2246 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2247 {
2248         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2249         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2250         int reg, i;
2251
2252         reg = read_phy_reg(ohci, 2);
2253         if (reg < 0)
2254                 return reg;
2255         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2256                 return 0;
2257
2258         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2259                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2260                 if (reg < 0)
2261                         return reg;
2262                 if (reg != id[i])
2263                         return 0;
2264         }
2265         return 1;
2266 }
2267
2268 static int ohci_enable(struct fw_card *card,
2269                        const __be32 *config_rom, size_t length)
2270 {
2271         struct fw_ohci *ohci = fw_ohci(card);
2272         u32 lps, version, irqs;
2273         int i, ret;
2274
2275         if (software_reset(ohci)) {
2276                 ohci_err(ohci, "failed to reset ohci card\n");
2277                 return -EBUSY;
2278         }
2279
2280         /*
2281          * Now enable LPS, which we need in order to start accessing
2282          * most of the registers.  In fact, on some cards (ALI M5251),
2283          * accessing registers in the SClk domain without LPS enabled
2284          * will lock up the machine.  Wait 50msec to make sure we have
2285          * full link enabled.  However, with some cards (well, at least
2286          * a JMicron PCIe card), we have to try again sometimes.
2287          *
2288          * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2289          * cannot actually use the phy at that time.  These need tens of
2290          * millisecods pause between LPS write and first phy access too.
2291          */
2292
2293         reg_write(ohci, OHCI1394_HCControlSet,
2294                   OHCI1394_HCControl_LPS |
2295                   OHCI1394_HCControl_postedWriteEnable);
2296         flush_writes(ohci);
2297
2298         for (lps = 0, i = 0; !lps && i < 3; i++) {
2299                 msleep(50);
2300                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2301                       OHCI1394_HCControl_LPS;
2302         }
2303
2304         if (!lps) {
2305                 ohci_err(ohci, "failed to set Link Power Status\n");
2306                 return -EIO;
2307         }
2308
2309         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2310                 ret = probe_tsb41ba3d(ohci);
2311                 if (ret < 0)
2312                         return ret;
2313                 if (ret)
2314                         ohci_notice(ohci, "local TSB41BA3D phy\n");
2315                 else
2316                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2317         }
2318
2319         reg_write(ohci, OHCI1394_HCControlClear,
2320                   OHCI1394_HCControl_noByteSwapData);
2321
2322         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2323         reg_write(ohci, OHCI1394_LinkControlSet,
2324                   OHCI1394_LinkControl_cycleTimerEnable |
2325                   OHCI1394_LinkControl_cycleMaster);
2326
2327         reg_write(ohci, OHCI1394_ATRetries,
2328                   OHCI1394_MAX_AT_REQ_RETRIES |
2329                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2330                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2331                   (200 << 16));
2332
2333         ohci->bus_time_running = false;
2334
2335         for (i = 0; i < 32; i++)
2336                 if (ohci->ir_context_support & (1 << i))
2337                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2338                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2339
2340         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2341         if (version >= OHCI_VERSION_1_1) {
2342                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2343                           0xfffffffe);
2344                 card->broadcast_channel_auto_allocated = true;
2345         }
2346
2347         /* Get implemented bits of the priority arbitration request counter. */
2348         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2349         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2350         reg_write(ohci, OHCI1394_FairnessControl, 0);
2351         card->priority_budget_implemented = ohci->pri_req_max != 0;
2352
2353         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2354         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2355         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2356
2357         ret = configure_1394a_enhancements(ohci);
2358         if (ret < 0)
2359                 return ret;
2360
2361         /* Activate link_on bit and contender bit in our self ID packets.*/
2362         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2363         if (ret < 0)
2364                 return ret;
2365
2366         /*
2367          * When the link is not yet enabled, the atomic config rom
2368          * update mechanism described below in ohci_set_config_rom()
2369          * is not active.  We have to update ConfigRomHeader and
2370          * BusOptions manually, and the write to ConfigROMmap takes
2371          * effect immediately.  We tie this to the enabling of the
2372          * link, so we have a valid config rom before enabling - the
2373          * OHCI requires that ConfigROMhdr and BusOptions have valid
2374          * values before enabling.
2375          *
2376          * However, when the ConfigROMmap is written, some controllers
2377          * always read back quadlets 0 and 2 from the config rom to
2378          * the ConfigRomHeader and BusOptions registers on bus reset.
2379          * They shouldn't do that in this initial case where the link
2380          * isn't enabled.  This means we have to use the same
2381          * workaround here, setting the bus header to 0 and then write
2382          * the right values in the bus reset tasklet.
2383          */
2384
2385         if (config_rom) {
2386                 ohci->next_config_rom =
2387                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2388                                            &ohci->next_config_rom_bus,
2389                                            GFP_KERNEL);
2390                 if (ohci->next_config_rom == NULL)
2391                         return -ENOMEM;
2392
2393                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2394         } else {
2395                 /*
2396                  * In the suspend case, config_rom is NULL, which
2397                  * means that we just reuse the old config rom.
2398                  */
2399                 ohci->next_config_rom = ohci->config_rom;
2400                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2401         }
2402
2403         ohci->next_header = ohci->next_config_rom[0];
2404         ohci->next_config_rom[0] = 0;
2405         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2406         reg_write(ohci, OHCI1394_BusOptions,
2407                   be32_to_cpu(ohci->next_config_rom[2]));
2408         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2409
2410         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2411
2412         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2413                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2414                 OHCI1394_isochTx | OHCI1394_isochRx |
2415                 OHCI1394_postedWriteErr |
2416                 OHCI1394_selfIDComplete |
2417                 OHCI1394_regAccessFail |
2418                 OHCI1394_cycleInconsistent |
2419                 OHCI1394_unrecoverableError |
2420                 OHCI1394_cycleTooLong |
2421                 OHCI1394_masterIntEnable;
2422         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2423                 irqs |= OHCI1394_busReset;
2424         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2425
2426         reg_write(ohci, OHCI1394_HCControlSet,
2427                   OHCI1394_HCControl_linkEnable |
2428                   OHCI1394_HCControl_BIBimageValid);
2429
2430         reg_write(ohci, OHCI1394_LinkControlSet,
2431                   OHCI1394_LinkControl_rcvSelfID |
2432                   OHCI1394_LinkControl_rcvPhyPkt);
2433
2434         ar_context_run(&ohci->ar_request_ctx);
2435         ar_context_run(&ohci->ar_response_ctx);
2436
2437         flush_writes(ohci);
2438
2439         /* We are ready to go, reset bus to finish initialization. */
2440         fw_schedule_bus_reset(&ohci->card, false, true);
2441
2442         return 0;
2443 }
2444
2445 static int ohci_set_config_rom(struct fw_card *card,
2446                                const __be32 *config_rom, size_t length)
2447 {
2448         struct fw_ohci *ohci;
2449         __be32 *next_config_rom;
2450         dma_addr_t uninitialized_var(next_config_rom_bus);
2451
2452         ohci = fw_ohci(card);
2453
2454         /*
2455          * When the OHCI controller is enabled, the config rom update
2456          * mechanism is a bit tricky, but easy enough to use.  See
2457          * section 5.5.6 in the OHCI specification.
2458          *
2459          * The OHCI controller caches the new config rom address in a
2460          * shadow register (ConfigROMmapNext) and needs a bus reset
2461          * for the changes to take place.  When the bus reset is
2462          * detected, the controller loads the new values for the
2463          * ConfigRomHeader and BusOptions registers from the specified
2464          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2465          * shadow register. All automatically and atomically.
2466          *
2467          * Now, there's a twist to this story.  The automatic load of
2468          * ConfigRomHeader and BusOptions doesn't honor the
2469          * noByteSwapData bit, so with a be32 config rom, the
2470          * controller will load be32 values in to these registers
2471          * during the atomic update, even on litte endian
2472          * architectures.  The workaround we use is to put a 0 in the
2473          * header quadlet; 0 is endian agnostic and means that the
2474          * config rom isn't ready yet.  In the bus reset tasklet we
2475          * then set up the real values for the two registers.
2476          *
2477          * We use ohci->lock to avoid racing with the code that sets
2478          * ohci->next_config_rom to NULL (see bus_reset_work).
2479          */
2480
2481         next_config_rom =
2482                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2483                                    &next_config_rom_bus, GFP_KERNEL);
2484         if (next_config_rom == NULL)
2485                 return -ENOMEM;
2486
2487         spin_lock_irq(&ohci->lock);
2488
2489         /*
2490          * If there is not an already pending config_rom update,
2491          * push our new allocation into the ohci->next_config_rom
2492          * and then mark the local variable as null so that we
2493          * won't deallocate the new buffer.
2494          *
2495          * OTOH, if there is a pending config_rom update, just
2496          * use that buffer with the new config_rom data, and
2497          * let this routine free the unused DMA allocation.
2498          */
2499
2500         if (ohci->next_config_rom == NULL) {
2501                 ohci->next_config_rom = next_config_rom;
2502                 ohci->next_config_rom_bus = next_config_rom_bus;
2503                 next_config_rom = NULL;
2504         }
2505
2506         copy_config_rom(ohci->next_config_rom, config_rom, length);
2507
2508         ohci->next_header = config_rom[0];
2509         ohci->next_config_rom[0] = 0;
2510
2511         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2512
2513         spin_unlock_irq(&ohci->lock);
2514
2515         /* If we didn't use the DMA allocation, delete it. */
2516         if (next_config_rom != NULL)
2517                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2518                                   next_config_rom, next_config_rom_bus);
2519
2520         /*
2521          * Now initiate a bus reset to have the changes take
2522          * effect. We clean up the old config rom memory and DMA
2523          * mappings in the bus reset tasklet, since the OHCI
2524          * controller could need to access it before the bus reset
2525          * takes effect.
2526          */
2527
2528         fw_schedule_bus_reset(&ohci->card, true, true);
2529
2530         return 0;
2531 }
2532
2533 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2534 {
2535         struct fw_ohci *ohci = fw_ohci(card);
2536
2537         at_context_transmit(&ohci->at_request_ctx, packet);
2538 }
2539
2540 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2541 {
2542         struct fw_ohci *ohci = fw_ohci(card);
2543
2544         at_context_transmit(&ohci->at_response_ctx, packet);
2545 }
2546
2547 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2548 {
2549         struct fw_ohci *ohci = fw_ohci(card);
2550         struct context *ctx = &ohci->at_request_ctx;
2551         struct driver_data *driver_data = packet->driver_data;
2552         int ret = -ENOENT;
2553
2554         tasklet_disable(&ctx->tasklet);
2555
2556         if (packet->ack != 0)
2557                 goto out;
2558
2559         if (packet->payload_mapped)
2560                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2561                                  packet->payload_length, DMA_TO_DEVICE);
2562
2563         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2564         driver_data->packet = NULL;
2565         packet->ack = RCODE_CANCELLED;
2566         packet->callback(packet, &ohci->card, packet->ack);
2567         ret = 0;
2568  out:
2569         tasklet_enable(&ctx->tasklet);
2570
2571         return ret;
2572 }
2573
2574 static int ohci_enable_phys_dma(struct fw_card *card,
2575                                 int node_id, int generation)
2576 {
2577 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2578         return 0;
2579 #else
2580         struct fw_ohci *ohci = fw_ohci(card);
2581         unsigned long flags;
2582         int n, ret = 0;
2583
2584         /*
2585          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2586          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2587          */
2588
2589         spin_lock_irqsave(&ohci->lock, flags);
2590
2591         if (ohci->generation != generation) {
2592                 ret = -ESTALE;
2593                 goto out;
2594         }
2595
2596         /*
2597          * Note, if the node ID contains a non-local bus ID, physical DMA is
2598          * enabled for _all_ nodes on remote buses.
2599          */
2600
2601         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2602         if (n < 32)
2603                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2604         else
2605                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2606
2607         flush_writes(ohci);
2608  out:
2609         spin_unlock_irqrestore(&ohci->lock, flags);
2610
2611         return ret;
2612 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2613 }
2614
2615 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2616 {
2617         struct fw_ohci *ohci = fw_ohci(card);
2618         unsigned long flags;
2619         u32 value;
2620
2621         switch (csr_offset) {
2622         case CSR_STATE_CLEAR:
2623         case CSR_STATE_SET:
2624                 if (ohci->is_root &&
2625                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2626                      OHCI1394_LinkControl_cycleMaster))
2627                         value = CSR_STATE_BIT_CMSTR;
2628                 else
2629                         value = 0;
2630                 if (ohci->csr_state_setclear_abdicate)
2631                         value |= CSR_STATE_BIT_ABDICATE;
2632
2633                 return value;
2634
2635         case CSR_NODE_IDS:
2636                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2637
2638         case CSR_CYCLE_TIME:
2639                 return get_cycle_time(ohci);
2640
2641         case CSR_BUS_TIME:
2642                 /*
2643                  * We might be called just after the cycle timer has wrapped
2644                  * around but just before the cycle64Seconds handler, so we
2645                  * better check here, too, if the bus time needs to be updated.
2646                  */
2647                 spin_lock_irqsave(&ohci->lock, flags);
2648                 value = update_bus_time(ohci);
2649                 spin_unlock_irqrestore(&ohci->lock, flags);
2650                 return value;
2651
2652         case CSR_BUSY_TIMEOUT:
2653                 value = reg_read(ohci, OHCI1394_ATRetries);
2654                 return (value >> 4) & 0x0ffff00f;
2655
2656         case CSR_PRIORITY_BUDGET:
2657                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2658                         (ohci->pri_req_max << 8);
2659
2660         default:
2661                 WARN_ON(1);
2662                 return 0;
2663         }
2664 }
2665
2666 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2667 {
2668         struct fw_ohci *ohci = fw_ohci(card);
2669         unsigned long flags;
2670
2671         switch (csr_offset) {
2672         case CSR_STATE_CLEAR:
2673                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2674                         reg_write(ohci, OHCI1394_LinkControlClear,
2675                                   OHCI1394_LinkControl_cycleMaster);
2676                         flush_writes(ohci);
2677                 }
2678                 if (value & CSR_STATE_BIT_ABDICATE)
2679                         ohci->csr_state_setclear_abdicate = false;
2680                 break;
2681
2682         case CSR_STATE_SET:
2683                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2684                         reg_write(ohci, OHCI1394_LinkControlSet,
2685                                   OHCI1394_LinkControl_cycleMaster);
2686                         flush_writes(ohci);
2687                 }
2688                 if (value & CSR_STATE_BIT_ABDICATE)
2689                         ohci->csr_state_setclear_abdicate = true;
2690                 break;
2691
2692         case CSR_NODE_IDS:
2693                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2694                 flush_writes(ohci);
2695                 break;
2696
2697         case CSR_CYCLE_TIME:
2698                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2699                 reg_write(ohci, OHCI1394_IntEventSet,
2700                           OHCI1394_cycleInconsistent);
2701                 flush_writes(ohci);
2702                 break;
2703
2704         case CSR_BUS_TIME:
2705                 spin_lock_irqsave(&ohci->lock, flags);
2706                 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2707                                  (value & ~0x7f);
2708                 spin_unlock_irqrestore(&ohci->lock, flags);
2709                 break;
2710
2711         case CSR_BUSY_TIMEOUT:
2712                 value = (value & 0xf) | ((value & 0xf) << 4) |
2713                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2714                 reg_write(ohci, OHCI1394_ATRetries, value);
2715                 flush_writes(ohci);
2716                 break;
2717
2718         case CSR_PRIORITY_BUDGET:
2719                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2720                 flush_writes(ohci);
2721                 break;
2722
2723         default:
2724                 WARN_ON(1);
2725                 break;
2726         }
2727 }
2728
2729 static void flush_iso_completions(struct iso_context *ctx)
2730 {
2731         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2732                               ctx->header_length, ctx->header,
2733                               ctx->base.callback_data);
2734         ctx->header_length = 0;
2735 }
2736
2737 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2738 {
2739         u32 *ctx_hdr;
2740
2741         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2742                 if (ctx->base.drop_overflow_headers)
2743                         return;
2744                 flush_iso_completions(ctx);
2745         }
2746
2747         ctx_hdr = ctx->header + ctx->header_length;
2748         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2749
2750         /*
2751          * The two iso header quadlets are byteswapped to little
2752          * endian by the controller, but we want to present them
2753          * as big endian for consistency with the bus endianness.
2754          */
2755         if (ctx->base.header_size > 0)
2756                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2757         if (ctx->base.header_size > 4)
2758                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2759         if (ctx->base.header_size > 8)
2760                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2761         ctx->header_length += ctx->base.header_size;
2762 }
2763
2764 static int handle_ir_packet_per_buffer(struct context *context,
2765                                        struct descriptor *d,
2766                                        struct descriptor *last)
2767 {
2768         struct iso_context *ctx =
2769                 container_of(context, struct iso_context, context);
2770         struct descriptor *pd;
2771         u32 buffer_dma;
2772
2773         for (pd = d; pd <= last; pd++)
2774                 if (pd->transfer_status)
2775                         break;
2776         if (pd > last)
2777                 /* Descriptor(s) not done yet, stop iteration */
2778                 return 0;
2779
2780         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2781                 d++;
2782                 buffer_dma = le32_to_cpu(d->data_address);
2783                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2784                                               buffer_dma & PAGE_MASK,
2785                                               buffer_dma & ~PAGE_MASK,
2786                                               le16_to_cpu(d->req_count),
2787                                               DMA_FROM_DEVICE);
2788         }
2789
2790         copy_iso_headers(ctx, (u32 *) (last + 1));
2791
2792         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2793                 flush_iso_completions(ctx);
2794
2795         return 1;
2796 }
2797
2798 /* d == last because each descriptor block is only a single descriptor. */
2799 static int handle_ir_buffer_fill(struct context *context,
2800                                  struct descriptor *d,
2801                                  struct descriptor *last)
2802 {
2803         struct iso_context *ctx =
2804                 container_of(context, struct iso_context, context);
2805         unsigned int req_count, res_count, completed;
2806         u32 buffer_dma;
2807
2808         req_count = le16_to_cpu(last->req_count);
2809         res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2810         completed = req_count - res_count;
2811         buffer_dma = le32_to_cpu(last->data_address);
2812
2813         if (completed > 0) {
2814                 ctx->mc_buffer_bus = buffer_dma;
2815                 ctx->mc_completed = completed;
2816         }
2817
2818         if (res_count != 0)
2819                 /* Descriptor(s) not done yet, stop iteration */
2820                 return 0;
2821
2822         dma_sync_single_range_for_cpu(context->ohci->card.device,
2823                                       buffer_dma & PAGE_MASK,
2824                                       buffer_dma & ~PAGE_MASK,
2825                                       completed, DMA_FROM_DEVICE);
2826
2827         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2828                 ctx->base.callback.mc(&ctx->base,
2829                                       buffer_dma + completed,
2830                                       ctx->base.callback_data);
2831                 ctx->mc_completed = 0;
2832         }
2833
2834         return 1;
2835 }
2836
2837 static void flush_ir_buffer_fill(struct iso_context *ctx)
2838 {
2839         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2840                                       ctx->mc_buffer_bus & PAGE_MASK,
2841                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2842                                       ctx->mc_completed, DMA_FROM_DEVICE);
2843
2844         ctx->base.callback.mc(&ctx->base,
2845                               ctx->mc_buffer_bus + ctx->mc_completed,
2846                               ctx->base.callback_data);
2847         ctx->mc_completed = 0;
2848 }
2849
2850 static inline void sync_it_packet_for_cpu(struct context *context,
2851                                           struct descriptor *pd)
2852 {
2853         __le16 control;
2854         u32 buffer_dma;
2855
2856         /* only packets beginning with OUTPUT_MORE* have data buffers */
2857         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2858                 return;
2859
2860         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2861         pd += 2;
2862
2863         /*
2864          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2865          * data buffer is in the context program's coherent page and must not
2866          * be synced.
2867          */
2868         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2869             (context->current_bus          & PAGE_MASK)) {
2870                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2871                         return;
2872                 pd++;
2873         }
2874
2875         do {
2876                 buffer_dma = le32_to_cpu(pd->data_address);
2877                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2878                                               buffer_dma & PAGE_MASK,
2879                                               buffer_dma & ~PAGE_MASK,
2880                                               le16_to_cpu(pd->req_count),
2881                                               DMA_TO_DEVICE);
2882                 control = pd->control;
2883                 pd++;
2884         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2885 }
2886
2887 static int handle_it_packet(struct context *context,
2888                             struct descriptor *d,
2889                             struct descriptor *last)
2890 {
2891         struct iso_context *ctx =
2892                 container_of(context, struct iso_context, context);
2893         struct descriptor *pd;
2894         __be32 *ctx_hdr;
2895
2896         for (pd = d; pd <= last; pd++)
2897                 if (pd->transfer_status)
2898                         break;
2899         if (pd > last)
2900                 /* Descriptor(s) not done yet, stop iteration */
2901                 return 0;
2902
2903         sync_it_packet_for_cpu(context, d);
2904
2905         if (ctx->header_length + 4 > PAGE_SIZE) {
2906                 if (ctx->base.drop_overflow_headers)
2907                         return 1;
2908                 flush_iso_completions(ctx);
2909         }
2910
2911         ctx_hdr = ctx->header + ctx->header_length;
2912         ctx->last_timestamp = le16_to_cpu(last->res_count);
2913         /* Present this value as big-endian to match the receive code */
2914         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2915                                le16_to_cpu(pd->res_count));
2916         ctx->header_length += 4;
2917
2918         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2919                 flush_iso_completions(ctx);
2920
2921         return 1;
2922 }
2923
2924 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2925 {
2926         u32 hi = channels >> 32, lo = channels;
2927
2928         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2929         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2930         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2931         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2932         mmiowb();
2933         ohci->mc_channels = channels;
2934 }
2935
2936 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2937                                 int type, int channel, size_t header_size)
2938 {
2939         struct fw_ohci *ohci = fw_ohci(card);
2940         struct iso_context *uninitialized_var(ctx);
2941         descriptor_callback_t uninitialized_var(callback);
2942         u64 *uninitialized_var(channels);
2943         u32 *uninitialized_var(mask), uninitialized_var(regs);
2944         int index, ret = -EBUSY;
2945
2946         spin_lock_irq(&ohci->lock);
2947
2948         switch (type) {
2949         case FW_ISO_CONTEXT_TRANSMIT:
2950                 mask     = &ohci->it_context_mask;
2951                 callback = handle_it_packet;
2952                 index    = ffs(*mask) - 1;
2953                 if (index >= 0) {
2954                         *mask &= ~(1 << index);
2955                         regs = OHCI1394_IsoXmitContextBase(index);
2956                         ctx  = &ohci->it_context_list[index];
2957                 }
2958                 break;
2959
2960         case FW_ISO_CONTEXT_RECEIVE:
2961                 channels = &ohci->ir_context_channels;
2962                 mask     = &ohci->ir_context_mask;
2963                 callback = handle_ir_packet_per_buffer;
2964                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2965                 if (index >= 0) {
2966                         *channels &= ~(1ULL << channel);
2967                         *mask     &= ~(1 << index);
2968                         regs = OHCI1394_IsoRcvContextBase(index);
2969                         ctx  = &ohci->ir_context_list[index];
2970                 }
2971                 break;
2972
2973         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2974                 mask     = &ohci->ir_context_mask;
2975                 callback = handle_ir_buffer_fill;
2976                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2977                 if (index >= 0) {
2978                         ohci->mc_allocated = true;
2979                         *mask &= ~(1 << index);
2980                         regs = OHCI1394_IsoRcvContextBase(index);
2981                         ctx  = &ohci->ir_context_list[index];
2982                 }
2983                 break;
2984
2985         default:
2986                 index = -1;
2987                 ret = -ENOSYS;
2988         }
2989
2990         spin_unlock_irq(&ohci->lock);
2991
2992         if (index < 0)
2993                 return ERR_PTR(ret);
2994
2995         memset(ctx, 0, sizeof(*ctx));
2996         ctx->header_length = 0;
2997         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2998         if (ctx->header == NULL) {
2999                 ret = -ENOMEM;
3000                 goto out;
3001         }
3002         ret = context_init(&ctx->context, ohci, regs, callback);
3003         if (ret < 0)
3004                 goto out_with_header;
3005
3006         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3007                 set_multichannel_mask(ohci, 0);
3008                 ctx->mc_completed = 0;
3009         }
3010
3011         return &ctx->base;
3012
3013  out_with_header:
3014         free_page((unsigned long)ctx->header);
3015  out:
3016         spin_lock_irq(&ohci->lock);
3017
3018         switch (type) {
3019         case FW_ISO_CONTEXT_RECEIVE:
3020                 *channels |= 1ULL << channel;
3021                 break;
3022
3023         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3024                 ohci->mc_allocated = false;
3025                 break;
3026         }
3027         *mask |= 1 << index;
3028
3029         spin_unlock_irq(&ohci->lock);
3030
3031         return ERR_PTR(ret);
3032 }
3033
3034 static int ohci_start_iso(struct fw_iso_context *base,
3035                           s32 cycle, u32 sync, u32 tags)
3036 {
3037         struct iso_context *ctx = container_of(base, struct iso_context, base);
3038         struct fw_ohci *ohci = ctx->context.ohci;
3039         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3040         int index;
3041
3042         /* the controller cannot start without any queued packets */
3043         if (ctx->context.last->branch_address == 0)
3044                 return -ENODATA;
3045
3046         switch (ctx->base.type) {
3047         case FW_ISO_CONTEXT_TRANSMIT:
3048                 index = ctx - ohci->it_context_list;
3049                 match = 0;
3050                 if (cycle >= 0)
3051                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3052                                 (cycle & 0x7fff) << 16;
3053
3054                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3055                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3056                 context_run(&ctx->context, match);
3057                 break;
3058
3059         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3060                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3061                 /* fall through */
3062         case FW_ISO_CONTEXT_RECEIVE:
3063                 index = ctx - ohci->ir_context_list;
3064                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3065                 if (cycle >= 0) {
3066                         match |= (cycle & 0x07fff) << 12;
3067                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3068                 }
3069
3070                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3071                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3072                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3073                 context_run(&ctx->context, control);
3074
3075                 ctx->sync = sync;
3076                 ctx->tags = tags;
3077
3078                 break;
3079         }
3080
3081         return 0;
3082 }
3083
3084 static int ohci_stop_iso(struct fw_iso_context *base)
3085 {
3086         struct fw_ohci *ohci = fw_ohci(base->card);
3087         struct iso_context *ctx = container_of(base, struct iso_context, base);
3088         int index;
3089
3090         switch (ctx->base.type) {
3091         case FW_ISO_CONTEXT_TRANSMIT:
3092                 index = ctx - ohci->it_context_list;
3093                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3094                 break;
3095
3096         case FW_ISO_CONTEXT_RECEIVE:
3097         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3098                 index = ctx - ohci->ir_context_list;
3099                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3100                 break;
3101         }
3102         flush_writes(ohci);
3103         context_stop(&ctx->context);
3104         tasklet_kill(&ctx->context.tasklet);
3105
3106         return 0;
3107 }
3108
3109 static void ohci_free_iso_context(struct fw_iso_context *base)
3110 {
3111         struct fw_ohci *ohci = fw_ohci(base->card);
3112         struct iso_context *ctx = container_of(base, struct iso_context, base);
3113         unsigned long flags;
3114         int index;
3115
3116         ohci_stop_iso(base);
3117         context_release(&ctx->context);
3118         free_page((unsigned long)ctx->header);
3119
3120         spin_lock_irqsave(&ohci->lock, flags);
3121
3122         switch (base->type) {
3123         case FW_ISO_CONTEXT_TRANSMIT:
3124                 index = ctx - ohci->it_context_list;
3125                 ohci->it_context_mask |= 1 << index;
3126                 break;
3127
3128         case FW_ISO_CONTEXT_RECEIVE:
3129                 index = ctx - ohci->ir_context_list;
3130                 ohci->ir_context_mask |= 1 << index;
3131                 ohci->ir_context_channels |= 1ULL << base->channel;
3132                 break;
3133
3134         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3135                 index = ctx - ohci->ir_context_list;
3136                 ohci->ir_context_mask |= 1 << index;
3137                 ohci->ir_context_channels |= ohci->mc_channels;
3138                 ohci->mc_channels = 0;
3139                 ohci->mc_allocated = false;
3140                 break;
3141         }
3142
3143         spin_unlock_irqrestore(&ohci->lock, flags);
3144 }
3145
3146 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3147 {
3148         struct fw_ohci *ohci = fw_ohci(base->card);
3149         unsigned long flags;
3150         int ret;
3151
3152         switch (base->type) {
3153         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3154
3155                 spin_lock_irqsave(&ohci->lock, flags);
3156
3157                 /* Don't allow multichannel to grab other contexts' channels. */
3158                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3159                         *channels = ohci->ir_context_channels;
3160                         ret = -EBUSY;
3161                 } else {
3162                         set_multichannel_mask(ohci, *channels);
3163                         ret = 0;
3164                 }
3165
3166                 spin_unlock_irqrestore(&ohci->lock, flags);
3167
3168                 break;
3169         default:
3170                 ret = -EINVAL;
3171         }
3172
3173         return ret;
3174 }
3175
3176 #ifdef CONFIG_PM
3177 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3178 {
3179         int i;
3180         struct iso_context *ctx;
3181
3182         for (i = 0 ; i < ohci->n_ir ; i++) {
3183                 ctx = &ohci->ir_context_list[i];
3184                 if (ctx->context.running)
3185                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3186         }
3187
3188         for (i = 0 ; i < ohci->n_it ; i++) {
3189                 ctx = &ohci->it_context_list[i];
3190                 if (ctx->context.running)
3191                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3192         }
3193 }
3194 #endif
3195
3196 static int queue_iso_transmit(struct iso_context *ctx,
3197                               struct fw_iso_packet *packet,
3198                               struct fw_iso_buffer *buffer,
3199                               unsigned long payload)
3200 {
3201         struct descriptor *d, *last, *pd;
3202         struct fw_iso_packet *p;
3203         __le32 *header;
3204         dma_addr_t d_bus, page_bus;
3205         u32 z, header_z, payload_z, irq;
3206         u32 payload_index, payload_end_index, next_page_index;
3207         int page, end_page, i, length, offset;
3208
3209         p = packet;
3210         payload_index = payload;
3211
3212         if (p->skip)
3213                 z = 1;
3214         else
3215                 z = 2;
3216         if (p->header_length > 0)
3217                 z++;
3218
3219         /* Determine the first page the payload isn't contained in. */
3220         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3221         if (p->payload_length > 0)
3222                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3223         else
3224                 payload_z = 0;
3225
3226         z += payload_z;
3227
3228         /* Get header size in number of descriptors. */
3229         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3230
3231         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3232         if (d == NULL)
3233                 return -ENOMEM;
3234
3235         if (!p->skip) {
3236                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3237                 d[0].req_count = cpu_to_le16(8);
3238                 /*
3239                  * Link the skip address to this descriptor itself.  This causes
3240                  * a context to skip a cycle whenever lost cycles or FIFO
3241                  * overruns occur, without dropping the data.  The application
3242                  * should then decide whether this is an error condition or not.
3243                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3244                  */
3245                 d[0].branch_address = cpu_to_le32(d_bus | z);
3246
3247                 header = (__le32 *) &d[1];
3248                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3249                                         IT_HEADER_TAG(p->tag) |
3250                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3251                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3252                                         IT_HEADER_SPEED(ctx->base.speed));
3253                 header[1] =
3254                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3255                                                           p->payload_length));
3256         }
3257
3258         if (p->header_length > 0) {
3259                 d[2].req_count    = cpu_to_le16(p->header_length);
3260                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3261                 memcpy(&d[z], p->header, p->header_length);
3262         }
3263
3264         pd = d + z - payload_z;
3265         payload_end_index = payload_index + p->payload_length;
3266         for (i = 0; i < payload_z; i++) {
3267                 page               = payload_index >> PAGE_SHIFT;
3268                 offset             = payload_index & ~PAGE_MASK;
3269                 next_page_index    = (page + 1) << PAGE_SHIFT;
3270                 length             =
3271                         min(next_page_index, payload_end_index) - payload_index;
3272                 pd[i].req_count    = cpu_to_le16(length);
3273
3274                 page_bus = page_private(buffer->pages[page]);
3275                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3276
3277                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3278                                                  page_bus, offset, length,
3279                                                  DMA_TO_DEVICE);
3280
3281                 payload_index += length;
3282         }
3283
3284         if (p->interrupt)
3285                 irq = DESCRIPTOR_IRQ_ALWAYS;
3286         else
3287                 irq = DESCRIPTOR_NO_IRQ;
3288
3289         last = z == 2 ? d : d + z - 1;
3290         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3291                                      DESCRIPTOR_STATUS |
3292                                      DESCRIPTOR_BRANCH_ALWAYS |
3293                                      irq);
3294
3295         context_append(&ctx->context, d, z, header_z);
3296
3297         return 0;
3298 }
3299
3300 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3301                                        struct fw_iso_packet *packet,
3302                                        struct fw_iso_buffer *buffer,
3303                                        unsigned long payload)
3304 {
3305         struct device *device = ctx->context.ohci->card.device;
3306         struct descriptor *d, *pd;
3307         dma_addr_t d_bus, page_bus;
3308         u32 z, header_z, rest;
3309         int i, j, length;
3310         int page, offset, packet_count, header_size, payload_per_buffer;
3311
3312         /*
3313          * The OHCI controller puts the isochronous header and trailer in the
3314          * buffer, so we need at least 8 bytes.
3315          */
3316         packet_count = packet->header_length / ctx->base.header_size;
3317         header_size  = max(ctx->base.header_size, (size_t)8);
3318
3319         /* Get header size in number of descriptors. */
3320         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3321         page     = payload >> PAGE_SHIFT;
3322         offset   = payload & ~PAGE_MASK;
3323         payload_per_buffer = packet->payload_length / packet_count;
3324
3325         for (i = 0; i < packet_count; i++) {
3326                 /* d points to the header descriptor */
3327                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3328                 d = context_get_descriptors(&ctx->context,
3329                                 z + header_z, &d_bus);
3330                 if (d == NULL)
3331                         return -ENOMEM;
3332
3333                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3334                                               DESCRIPTOR_INPUT_MORE);
3335                 if (packet->skip && i == 0)
3336                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3337                 d->req_count    = cpu_to_le16(header_size);
3338                 d->res_count    = d->req_count;
3339                 d->transfer_status = 0;
3340                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3341
3342                 rest = payload_per_buffer;
3343                 pd = d;
3344                 for (j = 1; j < z; j++) {
3345                         pd++;
3346                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3347                                                   DESCRIPTOR_INPUT_MORE);
3348
3349                         if (offset + rest < PAGE_SIZE)
3350                                 length = rest;
3351                         else
3352                                 length = PAGE_SIZE - offset;
3353                         pd->req_count = cpu_to_le16(length);
3354                         pd->res_count = pd->req_count;
3355                         pd->transfer_status = 0;
3356
3357                         page_bus = page_private(buffer->pages[page]);
3358                         pd->data_address = cpu_to_le32(page_bus + offset);
3359
3360                         dma_sync_single_range_for_device(device, page_bus,
3361                                                          offset, length,
3362                                                          DMA_FROM_DEVICE);
3363
3364                         offset = (offset + length) & ~PAGE_MASK;
3365                         rest -= length;
3366                         if (offset == 0)
3367                                 page++;
3368                 }
3369                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3370                                           DESCRIPTOR_INPUT_LAST |
3371                                           DESCRIPTOR_BRANCH_ALWAYS);
3372                 if (packet->interrupt && i == packet_count - 1)
3373                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3374
3375                 context_append(&ctx->context, d, z, header_z);
3376         }
3377
3378         return 0;
3379 }
3380
3381 static int queue_iso_buffer_fill(struct iso_context *ctx,
3382                                  struct fw_iso_packet *packet,
3383                                  struct fw_iso_buffer *buffer,
3384                                  unsigned long payload)
3385 {
3386         struct descriptor *d;
3387         dma_addr_t d_bus, page_bus;
3388         int page, offset, rest, z, i, length;
3389
3390         page   = payload >> PAGE_SHIFT;
3391         offset = payload & ~PAGE_MASK;
3392         rest   = packet->payload_length;
3393
3394         /* We need one descriptor for each page in the buffer. */
3395         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3396
3397         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3398                 return -EFAULT;
3399
3400         for (i = 0; i < z; i++) {
3401                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3402                 if (d == NULL)
3403                         return -ENOMEM;
3404
3405                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3406                                          DESCRIPTOR_BRANCH_ALWAYS);
3407                 if (packet->skip && i == 0)
3408                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3409                 if (packet->interrupt && i == z - 1)
3410                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3411
3412                 if (offset + rest < PAGE_SIZE)
3413                         length = rest;
3414                 else
3415                         length = PAGE_SIZE - offset;
3416                 d->req_count = cpu_to_le16(length);
3417                 d->res_count = d->req_count;
3418                 d->transfer_status = 0;
3419
3420                 page_bus = page_private(buffer->pages[page]);
3421                 d->data_address = cpu_to_le32(page_bus + offset);
3422
3423                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3424                                                  page_bus, offset, length,
3425                                                  DMA_FROM_DEVICE);
3426
3427                 rest -= length;
3428                 offset = 0;
3429                 page++;
3430
3431                 context_append(&ctx->context, d, 1, 0);
3432         }
3433
3434         return 0;
3435 }
3436
3437 static int ohci_queue_iso(struct fw_iso_context *base,
3438                           struct fw_iso_packet *packet,
3439                           struct fw_iso_buffer *buffer,
3440                           unsigned long payload)
3441 {
3442         struct iso_context *ctx = container_of(base, struct iso_context, base);
3443         unsigned long flags;
3444         int ret = -ENOSYS;
3445
3446         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3447         switch (base->type) {
3448         case FW_ISO_CONTEXT_TRANSMIT:
3449                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3450                 break;
3451         case FW_ISO_CONTEXT_RECEIVE:
3452                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3453                 break;
3454         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3455                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3456                 break;
3457         }
3458         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3459
3460         return ret;
3461 }
3462
3463 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3464 {
3465         struct context *ctx =
3466                         &container_of(base, struct iso_context, base)->context;
3467
3468         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3469 }
3470
3471 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3472 {
3473         struct iso_context *ctx = container_of(base, struct iso_context, base);
3474         int ret = 0;
3475
3476         tasklet_disable(&ctx->context.tasklet);
3477
3478         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3479                 context_tasklet((unsigned long)&ctx->context);
3480
3481                 switch (base->type) {
3482                 case FW_ISO_CONTEXT_TRANSMIT:
3483                 case FW_ISO_CONTEXT_RECEIVE:
3484                         if (ctx->header_length != 0)
3485                                 flush_iso_completions(ctx);
3486                         break;
3487                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3488                         if (ctx->mc_completed != 0)
3489                                 flush_ir_buffer_fill(ctx);
3490                         break;
3491                 default:
3492                         ret = -ENOSYS;
3493                 }
3494
3495                 clear_bit_unlock(0, &ctx->flushing_completions);
3496                 smp_mb__after_clear_bit();
3497         }
3498
3499         tasklet_enable(&ctx->context.tasklet);
3500
3501         return ret;
3502 }
3503
3504 static const struct fw_card_driver ohci_driver = {
3505         .enable                 = ohci_enable,
3506         .read_phy_reg           = ohci_read_phy_reg,
3507         .update_phy_reg         = ohci_update_phy_reg,
3508         .set_config_rom         = ohci_set_config_rom,
3509         .send_request           = ohci_send_request,
3510         .send_response          = ohci_send_response,
3511         .cancel_packet          = ohci_cancel_packet,
3512         .enable_phys_dma        = ohci_enable_phys_dma,
3513         .read_csr               = ohci_read_csr,
3514         .write_csr              = ohci_write_csr,
3515
3516         .allocate_iso_context   = ohci_allocate_iso_context,
3517         .free_iso_context       = ohci_free_iso_context,
3518         .set_iso_channels       = ohci_set_iso_channels,
3519         .queue_iso              = ohci_queue_iso,
3520         .flush_queue_iso        = ohci_flush_queue_iso,
3521         .flush_iso_completions  = ohci_flush_iso_completions,
3522         .start_iso              = ohci_start_iso,
3523         .stop_iso               = ohci_stop_iso,
3524 };
3525
3526 #ifdef CONFIG_PPC_PMAC
3527 static void pmac_ohci_on(struct pci_dev *dev)
3528 {
3529         if (machine_is(powermac)) {
3530                 struct device_node *ofn = pci_device_to_OF_node(dev);
3531
3532                 if (ofn) {
3533                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3534                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3535                 }
3536         }
3537 }
3538
3539 static void pmac_ohci_off(struct pci_dev *dev)
3540 {
3541         if (machine_is(powermac)) {
3542                 struct device_node *ofn = pci_device_to_OF_node(dev);
3543
3544                 if (ofn) {
3545                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3546                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3547                 }
3548         }
3549 }
3550 #else
3551 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3552 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3553 #endif /* CONFIG_PPC_PMAC */
3554
3555 static int pci_probe(struct pci_dev *dev,
3556                                const struct pci_device_id *ent)
3557 {
3558         struct fw_ohci *ohci;
3559         u32 bus_options, max_receive, link_speed, version;
3560         u64 guid;
3561         int i, err;
3562         size_t size;
3563
3564         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3565                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3566                 return -ENOSYS;
3567         }
3568
3569         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3570         if (ohci == NULL) {
3571                 err = -ENOMEM;
3572                 goto fail;
3573         }
3574
3575         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3576
3577         pmac_ohci_on(dev);
3578
3579         err = pci_enable_device(dev);
3580         if (err) {
3581                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3582                 goto fail_free;
3583         }
3584
3585         pci_set_master(dev);
3586         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3587         pci_set_drvdata(dev, ohci);
3588
3589         spin_lock_init(&ohci->lock);
3590         mutex_init(&ohci->phy_reg_mutex);
3591
3592         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3593
3594         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3595             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3596                 ohci_err(ohci, "invalid MMIO resource\n");
3597                 err = -ENXIO;
3598                 goto fail_disable;
3599         }
3600
3601         err = pci_request_region(dev, 0, ohci_driver_name);
3602         if (err) {
3603                 ohci_err(ohci, "MMIO resource unavailable\n");
3604                 goto fail_disable;
3605         }
3606
3607         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3608         if (ohci->registers == NULL) {
3609                 ohci_err(ohci, "failed to remap registers\n");
3610                 err = -ENXIO;
3611                 goto fail_iomem;
3612         }
3613
3614         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3615                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3616                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3617                      ohci_quirks[i].device == dev->device) &&
3618                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3619                      ohci_quirks[i].revision >= dev->revision)) {
3620                         ohci->quirks = ohci_quirks[i].flags;
3621                         break;
3622                 }
3623         if (param_quirks)
3624                 ohci->quirks = param_quirks;
3625
3626         /*
3627          * Because dma_alloc_coherent() allocates at least one page,
3628          * we save space by using a common buffer for the AR request/
3629          * response descriptors and the self IDs buffer.
3630          */
3631         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3632         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3633         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3634                                                PAGE_SIZE,
3635                                                &ohci->misc_buffer_bus,
3636                                                GFP_KERNEL);
3637         if (!ohci->misc_buffer) {
3638                 err = -ENOMEM;
3639                 goto fail_iounmap;
3640         }
3641
3642         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3643                               OHCI1394_AsReqRcvContextControlSet);
3644         if (err < 0)
3645                 goto fail_misc_buf;
3646
3647         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3648                               OHCI1394_AsRspRcvContextControlSet);
3649         if (err < 0)
3650                 goto fail_arreq_ctx;
3651
3652         err = context_init(&ohci->at_request_ctx, ohci,
3653                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3654         if (err < 0)
3655                 goto fail_arrsp_ctx;
3656
3657         err = context_init(&ohci->at_response_ctx, ohci,
3658                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3659         if (err < 0)
3660                 goto fail_atreq_ctx;
3661
3662         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3663         ohci->ir_context_channels = ~0ULL;
3664         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3665         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3666         ohci->ir_context_mask = ohci->ir_context_support;
3667         ohci->n_ir = hweight32(ohci->ir_context_mask);
3668         size = sizeof(struct iso_context) * ohci->n_ir;
3669         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3670
3671         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3672         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3673         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3674         ohci->it_context_mask = ohci->it_context_support;
3675         ohci->n_it = hweight32(ohci->it_context_mask);
3676         size = sizeof(struct iso_context) * ohci->n_it;
3677         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3678
3679         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3680                 err = -ENOMEM;
3681                 goto fail_contexts;
3682         }
3683
3684         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3685         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3686
3687         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3688         max_receive = (bus_options >> 12) & 0xf;
3689         link_speed = bus_options & 0x7;
3690         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3691                 reg_read(ohci, OHCI1394_GUIDLo);
3692
3693         if (!(ohci->quirks & QUIRK_NO_MSI))
3694                 pci_enable_msi(dev);
3695         if (request_irq(dev->irq, irq_handler,
3696                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3697                         ohci_driver_name, ohci)) {
3698                 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3699                 err = -EIO;
3700                 goto fail_msi;
3701         }
3702
3703         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3704         if (err)
3705                 goto fail_irq;
3706
3707         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3708         ohci_notice(ohci,
3709                     "added OHCI v%x.%x device as card %d, "
3710                     "%d IR + %d IT contexts, quirks 0x%x\n",
3711                     version >> 16, version & 0xff, ohci->card.index,
3712                     ohci->n_ir, ohci->n_it, ohci->quirks);
3713
3714         return 0;
3715
3716  fail_irq:
3717         free_irq(dev->irq, ohci);
3718  fail_msi:
3719         pci_disable_msi(dev);
3720  fail_contexts:
3721         kfree(ohci->ir_context_list);
3722         kfree(ohci->it_context_list);
3723         context_release(&ohci->at_response_ctx);
3724  fail_atreq_ctx:
3725         context_release(&ohci->at_request_ctx);
3726  fail_arrsp_ctx:
3727         ar_context_release(&ohci->ar_response_ctx);
3728  fail_arreq_ctx:
3729         ar_context_release(&ohci->ar_request_ctx);
3730  fail_misc_buf:
3731         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3732                           ohci->misc_buffer, ohci->misc_buffer_bus);
3733  fail_iounmap:
3734         pci_iounmap(dev, ohci->registers);
3735  fail_iomem:
3736         pci_release_region(dev, 0);
3737  fail_disable:
3738         pci_disable_device(dev);
3739  fail_free:
3740         kfree(ohci);
3741         pmac_ohci_off(dev);
3742  fail:
3743         return err;
3744 }
3745
3746 static void pci_remove(struct pci_dev *dev)
3747 {
3748         struct fw_ohci *ohci = pci_get_drvdata(dev);
3749
3750         /*
3751          * If the removal is happening from the suspend state, LPS won't be
3752          * enabled and host registers (eg., IntMaskClear) won't be accessible.
3753          */
3754         if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3755                 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3756                 flush_writes(ohci);
3757         }
3758         cancel_work_sync(&ohci->bus_reset_work);
3759         fw_core_remove_card(&ohci->card);
3760
3761         /*
3762          * FIXME: Fail all pending packets here, now that the upper
3763          * layers can't queue any more.
3764          */
3765
3766         software_reset(ohci);
3767         free_irq(dev->irq, ohci);
3768
3769         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3770                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3771                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3772         if (ohci->config_rom)
3773                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3774                                   ohci->config_rom, ohci->config_rom_bus);
3775         ar_context_release(&ohci->ar_request_ctx);
3776         ar_context_release(&ohci->ar_response_ctx);
3777         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3778                           ohci->misc_buffer, ohci->misc_buffer_bus);
3779         context_release(&ohci->at_request_ctx);
3780         context_release(&ohci->at_response_ctx);
3781         kfree(ohci->it_context_list);
3782         kfree(ohci->ir_context_list);
3783         pci_disable_msi(dev);
3784         pci_iounmap(dev, ohci->registers);
3785         pci_release_region(dev, 0);
3786         pci_disable_device(dev);
3787         kfree(ohci);
3788         pmac_ohci_off(dev);
3789
3790         dev_notice(&dev->dev, "removed fw-ohci device\n");
3791 }
3792
3793 #ifdef CONFIG_PM
3794 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3795 {
3796         struct fw_ohci *ohci = pci_get_drvdata(dev);
3797         int err;
3798
3799         software_reset(ohci);
3800         err = pci_save_state(dev);
3801         if (err) {
3802                 ohci_err(ohci, "pci_save_state failed\n");
3803                 return err;
3804         }
3805         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3806         if (err)
3807                 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3808         pmac_ohci_off(dev);
3809
3810         return 0;
3811 }
3812
3813 static int pci_resume(struct pci_dev *dev)
3814 {
3815         struct fw_ohci *ohci = pci_get_drvdata(dev);
3816         int err;
3817
3818         pmac_ohci_on(dev);
3819         pci_set_power_state(dev, PCI_D0);
3820         pci_restore_state(dev);
3821         err = pci_enable_device(dev);
3822         if (err) {
3823                 ohci_err(ohci, "pci_enable_device failed\n");
3824                 return err;
3825         }
3826
3827         /* Some systems don't setup GUID register on resume from ram  */
3828         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3829                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3830                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3831                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3832         }
3833
3834         err = ohci_enable(&ohci->card, NULL, 0);
3835         if (err)
3836                 return err;
3837
3838         ohci_resume_iso_dma(ohci);
3839
3840         return 0;
3841 }
3842 #endif
3843
3844 static const struct pci_device_id pci_table[] = {
3845         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3846         { }
3847 };
3848
3849 MODULE_DEVICE_TABLE(pci, pci_table);
3850
3851 static struct pci_driver fw_ohci_pci_driver = {
3852         .name           = ohci_driver_name,
3853         .id_table       = pci_table,
3854         .probe          = pci_probe,
3855         .remove         = pci_remove,
3856 #ifdef CONFIG_PM
3857         .resume         = pci_resume,
3858         .suspend        = pci_suspend,
3859 #endif
3860 };
3861
3862 module_pci_driver(fw_ohci_pci_driver);
3863
3864 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3865 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3866 MODULE_LICENSE("GPL");
3867
3868 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3869 MODULE_ALIAS("ohci1394");