2 * Intel 82860 Memory Controller kernel module
3 * (C) 2005 Red Hat (http://www.redhat.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Ben Woodard <woodard@redhat.com>
8 * shamelessly copied from and based upon the edac_i82875 driver
9 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
19 #define I82860_REVISION " Ver: 2.0.2"
20 #define EDAC_MOD_STR "i82860_edac"
22 #define i82860_printk(level, fmt, arg...) \
23 edac_printk(level, "i82860", fmt, ##arg)
25 #define i82860_mc_printk(mci, level, fmt, arg...) \
26 edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
28 #ifndef PCI_DEVICE_ID_INTEL_82860_0
29 #define PCI_DEVICE_ID_INTEL_82860_0 0x2531
30 #endif /* PCI_DEVICE_ID_INTEL_82860_0 */
32 #define I82860_MCHCFG 0x50
33 #define I82860_GBA 0x60
34 #define I82860_GBA_MASK 0x7FF
35 #define I82860_GBA_SHIFT 24
36 #define I82860_ERRSTS 0xC8
37 #define I82860_EAP 0xE4
38 #define I82860_DERRCTL_STS 0xE2
44 struct i82860_dev_info {
48 struct i82860_error_info {
55 static const struct i82860_dev_info i82860_devs[] = {
57 .ctl_name = "i82860"},
60 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code
61 * has already registered driver
63 static struct edac_pci_ctl_info *i82860_pci;
65 static void i82860_get_error_info(struct mem_ctl_info *mci,
66 struct i82860_error_info *info)
70 pdev = to_pci_dev(mci->dev);
73 * This is a mess because there is no atomic way to read all the
74 * registers at once and the registers can transition from CE being
77 pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
78 pci_read_config_dword(pdev, I82860_EAP, &info->eap);
79 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
80 pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
82 pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
85 * If the error is the same for both reads then the first set of reads
86 * is valid. If there is a change then there is a CE no info and the
87 * second set of reads is valid and should be UE info.
89 if (!(info->errsts2 & 0x0003))
92 if ((info->errsts ^ info->errsts2) & 0x0003) {
93 pci_read_config_dword(pdev, I82860_EAP, &info->eap);
94 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
98 static int i82860_process_error_info(struct mem_ctl_info *mci,
99 struct i82860_error_info *info,
104 if (!(info->errsts2 & 0x0003))
110 if ((info->errsts ^ info->errsts2) & 0x0003) {
111 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
112 info->errsts = info->errsts2;
115 info->eap >>= PAGE_SHIFT;
116 row = edac_mc_find_csrow_by_page(mci, info->eap);
118 if (info->errsts & 0x0002)
119 edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
121 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
127 static void i82860_check(struct mem_ctl_info *mci)
129 struct i82860_error_info info;
131 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
132 i82860_get_error_info(mci, &info);
133 i82860_process_error_info(mci, &info, 1);
136 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
138 unsigned long last_cumul_size;
139 u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
142 struct csrow_info *csrow;
143 struct dimm_info *dimm;
146 pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
147 mchcfg_ddim = mchcfg_ddim & 0x180;
150 /* The group row boundary (GRA) reg values are boundary address
151 * for each DRAM row with a granularity of 16MB. GRA regs are
152 * cumulative; therefore GRA15 will contain the total memory contained
155 for (index = 0; index < mci->nr_csrows; index++) {
156 csrow = &mci->csrows[index];
157 dimm = csrow->channels[0].dimm;
159 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
160 cumul_size = (value & I82860_GBA_MASK) <<
161 (I82860_GBA_SHIFT - PAGE_SHIFT);
162 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
165 if (cumul_size == last_cumul_size)
166 continue; /* not populated */
168 csrow->first_page = last_cumul_size;
169 csrow->last_page = cumul_size - 1;
170 dimm->nr_pages = cumul_size - last_cumul_size;
171 last_cumul_size = cumul_size;
172 dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
173 dimm->mtype = MEM_RMBS;
174 dimm->dtype = DEV_UNKNOWN;
175 dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
179 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
181 struct mem_ctl_info *mci;
182 struct i82860_error_info discard;
184 /* RDRAM has channels but these don't map onto the abstractions that
186 The device groups from the GRA registers seem to map reasonably
187 well onto the notion of a chip select row.
188 There are 16 GRA registers and since the name is associated with
189 the channel and the GRA registers map to physical devices so we are
190 going to make 1 channel for group.
192 mci = edac_mc_alloc(0, 16, 1, 0);
197 debugf3("%s(): init mci\n", __func__);
198 mci->dev = &pdev->dev;
199 mci->mtype_cap = MEM_FLAG_DDR;
200 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
201 /* I"m not sure about this but I think that all RDRAM is SECDED */
202 mci->edac_cap = EDAC_FLAG_SECDED;
203 mci->mod_name = EDAC_MOD_STR;
204 mci->mod_ver = I82860_REVISION;
205 mci->ctl_name = i82860_devs[dev_idx].ctl_name;
206 mci->dev_name = pci_name(pdev);
207 mci->edac_check = i82860_check;
208 mci->ctl_page_to_phys = NULL;
209 i82860_init_csrows(mci, pdev);
210 i82860_get_error_info(mci, &discard); /* clear counters */
212 /* Here we assume that we will never see multiple instances of this
213 * type of memory controller. The ID is therefore hardcoded to 0.
215 if (edac_mc_add_mc(mci)) {
216 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
220 /* allocating generic PCI control info */
221 i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
224 "%s(): Unable to create PCI control\n",
227 "%s(): PCI error report via EDAC not setup\n",
231 /* get this far and it's successful */
232 debugf3("%s(): success\n", __func__);
241 /* returns count (>= 0), or negative on error */
242 static int __devinit i82860_init_one(struct pci_dev *pdev,
243 const struct pci_device_id *ent)
247 debugf0("%s()\n", __func__);
248 i82860_printk(KERN_INFO, "i82860 init one\n");
250 if (pci_enable_device(pdev) < 0)
253 rc = i82860_probe1(pdev, ent->driver_data);
256 mci_pdev = pci_dev_get(pdev);
261 static void __devexit i82860_remove_one(struct pci_dev *pdev)
263 struct mem_ctl_info *mci;
265 debugf0("%s()\n", __func__);
268 edac_pci_release_generic_ctl(i82860_pci);
270 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
276 static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
278 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 } /* 0 terminated list. */
285 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
287 static struct pci_driver i82860_driver = {
288 .name = EDAC_MOD_STR,
289 .probe = i82860_init_one,
290 .remove = __devexit_p(i82860_remove_one),
291 .id_table = i82860_pci_tbl,
294 static int __init i82860_init(void)
298 debugf3("%s()\n", __func__);
300 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
303 if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
307 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
308 PCI_DEVICE_ID_INTEL_82860_0, NULL);
310 if (mci_pdev == NULL) {
311 debugf0("860 pci_get_device fail\n");
316 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
319 debugf0("860 init fail\n");
328 pci_unregister_driver(&i82860_driver);
331 if (mci_pdev != NULL)
332 pci_dev_put(mci_pdev);
337 static void __exit i82860_exit(void)
339 debugf3("%s()\n", __func__);
341 pci_unregister_driver(&i82860_driver);
343 if (mci_pdev != NULL)
344 pci_dev_put(mci_pdev);
347 module_init(i82860_init);
348 module_exit(i82860_exit);
350 MODULE_LICENSE("GPL");
351 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
352 "Ben Woodard <woodard@redhat.com>");
353 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
355 module_param(edac_op_state, int, 0444);
356 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");