2 * Cell MIC driver for ECC counting
4 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
5 * <benh@kernel.crashing.org>
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
12 #include <linux/edac.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/stop_machine.h>
18 #include <asm/machdep.h>
19 #include <asm/cell-regs.h>
21 #include "edac_core.h"
25 struct cbe_mic_tm_regs __iomem *regs;
33 static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
35 struct cell_edac_priv *priv = mci->pvt_info;
36 struct csrow_info *csrow = &mci->csrows[0];
37 unsigned long address, pfn, offset, syndrome;
39 dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
40 priv->node, chan, ar);
42 /* Address decoding is likely a bit bogus, to dbl check */
43 address = (ar & 0xffffffffe0000000ul) >> 29;
44 if (priv->chanmask == 0x3)
45 address = (address << 1) | chan;
46 pfn = address >> PAGE_SHIFT;
47 offset = address & ~PAGE_MASK;
48 syndrome = (ar & 0x000000001fe00000ul) >> 21;
50 /* TODO: Decoding of the error address */
51 edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
52 syndrome, 0, chan, "");
55 static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
57 struct cell_edac_priv *priv = mci->pvt_info;
58 struct csrow_info *csrow = &mci->csrows[0];
59 unsigned long address, pfn, offset;
61 dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
62 priv->node, chan, ar);
64 /* Address decoding is likely a bit bogus, to dbl check */
65 address = (ar & 0xffffffffe0000000ul) >> 29;
66 if (priv->chanmask == 0x3)
67 address = (address << 1) | chan;
68 pfn = address >> PAGE_SHIFT;
69 offset = address & ~PAGE_MASK;
71 /* TODO: Decoding of the error address */
72 edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
75 static void cell_edac_check(struct mem_ctl_info *mci)
77 struct cell_edac_priv *priv = mci->pvt_info;
78 u64 fir, addreg, clear = 0;
80 fir = in_be64(&priv->regs->mic_fir);
82 if (fir != priv->prev_fir) {
83 dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir);
87 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
88 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
89 clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
90 cell_edac_count_ce(mci, 0, addreg);
92 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
93 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
94 clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
95 cell_edac_count_ce(mci, 1, addreg);
97 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
98 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
99 clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
100 cell_edac_count_ue(mci, 0, addreg);
102 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
103 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
104 clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
105 cell_edac_count_ue(mci, 1, addreg);
108 /* The procedure for clearing FIR bits is a bit ... weird */
110 fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
111 fir |= CBE_MIC_FIR_ECC_RESET_MASK;
113 out_be64(&priv->regs->mic_fir, fir);
114 (void)in_be64(&priv->regs->mic_fir);
118 fir = in_be64(&priv->regs->mic_fir);
119 dev_dbg(mci->dev, "fir clear : 0x%016lx\n", fir);
124 static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci)
126 struct csrow_info *csrow = &mci->csrows[0];
127 struct dimm_info *dimm;
128 struct cell_edac_priv *priv = mci->pvt_info;
129 struct device_node *np;
134 (np = of_find_node_by_name(np, "memory")) != NULL;) {
137 /* We "know" that the Cell firmware only creates one entry
138 * in the "memory" nodes. If that changes, this code will
139 * need to be adapted.
141 if (of_address_to_resource(np, 0, &r))
143 if (of_node_to_nid(np) != priv->node)
145 csrow->first_page = r.start >> PAGE_SHIFT;
146 nr_pages = resource_size(&r) >> PAGE_SHIFT;
147 csrow->last_page = csrow->first_page + nr_pages - 1;
149 for (j = 0; j < csrow->nr_channels; j++) {
150 dimm = csrow->channels[j].dimm;
151 dimm->mtype = MEM_XDR;
152 dimm->edac_mode = EDAC_SECDED;
153 dimm->nr_pages = nr_pages / csrow->nr_channels;
156 "Initialized on node %d, chanmask=0x%x,"
157 " first_page=0x%lx, nr_pages=0x%x\n",
158 priv->node, priv->chanmask,
159 csrow->first_page, dimm->nr_pages);
164 static int __devinit cell_edac_probe(struct platform_device *pdev)
166 struct cbe_mic_tm_regs __iomem *regs;
167 struct mem_ctl_info *mci;
168 struct cell_edac_priv *priv;
172 regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
176 edac_op_state = EDAC_OPSTATE_POLL;
178 /* Get channel population */
179 reg = in_be64(®s->mic_mnt_cfg);
180 dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
182 if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
184 if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
188 "Yuck ! No channel populated ? Aborting !\n");
191 dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
192 in_be64(®s->mic_fir));
194 /* Allocate & init EDAC MC data structure */
195 mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1,
196 chanmask == 3 ? 2 : 1, pdev->id);
199 priv = mci->pvt_info;
201 priv->node = pdev->id;
202 priv->chanmask = chanmask;
203 mci->dev = &pdev->dev;
204 mci->mtype_cap = MEM_FLAG_XDR;
205 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
206 mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
207 mci->mod_name = "cell_edac";
208 mci->ctl_name = "MIC";
209 mci->dev_name = dev_name(&pdev->dev);
210 mci->edac_check = cell_edac_check;
211 cell_edac_init_csrows(mci);
213 /* Register with EDAC core */
214 rc = edac_mc_add_mc(mci);
216 dev_err(&pdev->dev, "failed to register with EDAC core\n");
224 static int __devexit cell_edac_remove(struct platform_device *pdev)
226 struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
232 static struct platform_driver cell_edac_driver = {
235 .owner = THIS_MODULE,
237 .probe = cell_edac_probe,
238 .remove = __devexit_p(cell_edac_remove),
241 static int __init cell_edac_init(void)
243 /* Sanity check registers data structure */
244 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
245 mic_df_ecc_address_0) != 0xf8);
246 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
247 mic_df_ecc_address_1) != 0x1b8);
248 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
249 mic_df_config) != 0x218);
250 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
252 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
253 mic_mnt_cfg) != 0x210);
254 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
257 return platform_driver_register(&cell_edac_driver);
260 static void __exit cell_edac_exit(void)
262 platform_driver_unregister(&cell_edac_driver);
265 module_init(cell_edac_init);
266 module_exit(cell_edac_exit);
268 MODULE_LICENSE("GPL");
269 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
270 MODULE_DESCRIPTION("ECC counting for Cell MIC");