drivers/edac/cell_edac.c

   1 /*
   2  * Cell MIC driver for ECC counting
   3  *
   4  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   5  *                <benh@kernel.crashing.org>
   6  *
   7  * This file may be distributed under the terms of the
   8  * GNU General Public License.
   9  */
  10 #undef DEBUG
  11
  12 #include <linux/edac.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/stop_machine.h>
  17 #include <linux/io.h>
  18 #include <asm/machdep.h>
  19 #include <asm/cell-regs.h>
  20
  21 #include "edac_core.h"
  22
  23 struct cell_edac_priv
  24 {
  25         struct cbe_mic_tm_regs __iomem  *regs;
  26         int                             node;
  27         int                             chanmask;
  28 #ifdef DEBUG
  29         u64                             prev_fir;
  30 #endif
  31 };
  32
  33 static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
  34 {
  35         struct cell_edac_priv           *priv = mci->pvt_info;
  36         struct csrow_info               *csrow = &mci->csrows[0];
  37         unsigned long                   address, pfn, offset, syndrome;
  38
  39         dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
  40                 priv->node, chan, ar);
  41
  42         /* Address decoding is likely a bit bogus, to dbl check */
  43         address = (ar & 0xffffffffe0000000ul) >> 29;
  44         if (priv->chanmask == 0x3)
  45                 address = (address << 1) | chan;
  46         pfn = address >> PAGE_SHIFT;
  47         offset = address & ~PAGE_MASK;
  48         syndrome = (ar & 0x000000001fe00000ul) >> 21;
  49
  50         /* TODO: Decoding of the error address */
  51         edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
  52                           syndrome, 0, chan, "");
  53 }
  54
  55 static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
  56 {
  57         struct cell_edac_priv           *priv = mci->pvt_info;
  58         struct csrow_info               *csrow = &mci->csrows[0];
  59         unsigned long                   address, pfn, offset;
  60
  61         dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
  62                 priv->node, chan, ar);
  63
  64         /* Address decoding is likely a bit bogus, to dbl check */
  65         address = (ar & 0xffffffffe0000000ul) >> 29;
  66         if (priv->chanmask == 0x3)
  67                 address = (address << 1) | chan;
  68         pfn = address >> PAGE_SHIFT;
  69         offset = address & ~PAGE_MASK;
  70
  71         /* TODO: Decoding of the error address */
  72         edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
  73 }
  74
  75 static void cell_edac_check(struct mem_ctl_info *mci)
  76 {
  77         struct cell_edac_priv           *priv = mci->pvt_info;
  78         u64                             fir, addreg, clear = 0;
  79
  80         fir = in_be64(&priv->regs->mic_fir);
  81 #ifdef DEBUG
  82         if (fir != priv->prev_fir) {
  83                 dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir);
  84                 priv->prev_fir = fir;
  85         }
  86 #endif
  87         if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
  88                 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
  89                 clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
  90                 cell_edac_count_ce(mci, 0, addreg);
  91         }
  92         if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
  93                 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
  94                 clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
  95                 cell_edac_count_ce(mci, 1, addreg);
  96         }
  97         if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
  98                 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
  99                 clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
 100                 cell_edac_count_ue(mci, 0, addreg);
 101         }
 102         if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
 103                 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
 104                 clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
 105                 cell_edac_count_ue(mci, 1, addreg);
 106         }
 107
 108         /* The procedure for clearing FIR bits is a bit ... weird */
 109         if (clear) {
 110                 fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
 111                 fir |= CBE_MIC_FIR_ECC_RESET_MASK;
 112                 fir &= ~clear;
 113                 out_be64(&priv->regs->mic_fir, fir);
 114                 (void)in_be64(&priv->regs->mic_fir);
 115
 116                 mb();   /* sync up */
 117 #ifdef DEBUG
 118                 fir = in_be64(&priv->regs->mic_fir);
 119                 dev_dbg(mci->dev, "fir clear  : 0x%016lx\n", fir);
 120 #endif
 121         }
 122 }
 123
 124 static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci)
 125 {
 126         struct csrow_info               *csrow = &mci->csrows[0];
 127         struct dimm_info                *dimm;
 128         struct cell_edac_priv           *priv = mci->pvt_info;
 129         struct device_node              *np;
 130         int                             j;
 131
 132         for (np = NULL;
 133              (np = of_find_node_by_name(np, "memory")) != NULL;) {
 134                 struct resource r;
 135
 136                 /* We "know" that the Cell firmware only creates one entry
 137                  * in the "memory" nodes. If that changes, this code will
 138                  * need to be adapted.
 139                  */
 140                 if (of_address_to_resource(np, 0, &r))
 141                         continue;
 142                 if (of_node_to_nid(np) != priv->node)
 143                         continue;
 144                 csrow->first_page = r.start >> PAGE_SHIFT;
 145                 csrow->nr_pages = resource_size(&r) >> PAGE_SHIFT;
 146                 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
 147
 148                 for (j = 0; j < csrow->nr_channels; j++) {
 149                         dimm = csrow->channels[j].dimm;
 150                         dimm->mtype = MEM_XDR;
 151                         dimm->edac_mode = EDAC_SECDED;
 152                 }
 153                 dev_dbg(mci->dev,
 154                         "Initialized on node %d, chanmask=0x%x,"
 155                         " first_page=0x%lx, nr_pages=0x%x\n",
 156                         priv->node, priv->chanmask,
 157                         csrow->first_page, csrow->nr_pages);
 158                 break;
 159         }
 160 }
 161
 162 static int __devinit cell_edac_probe(struct platform_device *pdev)
 163 {
 164         struct cbe_mic_tm_regs __iomem  *regs;
 165         struct mem_ctl_info             *mci;
 166         struct cell_edac_priv           *priv;
 167         u64                             reg;
 168         int                             rc, chanmask;
 169
 170         regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
 171         if (regs == NULL)
 172                 return -ENODEV;
 173
 174         edac_op_state = EDAC_OPSTATE_POLL;
 175
 176         /* Get channel population */
 177         reg = in_be64(&regs->mic_mnt_cfg);
 178         dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
 179         chanmask = 0;
 180         if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
 181                 chanmask |= 0x1;
 182         if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
 183                 chanmask |= 0x2;
 184         if (chanmask == 0) {
 185                 dev_warn(&pdev->dev,
 186                          "Yuck ! No channel populated ? Aborting !\n");
 187                 return -ENODEV;
 188         }
 189         dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
 190                 in_be64(&regs->mic_fir));
 191
 192         /* Allocate & init EDAC MC data structure */
 193         mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1,
 194                             chanmask == 3 ? 2 : 1, pdev->id);
 195         if (mci == NULL)
 196                 return -ENOMEM;
 197         priv = mci->pvt_info;
 198         priv->regs = regs;
 199         priv->node = pdev->id;
 200         priv->chanmask = chanmask;
 201         mci->dev = &pdev->dev;
 202         mci->mtype_cap = MEM_FLAG_XDR;
 203         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 204         mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 205         mci->mod_name = "cell_edac";
 206         mci->ctl_name = "MIC";
 207         mci->dev_name = dev_name(&pdev->dev);
 208         mci->edac_check = cell_edac_check;
 209         cell_edac_init_csrows(mci);
 210
 211         /* Register with EDAC core */
 212         rc = edac_mc_add_mc(mci);
 213         if (rc) {
 214                 dev_err(&pdev->dev, "failed to register with EDAC core\n");
 215                 edac_mc_free(mci);
 216                 return rc;
 217         }
 218
 219         return 0;
 220 }
 221
 222 static int __devexit cell_edac_remove(struct platform_device *pdev)
 223 {
 224         struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
 225         if (mci)
 226                 edac_mc_free(mci);
 227         return 0;
 228 }
 229
 230 static struct platform_driver cell_edac_driver = {
 231         .driver         = {
 232                 .name   = "cbe-mic",
 233                 .owner  = THIS_MODULE,
 234         },
 235         .probe          = cell_edac_probe,
 236         .remove         = __devexit_p(cell_edac_remove),
 237 };
 238
 239 static int __init cell_edac_init(void)
 240 {
 241         /* Sanity check registers data structure */
 242         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 243                               mic_df_ecc_address_0) != 0xf8);
 244         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 245                               mic_df_ecc_address_1) != 0x1b8);
 246         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 247                               mic_df_config) != 0x218);
 248         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 249                               mic_fir) != 0x230);
 250         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 251                               mic_mnt_cfg) != 0x210);
 252         BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
 253                               mic_exc) != 0x208);
 254
 255         return platform_driver_register(&cell_edac_driver);
 256 }
 257
 258 static void __exit cell_edac_exit(void)
 259 {
 260         platform_driver_unregister(&cell_edac_driver);
 261 }
 262
 263 module_init(cell_edac_init);
 264 module_exit(cell_edac_exit);
 265
 266 MODULE_LICENSE("GPL");
 267 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
 268 MODULE_DESCRIPTION("ECC counting for Cell MIC");