drivers/dma/xgene-dma.c

   1 /*
   2  * Applied Micro X-Gene SoC DMA engine Driver
   3  *
   4  * Copyright (c) 2015, Applied Micro Circuits Corporation
   5  * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
   6  *          Loc Ho <lho@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  *
  21  * NOTE: PM support is currently not available.
  22  */
  23
  24 #include <linux/acpi.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/module.h>
  33 #include <linux/of_device.h>
  34
  35 #include "dmaengine.h"
  36
  37 /* X-Gene DMA ring csr registers and bit definations */
  38 #define XGENE_DMA_RING_CONFIG                   0x04
  39 #define XGENE_DMA_RING_ENABLE                   BIT(31)
  40 #define XGENE_DMA_RING_ID                       0x08
  41 #define XGENE_DMA_RING_ID_SETUP(v)              ((v) | BIT(31))
  42 #define XGENE_DMA_RING_ID_BUF                   0x0C
  43 #define XGENE_DMA_RING_ID_BUF_SETUP(v)          (((v) << 9) | BIT(21))
  44 #define XGENE_DMA_RING_THRESLD0_SET1            0x30
  45 #define XGENE_DMA_RING_THRESLD0_SET1_VAL        0X64
  46 #define XGENE_DMA_RING_THRESLD1_SET1            0x34
  47 #define XGENE_DMA_RING_THRESLD1_SET1_VAL        0xC8
  48 #define XGENE_DMA_RING_HYSTERESIS               0x68
  49 #define XGENE_DMA_RING_HYSTERESIS_VAL           0xFFFFFFFF
  50 #define XGENE_DMA_RING_STATE                    0x6C
  51 #define XGENE_DMA_RING_STATE_WR_BASE            0x70
  52 #define XGENE_DMA_RING_NE_INT_MODE              0x017C
  53 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v)    \
  54         ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
  55 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v)  \
  56         ((m) &= (~BIT(31 - (v))))
  57 #define XGENE_DMA_RING_CLKEN                    0xC208
  58 #define XGENE_DMA_RING_SRST                     0xC200
  59 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN         0xD070
  60 #define XGENE_DMA_RING_BLK_MEM_RDY              0xD074
  61 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL          0xFFFFFFFF
  62 #define XGENE_DMA_RING_DESC_CNT(v)              (((v) & 0x0001FFFE) >> 1)
  63 #define XGENE_DMA_RING_ID_GET(owner, num)       (((owner) << 6) | (num))
  64 #define XGENE_DMA_RING_DST_ID(v)                ((1 << 10) | (v))
  65 #define XGENE_DMA_RING_CMD_OFFSET               0x2C
  66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v)       ((v) << 6)
  67 #define XGENE_DMA_RING_COHERENT_SET(m)          \
  68         (((u32 *)(m))[2] |= BIT(4))
  69 #define XGENE_DMA_RING_ADDRL_SET(m, v)          \
  70         (((u32 *)(m))[2] |= (((v) >> 8) << 5))
  71 #define XGENE_DMA_RING_ADDRH_SET(m, v)          \
  72         (((u32 *)(m))[3] |= ((v) >> 35))
  73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m)        \
  74         (((u32 *)(m))[3] |= BIT(19))
  75 #define XGENE_DMA_RING_SIZE_SET(m, v)           \
  76         (((u32 *)(m))[3] |= ((v) << 23))
  77 #define XGENE_DMA_RING_RECOMBBUF_SET(m)         \
  78         (((u32 *)(m))[3] |= BIT(27))
  79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m)     \
  80         (((u32 *)(m))[3] |= (0x7 << 28))
  81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m)     \
  82         (((u32 *)(m))[4] |= 0x3)
  83 #define XGENE_DMA_RING_SELTHRSH_SET(m)          \
  84         (((u32 *)(m))[4] |= BIT(3))
  85 #define XGENE_DMA_RING_TYPE_SET(m, v)           \
  86         (((u32 *)(m))[4] |= ((v) << 19))
  87
  88 /* X-Gene DMA device csr registers and bit definitions */
  89 #define XGENE_DMA_IPBRR                         0x0
  90 #define XGENE_DMA_DEV_ID_RD(v)                  ((v) & 0x00000FFF)
  91 #define XGENE_DMA_BUS_ID_RD(v)                  (((v) >> 12) & 3)
  92 #define XGENE_DMA_REV_NO_RD(v)                  (((v) >> 14) & 3)
  93 #define XGENE_DMA_GCR                           0x10
  94 #define XGENE_DMA_CH_SETUP(v)                   \
  95         ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
  96 #define XGENE_DMA_ENABLE(v)                     ((v) |= BIT(31))
  97 #define XGENE_DMA_DISABLE(v)                    ((v) &= ~BIT(31))
  98 #define XGENE_DMA_RAID6_CONT                    0x14
  99 #define XGENE_DMA_RAID6_MULTI_CTRL(v)           ((v) << 24)
 100 #define XGENE_DMA_INT                           0x70
 101 #define XGENE_DMA_INT_MASK                      0x74
 102 #define XGENE_DMA_INT_ALL_MASK                  0xFFFFFFFF
 103 #define XGENE_DMA_INT_ALL_UNMASK                0x0
 104 #define XGENE_DMA_INT_MASK_SHIFT                0x14
 105 #define XGENE_DMA_RING_INT0_MASK                0x90A0
 106 #define XGENE_DMA_RING_INT1_MASK                0x90A8
 107 #define XGENE_DMA_RING_INT2_MASK                0x90B0
 108 #define XGENE_DMA_RING_INT3_MASK                0x90B8
 109 #define XGENE_DMA_RING_INT4_MASK                0x90C0
 110 #define XGENE_DMA_CFG_RING_WQ_ASSOC             0x90E0
 111 #define XGENE_DMA_ASSOC_RING_MNGR1              0xFFFFFFFF
 112 #define XGENE_DMA_MEM_RAM_SHUTDOWN              0xD070
 113 #define XGENE_DMA_BLK_MEM_RDY                   0xD074
 114 #define XGENE_DMA_BLK_MEM_RDY_VAL               0xFFFFFFFF
 115 #define XGENE_DMA_RING_CMD_SM_OFFSET            0x8000
 116
 117 /* X-Gene SoC EFUSE csr register and bit defination */
 118 #define XGENE_SOC_JTAG1_SHADOW                  0x18
 119 #define XGENE_DMA_PQ_DISABLE_MASK               BIT(13)
 120
 121 /* X-Gene DMA Descriptor format */
 122 #define XGENE_DMA_DESC_NV_BIT                   BIT_ULL(50)
 123 #define XGENE_DMA_DESC_IN_BIT                   BIT_ULL(55)
 124 #define XGENE_DMA_DESC_C_BIT                    BIT_ULL(63)
 125 #define XGENE_DMA_DESC_DR_BIT                   BIT_ULL(61)
 126 #define XGENE_DMA_DESC_ELERR_POS                46
 127 #define XGENE_DMA_DESC_RTYPE_POS                56
 128 #define XGENE_DMA_DESC_LERR_POS                 60
 129 #define XGENE_DMA_DESC_BUFLEN_POS               48
 130 #define XGENE_DMA_DESC_HOENQ_NUM_POS            48
 131 #define XGENE_DMA_DESC_ELERR_RD(m)              \
 132         (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
 133 #define XGENE_DMA_DESC_LERR_RD(m)               \
 134         (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
 135 #define XGENE_DMA_DESC_STATUS(elerr, lerr)      \
 136         (((elerr) << 4) | (lerr))
 137
 138 /* X-Gene DMA descriptor empty s/w signature */
 139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE          ~0ULL
 140
 141 /* X-Gene DMA configurable parameters defines */
 142 #define XGENE_DMA_RING_NUM              512
 143 #define XGENE_DMA_BUFNUM                0x0
 144 #define XGENE_DMA_CPU_BUFNUM            0x18
 145 #define XGENE_DMA_RING_OWNER_DMA        0x03
 146 #define XGENE_DMA_RING_OWNER_CPU        0x0F
 147 #define XGENE_DMA_RING_TYPE_REGULAR     0x01
 148 #define XGENE_DMA_RING_WQ_DESC_SIZE     32      /* 32 Bytes */
 149 #define XGENE_DMA_RING_NUM_CONFIG       5
 150 #define XGENE_DMA_MAX_CHANNEL           4
 151 #define XGENE_DMA_XOR_CHANNEL           0
 152 #define XGENE_DMA_PQ_CHANNEL            1
 153 #define XGENE_DMA_MAX_BYTE_CNT          0x4000  /* 16 KB */
 154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
 155 #define XGENE_DMA_MAX_XOR_SRC           5
 156 #define XGENE_DMA_16K_BUFFER_LEN_CODE   0x0
 157 #define XGENE_DMA_INVALID_LEN_CODE      0x7800000000000000ULL
 158
 159 /* X-Gene DMA descriptor error codes */
 160 #define ERR_DESC_AXI                    0x01
 161 #define ERR_BAD_DESC                    0x02
 162 #define ERR_READ_DATA_AXI               0x03
 163 #define ERR_WRITE_DATA_AXI              0x04
 164 #define ERR_FBP_TIMEOUT                 0x05
 165 #define ERR_ECC                         0x06
 166 #define ERR_DIFF_SIZE                   0x08
 167 #define ERR_SCT_GAT_LEN                 0x09
 168 #define ERR_CRC_ERR                     0x11
 169 #define ERR_CHKSUM                      0x12
 170 #define ERR_DIF                         0x13
 171
 172 /* X-Gene DMA error interrupt codes */
 173 #define ERR_DIF_SIZE_INT                0x0
 174 #define ERR_GS_ERR_INT                  0x1
 175 #define ERR_FPB_TIMEO_INT               0x2
 176 #define ERR_WFIFO_OVF_INT               0x3
 177 #define ERR_RFIFO_OVF_INT               0x4
 178 #define ERR_WR_TIMEO_INT                0x5
 179 #define ERR_RD_TIMEO_INT                0x6
 180 #define ERR_WR_ERR_INT                  0x7
 181 #define ERR_RD_ERR_INT                  0x8
 182 #define ERR_BAD_DESC_INT                0x9
 183 #define ERR_DESC_DST_INT                0xA
 184 #define ERR_DESC_SRC_INT                0xB
 185
 186 /* X-Gene DMA flyby operation code */
 187 #define FLYBY_2SRC_XOR                  0x80
 188 #define FLYBY_3SRC_XOR                  0x90
 189 #define FLYBY_4SRC_XOR                  0xA0
 190 #define FLYBY_5SRC_XOR                  0xB0
 191
 192 /* X-Gene DMA SW descriptor flags */
 193 #define XGENE_DMA_FLAG_64B_DESC         BIT(0)
 194
 195 /* Define to dump X-Gene DMA descriptor */
 196 #define XGENE_DMA_DESC_DUMP(desc, m)    \
 197         print_hex_dump(KERN_ERR, (m),   \
 198                         DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
 199
 200 #define to_dma_desc_sw(tx)              \
 201         container_of(tx, struct xgene_dma_desc_sw, tx)
 202 #define to_dma_chan(dchan)              \
 203         container_of(dchan, struct xgene_dma_chan, dma_chan)
 204
 205 #define chan_dbg(chan, fmt, arg...)     \
 206         dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
 207 #define chan_err(chan, fmt, arg...)     \
 208         dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 209
 210 struct xgene_dma_desc_hw {
 211         __le64 m0;
 212         __le64 m1;
 213         __le64 m2;
 214         __le64 m3;
 215 };
 216
 217 enum xgene_dma_ring_cfgsize {
 218         XGENE_DMA_RING_CFG_SIZE_512B,
 219         XGENE_DMA_RING_CFG_SIZE_2KB,
 220         XGENE_DMA_RING_CFG_SIZE_16KB,
 221         XGENE_DMA_RING_CFG_SIZE_64KB,
 222         XGENE_DMA_RING_CFG_SIZE_512KB,
 223         XGENE_DMA_RING_CFG_SIZE_INVALID
 224 };
 225
 226 struct xgene_dma_ring {
 227         struct xgene_dma *pdma;
 228         u8 buf_num;
 229         u16 id;
 230         u16 num;
 231         u16 head;
 232         u16 owner;
 233         u16 slots;
 234         u16 dst_ring_num;
 235         u32 size;
 236         void __iomem *cmd;
 237         void __iomem *cmd_base;
 238         dma_addr_t desc_paddr;
 239         u32 state[XGENE_DMA_RING_NUM_CONFIG];
 240         enum xgene_dma_ring_cfgsize cfgsize;
 241         union {
 242                 void *desc_vaddr;
 243                 struct xgene_dma_desc_hw *desc_hw;
 244         };
 245 };
 246
 247 struct xgene_dma_desc_sw {
 248         struct xgene_dma_desc_hw desc1;
 249         struct xgene_dma_desc_hw desc2;
 250         u32 flags;
 251         struct list_head node;
 252         struct list_head tx_list;
 253         struct dma_async_tx_descriptor tx;
 254 };
 255
 256 /**
 257  * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
 258  * @dma_chan: dmaengine channel object member
 259  * @pdma: X-Gene DMA device structure reference
 260  * @dev: struct device reference for dma mapping api
 261  * @id: raw id of this channel
 262  * @rx_irq: channel IRQ
 263  * @name: name of X-Gene DMA channel
 264  * @lock: serializes enqueue/dequeue operations to the descriptor pool
 265  * @pending: number of transaction request pushed to DMA controller for
 266  *      execution, but still waiting for completion,
 267  * @max_outstanding: max number of outstanding request we can push to channel
 268  * @ld_pending: descriptors which are queued to run, but have not yet been
 269  *      submitted to the hardware for execution
 270  * @ld_running: descriptors which are currently being executing by the hardware
 271  * @ld_completed: descriptors which have finished execution by the hardware.
 272  *      These descriptors have already had their cleanup actions run. They
 273  *      are waiting for the ACK bit to be set by the async tx API.
 274  * @desc_pool: descriptor pool for DMA operations
 275  * @tasklet: bottom half where all completed descriptors cleans
 276  * @tx_ring: transmit ring descriptor that we use to prepare actual
 277  *      descriptors for further executions
 278  * @rx_ring: receive ring descriptor that we use to get completed DMA
 279  *      descriptors during cleanup time
 280  */
 281 struct xgene_dma_chan {
 282         struct dma_chan dma_chan;
 283         struct xgene_dma *pdma;
 284         struct device *dev;
 285         int id;
 286         int rx_irq;
 287         char name[10];
 288         spinlock_t lock;
 289         int pending;
 290         int max_outstanding;
 291         struct list_head ld_pending;
 292         struct list_head ld_running;
 293         struct list_head ld_completed;
 294         struct dma_pool *desc_pool;
 295         struct tasklet_struct tasklet;
 296         struct xgene_dma_ring tx_ring;
 297         struct xgene_dma_ring rx_ring;
 298 };
 299
 300 /**
 301  * struct xgene_dma - internal representation of an X-Gene DMA device
 302  * @err_irq: DMA error irq number
 303  * @ring_num: start id number for DMA ring
 304  * @csr_dma: base for DMA register access
 305  * @csr_ring: base for DMA ring register access
 306  * @csr_ring_cmd: base for DMA ring command register access
 307  * @csr_efuse: base for efuse register access
 308  * @dma_dev: embedded struct dma_device
 309  * @chan: reference to X-Gene DMA channels
 310  */
 311 struct xgene_dma {
 312         struct device *dev;
 313         struct clk *clk;
 314         int err_irq;
 315         int ring_num;
 316         void __iomem *csr_dma;
 317         void __iomem *csr_ring;
 318         void __iomem *csr_ring_cmd;
 319         void __iomem *csr_efuse;
 320         struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
 321         struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
 322 };
 323
 324 static const char * const xgene_dma_desc_err[] = {
 325         [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
 326         [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
 327         [ERR_READ_DATA_AXI] = "AXI error when reading data",
 328         [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
 329         [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
 330         [ERR_ECC] = "ECC double bit error",
 331         [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
 332         [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
 333         [ERR_CRC_ERR] = "CRC error",
 334         [ERR_CHKSUM] = "Checksum error",
 335         [ERR_DIF] = "DIF error",
 336 };
 337
 338 static const char * const xgene_dma_err[] = {
 339         [ERR_DIF_SIZE_INT] = "DIF size error",
 340         [ERR_GS_ERR_INT] = "Gather scatter not same size error",
 341         [ERR_FPB_TIMEO_INT] = "Free pool time out error",
 342         [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
 343         [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
 344         [ERR_WR_TIMEO_INT] = "Write time out error",
 345         [ERR_RD_TIMEO_INT] = "Read time out error",
 346         [ERR_WR_ERR_INT] = "HBF bus write error",
 347         [ERR_RD_ERR_INT] = "HBF bus read error",
 348         [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
 349         [ERR_DESC_DST_INT] = "HFB reading dst link address error",
 350         [ERR_DESC_SRC_INT] = "HFB reading src link address error",
 351 };
 352
 353 static bool is_pq_enabled(struct xgene_dma *pdma)
 354 {
 355         u32 val;
 356
 357         val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
 358         return !(val & XGENE_DMA_PQ_DISABLE_MASK);
 359 }
 360
 361 static u64 xgene_dma_encode_len(size_t len)
 362 {
 363         return (len < XGENE_DMA_MAX_BYTE_CNT) ?
 364                 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
 365                 XGENE_DMA_16K_BUFFER_LEN_CODE;
 366 }
 367
 368 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
 369 {
 370         static u8 flyby_type[] = {
 371                 FLYBY_2SRC_XOR, /* Dummy */
 372                 FLYBY_2SRC_XOR, /* Dummy */
 373                 FLYBY_2SRC_XOR,
 374                 FLYBY_3SRC_XOR,
 375                 FLYBY_4SRC_XOR,
 376                 FLYBY_5SRC_XOR
 377         };
 378
 379         return flyby_type[src_cnt];
 380 }
 381
 382 static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring)
 383 {
 384         u32 __iomem *cmd_base = ring->cmd_base;
 385         u32 ring_state = ioread32(&cmd_base[1]);
 386
 387         return XGENE_DMA_RING_DESC_CNT(ring_state);
 388 }
 389
 390 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
 391                                      dma_addr_t *paddr)
 392 {
 393         size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
 394                         *len : XGENE_DMA_MAX_BYTE_CNT;
 395
 396         *ext8 |= cpu_to_le64(*paddr);
 397         *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
 398         *len -= nbytes;
 399         *paddr += nbytes;
 400 }
 401
 402 static void xgene_dma_invalidate_buffer(__le64 *ext8)
 403 {
 404         *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE);
 405 }
 406
 407 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
 408 {
 409         switch (idx) {
 410         case 0:
 411                 return &desc->m1;
 412         case 1:
 413                 return &desc->m0;
 414         case 2:
 415                 return &desc->m3;
 416         case 3:
 417                 return &desc->m2;
 418         default:
 419                 pr_err("Invalid dma descriptor index\n");
 420         }
 421
 422         return NULL;
 423 }
 424
 425 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
 426                                 u16 dst_ring_num)
 427 {
 428         desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
 429         desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
 430                                 XGENE_DMA_DESC_RTYPE_POS);
 431         desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
 432         desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
 433                                 XGENE_DMA_DESC_HOENQ_NUM_POS);
 434 }
 435
 436 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan,
 437                                     struct xgene_dma_desc_sw *desc_sw,
 438                                     dma_addr_t dst, dma_addr_t src,
 439                                     size_t len)
 440 {
 441         struct xgene_dma_desc_hw *desc1, *desc2;
 442         int i;
 443
 444         /* Get 1st descriptor */
 445         desc1 = &desc_sw->desc1;
 446         xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
 447
 448         /* Set destination address */
 449         desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
 450         desc1->m3 |= cpu_to_le64(dst);
 451
 452         /* Set 1st source address */
 453         xgene_dma_set_src_buffer(&desc1->m1, &len, &src);
 454
 455         if (!len)
 456                 return;
 457
 458         /*
 459          * We need to split this source buffer,
 460          * and need to use 2nd descriptor
 461          */
 462         desc2 = &desc_sw->desc2;
 463         desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
 464
 465         /* Set 2nd to 5th source address */
 466         for (i = 0; i < 4 && len; i++)
 467                 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i),
 468                                          &len, &src);
 469
 470         /* Invalidate unused source address field */
 471         for (; i < 4; i++)
 472                 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
 473
 474         /* Updated flag that we have prepared 64B descriptor */
 475         desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
 476 }
 477
 478 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
 479                                     struct xgene_dma_desc_sw *desc_sw,
 480                                     dma_addr_t *dst, dma_addr_t *src,
 481                                     u32 src_cnt, size_t *nbytes,
 482                                     const u8 *scf)
 483 {
 484         struct xgene_dma_desc_hw *desc1, *desc2;
 485         size_t len = *nbytes;
 486         int i;
 487
 488         desc1 = &desc_sw->desc1;
 489         desc2 = &desc_sw->desc2;
 490
 491         /* Initialize DMA descriptor */
 492         xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
 493
 494         /* Set destination address */
 495         desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
 496         desc1->m3 |= cpu_to_le64(*dst);
 497
 498         /* We have multiple source addresses, so need to set NV bit*/
 499         desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
 500
 501         /* Set flyby opcode */
 502         desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
 503
 504         /* Set 1st to 5th source addresses */
 505         for (i = 0; i < src_cnt; i++) {
 506                 len = *nbytes;
 507                 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
 508                                          xgene_dma_lookup_ext8(desc2, i - 1),
 509                                          &len, &src[i]);
 510                 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
 511         }
 512
 513         /* Update meta data */
 514         *nbytes = len;
 515         *dst += XGENE_DMA_MAX_BYTE_CNT;
 516
 517         /* We need always 64B descriptor to perform xor or pq operations */
 518         desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
 519 }
 520
 521 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 522 {
 523         struct xgene_dma_desc_sw *desc;
 524         struct xgene_dma_chan *chan;
 525         dma_cookie_t cookie;
 526
 527         if (unlikely(!tx))
 528                 return -EINVAL;
 529
 530         chan = to_dma_chan(tx->chan);
 531         desc = to_dma_desc_sw(tx);
 532
 533         spin_lock_bh(&chan->lock);
 534
 535         cookie = dma_cookie_assign(tx);
 536
 537         /* Add this transaction list onto the tail of the pending queue */
 538         list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
 539
 540         spin_unlock_bh(&chan->lock);
 541
 542         return cookie;
 543 }
 544
 545 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
 546                                        struct xgene_dma_desc_sw *desc)
 547 {
 548         list_del(&desc->node);
 549         chan_dbg(chan, "LD %p free\n", desc);
 550         dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
 551 }
 552
 553 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
 554                                  struct xgene_dma_chan *chan)
 555 {
 556         struct xgene_dma_desc_sw *desc;
 557         dma_addr_t phys;
 558
 559         desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
 560         if (!desc) {
 561                 chan_err(chan, "Failed to allocate LDs\n");
 562                 return NULL;
 563         }
 564
 565         INIT_LIST_HEAD(&desc->tx_list);
 566         desc->tx.phys = phys;
 567         desc->tx.tx_submit = xgene_dma_tx_submit;
 568         dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
 569
 570         chan_dbg(chan, "LD %p allocated\n", desc);
 571
 572         return desc;
 573 }
 574
 575 /**
 576  * xgene_dma_clean_completed_descriptor - free all descriptors which
 577  * has been completed and acked
 578  * @chan: X-Gene DMA channel
 579  *
 580  * This function is used on all completed and acked descriptors.
 581  */
 582 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
 583 {
 584         struct xgene_dma_desc_sw *desc, *_desc;
 585
 586         /* Run the callback for each descriptor, in order */
 587         list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
 588                 if (async_tx_test_ack(&desc->tx))
 589                         xgene_dma_clean_descriptor(chan, desc);
 590         }
 591 }
 592
 593 /**
 594  * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
 595  * @chan: X-Gene DMA channel
 596  * @desc: descriptor to cleanup and free
 597  *
 598  * This function is used on a descriptor which has been executed by the DMA
 599  * controller. It will run any callbacks, submit any dependencies.
 600  */
 601 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
 602                                               struct xgene_dma_desc_sw *desc)
 603 {
 604         struct dma_async_tx_descriptor *tx = &desc->tx;
 605
 606         /*
 607          * If this is not the last transaction in the group,
 608          * then no need to complete cookie and run any callback as
 609          * this is not the tx_descriptor which had been sent to caller
 610          * of this DMA request
 611          */
 612
 613         if (tx->cookie == 0)
 614                 return;
 615
 616         dma_cookie_complete(tx);
 617
 618         /* Run the link descriptor callback function */
 619         if (tx->callback)
 620                 tx->callback(tx->callback_param);
 621
 622         dma_descriptor_unmap(tx);
 623
 624         /* Run any dependencies */
 625         dma_run_dependencies(tx);
 626 }
 627
 628 /**
 629  * xgene_dma_clean_running_descriptor - move the completed descriptor from
 630  * ld_running to ld_completed
 631  * @chan: X-Gene DMA channel
 632  * @desc: the descriptor which is completed
 633  *
 634  * Free the descriptor directly if acked by async_tx api,
 635  * else move it to queue ld_completed.
 636  */
 637 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
 638                                                struct xgene_dma_desc_sw *desc)
 639 {
 640         /* Remove from the list of running transactions */
 641         list_del(&desc->node);
 642
 643         /*
 644          * the client is allowed to attach dependent operations
 645          * until 'ack' is set
 646          */
 647         if (!async_tx_test_ack(&desc->tx)) {
 648                 /*
 649                  * Move this descriptor to the list of descriptors which is
 650                  * completed, but still awaiting the 'ack' bit to be set.
 651                  */
 652                 list_add_tail(&desc->node, &chan->ld_completed);
 653                 return;
 654         }
 655
 656         chan_dbg(chan, "LD %p free\n", desc);
 657         dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
 658 }
 659
 660 static int xgene_chan_xfer_request(struct xgene_dma_ring *ring,
 661                                    struct xgene_dma_desc_sw *desc_sw)
 662 {
 663         struct xgene_dma_desc_hw *desc_hw;
 664
 665         /* Check if can push more descriptor to hw for execution */
 666         if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2))
 667                 return -EBUSY;
 668
 669         /* Get hw descriptor from DMA tx ring */
 670         desc_hw = &ring->desc_hw[ring->head];
 671
 672         /*
 673          * Increment the head count to point next
 674          * descriptor for next time
 675          */
 676         if (++ring->head == ring->slots)
 677                 ring->head = 0;
 678
 679         /* Copy prepared sw descriptor data to hw descriptor */
 680         memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
 681
 682         /*
 683          * Check if we have prepared 64B descriptor,
 684          * in this case we need one more hw descriptor
 685          */
 686         if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
 687                 desc_hw = &ring->desc_hw[ring->head];
 688
 689                 if (++ring->head == ring->slots)
 690                         ring->head = 0;
 691
 692                 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
 693         }
 694
 695         /* Notify the hw that we have descriptor ready for execution */
 696         iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
 697                   2 : 1, ring->cmd);
 698
 699         return 0;
 700 }
 701
 702 /**
 703  * xgene_chan_xfer_ld_pending - push any pending transactions to hw
 704  * @chan : X-Gene DMA channel
 705  *
 706  * LOCKING: must hold chan->lock
 707  */
 708 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
 709 {
 710         struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
 711         int ret;
 712
 713         /*
 714          * If the list of pending descriptors is empty, then we
 715          * don't need to do any work at all
 716          */
 717         if (list_empty(&chan->ld_pending)) {
 718                 chan_dbg(chan, "No pending LDs\n");
 719                 return;
 720         }
 721
 722         /*
 723          * Move elements from the queue of pending transactions onto the list
 724          * of running transactions and push it to hw for further executions
 725          */
 726         list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
 727                 /*
 728                  * Check if have pushed max number of transactions to hw
 729                  * as capable, so let's stop here and will push remaining
 730                  * elements from pening ld queue after completing some
 731                  * descriptors that we have already pushed
 732                  */
 733                 if (chan->pending >= chan->max_outstanding)
 734                         return;
 735
 736                 ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw);
 737                 if (ret)
 738                         return;
 739
 740                 /*
 741                  * Delete this element from ld pending queue and append it to
 742                  * ld running queue
 743                  */
 744                 list_move_tail(&desc_sw->node, &chan->ld_running);
 745
 746                 /* Increment the pending transaction count */
 747                 chan->pending++;
 748         }
 749 }
 750
 751 /**
 752  * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
 753  * and move them to ld_completed to free until flag 'ack' is set
 754  * @chan: X-Gene DMA channel
 755  *
 756  * This function is used on descriptors which have been executed by the DMA
 757  * controller. It will run any callbacks, submit any dependencies, then
 758  * free these descriptors if flag 'ack' is set.
 759  */
 760 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
 761 {
 762         struct xgene_dma_ring *ring = &chan->rx_ring;
 763         struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
 764         struct xgene_dma_desc_hw *desc_hw;
 765         struct list_head ld_completed;
 766         u8 status;
 767
 768         INIT_LIST_HEAD(&ld_completed);
 769
 770         spin_lock_bh(&chan->lock);
 771
 772         /* Clean already completed and acked descriptors */
 773         xgene_dma_clean_completed_descriptor(chan);
 774
 775         /* Move all completed descriptors to ld completed queue, in order */
 776         list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
 777                 /* Get subsequent hw descriptor from DMA rx ring */
 778                 desc_hw = &ring->desc_hw[ring->head];
 779
 780                 /* Check if this descriptor has been completed */
 781                 if (unlikely(le64_to_cpu(desc_hw->m0) ==
 782                              XGENE_DMA_DESC_EMPTY_SIGNATURE))
 783                         break;
 784
 785                 if (++ring->head == ring->slots)
 786                         ring->head = 0;
 787
 788                 /* Check if we have any error with DMA transactions */
 789                 status = XGENE_DMA_DESC_STATUS(
 790                                 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
 791                                                         desc_hw->m0)),
 792                                 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
 793                                                        desc_hw->m0)));
 794                 if (status) {
 795                         /* Print the DMA error type */
 796                         chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
 797
 798                         /*
 799                          * We have DMA transactions error here. Dump DMA Tx
 800                          * and Rx descriptors for this request */
 801                         XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
 802                                             "X-Gene DMA TX DESC1: ");
 803
 804                         if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
 805                                 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
 806                                                     "X-Gene DMA TX DESC2: ");
 807
 808                         XGENE_DMA_DESC_DUMP(desc_hw,
 809                                             "X-Gene DMA RX ERR DESC: ");
 810                 }
 811
 812                 /* Notify the hw about this completed descriptor */
 813                 iowrite32(-1, ring->cmd);
 814
 815                 /* Mark this hw descriptor as processed */
 816                 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
 817
 818                 /*
 819                  * Decrement the pending transaction count
 820                  * as we have processed one
 821                  */
 822                 chan->pending--;
 823
 824                 /*
 825                  * Delete this node from ld running queue and append it to
 826                  * ld completed queue for further processing
 827                  */
 828                 list_move_tail(&desc_sw->node, &ld_completed);
 829         }
 830
 831         /*
 832          * Start any pending transactions automatically
 833          * In the ideal case, we keep the DMA controller busy while we go
 834          * ahead and free the descriptors below.
 835          */
 836         xgene_chan_xfer_ld_pending(chan);
 837
 838         spin_unlock_bh(&chan->lock);
 839
 840         /* Run the callback for each descriptor, in order */
 841         list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
 842                 xgene_dma_run_tx_complete_actions(chan, desc_sw);
 843                 xgene_dma_clean_running_descriptor(chan, desc_sw);
 844         }
 845 }
 846
 847 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
 848 {
 849         struct xgene_dma_chan *chan = to_dma_chan(dchan);
 850
 851         /* Has this channel already been allocated? */
 852         if (chan->desc_pool)
 853                 return 1;
 854
 855         chan->desc_pool = dma_pool_create(chan->name, chan->dev,
 856                                           sizeof(struct xgene_dma_desc_sw),
 857                                           0, 0);
 858         if (!chan->desc_pool) {
 859                 chan_err(chan, "Failed to allocate descriptor pool\n");
 860                 return -ENOMEM;
 861         }
 862
 863         chan_dbg(chan, "Allocate descripto pool\n");
 864
 865         return 1;
 866 }
 867
 868 /**
 869  * xgene_dma_free_desc_list - Free all descriptors in a queue
 870  * @chan: X-Gene DMA channel
 871  * @list: the list to free
 872  *
 873  * LOCKING: must hold chan->lock
 874  */
 875 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
 876                                      struct list_head *list)
 877 {
 878         struct xgene_dma_desc_sw *desc, *_desc;
 879
 880         list_for_each_entry_safe(desc, _desc, list, node)
 881                 xgene_dma_clean_descriptor(chan, desc);
 882 }
 883
 884 static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
 885 {
 886         struct xgene_dma_chan *chan = to_dma_chan(dchan);
 887
 888         chan_dbg(chan, "Free all resources\n");
 889
 890         if (!chan->desc_pool)
 891                 return;
 892
 893         /* Process all running descriptor */
 894         xgene_dma_cleanup_descriptors(chan);
 895
 896         spin_lock_bh(&chan->lock);
 897
 898         /* Clean all link descriptor queues */
 899         xgene_dma_free_desc_list(chan, &chan->ld_pending);
 900         xgene_dma_free_desc_list(chan, &chan->ld_running);
 901         xgene_dma_free_desc_list(chan, &chan->ld_completed);
 902
 903         spin_unlock_bh(&chan->lock);
 904
 905         /* Delete this channel DMA pool */
 906         dma_pool_destroy(chan->desc_pool);
 907         chan->desc_pool = NULL;
 908 }
 909
 910 static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
 911         struct dma_chan *dchan, struct scatterlist *dst_sg,
 912         u32 dst_nents, struct scatterlist *src_sg,
 913         u32 src_nents, unsigned long flags)
 914 {
 915         struct xgene_dma_desc_sw *first = NULL, *new = NULL;
 916         struct xgene_dma_chan *chan;
 917         size_t dst_avail, src_avail;
 918         dma_addr_t dst, src;
 919         size_t len;
 920
 921         if (unlikely(!dchan))
 922                 return NULL;
 923
 924         if (unlikely(!dst_nents || !src_nents))
 925                 return NULL;
 926
 927         if (unlikely(!dst_sg || !src_sg))
 928                 return NULL;
 929
 930         chan = to_dma_chan(dchan);
 931
 932         /* Get prepared for the loop */
 933         dst_avail = sg_dma_len(dst_sg);
 934         src_avail = sg_dma_len(src_sg);
 935         dst_nents--;
 936         src_nents--;
 937
 938         /* Run until we are out of scatterlist entries */
 939         while (true) {
 940                 /* Create the largest transaction possible */
 941                 len = min_t(size_t, src_avail, dst_avail);
 942                 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
 943                 if (len == 0)
 944                         goto fetch;
 945
 946                 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
 947                 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
 948
 949                 /* Allocate the link descriptor from DMA pool */
 950                 new = xgene_dma_alloc_descriptor(chan);
 951                 if (!new)
 952                         goto fail;
 953
 954                 /* Prepare DMA descriptor */
 955                 xgene_dma_prep_cpy_desc(chan, new, dst, src, len);
 956
 957                 if (!first)
 958                         first = new;
 959
 960                 new->tx.cookie = 0;
 961                 async_tx_ack(&new->tx);
 962
 963                 /* update metadata */
 964                 dst_avail -= len;
 965                 src_avail -= len;
 966
 967                 /* Insert the link descriptor to the LD ring */
 968                 list_add_tail(&new->node, &first->tx_list);
 969
 970 fetch:
 971                 /* fetch the next dst scatterlist entry */
 972                 if (dst_avail == 0) {
 973                         /* no more entries: we're done */
 974                         if (dst_nents == 0)
 975                                 break;
 976
 977                         /* fetch the next entry: if there are no more: done */
 978                         dst_sg = sg_next(dst_sg);
 979                         if (!dst_sg)
 980                                 break;
 981
 982                         dst_nents--;
 983                         dst_avail = sg_dma_len(dst_sg);
 984                 }
 985
 986                 /* fetch the next src scatterlist entry */
 987                 if (src_avail == 0) {
 988                         /* no more entries: we're done */
 989                         if (src_nents == 0)
 990                                 break;
 991
 992                         /* fetch the next entry: if there are no more: done */
 993                         src_sg = sg_next(src_sg);
 994                         if (!src_sg)
 995                                 break;
 996
 997                         src_nents--;
 998                         src_avail = sg_dma_len(src_sg);
 999                 }
1000         }
1001
1002         if (!new)
1003                 return NULL;
1004
1005         new->tx.flags = flags; /* client is in control of this ack */
1006         new->tx.cookie = -EBUSY;
1007         list_splice(&first->tx_list, &new->tx_list);
1008
1009         return &new->tx;
1010 fail:
1011         if (!first)
1012                 return NULL;
1013
1014         xgene_dma_free_desc_list(chan, &first->tx_list);
1015         return NULL;
1016 }
1017
1018 static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
1019         struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
1020         u32 src_cnt, size_t len, unsigned long flags)
1021 {
1022         struct xgene_dma_desc_sw *first = NULL, *new;
1023         struct xgene_dma_chan *chan;
1024         static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
1025                                 0x01, 0x01, 0x01, 0x01, 0x01};
1026
1027         if (unlikely(!dchan || !len))
1028                 return NULL;
1029
1030         chan = to_dma_chan(dchan);
1031
1032         do {
1033                 /* Allocate the link descriptor from DMA pool */
1034                 new = xgene_dma_alloc_descriptor(chan);
1035                 if (!new)
1036                         goto fail;
1037
1038                 /* Prepare xor DMA descriptor */
1039                 xgene_dma_prep_xor_desc(chan, new, &dst, src,
1040                                         src_cnt, &len, multi);
1041
1042                 if (!first)
1043                         first = new;
1044
1045                 new->tx.cookie = 0;
1046                 async_tx_ack(&new->tx);
1047
1048                 /* Insert the link descriptor to the LD ring */
1049                 list_add_tail(&new->node, &first->tx_list);
1050         } while (len);
1051
1052         new->tx.flags = flags; /* client is in control of this ack */
1053         new->tx.cookie = -EBUSY;
1054         list_splice(&first->tx_list, &new->tx_list);
1055
1056         return &new->tx;
1057
1058 fail:
1059         if (!first)
1060                 return NULL;
1061
1062         xgene_dma_free_desc_list(chan, &first->tx_list);
1063         return NULL;
1064 }
1065
1066 static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
1067         struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1068         u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1069 {
1070         struct xgene_dma_desc_sw *first = NULL, *new;
1071         struct xgene_dma_chan *chan;
1072         size_t _len = len;
1073         dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
1074         static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
1075
1076         if (unlikely(!dchan || !len))
1077                 return NULL;
1078
1079         chan = to_dma_chan(dchan);
1080
1081         /*
1082          * Save source addresses on local variable, may be we have to
1083          * prepare two descriptor to generate P and Q if both enabled
1084          * in the flags by client
1085          */
1086         memcpy(_src, src, sizeof(*src) * src_cnt);
1087
1088         if (flags & DMA_PREP_PQ_DISABLE_P)
1089                 len = 0;
1090
1091         if (flags & DMA_PREP_PQ_DISABLE_Q)
1092                 _len = 0;
1093
1094         do {
1095                 /* Allocate the link descriptor from DMA pool */
1096                 new = xgene_dma_alloc_descriptor(chan);
1097                 if (!new)
1098                         goto fail;
1099
1100                 if (!first)
1101                         first = new;
1102
1103                 new->tx.cookie = 0;
1104                 async_tx_ack(&new->tx);
1105
1106                 /* Insert the link descriptor to the LD ring */
1107                 list_add_tail(&new->node, &first->tx_list);
1108
1109                 /*
1110                  * Prepare DMA descriptor to generate P,
1111                  * if DMA_PREP_PQ_DISABLE_P flag is not set
1112                  */
1113                 if (len) {
1114                         xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
1115                                                 src_cnt, &len, multi);
1116                         continue;
1117                 }
1118
1119                 /*
1120                  * Prepare DMA descriptor to generate Q,
1121                  * if DMA_PREP_PQ_DISABLE_Q flag is not set
1122                  */
1123                 if (_len) {
1124                         xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
1125                                                 src_cnt, &_len, scf);
1126                 }
1127         } while (len || _len);
1128
1129         new->tx.flags = flags; /* client is in control of this ack */
1130         new->tx.cookie = -EBUSY;
1131         list_splice(&first->tx_list, &new->tx_list);
1132
1133         return &new->tx;
1134
1135 fail:
1136         if (!first)
1137                 return NULL;
1138
1139         xgene_dma_free_desc_list(chan, &first->tx_list);
1140         return NULL;
1141 }
1142
1143 static void xgene_dma_issue_pending(struct dma_chan *dchan)
1144 {
1145         struct xgene_dma_chan *chan = to_dma_chan(dchan);
1146
1147         spin_lock_bh(&chan->lock);
1148         xgene_chan_xfer_ld_pending(chan);
1149         spin_unlock_bh(&chan->lock);
1150 }
1151
1152 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
1153                                            dma_cookie_t cookie,
1154                                            struct dma_tx_state *txstate)
1155 {
1156         return dma_cookie_status(dchan, cookie, txstate);
1157 }
1158
1159 static void xgene_dma_tasklet_cb(unsigned long data)
1160 {
1161         struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
1162
1163         /* Run all cleanup for descriptors which have been completed */
1164         xgene_dma_cleanup_descriptors(chan);
1165
1166         /* Re-enable DMA channel IRQ */
1167         enable_irq(chan->rx_irq);
1168 }
1169
1170 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
1171 {
1172         struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
1173
1174         BUG_ON(!chan);
1175
1176         /*
1177          * Disable DMA channel IRQ until we process completed
1178          * descriptors
1179          */
1180         disable_irq_nosync(chan->rx_irq);
1181
1182         /*
1183          * Schedule the tasklet to handle all cleanup of the current
1184          * transaction. It will start a new transaction if there is
1185          * one pending.
1186          */
1187         tasklet_schedule(&chan->tasklet);
1188
1189         return IRQ_HANDLED;
1190 }
1191
1192 static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1193 {
1194         struct xgene_dma *pdma = (struct xgene_dma *)id;
1195         unsigned long int_mask;
1196         u32 val, i;
1197
1198         val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1199
1200         /* Clear DMA interrupts */
1201         iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1202
1203         /* Print DMA error info */
1204         int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1205         for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1206                 dev_err(pdma->dev,
1207                         "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1208
1209         return IRQ_HANDLED;
1210 }
1211
1212 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1213 {
1214         int i;
1215
1216         iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1217
1218         for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1219                 iowrite32(ring->state[i], ring->pdma->csr_ring +
1220                           XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1221 }
1222
1223 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1224 {
1225         memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1226         xgene_dma_wr_ring_state(ring);
1227 }
1228
1229 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1230 {
1231         void *ring_cfg = ring->state;
1232         u64 addr = ring->desc_paddr;
1233         u32 i, val;
1234
1235         ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1236
1237         /* Clear DMA ring state */
1238         xgene_dma_clr_ring_state(ring);
1239
1240         /* Set DMA ring type */
1241         XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1242
1243         if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1244                 /* Set recombination buffer and timeout */
1245                 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1246                 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1247                 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1248         }
1249
1250         /* Initialize DMA ring state */
1251         XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1252         XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1253         XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1254         XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1255         XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1256         XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1257
1258         /* Write DMA ring configurations */
1259         xgene_dma_wr_ring_state(ring);
1260
1261         /* Set DMA ring id */
1262         iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1263                   ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1264
1265         /* Set DMA ring buffer */
1266         iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1267                   ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1268
1269         if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1270                 return;
1271
1272         /* Set empty signature to DMA Rx ring descriptors */
1273         for (i = 0; i < ring->slots; i++) {
1274                 struct xgene_dma_desc_hw *desc;
1275
1276                 desc = &ring->desc_hw[i];
1277                 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1278         }
1279
1280         /* Enable DMA Rx ring interrupt */
1281         val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1282         XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1283         iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1284 }
1285
1286 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1287 {
1288         u32 ring_id, val;
1289
1290         if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1291                 /* Disable DMA Rx ring interrupt */
1292                 val = ioread32(ring->pdma->csr_ring +
1293                                XGENE_DMA_RING_NE_INT_MODE);
1294                 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1295                 iowrite32(val, ring->pdma->csr_ring +
1296                           XGENE_DMA_RING_NE_INT_MODE);
1297         }
1298
1299         /* Clear DMA ring state */
1300         ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1301         iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1302
1303         iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1304         xgene_dma_clr_ring_state(ring);
1305 }
1306
1307 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1308 {
1309         ring->cmd_base = ring->pdma->csr_ring_cmd +
1310                                 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1311                                                           XGENE_DMA_RING_NUM));
1312
1313         ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1314 }
1315
1316 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1317                                    enum xgene_dma_ring_cfgsize cfgsize)
1318 {
1319         int size;
1320
1321         switch (cfgsize) {
1322         case XGENE_DMA_RING_CFG_SIZE_512B:
1323                 size = 0x200;
1324                 break;
1325         case XGENE_DMA_RING_CFG_SIZE_2KB:
1326                 size = 0x800;
1327                 break;
1328         case XGENE_DMA_RING_CFG_SIZE_16KB:
1329                 size = 0x4000;
1330                 break;
1331         case XGENE_DMA_RING_CFG_SIZE_64KB:
1332                 size = 0x10000;
1333                 break;
1334         case XGENE_DMA_RING_CFG_SIZE_512KB:
1335                 size = 0x80000;
1336                 break;
1337         default:
1338                 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1339                 return -EINVAL;
1340         }
1341
1342         return size;
1343 }
1344
1345 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1346 {
1347         /* Clear DMA ring configurations */
1348         xgene_dma_clear_ring(ring);
1349
1350         /* De-allocate DMA ring descriptor */
1351         if (ring->desc_vaddr) {
1352                 dma_free_coherent(ring->pdma->dev, ring->size,
1353                                   ring->desc_vaddr, ring->desc_paddr);
1354                 ring->desc_vaddr = NULL;
1355         }
1356 }
1357
1358 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1359 {
1360         xgene_dma_delete_ring_one(&chan->rx_ring);
1361         xgene_dma_delete_ring_one(&chan->tx_ring);
1362 }
1363
1364 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1365                                      struct xgene_dma_ring *ring,
1366                                      enum xgene_dma_ring_cfgsize cfgsize)
1367 {
1368         /* Setup DMA ring descriptor variables */
1369         ring->pdma = chan->pdma;
1370         ring->cfgsize = cfgsize;
1371         ring->num = chan->pdma->ring_num++;
1372         ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1373
1374         ring->size = xgene_dma_get_ring_size(chan, cfgsize);
1375         if (ring->size <= 0)
1376                 return ring->size;
1377
1378         /* Allocate memory for DMA ring descriptor */
1379         ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size,
1380                                                &ring->desc_paddr, GFP_KERNEL);
1381         if (!ring->desc_vaddr) {
1382                 chan_err(chan, "Failed to allocate ring desc\n");
1383                 return -ENOMEM;
1384         }
1385
1386         /* Configure and enable DMA ring */
1387         xgene_dma_set_ring_cmd(ring);
1388         xgene_dma_setup_ring(ring);
1389
1390         return 0;
1391 }
1392
1393 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1394 {
1395         struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1396         struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1397         int ret;
1398
1399         /* Create DMA Rx ring descriptor */
1400         rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1401         rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1402
1403         ret = xgene_dma_create_ring_one(chan, rx_ring,
1404                                         XGENE_DMA_RING_CFG_SIZE_64KB);
1405         if (ret)
1406                 return ret;
1407
1408         chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1409                  rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1410
1411         /* Create DMA Tx ring descriptor */
1412         tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1413         tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1414
1415         ret = xgene_dma_create_ring_one(chan, tx_ring,
1416                                         XGENE_DMA_RING_CFG_SIZE_64KB);
1417         if (ret) {
1418                 xgene_dma_delete_ring_one(rx_ring);
1419                 return ret;
1420         }
1421
1422         tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1423
1424         chan_dbg(chan,
1425                  "Tx ring id 0x%X num %d desc 0x%p\n",
1426                  tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1427
1428         /* Set the max outstanding request possible to this channel */
1429         chan->max_outstanding = rx_ring->slots;
1430
1431         return ret;
1432 }
1433
1434 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1435 {
1436         int ret, i, j;
1437
1438         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1439                 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1440                 if (ret) {
1441                         for (j = 0; j < i; j++)
1442                                 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1443                         return ret;
1444                 }
1445         }
1446
1447         return ret;
1448 }
1449
1450 static void xgene_dma_enable(struct xgene_dma *pdma)
1451 {
1452         u32 val;
1453
1454         /* Configure and enable DMA engine */
1455         val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1456         XGENE_DMA_CH_SETUP(val);
1457         XGENE_DMA_ENABLE(val);
1458         iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1459 }
1460
1461 static void xgene_dma_disable(struct xgene_dma *pdma)
1462 {
1463         u32 val;
1464
1465         val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1466         XGENE_DMA_DISABLE(val);
1467         iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1468 }
1469
1470 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1471 {
1472         /*
1473          * Mask DMA ring overflow, underflow and
1474          * AXI write/read error interrupts
1475          */
1476         iowrite32(XGENE_DMA_INT_ALL_MASK,
1477                   pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1478         iowrite32(XGENE_DMA_INT_ALL_MASK,
1479                   pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1480         iowrite32(XGENE_DMA_INT_ALL_MASK,
1481                   pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1482         iowrite32(XGENE_DMA_INT_ALL_MASK,
1483                   pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1484         iowrite32(XGENE_DMA_INT_ALL_MASK,
1485                   pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1486
1487         /* Mask DMA error interrupts */
1488         iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1489 }
1490
1491 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1492 {
1493         /*
1494          * Unmask DMA ring overflow, underflow and
1495          * AXI write/read error interrupts
1496          */
1497         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1498                   pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1499         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1500                   pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1501         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1502                   pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1503         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1504                   pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1505         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1506                   pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1507
1508         /* Unmask DMA error interrupts */
1509         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1510                   pdma->csr_dma + XGENE_DMA_INT_MASK);
1511 }
1512
1513 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1514 {
1515         u32 val;
1516
1517         /* Associate DMA ring to corresponding ring HW */
1518         iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1519                   pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1520
1521         /* Configure RAID6 polynomial control setting */
1522         if (is_pq_enabled(pdma))
1523                 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1524                           pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1525         else
1526                 dev_info(pdma->dev, "PQ is disabled in HW\n");
1527
1528         xgene_dma_enable(pdma);
1529         xgene_dma_unmask_interrupts(pdma);
1530
1531         /* Get DMA id and version info */
1532         val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1533
1534         /* DMA device info */
1535         dev_info(pdma->dev,
1536                  "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1537                  XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1538                  XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1539 }
1540
1541 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1542 {
1543         if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1544             (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1545                 return 0;
1546
1547         iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1548         iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1549
1550         /* Bring up memory */
1551         iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1552
1553         /* Force a barrier */
1554         ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1555
1556         /* reset may take up to 1ms */
1557         usleep_range(1000, 1100);
1558
1559         if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1560                 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1561                 dev_err(pdma->dev,
1562                         "Failed to release ring mngr memory from shutdown\n");
1563                 return -ENODEV;
1564         }
1565
1566         /* program threshold set 1 and all hysteresis */
1567         iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1568                   pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1569         iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1570                   pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1571         iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1572                   pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1573
1574         /* Enable QPcore and assign error queue */
1575         iowrite32(XGENE_DMA_RING_ENABLE,
1576                   pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1577
1578         return 0;
1579 }
1580
1581 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1582 {
1583         int ret;
1584
1585         ret = xgene_dma_init_ring_mngr(pdma);
1586         if (ret)
1587                 return ret;
1588
1589         /* Bring up memory */
1590         iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1591
1592         /* Force a barrier */
1593         ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1594
1595         /* reset may take up to 1ms */
1596         usleep_range(1000, 1100);
1597
1598         if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1599                 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1600                 dev_err(pdma->dev,
1601                         "Failed to release DMA memory from shutdown\n");
1602                 return -ENODEV;
1603         }
1604
1605         return 0;
1606 }
1607
1608 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1609 {
1610         struct xgene_dma_chan *chan;
1611         int ret, i, j;
1612
1613         /* Register DMA error irq */
1614         ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1615                                0, "dma_error", pdma);
1616         if (ret) {
1617                 dev_err(pdma->dev,
1618                         "Failed to register error IRQ %d\n", pdma->err_irq);
1619                 return ret;
1620         }
1621
1622         /* Register DMA channel rx irq */
1623         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1624                 chan = &pdma->chan[i];
1625                 ret = devm_request_irq(chan->dev, chan->rx_irq,
1626                                        xgene_dma_chan_ring_isr,
1627                                        0, chan->name, chan);
1628                 if (ret) {
1629                         chan_err(chan, "Failed to register Rx IRQ %d\n",
1630                                  chan->rx_irq);
1631                         devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1632
1633                         for (j = 0; j < i; j++) {
1634                                 chan = &pdma->chan[i];
1635                                 devm_free_irq(chan->dev, chan->rx_irq, chan);
1636                         }
1637
1638                         return ret;
1639                 }
1640         }
1641
1642         return 0;
1643 }
1644
1645 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1646 {
1647         struct xgene_dma_chan *chan;
1648         int i;
1649
1650         /* Free DMA device error irq */
1651         devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1652
1653         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1654                 chan = &pdma->chan[i];
1655                 devm_free_irq(chan->dev, chan->rx_irq, chan);
1656         }
1657 }
1658
1659 static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1660                                struct dma_device *dma_dev)
1661 {
1662         /* Initialize DMA device capability mask */
1663         dma_cap_zero(dma_dev->cap_mask);
1664
1665         /* Set DMA device capability */
1666         dma_cap_set(DMA_SG, dma_dev->cap_mask);
1667
1668         /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1669          * and channel 1 supports XOR, PQ both. First thing here is we have
1670          * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1671          * we can make sure this by reading SoC Efuse register.
1672          * Second thing, we have hw errata that if we run channel 0 and
1673          * channel 1 simultaneously with executing XOR and PQ request,
1674          * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1675          * if XOR and PQ supports on channel 1 is disabled.
1676          */
1677         if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1678             is_pq_enabled(chan->pdma)) {
1679                 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1680                 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1681         } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1682                    !is_pq_enabled(chan->pdma)) {
1683                 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1684         }
1685
1686         /* Set base and prep routines */
1687         dma_dev->dev = chan->dev;
1688         dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1689         dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1690         dma_dev->device_issue_pending = xgene_dma_issue_pending;
1691         dma_dev->device_tx_status = xgene_dma_tx_status;
1692         dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
1693
1694         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1695                 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1696                 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1697                 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
1698         }
1699
1700         if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1701                 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1702                 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1703                 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
1704         }
1705 }
1706
1707 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1708 {
1709         struct xgene_dma_chan *chan = &pdma->chan[id];
1710         struct dma_device *dma_dev = &pdma->dma_dev[id];
1711         int ret;
1712
1713         chan->dma_chan.device = dma_dev;
1714
1715         spin_lock_init(&chan->lock);
1716         INIT_LIST_HEAD(&chan->ld_pending);
1717         INIT_LIST_HEAD(&chan->ld_running);
1718         INIT_LIST_HEAD(&chan->ld_completed);
1719         tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1720                      (unsigned long)chan);
1721
1722         chan->pending = 0;
1723         chan->desc_pool = NULL;
1724         dma_cookie_init(&chan->dma_chan);
1725
1726         /* Setup dma device capabilities and prep routines */
1727         xgene_dma_set_caps(chan, dma_dev);
1728
1729         /* Initialize DMA device list head */
1730         INIT_LIST_HEAD(&dma_dev->channels);
1731         list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1732
1733         /* Register with Linux async DMA framework*/
1734         ret = dma_async_device_register(dma_dev);
1735         if (ret) {
1736                 chan_err(chan, "Failed to register async device %d", ret);
1737                 tasklet_kill(&chan->tasklet);
1738
1739                 return ret;
1740         }
1741
1742         /* DMA capability info */
1743         dev_info(pdma->dev,
1744                  "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan),
1745                  dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
1746                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1747                  dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1748
1749         return 0;
1750 }
1751
1752 static int xgene_dma_init_async(struct xgene_dma *pdma)
1753 {
1754         int ret, i, j;
1755
1756         for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1757                 ret = xgene_dma_async_register(pdma, i);
1758                 if (ret) {
1759                         for (j = 0; j < i; j++) {
1760                                 dma_async_device_unregister(&pdma->dma_dev[j]);
1761                                 tasklet_kill(&pdma->chan[j].tasklet);
1762                         }
1763
1764                         return ret;
1765                 }
1766         }
1767
1768         return ret;
1769 }
1770
1771 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1772 {
1773         int i;
1774
1775         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1776                 dma_async_device_unregister(&pdma->dma_dev[i]);
1777 }
1778
1779 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1780 {
1781         struct xgene_dma_chan *chan;
1782         int i;
1783
1784         pdma->ring_num = XGENE_DMA_RING_NUM;
1785
1786         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1787                 chan = &pdma->chan[i];
1788                 chan->dev = pdma->dev;
1789                 chan->pdma = pdma;
1790                 chan->id = i;
1791                 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1792         }
1793 }
1794
1795 static int xgene_dma_get_resources(struct platform_device *pdev,
1796                                    struct xgene_dma *pdma)
1797 {
1798         struct resource *res;
1799         int irq, i;
1800
1801         /* Get DMA csr region */
1802         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1803         if (!res) {
1804                 dev_err(&pdev->dev, "Failed to get csr region\n");
1805                 return -ENXIO;
1806         }
1807
1808         pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1809                                      resource_size(res));
1810         if (!pdma->csr_dma) {
1811                 dev_err(&pdev->dev, "Failed to ioremap csr region");
1812                 return -ENOMEM;
1813         }
1814
1815         /* Get DMA ring csr region */
1816         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1817         if (!res) {
1818                 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1819                 return -ENXIO;
1820         }
1821
1822         pdma->csr_ring =  devm_ioremap(&pdev->dev, res->start,
1823                                        resource_size(res));
1824         if (!pdma->csr_ring) {
1825                 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1826                 return -ENOMEM;
1827         }
1828
1829         /* Get DMA ring cmd csr region */
1830         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1831         if (!res) {
1832                 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1833                 return -ENXIO;
1834         }
1835
1836         pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1837                                           resource_size(res));
1838         if (!pdma->csr_ring_cmd) {
1839                 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1840                 return -ENOMEM;
1841         }
1842
1843         pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1844
1845         /* Get efuse csr region */
1846         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1847         if (!res) {
1848                 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1849                 return -ENXIO;
1850         }
1851
1852         pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1853                                        resource_size(res));
1854         if (!pdma->csr_efuse) {
1855                 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1856                 return -ENOMEM;
1857         }
1858
1859         /* Get DMA error interrupt */
1860         irq = platform_get_irq(pdev, 0);
1861         if (irq <= 0) {
1862                 dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1863                 return -ENXIO;
1864         }
1865
1866         pdma->err_irq = irq;
1867
1868         /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1869         for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1870                 irq = platform_get_irq(pdev, i);
1871                 if (irq <= 0) {
1872                         dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1873                         return -ENXIO;
1874                 }
1875
1876                 pdma->chan[i - 1].rx_irq = irq;
1877         }
1878
1879         return 0;
1880 }
1881
1882 static int xgene_dma_probe(struct platform_device *pdev)
1883 {
1884         struct xgene_dma *pdma;
1885         int ret, i;
1886
1887         pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1888         if (!pdma)
1889                 return -ENOMEM;
1890
1891         pdma->dev = &pdev->dev;
1892         platform_set_drvdata(pdev, pdma);
1893
1894         ret = xgene_dma_get_resources(pdev, pdma);
1895         if (ret)
1896                 return ret;
1897
1898         pdma->clk = devm_clk_get(&pdev->dev, NULL);
1899         if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1900                 dev_err(&pdev->dev, "Failed to get clk\n");
1901                 return PTR_ERR(pdma->clk);
1902         }
1903
1904         /* Enable clk before accessing registers */
1905         if (!IS_ERR(pdma->clk)) {
1906                 ret = clk_prepare_enable(pdma->clk);
1907                 if (ret) {
1908                         dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1909                         return ret;
1910                 }
1911         }
1912
1913         /* Remove DMA RAM out of shutdown */
1914         ret = xgene_dma_init_mem(pdma);
1915         if (ret)
1916                 goto err_clk_enable;
1917
1918         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1919         if (ret) {
1920                 dev_err(&pdev->dev, "No usable DMA configuration\n");
1921                 goto err_dma_mask;
1922         }
1923
1924         /* Initialize DMA channels software state */
1925         xgene_dma_init_channels(pdma);
1926
1927         /* Configue DMA rings */
1928         ret = xgene_dma_init_rings(pdma);
1929         if (ret)
1930                 goto err_clk_enable;
1931
1932         ret = xgene_dma_request_irqs(pdma);
1933         if (ret)
1934                 goto err_request_irq;
1935
1936         /* Configure and enable DMA engine */
1937         xgene_dma_init_hw(pdma);
1938
1939         /* Register DMA device with linux async framework */
1940         ret = xgene_dma_init_async(pdma);
1941         if (ret)
1942                 goto err_async_init;
1943
1944         return 0;
1945
1946 err_async_init:
1947         xgene_dma_free_irqs(pdma);
1948
1949 err_request_irq:
1950         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1951                 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1952
1953 err_dma_mask:
1954 err_clk_enable:
1955         if (!IS_ERR(pdma->clk))
1956                 clk_disable_unprepare(pdma->clk);
1957
1958         return ret;
1959 }
1960
1961 static int xgene_dma_remove(struct platform_device *pdev)
1962 {
1963         struct xgene_dma *pdma = platform_get_drvdata(pdev);
1964         struct xgene_dma_chan *chan;
1965         int i;
1966
1967         xgene_dma_async_unregister(pdma);
1968
1969         /* Mask interrupts and disable DMA engine */
1970         xgene_dma_mask_interrupts(pdma);
1971         xgene_dma_disable(pdma);
1972         xgene_dma_free_irqs(pdma);
1973
1974         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1975                 chan = &pdma->chan[i];
1976                 tasklet_kill(&chan->tasklet);
1977                 xgene_dma_delete_chan_rings(chan);
1978         }
1979
1980         if (!IS_ERR(pdma->clk))
1981                 clk_disable_unprepare(pdma->clk);
1982
1983         return 0;
1984 }
1985
1986 #ifdef CONFIG_ACPI
1987 static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
1988         {"APMC0D43", 0},
1989         {},
1990 };
1991 MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
1992 #endif
1993
1994 static const struct of_device_id xgene_dma_of_match_ptr[] = {
1995         {.compatible = "apm,xgene-storm-dma",},
1996         {},
1997 };
1998 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
1999
2000 static struct platform_driver xgene_dma_driver = {
2001         .probe = xgene_dma_probe,
2002         .remove = xgene_dma_remove,
2003         .driver = {
2004                 .name = "X-Gene-DMA",
2005                 .of_match_table = xgene_dma_of_match_ptr,
2006                 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
2007         },
2008 };
2009
2010 module_platform_driver(xgene_dma_driver);
2011
2012 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2013 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2014 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2015 MODULE_LICENSE("GPL");
2016 MODULE_VERSION("1.0");